src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_util.h"
   3
   4 #include "nv40_context.h"
   5 #include "nv40_screen.h"
   6
   7 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   8 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   9 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  10
  11 static const char *
  12 nv40_screen_get_name(struct pipe_screen *pscreen)
  13 {
  14         struct nv40_screen *screen = nv40_screen(pscreen);
  15         struct nouveau_device *dev = screen->nvws->channel->device;
  16         static char buffer[128];
  17
  18         snprintf(buffer, sizeof(buffer), "NV%02X", dev->chipset);
  19         return buffer;
  20 }
  21
  22 static const char *
  23 nv40_screen_get_vendor(struct pipe_screen *pscreen)
  24 {
  25         return "nouveau";
  26 }
  27
  28 static int
  29 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  30 {
  31         struct nv40_screen *screen = nv40_screen(pscreen);
  32
  33         switch (param) {
  34         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  35                 return 16;
  36         case PIPE_CAP_NPOT_TEXTURES:
  37                 return 1;
  38         case PIPE_CAP_TWO_SIDED_STENCIL:
  39                 return 1;
  40         case PIPE_CAP_GLSL:
  41                 return 0;
  42         case PIPE_CAP_S3TC:
  43                 return 1;
  44         case PIPE_CAP_ANISOTROPIC_FILTER:
  45                 return 1;
  46         case PIPE_CAP_POINT_SPRITE:
  47                 return 1;
  48         case PIPE_CAP_MAX_RENDER_TARGETS:
  49                 return 4;
  50         case PIPE_CAP_OCCLUSION_QUERY:
  51                 return 1;
  52         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  53                 return 1;
  54         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  55                 return 13;
  56         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  57                 return 10;
  58         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  59                 return 13;
  60         case NOUVEAU_CAP_HW_VTXBUF:
  61                 return 1;
  62         case NOUVEAU_CAP_HW_IDXBUF:
  63                 if (screen->curie->grclass == NV40TCL)
  64                         return 1;
  65                 return 0;
  66         default:
  67                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  68                 return 0;
  69         }
  70 }
  71
  72 static float
  73 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  74 {
  75         switch (param) {
  76         case PIPE_CAP_MAX_LINE_WIDTH:
  77         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  78                 return 10.0;
  79         case PIPE_CAP_MAX_POINT_WIDTH:
  80         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  81                 return 64.0;
  82         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  83                 return 16.0;
  84         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  85                 return 16.0;
  86         default:
  87                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  88                 return 0.0;
  89         }
  90 }
  91
  92 static boolean
  93 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  94                                      enum pipe_format format,
  95                                      enum pipe_texture_target target,
  96                                      unsigned tex_usage, unsigned geom_flags)
  97 {
  98         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
  99                 switch (format) {
 100                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 101                 case PIPE_FORMAT_R5G6B5_UNORM:
 102                 case PIPE_FORMAT_Z24S8_UNORM:
 103                 case PIPE_FORMAT_Z16_UNORM:
 104                         return TRUE;
 105                 default:
 106                         break;
 107                 }
 108         } else {
 109                 switch (format) {
 110                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 111                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 112                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 113                 case PIPE_FORMAT_R5G6B5_UNORM:
 114                 case PIPE_FORMAT_L8_UNORM:
 115                 case PIPE_FORMAT_A8_UNORM:
 116                 case PIPE_FORMAT_I8_UNORM:
 117                 case PIPE_FORMAT_A8L8_UNORM:
 118                 case PIPE_FORMAT_Z16_UNORM:
 119                 case PIPE_FORMAT_Z24S8_UNORM:
 120                 case PIPE_FORMAT_DXT1_RGB:
 121                 case PIPE_FORMAT_DXT1_RGBA:
 122                 case PIPE_FORMAT_DXT3_RGBA:
 123                 case PIPE_FORMAT_DXT5_RGBA:
 124                         return TRUE;
 125                 default:
 126                         break;
 127                 }
 128         }
 129
 130         return FALSE;
 131 }
 132
 133 static void *
 134 nv40_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
 135                  unsigned flags )
 136 {
 137         struct pipe_winsys *ws = screen->winsys;
 138         void *map;
 139
 140         map = ws->buffer_map(ws, surface->buffer, flags);
 141         if (!map)
 142                 return NULL;
 143
 144         return map + surface->offset;
 145 }
 146
 147 static void
 148 nv40_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
 149 {
 150         struct pipe_winsys *ws = screen->winsys;
 151
 152         ws->buffer_unmap(ws, surface->buffer);
 153 }
 154
 155 static void
 156 nv40_screen_destroy(struct pipe_screen *pscreen)
 157 {
 158         struct nv40_screen *screen = nv40_screen(pscreen);
 159         struct nouveau_winsys *nvws = screen->nvws;
 160
 161         nvws->res_free(&screen->vp_exec_heap);
 162         nvws->res_free(&screen->vp_data_heap);
 163         nvws->res_free(&screen->query_heap);
 164         nvws->notifier_free(&screen->query);
 165         nvws->notifier_free(&screen->sync);
 166         nvws->grobj_free(&screen->curie);
 167
 168         FREE(pscreen);
 169 }
 170
 171 struct pipe_screen *
 172 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 173 {
 174         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 175         struct nouveau_stateobj *so;
 176         unsigned curie_class;
 177         unsigned chipset = nvws->channel->device->chipset;
 178         int ret;
 179
 180         if (!screen)
 181                 return NULL;
 182         screen->nvws = nvws;
 183
 184         /* 3D object */
 185         switch (chipset & 0xf0) {
 186         case 0x40:
 187                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f)))
 188                         curie_class = NV40TCL;
 189                 else
 190                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 191                         curie_class = NV44TCL;
 192                 break;
 193         case 0x60:
 194                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 195                         curie_class = NV44TCL;
 196                 break;
 197         default:
 198                 break;
 199         }
 200
 201         if (!curie_class) {
 202                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", chipset);
 203                 return NULL;
 204         }
 205
 206         ret = nvws->grobj_alloc(nvws, curie_class, &screen->curie);
 207         if (ret) {
 208                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 209                 return FALSE;
 210         }
 211
 212         /* Notifier for sync purposes */
 213         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 214         if (ret) {
 215                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 216                 nv40_screen_destroy(&screen->pipe);
 217                 return NULL;
 218         }
 219
 220         /* Query objects */
 221         ret = nvws->notifier_alloc(nvws, 32, &screen->query);
 222         if (ret) {
 223                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 224                 nv40_screen_destroy(&screen->pipe);
 225                 return NULL;
 226         }
 227
 228         ret = nvws->res_init(&screen->query_heap, 0, 32);
 229         if (ret) {
 230                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 231                 nv40_screen_destroy(&screen->pipe);
 232                 return NULL;
 233         }
 234
 235         /* Vtxprog resources */
 236         if (nvws->res_init(&screen->vp_exec_heap, 0, 512) ||
 237             nvws->res_init(&screen->vp_data_heap, 0, 256)) {
 238                 nv40_screen_destroy(&screen->pipe);
 239                 return NULL;
 240         }
 241
 242         /* Static curie initialisation */
 243         so = so_new(128, 0);
 244         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 245         so_data  (so, screen->sync->handle);
 246         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 247         so_data  (so, nvws->channel->vram->handle);
 248         so_data  (so, nvws->channel->gart->handle);
 249         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 250         so_data  (so, nvws->channel->vram->handle);
 251         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 252         so_data  (so, nvws->channel->vram->handle);
 253         so_data  (so, nvws->channel->vram->handle);
 254         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 255         so_data  (so, nvws->channel->vram->handle);
 256         so_data  (so, nvws->channel->gart->handle);
 257         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 258         so_data  (so, 0);
 259         so_data  (so, screen->query->handle);
 260         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 261         so_data  (so, nvws->channel->vram->handle);
 262         so_data  (so, nvws->channel->vram->handle);
 263         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 264         so_data  (so, nvws->channel->vram->handle);
 265         so_data  (so, nvws->channel->vram->handle);
 266
 267         so_method(so, screen->curie, 0x1ea4, 3);
 268         so_data  (so, 0x00000010);
 269         so_data  (so, 0x01000100);
 270         so_data  (so, 0xff800006);
 271
 272         /* vtxprog output routing */
 273         so_method(so, screen->curie, 0x1fc4, 1);
 274         so_data  (so, 0x06144321);
 275         so_method(so, screen->curie, 0x1fc8, 2);
 276         so_data  (so, 0xedcba987);
 277         so_data  (so, 0x00000021);
 278         so_method(so, screen->curie, 0x1fd0, 1);
 279         so_data  (so, 0x00171615);
 280         so_method(so, screen->curie, 0x1fd4, 1);
 281         so_data  (so, 0x001b1a19);
 282
 283         so_method(so, screen->curie, 0x1ef8, 1);
 284         so_data  (so, 0x0020ffff);
 285         so_method(so, screen->curie, 0x1d64, 1);
 286         so_data  (so, 0x00d30000);
 287         so_method(so, screen->curie, 0x1e94, 1);
 288         so_data  (so, 0x00000001);
 289
 290         so_emit(nvws, so);
 291         so_ref(NULL, &so);
 292         nvws->push_flush(nvws, 0, NULL);
 293
 294         screen->pipe.winsys = ws;
 295         screen->pipe.destroy = nv40_screen_destroy;
 296
 297         screen->pipe.get_name = nv40_screen_get_name;
 298         screen->pipe.get_vendor = nv40_screen_get_vendor;
 299         screen->pipe.get_param = nv40_screen_get_param;
 300         screen->pipe.get_paramf = nv40_screen_get_paramf;
 301
 302         screen->pipe.is_format_supported = nv40_screen_surface_format_supported;
 303
 304         screen->pipe.surface_map = nv40_surface_map;
 305         screen->pipe.surface_unmap = nv40_surface_unmap;
 306
 307         nv40_screen_init_miptree_functions(&screen->pipe);
 308
 309         return &screen->pipe;
 310 }
 311