src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2
   3 #include "nv40_context.h"
   4 #include "nv40_screen.h"
   5
   6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
   9
  10 static int
  11 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  12 {
  13         struct nv40_screen *screen = nv40_screen(pscreen);
  14
  15         switch (param) {
  16         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  17                 return 16;
  18         case PIPE_CAP_NPOT_TEXTURES:
  19                 return 1;
  20         case PIPE_CAP_TWO_SIDED_STENCIL:
  21                 return 1;
  22         case PIPE_CAP_GLSL:
  23                 return 0;
  24         case PIPE_CAP_S3TC:
  25                 return 1;
  26         case PIPE_CAP_ANISOTROPIC_FILTER:
  27                 return 1;
  28         case PIPE_CAP_POINT_SPRITE:
  29                 return 1;
  30         case PIPE_CAP_MAX_RENDER_TARGETS:
  31                 return 4;
  32         case PIPE_CAP_OCCLUSION_QUERY:
  33                 return 1;
  34         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  35                 return 1;
  36         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  37                 return 13;
  38         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  39                 return 10;
  40         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  41                 return 13;
  42         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  43         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  44                 return 1;
  45         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  46                 return 0; /* We have 4 - but unsupported currently */
  47         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  48                 return 0;
  49         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  50                 return 1;
  51         case NOUVEAU_CAP_HW_VTXBUF:
  52                 return 1;
  53         case NOUVEAU_CAP_HW_IDXBUF:
  54                 if (screen->curie->grclass == NV40TCL)
  55                         return 1;
  56                 return 0;
  57         default:
  58                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  59                 return 0;
  60         }
  61 }
  62
  63 static float
  64 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  65 {
  66         switch (param) {
  67         case PIPE_CAP_MAX_LINE_WIDTH:
  68         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  69                 return 10.0;
  70         case PIPE_CAP_MAX_POINT_WIDTH:
  71         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  72                 return 64.0;
  73         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  74                 return 16.0;
  75         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  76                 return 16.0;
  77         default:
  78                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  79                 return 0.0;
  80         }
  81 }
  82
  83 static boolean
  84 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  85                                      enum pipe_format format,
  86                                      enum pipe_texture_target target,
  87                                      unsigned tex_usage, unsigned geom_flags)
  88 {
  89         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
  90                 switch (format) {
  91                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  92                 case PIPE_FORMAT_R5G6B5_UNORM:
  93                         return TRUE;
  94                 default:
  95                         break;
  96                 }
  97         } else
  98         if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
  99                 switch (format) {
 100                 case PIPE_FORMAT_Z24S8_UNORM:
 101                 case PIPE_FORMAT_Z24X8_UNORM:
 102                 case PIPE_FORMAT_Z16_UNORM:
 103                         return TRUE;
 104                 default:
 105                         break;
 106                 }
 107         } else {
 108                 switch (format) {
 109                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 110                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 111                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 112                 case PIPE_FORMAT_R5G6B5_UNORM:
 113                 case PIPE_FORMAT_R16_SNORM:
 114                 case PIPE_FORMAT_L8_UNORM:
 115                 case PIPE_FORMAT_A8_UNORM:
 116                 case PIPE_FORMAT_I8_UNORM:
 117                 case PIPE_FORMAT_A8L8_UNORM:
 118                 case PIPE_FORMAT_Z16_UNORM:
 119                 case PIPE_FORMAT_Z24S8_UNORM:
 120                 case PIPE_FORMAT_DXT1_RGB:
 121                 case PIPE_FORMAT_DXT1_RGBA:
 122                 case PIPE_FORMAT_DXT3_RGBA:
 123                 case PIPE_FORMAT_DXT5_RGBA:
 124                         return TRUE;
 125                 default:
 126                         break;
 127                 }
 128         }
 129
 130         return FALSE;
 131 }
 132
 133 static struct pipe_buffer *
 134 nv40_surface_buffer(struct pipe_surface *surf)
 135 {
 136         struct nv40_miptree *mt = (struct nv40_miptree *)surf->texture;
 137
 138         return mt->buffer;
 139 }
 140
 141 static void
 142 nv40_screen_destroy(struct pipe_screen *pscreen)
 143 {
 144         struct nv40_screen *screen = nv40_screen(pscreen);
 145
 146         nouveau_resource_free(&screen->vp_exec_heap);
 147         nouveau_resource_free(&screen->vp_data_heap);
 148         nouveau_resource_free(&screen->query_heap);
 149         nouveau_notifier_free(&screen->query);
 150         nouveau_notifier_free(&screen->sync);
 151         nouveau_grobj_free(&screen->curie);
 152
 153         nouveau_screen_fini(&screen->base);
 154
 155         FREE(pscreen);
 156 }
 157
 158 struct pipe_screen *
 159 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 160 {
 161         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 162         struct nouveau_channel *chan;
 163         struct pipe_screen *pscreen;
 164         struct nouveau_stateobj *so;
 165         unsigned curie_class = 0;
 166         int ret;
 167
 168         if (!screen)
 169                 return NULL;
 170         pscreen = &screen->base.base;
 171
 172         ret = nouveau_screen_init(&screen->base, dev);
 173         if (ret) {
 174                 nv40_screen_destroy(pscreen);
 175                 return NULL;
 176         }
 177         chan = screen->base.channel;
 178
 179         pscreen->winsys = ws;
 180         pscreen->destroy = nv40_screen_destroy;
 181         pscreen->get_param = nv40_screen_get_param;
 182         pscreen->get_paramf = nv40_screen_get_paramf;
 183         pscreen->is_format_supported = nv40_screen_surface_format_supported;
 184
 185         nv40_screen_init_miptree_functions(pscreen);
 186         nv40_screen_init_transfer_functions(pscreen);
 187
 188         /* 3D object */
 189         switch (dev->chipset & 0xf0) {
 190         case 0x40:
 191                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 192                         curie_class = NV40TCL;
 193                 else
 194                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 195                         curie_class = NV44TCL;
 196                 break;
 197         case 0x60:
 198                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 199                         curie_class = NV44TCL;
 200                 break;
 201         }
 202
 203         if (!curie_class) {
 204                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev->chipset);
 205                 return NULL;
 206         }
 207
 208         ret = nouveau_grobj_alloc(chan, 0xbeef3097, curie_class, &screen->curie);
 209         if (ret) {
 210                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 211                 return FALSE;
 212         }
 213         BIND_RING(chan, screen->curie, 7);
 214
 215         /* 2D engine setup */
 216         screen->eng2d = nv04_surface_2d_init(&screen->base);
 217         screen->eng2d->buf = nv40_surface_buffer;
 218
 219         /* Notifier for sync purposes */
 220         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 221         if (ret) {
 222                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 223                 nv40_screen_destroy(pscreen);
 224                 return NULL;
 225         }
 226
 227         /* Query objects */
 228         ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
 229         if (ret) {
 230                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 231                 nv40_screen_destroy(pscreen);
 232                 return NULL;
 233         }
 234
 235         nouveau_resource_init(&screen->query_heap, 0, 32);
 236         if (ret) {
 237                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 238                 nv40_screen_destroy(pscreen);
 239                 return NULL;
 240         }
 241
 242         /* Vtxprog resources */
 243         if (nouveau_resource_init(&screen->vp_exec_heap, 0, 512) ||
 244             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 245                 nv40_screen_destroy(pscreen);
 246                 return NULL;
 247         }
 248
 249         /* Static curie initialisation */
 250         so = so_new(128, 0);
 251         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 252         so_data  (so, screen->sync->handle);
 253         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 254         so_data  (so, chan->vram->handle);
 255         so_data  (so, chan->gart->handle);
 256         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 257         so_data  (so, chan->vram->handle);
 258         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 259         so_data  (so, chan->vram->handle);
 260         so_data  (so, chan->vram->handle);
 261         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 262         so_data  (so, chan->vram->handle);
 263         so_data  (so, chan->gart->handle);
 264         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 265         so_data  (so, 0);
 266         so_data  (so, screen->query->handle);
 267         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 268         so_data  (so, chan->vram->handle);
 269         so_data  (so, chan->vram->handle);
 270         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 271         so_data  (so, chan->vram->handle);
 272         so_data  (so, chan->vram->handle);
 273
 274         so_method(so, screen->curie, 0x1ea4, 3);
 275         so_data  (so, 0x00000010);
 276         so_data  (so, 0x01000100);
 277         so_data  (so, 0xff800006);
 278
 279         /* vtxprog output routing */
 280         so_method(so, screen->curie, 0x1fc4, 1);
 281         so_data  (so, 0x06144321);
 282         so_method(so, screen->curie, 0x1fc8, 2);
 283         so_data  (so, 0xedcba987);
 284         so_data  (so, 0x00000021);
 285         so_method(so, screen->curie, 0x1fd0, 1);
 286         so_data  (so, 0x00171615);
 287         so_method(so, screen->curie, 0x1fd4, 1);
 288         so_data  (so, 0x001b1a19);
 289
 290         so_method(so, screen->curie, 0x1ef8, 1);
 291         so_data  (so, 0x0020ffff);
 292         so_method(so, screen->curie, 0x1d64, 1);
 293         so_data  (so, 0x00d30000);
 294         so_method(so, screen->curie, 0x1e94, 1);
 295         so_data  (so, 0x00000001);
 296
 297         so_emit(chan, so);
 298         so_ref(NULL, &so);
 299         nouveau_pushbuf_flush(chan, 0);
 300
 301         return pscreen;
 302 }
 303