src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_util.h"
   3
   4 #include "nv40_context.h"
   5 #include "nv40_screen.h"
   6
   7 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   8 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   9 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  10
  11 static const char *
  12 nv40_screen_get_name(struct pipe_screen *pscreen)
  13 {
  14         struct nv40_screen *screen = nv40_screen(pscreen);
  15         static char buffer[128];
  16
  17         snprintf(buffer, sizeof(buffer), "NV%02X", screen->chipset);
  18         return buffer;
  19 }
  20
  21 static const char *
  22 nv40_screen_get_vendor(struct pipe_screen *pscreen)
  23 {
  24         return "nouveau";
  25 }
  26
  27 static int
  28 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  29 {
  30         switch (param) {
  31         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  32                 return 16;
  33         case PIPE_CAP_NPOT_TEXTURES:
  34                 return 1;
  35         case PIPE_CAP_TWO_SIDED_STENCIL:
  36                 return 1;
  37         case PIPE_CAP_GLSL:
  38                 return 0;
  39         case PIPE_CAP_S3TC:
  40                 return 0;
  41         case PIPE_CAP_ANISOTROPIC_FILTER:
  42                 return 1;
  43         case PIPE_CAP_POINT_SPRITE:
  44                 return 1;
  45         case PIPE_CAP_MAX_RENDER_TARGETS:
  46                 return 4;
  47         case PIPE_CAP_OCCLUSION_QUERY:
  48                 return 1;
  49         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  50                 return 1;
  51         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  52                 return 13;
  53         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  54                 return 10;
  55         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  56                 return 13;
  57         default:
  58                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  59                 return 0;
  60         }
  61 }
  62
  63 static float
  64 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  65 {
  66         switch (param) {
  67         case PIPE_CAP_MAX_LINE_WIDTH:
  68         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  69                 return 10.0;
  70         case PIPE_CAP_MAX_POINT_WIDTH:
  71         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  72                 return 64.0;
  73         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  74                 return 16.0;
  75         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  76                 return 16.0;
  77         case PIPE_CAP_BITMAP_TEXCOORD_BIAS:
  78                 return 0.0;
  79         default:
  80                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  81                 return 0.0;
  82         }
  83 }
  84
  85 static boolean
  86 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  87                                      enum pipe_format format, uint type)
  88 {
  89         switch (type) {
  90         case PIPE_SURFACE:
  91                 switch (format) {
  92                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  93                 case PIPE_FORMAT_R5G6B5_UNORM:
  94                 case PIPE_FORMAT_Z24S8_UNORM:
  95                 case PIPE_FORMAT_Z16_UNORM:
  96                         return TRUE;
  97                 default:
  98                         break;
  99                 }
 100                 break;
 101         case PIPE_TEXTURE:
 102                 switch (format) {
 103                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 104                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 105                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 106                 case PIPE_FORMAT_R5G6B5_UNORM:
 107                 case PIPE_FORMAT_U_L8:
 108                 case PIPE_FORMAT_U_A8:
 109                 case PIPE_FORMAT_U_I8:
 110                 case PIPE_FORMAT_U_A8_L8:
 111                 case PIPE_FORMAT_Z16_UNORM:
 112                 case PIPE_FORMAT_Z24S8_UNORM:
 113 #if 0 /* state tracker not up to the task just yet. */
 114                 case PIPE_FORMAT_DXT1_RGB:
 115                 case PIPE_FORMAT_DXT1_RGBA:
 116                 case PIPE_FORMAT_DXT3_RGBA:
 117                 case PIPE_FORMAT_DXT5_RGBA:
 118 #endif
 119                         return TRUE;
 120                 default:
 121                         break;
 122                 }
 123                 break;
 124         default:
 125                 assert(0);
 126         };
 127
 128         return FALSE;
 129 }
 130
 131 static void
 132 nv40_screen_destroy(struct pipe_screen *pscreen)
 133 {
 134         struct nv40_screen *screen = nv40_screen(pscreen);
 135         struct nouveau_winsys *nvws = screen->nvws;
 136
 137         nvws->res_free(&screen->vp_exec_heap);
 138         nvws->res_free(&screen->vp_data_heap);
 139         nvws->res_free(&screen->query_heap);
 140         nvws->notifier_free(&screen->query);
 141         nvws->notifier_free(&screen->sync);
 142         nvws->grobj_free(&screen->curie);
 143
 144         FREE(pscreen);
 145 }
 146
 147 struct pipe_screen *
 148 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws,
 149                    unsigned chipset)
 150 {
 151         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 152         struct nouveau_stateobj *so;
 153         unsigned curie_class;
 154         int ret;
 155
 156         if (!screen)
 157                 return NULL;
 158         screen->chipset = chipset;
 159         screen->nvws = nvws;
 160
 161         /* 3D object */
 162         switch (chipset & 0xf0) {
 163         case 0x40:
 164                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f)))
 165                         curie_class = NV40TCL;
 166                 else
 167                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 168                         curie_class = NV44TCL;
 169                 break;
 170         case 0x60:
 171                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 172                         curie_class = NV44TCL;
 173                 break;
 174         default:
 175                 break;
 176         }
 177
 178         if (!curie_class) {
 179                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", chipset);
 180                 return NULL;
 181         }
 182
 183         ret = nvws->grobj_alloc(nvws, curie_class, &screen->curie);
 184         if (ret) {
 185                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 186                 return FALSE;
 187         }
 188
 189         /* Notifier for sync purposes */
 190         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 191         if (ret) {
 192                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 193                 nv40_screen_destroy(&screen->pipe);
 194                 return NULL;
 195         }
 196
 197         /* Query objects */
 198         ret = nvws->notifier_alloc(nvws, 32, &screen->query);
 199         if (ret) {
 200                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 201                 nv40_screen_destroy(&screen->pipe);
 202                 return NULL;
 203         }
 204
 205         ret = nvws->res_init(&screen->query_heap, 0, 32);
 206         if (ret) {
 207                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 208                 nv40_screen_destroy(&screen->pipe);
 209                 return NULL;
 210         }
 211
 212         /* Vtxprog resources */
 213         if (nvws->res_init(&screen->vp_exec_heap, 0, 512) ||
 214             nvws->res_init(&screen->vp_data_heap, 0, 256)) {
 215                 nv40_screen_destroy(&screen->pipe);
 216                 return NULL;
 217         }
 218
 219         /* Static curie initialisation */
 220         so = so_new(128, 0);
 221         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 222         so_data  (so, screen->sync->handle);
 223         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 224         so_data  (so, nvws->channel->vram->handle);
 225         so_data  (so, nvws->channel->gart->handle);
 226         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 227         so_data  (so, nvws->channel->vram->handle);
 228         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 229         so_data  (so, nvws->channel->vram->handle);
 230         so_data  (so, nvws->channel->vram->handle);
 231         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 232         so_data  (so, nvws->channel->vram->handle);
 233         so_data  (so, nvws->channel->gart->handle);
 234         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 235         so_data  (so, 0);
 236         so_data  (so, screen->query->handle);
 237         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 238         so_data  (so, nvws->channel->vram->handle);
 239         so_data  (so, nvws->channel->vram->handle);
 240         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 241         so_data  (so, nvws->channel->vram->handle);
 242         so_data  (so, nvws->channel->vram->handle);
 243
 244         so_method(so, screen->curie, 0x1ea4, 3);
 245         so_data  (so, 0x00000010);
 246         so_data  (so, 0x01000100);
 247         so_data  (so, 0xff800006);
 248
 249         /* vtxprog output routing */
 250         so_method(so, screen->curie, 0x1fc4, 1);
 251         so_data  (so, 0x06144321);
 252         so_method(so, screen->curie, 0x1fc8, 2);
 253         so_data  (so, 0xedcba987);
 254         so_data  (so, 0x00000021);
 255         so_method(so, screen->curie, 0x1fd0, 1);
 256         so_data  (so, 0x00171615);
 257         so_method(so, screen->curie, 0x1fd4, 1);
 258         so_data  (so, 0x001b1a19);
 259
 260         so_method(so, screen->curie, 0x1ef8, 1);
 261         so_data  (so, 0x0020ffff);
 262         so_method(so, screen->curie, 0x1d64, 1);
 263         so_data  (so, 0x00d30000);
 264         so_method(so, screen->curie, 0x1e94, 1);
 265         so_data  (so, 0x00000001);
 266
 267         so_emit(nvws, so);
 268         so_ref(NULL, &so);
 269         nvws->push_flush(nvws, 0, NULL);
 270
 271         screen->pipe.winsys = ws;
 272         screen->pipe.destroy = nv40_screen_destroy;
 273
 274         screen->pipe.get_name = nv40_screen_get_name;
 275         screen->pipe.get_vendor = nv40_screen_get_vendor;
 276         screen->pipe.get_param = nv40_screen_get_param;
 277         screen->pipe.get_paramf = nv40_screen_get_paramf;
 278
 279         screen->pipe.is_format_supported = nv40_screen_surface_format_supported;
 280
 281         nv40_screen_init_miptree_functions(&screen->pipe);
 282
 283         return &screen->pipe;
 284 }
 285