src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2
   3 #include "nv40_context.h"
   4 #include "nv40_screen.h"
   5
   6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
   9
  10 static const char *
  11 nv40_screen_get_name(struct pipe_screen *pscreen)
  12 {
  13         struct nv40_screen *screen = nv40_screen(pscreen);
  14         struct nouveau_device *dev = screen->nvws->channel->device;
  15         static char buffer[128];
  16
  17         snprintf(buffer, sizeof(buffer), "NV%02X", dev->chipset);
  18         return buffer;
  19 }
  20
  21 static const char *
  22 nv40_screen_get_vendor(struct pipe_screen *pscreen)
  23 {
  24         return "nouveau";
  25 }
  26
  27 static int
  28 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  29 {
  30         struct nv40_screen *screen = nv40_screen(pscreen);
  31
  32         switch (param) {
  33         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  34                 return 16;
  35         case PIPE_CAP_NPOT_TEXTURES:
  36                 return 1;
  37         case PIPE_CAP_TWO_SIDED_STENCIL:
  38                 return 1;
  39         case PIPE_CAP_GLSL:
  40                 return 0;
  41         case PIPE_CAP_S3TC:
  42                 return 1;
  43         case PIPE_CAP_ANISOTROPIC_FILTER:
  44                 return 1;
  45         case PIPE_CAP_POINT_SPRITE:
  46                 return 1;
  47         case PIPE_CAP_MAX_RENDER_TARGETS:
  48                 return 4;
  49         case PIPE_CAP_OCCLUSION_QUERY:
  50                 return 1;
  51         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  52                 return 1;
  53         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  54                 return 13;
  55         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  56                 return 10;
  57         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  58                 return 13;
  59         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  60         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  61                 return 1;
  62         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  63                 return 0; /* We have 4 - but unsupported currently */
  64         case NOUVEAU_CAP_HW_VTXBUF:
  65                 return 1;
  66         case NOUVEAU_CAP_HW_IDXBUF:
  67                 if (screen->curie->grclass == NV40TCL)
  68                         return 1;
  69                 return 0;
  70         default:
  71                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  72                 return 0;
  73         }
  74 }
  75
  76 static float
  77 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  78 {
  79         switch (param) {
  80         case PIPE_CAP_MAX_LINE_WIDTH:
  81         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  82                 return 10.0;
  83         case PIPE_CAP_MAX_POINT_WIDTH:
  84         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  85                 return 64.0;
  86         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  87                 return 16.0;
  88         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  89                 return 16.0;
  90         default:
  91                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  92                 return 0.0;
  93         }
  94 }
  95
  96 static boolean
  97 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  98                                      enum pipe_format format,
  99                                      enum pipe_texture_target target,
 100                                      unsigned tex_usage, unsigned geom_flags)
 101 {
 102         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
 103                 switch (format) {
 104                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 105                 case PIPE_FORMAT_R5G6B5_UNORM:
 106                 case PIPE_FORMAT_Z24S8_UNORM:
 107                 case PIPE_FORMAT_Z16_UNORM:
 108                         return TRUE;
 109                 default:
 110                         break;
 111                 }
 112         } else {
 113                 switch (format) {
 114                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 115                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 116                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 117                 case PIPE_FORMAT_R5G6B5_UNORM:
 118                 case PIPE_FORMAT_R16_SNORM:
 119                 case PIPE_FORMAT_L8_UNORM:
 120                 case PIPE_FORMAT_A8_UNORM:
 121                 case PIPE_FORMAT_I8_UNORM:
 122                 case PIPE_FORMAT_A8L8_UNORM:
 123                 case PIPE_FORMAT_Z16_UNORM:
 124                 case PIPE_FORMAT_Z24S8_UNORM:
 125                 case PIPE_FORMAT_DXT1_RGB:
 126                 case PIPE_FORMAT_DXT1_RGBA:
 127                 case PIPE_FORMAT_DXT3_RGBA:
 128                 case PIPE_FORMAT_DXT5_RGBA:
 129                         return TRUE;
 130                 default:
 131                         break;
 132                 }
 133         }
 134
 135         return FALSE;
 136 }
 137
 138 static void *
 139 nv40_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
 140                  unsigned flags )
 141 {
 142         struct pipe_winsys      *ws = screen->winsys;
 143         struct pipe_surface     *surface_to_map;
 144         void                    *map;
 145
 146         if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
 147                 struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
 148
 149                 if (!mt->shadow_tex) {
 150                         unsigned old_tex_usage = surface->texture->tex_usage;
 151                         surface->texture->tex_usage = NOUVEAU_TEXTURE_USAGE_LINEAR |
 152                                                       PIPE_TEXTURE_USAGE_DYNAMIC;
 153                         mt->shadow_tex = screen->texture_create(screen, surface->texture);
 154                         surface->texture->tex_usage = old_tex_usage;
 155
 156                         assert(mt->shadow_tex->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR);
 157                         mt->shadow_surface = screen->get_tex_surface
 158                         (
 159                                 screen, mt->shadow_tex,
 160                                 surface->face, surface->level, surface->zslice,
 161                                 surface->usage
 162                         );
 163                 }
 164
 165                 surface_to_map = mt->shadow_surface;
 166         }
 167         else
 168                 surface_to_map = surface;
 169
 170         assert(surface_to_map);
 171
 172         map = ws->buffer_map(ws, surface_to_map->buffer, flags);
 173         if (!map)
 174                 return NULL;
 175
 176         return map + surface_to_map->offset;
 177 }
 178
 179 static void
 180 nv40_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
 181 {
 182         struct pipe_winsys      *ws = screen->winsys;
 183         struct pipe_surface     *surface_to_unmap;
 184
 185         /* TODO: Copy from shadow just before push buffer is flushed instead.
 186                  There are probably some programs that map/unmap excessively
 187                  before rendering. */
 188         if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
 189                 struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
 190
 191                 assert(mt->shadow_tex);
 192
 193                 surface_to_unmap = mt->shadow_surface;
 194         }
 195         else
 196                 surface_to_unmap = surface;
 197
 198         assert(surface_to_unmap);
 199
 200         ws->buffer_unmap(ws, surface_to_unmap->buffer);
 201
 202         if (surface_to_unmap != surface) {
 203                 struct nv40_screen *nvscreen = nv40_screen(screen);
 204
 205                 nvscreen->nvws->surface_copy(nvscreen->nvws,
 206                                              surface, 0, 0,
 207                                              surface_to_unmap, 0, 0,
 208                                              surface->width, surface->height);
 209         }
 210 }
 211
 212 static void
 213 nv40_screen_destroy(struct pipe_screen *pscreen)
 214 {
 215         struct nv40_screen *screen = nv40_screen(pscreen);
 216         struct nouveau_winsys *nvws = screen->nvws;
 217
 218         nvws->res_free(&screen->vp_exec_heap);
 219         nvws->res_free(&screen->vp_data_heap);
 220         nvws->res_free(&screen->query_heap);
 221         nvws->notifier_free(&screen->query);
 222         nvws->notifier_free(&screen->sync);
 223         nvws->grobj_free(&screen->curie);
 224
 225         FREE(pscreen);
 226 }
 227
 228 struct pipe_screen *
 229 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 230 {
 231         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 232         struct nouveau_stateobj *so;
 233         unsigned curie_class;
 234         unsigned chipset = nvws->channel->device->chipset;
 235         int ret;
 236
 237         if (!screen)
 238                 return NULL;
 239         screen->nvws = nvws;
 240
 241         /* 3D object */
 242         switch (chipset & 0xf0) {
 243         case 0x40:
 244                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f)))
 245                         curie_class = NV40TCL;
 246                 else
 247                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 248                         curie_class = NV44TCL;
 249                 break;
 250         case 0x60:
 251                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 252                         curie_class = NV44TCL;
 253                 break;
 254         default:
 255                 break;
 256         }
 257
 258         if (!curie_class) {
 259                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", chipset);
 260                 return NULL;
 261         }
 262
 263         ret = nvws->grobj_alloc(nvws, curie_class, &screen->curie);
 264         if (ret) {
 265                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 266                 return FALSE;
 267         }
 268
 269         /* Notifier for sync purposes */
 270         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 271         if (ret) {
 272                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 273                 nv40_screen_destroy(&screen->pipe);
 274                 return NULL;
 275         }
 276
 277         /* Query objects */
 278         ret = nvws->notifier_alloc(nvws, 32, &screen->query);
 279         if (ret) {
 280                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 281                 nv40_screen_destroy(&screen->pipe);
 282                 return NULL;
 283         }
 284
 285         ret = nvws->res_init(&screen->query_heap, 0, 32);
 286         if (ret) {
 287                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 288                 nv40_screen_destroy(&screen->pipe);
 289                 return NULL;
 290         }
 291
 292         /* Vtxprog resources */
 293         if (nvws->res_init(&screen->vp_exec_heap, 0, 512) ||
 294             nvws->res_init(&screen->vp_data_heap, 0, 256)) {
 295                 nv40_screen_destroy(&screen->pipe);
 296                 return NULL;
 297         }
 298
 299         /* Static curie initialisation */
 300         so = so_new(128, 0);
 301         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 302         so_data  (so, screen->sync->handle);
 303         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 304         so_data  (so, nvws->channel->vram->handle);
 305         so_data  (so, nvws->channel->gart->handle);
 306         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 307         so_data  (so, nvws->channel->vram->handle);
 308         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 309         so_data  (so, nvws->channel->vram->handle);
 310         so_data  (so, nvws->channel->vram->handle);
 311         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 312         so_data  (so, nvws->channel->vram->handle);
 313         so_data  (so, nvws->channel->gart->handle);
 314         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 315         so_data  (so, 0);
 316         so_data  (so, screen->query->handle);
 317         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 318         so_data  (so, nvws->channel->vram->handle);
 319         so_data  (so, nvws->channel->vram->handle);
 320         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 321         so_data  (so, nvws->channel->vram->handle);
 322         so_data  (so, nvws->channel->vram->handle);
 323
 324         so_method(so, screen->curie, 0x1ea4, 3);
 325         so_data  (so, 0x00000010);
 326         so_data  (so, 0x01000100);
 327         so_data  (so, 0xff800006);
 328
 329         /* vtxprog output routing */
 330         so_method(so, screen->curie, 0x1fc4, 1);
 331         so_data  (so, 0x06144321);
 332         so_method(so, screen->curie, 0x1fc8, 2);
 333         so_data  (so, 0xedcba987);
 334         so_data  (so, 0x00000021);
 335         so_method(so, screen->curie, 0x1fd0, 1);
 336         so_data  (so, 0x00171615);
 337         so_method(so, screen->curie, 0x1fd4, 1);
 338         so_data  (so, 0x001b1a19);
 339
 340         so_method(so, screen->curie, 0x1ef8, 1);
 341         so_data  (so, 0x0020ffff);
 342         so_method(so, screen->curie, 0x1d64, 1);
 343         so_data  (so, 0x00d30000);
 344         so_method(so, screen->curie, 0x1e94, 1);
 345         so_data  (so, 0x00000001);
 346
 347         so_emit(nvws, so);
 348         so_ref(NULL, &so);
 349         nvws->push_flush(nvws, 0, NULL);
 350
 351         screen->pipe.winsys = ws;
 352         screen->pipe.destroy = nv40_screen_destroy;
 353
 354         screen->pipe.get_name = nv40_screen_get_name;
 355         screen->pipe.get_vendor = nv40_screen_get_vendor;
 356         screen->pipe.get_param = nv40_screen_get_param;
 357         screen->pipe.get_paramf = nv40_screen_get_paramf;
 358
 359         screen->pipe.is_format_supported = nv40_screen_surface_format_supported;
 360
 361         screen->pipe.surface_map = nv40_surface_map;
 362         screen->pipe.surface_unmap = nv40_surface_unmap;
 363
 364         nv40_screen_init_miptree_functions(&screen->pipe);
 365
 366         return &screen->pipe;
 367 }
 368