src/gallium/drivers/nv40/nv40_state_fb.c

   1 #include "nv40_context.h"
   2 #include "nouveau/nouveau_util.h"
   3
   4 static struct pipe_buffer *
   5 nv40_do_surface_buffer(struct pipe_surface *surface)
   6 {
   7         struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
   8         return mt->buffer;
   9 }
  10
  11 #define nv40_surface_buffer(ps) nouveau_bo(nv40_do_surface_buffer(ps))
  12
  13 static boolean
  14 nv40_state_framebuffer_validate(struct nv40_context *nv40)
  15 {
  16         struct nouveau_channel *chan = nv40->screen->base.channel;
  17         struct nouveau_grobj *curie = nv40->screen->curie;
  18         struct pipe_framebuffer_state *fb = &nv40->framebuffer;
  19         struct nv04_surface *rt[4], *zeta;
  20         uint32_t rt_enable, rt_format;
  21         int i, colour_format = 0, zeta_format = 0;
  22         struct nouveau_stateobj *so = so_new(64, 10);
  23         unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
  24         unsigned w = fb->width;
  25         unsigned h = fb->height;
  26
  27         rt_enable = 0;
  28         for (i = 0; i < fb->nr_cbufs; i++) {
  29                 if (colour_format) {
  30                         assert(colour_format == fb->cbufs[i]->format);
  31                 } else {
  32                         colour_format = fb->cbufs[i]->format;
  33                         rt_enable |= (NV40TCL_RT_ENABLE_COLOR0 << i);
  34                         rt[i] = (struct nv04_surface *)fb->cbufs[i];
  35                 }
  36         }
  37
  38         if (rt_enable & (NV40TCL_RT_ENABLE_COLOR1 | NV40TCL_RT_ENABLE_COLOR2 |
  39                          NV40TCL_RT_ENABLE_COLOR3))
  40                 rt_enable |= NV40TCL_RT_ENABLE_MRT;
  41
  42         if (fb->zsbuf) {
  43                 zeta_format = fb->zsbuf->format;
  44                 zeta = (struct nv04_surface *)fb->zsbuf;
  45         }
  46
  47         if (!(rt[0]->base.texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
  48                 assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
  49                 for (i = 1; i < fb->nr_cbufs; i++)
  50                         assert(!(rt[i]->base.texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR));
  51
  52                 rt_format = NV40TCL_RT_FORMAT_TYPE_SWIZZLED |
  53                             log2i(fb->width) << NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT |
  54                             log2i(fb->height) << NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT;
  55         }
  56         else
  57                 rt_format = NV40TCL_RT_FORMAT_TYPE_LINEAR;
  58
  59         switch (colour_format) {
  60         case PIPE_FORMAT_A8R8G8B8_UNORM:
  61         case 0:
  62                 rt_format |= NV40TCL_RT_FORMAT_COLOR_A8R8G8B8;
  63                 break;
  64         case PIPE_FORMAT_R5G6B5_UNORM:
  65                 rt_format |= NV40TCL_RT_FORMAT_COLOR_R5G6B5;
  66                 break;
  67         default:
  68                 assert(0);
  69         }
  70
  71         switch (zeta_format) {
  72         case PIPE_FORMAT_Z16_UNORM:
  73                 rt_format |= NV40TCL_RT_FORMAT_ZETA_Z16;
  74                 break;
  75         case PIPE_FORMAT_Z24S8_UNORM:
  76         case 0:
  77                 rt_format |= NV40TCL_RT_FORMAT_ZETA_Z24S8;
  78                 break;
  79         default:
  80                 assert(0);
  81         }
  82
  83         if (rt_enable & NV40TCL_RT_ENABLE_COLOR0) {
  84                 so_method(so, curie, NV40TCL_DMA_COLOR0, 1);
  85                 so_reloc (so, nv40_surface_buffer(&rt[0]->base), 0,
  86                               rt_flags | NOUVEAU_BO_OR,
  87                               chan->vram->handle, chan->gart->handle);
  88                 so_method(so, curie, NV40TCL_COLOR0_PITCH, 2);
  89                 so_data  (so, rt[0]->pitch);
  90                 so_reloc (so, nv40_surface_buffer(&rt[0]->base),
  91                               rt[0]->base.offset, rt_flags | NOUVEAU_BO_LOW,
  92                               0, 0);
  93         }
  94
  95         if (rt_enable & NV40TCL_RT_ENABLE_COLOR1) {
  96                 so_method(so, curie, NV40TCL_DMA_COLOR1, 1);
  97                 so_reloc (so, nv40_surface_buffer(&rt[1]->base), 0,
  98                               rt_flags | NOUVEAU_BO_OR,
  99                               chan->vram->handle, chan->gart->handle);
 100                 so_method(so, curie, NV40TCL_COLOR1_OFFSET, 2);
 101                 so_reloc (so, nv40_surface_buffer(&rt[1]->base),
 102                               rt[1]->base.offset, rt_flags | NOUVEAU_BO_LOW,
 103                               0, 0);
 104                 so_data  (so, rt[1]->pitch);
 105         }
 106
 107         if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) {
 108                 so_method(so, curie, NV40TCL_DMA_COLOR2, 1);
 109                 so_reloc (so, nv40_surface_buffer(&rt[2]->base), 0,
 110                               rt_flags | NOUVEAU_BO_OR,
 111                               chan->vram->handle, chan->gart->handle);
 112                 so_method(so, curie, NV40TCL_COLOR2_OFFSET, 1);
 113                 so_reloc (so, nv40_surface_buffer(&rt[2]->base),
 114                               rt[2]->base.offset, rt_flags | NOUVEAU_BO_LOW,
 115                               0, 0);
 116                 so_method(so, curie, NV40TCL_COLOR2_PITCH, 1);
 117                 so_data  (so, rt[2]->pitch);
 118         }
 119
 120         if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) {
 121                 so_method(so, curie, NV40TCL_DMA_COLOR3, 1);
 122                 so_reloc (so, nv40_surface_buffer(&rt[3]->base), 0,
 123                               rt_flags | NOUVEAU_BO_OR,
 124                               chan->vram->handle, chan->gart->handle);
 125                 so_method(so, curie, NV40TCL_COLOR3_OFFSET, 1);
 126                 so_reloc (so, nv40_surface_buffer(&rt[3]->base),
 127                               rt[3]->base.offset, rt_flags | NOUVEAU_BO_LOW,
 128                               0, 0);
 129                 so_method(so, curie, NV40TCL_COLOR3_PITCH, 1);
 130                 so_data  (so, rt[3]->pitch);
 131         }
 132
 133         if (zeta_format) {
 134                 so_method(so, curie, NV40TCL_DMA_ZETA, 1);
 135                 so_reloc (so, nv40_surface_buffer(&zeta->base), 0,
 136                               rt_flags | NOUVEAU_BO_OR,
 137                               chan->vram->handle, chan->gart->handle);
 138                 so_method(so, curie, NV40TCL_ZETA_OFFSET, 1);
 139                 so_reloc (so, nv40_surface_buffer(&zeta->base),
 140                               zeta->base.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0);
 141                 so_method(so, curie, NV40TCL_ZETA_PITCH, 1);
 142                 so_data  (so, zeta->pitch);
 143         }
 144
 145         so_method(so, curie, NV40TCL_RT_ENABLE, 1);
 146         so_data  (so, rt_enable);
 147         so_method(so, curie, NV40TCL_RT_HORIZ, 3);
 148         so_data  (so, (w << 16) | 0);
 149         so_data  (so, (h << 16) | 0);
 150         so_data  (so, rt_format);
 151         so_method(so, curie, NV40TCL_VIEWPORT_HORIZ, 2);
 152         so_data  (so, (w << 16) | 0);
 153         so_data  (so, (h << 16) | 0);
 154         so_method(so, curie, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2);
 155         so_data  (so, ((w - 1) << 16) | 0);
 156         so_data  (so, ((h - 1) << 16) | 0);
 157         so_method(so, curie, 0x1d88, 1);
 158         so_data  (so, (1 << 12) | h);
 159
 160         so_ref(so, &nv40->state.hw[NV40_STATE_FB]);
 161         so_ref(NULL, &so);
 162         return TRUE;
 163 }
 164
 165 struct nv40_state_entry nv40_state_framebuffer = {
 166         .validate = nv40_state_framebuffer_validate,
 167         .dirty = {
 168                 .pipe = NV40_NEW_FB,
 169                 .hw = NV40_STATE_FB
 170         }
 171 };