src/gallium/drivers/nv40/nv40_state_fb.c

   1 #include "nv40_context.h"
   2 #include "nouveau/nouveau_util.h"
   3
   4 static struct pipe_buffer *
   5 nv40_surface_buffer(struct pipe_surface *surface)
   6 {
   7         struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
   8         return mt->buffer;
   9 }
  10
  11 static boolean
  12 nv40_state_framebuffer_validate(struct nv40_context *nv40)
  13 {
  14         struct pipe_framebuffer_state *fb = &nv40->framebuffer;
  15         struct pipe_surface *rt[4], *zeta;
  16         uint32_t rt_enable, rt_format;
  17         int i, colour_format = 0, zeta_format = 0;
  18         struct nouveau_stateobj *so = so_new(64, 10);
  19         unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
  20         unsigned w = fb->width;
  21         unsigned h = fb->height;
  22
  23         rt_enable = 0;
  24         for (i = 0; i < fb->nr_cbufs; i++) {
  25                 if (colour_format) {
  26                         assert(colour_format == fb->cbufs[i]->format);
  27                 } else {
  28                         colour_format = fb->cbufs[i]->format;
  29                         rt_enable |= (NV40TCL_RT_ENABLE_COLOR0 << i);
  30                         rt[i] = fb->cbufs[i];
  31                 }
  32         }
  33
  34         if (rt_enable & (NV40TCL_RT_ENABLE_COLOR1 | NV40TCL_RT_ENABLE_COLOR2 |
  35                          NV40TCL_RT_ENABLE_COLOR3))
  36                 rt_enable |= NV40TCL_RT_ENABLE_MRT;
  37
  38         if (fb->zsbuf) {
  39                 zeta_format = fb->zsbuf->format;
  40                 zeta = fb->zsbuf;
  41         }
  42
  43         if (!(rt[0]->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
  44                 assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
  45                 for (i = 1; i < fb->nr_cbufs; i++)
  46                         assert(!(rt[i]->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR));
  47
  48                 rt_format = NV40TCL_RT_FORMAT_TYPE_SWIZZLED |
  49                             log2i(fb->width) << NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT |
  50                             log2i(fb->height) << NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT;
  51         }
  52         else
  53                 rt_format = NV40TCL_RT_FORMAT_TYPE_LINEAR;
  54
  55         switch (colour_format) {
  56         case PIPE_FORMAT_A8R8G8B8_UNORM:
  57         case 0:
  58                 rt_format |= NV40TCL_RT_FORMAT_COLOR_A8R8G8B8;
  59                 break;
  60         case PIPE_FORMAT_R5G6B5_UNORM:
  61                 rt_format |= NV40TCL_RT_FORMAT_COLOR_R5G6B5;
  62                 break;
  63         default:
  64                 assert(0);
  65         }
  66
  67         switch (zeta_format) {
  68         case PIPE_FORMAT_Z16_UNORM:
  69                 rt_format |= NV40TCL_RT_FORMAT_ZETA_Z16;
  70                 break;
  71         case PIPE_FORMAT_Z24S8_UNORM:
  72         case 0:
  73                 rt_format |= NV40TCL_RT_FORMAT_ZETA_Z24S8;
  74                 break;
  75         default:
  76                 assert(0);
  77         }
  78
  79         if (rt_enable & NV40TCL_RT_ENABLE_COLOR0) {
  80                 so_method(so, nv40->screen->curie, NV40TCL_DMA_COLOR0, 1);
  81                 so_reloc (so, nv40_surface_buffer(rt[0]), 0, rt_flags | NOUVEAU_BO_OR,
  82                           nv40->nvws->channel->vram->handle,
  83                           nv40->nvws->channel->gart->handle);
  84                 so_method(so, nv40->screen->curie, NV40TCL_COLOR0_PITCH, 2);
  85                 so_data  (so, rt[0]->stride);
  86                 so_reloc (so, nv40_surface_buffer(rt[0]), rt[0]->offset, rt_flags |
  87                           NOUVEAU_BO_LOW, 0, 0);
  88         }
  89
  90         if (rt_enable & NV40TCL_RT_ENABLE_COLOR1) {
  91                 so_method(so, nv40->screen->curie, NV40TCL_DMA_COLOR1, 1);
  92                 so_reloc (so, nv40_surface_buffer(rt[1]), 0, rt_flags | NOUVEAU_BO_OR,
  93                           nv40->nvws->channel->vram->handle,
  94                           nv40->nvws->channel->gart->handle);
  95                 so_method(so, nv40->screen->curie, NV40TCL_COLOR1_OFFSET, 2);
  96                 so_reloc (so, nv40_surface_buffer(rt[1]), rt[1]->offset, rt_flags |
  97                           NOUVEAU_BO_LOW, 0, 0);
  98                 so_data  (so, rt[1]->stride);
  99         }
 100
 101         if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) {
 102                 so_method(so, nv40->screen->curie, NV40TCL_DMA_COLOR2, 1);
 103                 so_reloc (so, nv40_surface_buffer(rt[2]), 0, rt_flags | NOUVEAU_BO_OR,
 104                           nv40->nvws->channel->vram->handle,
 105                           nv40->nvws->channel->gart->handle);
 106                 so_method(so, nv40->screen->curie, NV40TCL_COLOR2_OFFSET, 1);
 107                 so_reloc (so, nv40_surface_buffer(rt[2]), rt[2]->offset, rt_flags |
 108                           NOUVEAU_BO_LOW, 0, 0);
 109                 so_method(so, nv40->screen->curie, NV40TCL_COLOR2_PITCH, 1);
 110                 so_data  (so, rt[2]->stride);
 111         }
 112
 113         if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) {
 114                 so_method(so, nv40->screen->curie, NV40TCL_DMA_COLOR3, 1);
 115                 so_reloc (so, nv40_surface_buffer(rt[3]), 0, rt_flags | NOUVEAU_BO_OR,
 116                           nv40->nvws->channel->vram->handle,
 117                           nv40->nvws->channel->gart->handle);
 118                 so_method(so, nv40->screen->curie, NV40TCL_COLOR3_OFFSET, 1);
 119                 so_reloc (so, nv40_surface_buffer(rt[3]), rt[3]->offset, rt_flags |
 120                           NOUVEAU_BO_LOW, 0, 0);
 121                 so_method(so, nv40->screen->curie, NV40TCL_COLOR3_PITCH, 1);
 122                 so_data  (so, rt[3]->stride);
 123         }
 124
 125         if (zeta_format) {
 126                 so_method(so, nv40->screen->curie, NV40TCL_DMA_ZETA, 1);
 127                 so_reloc (so, nv40_surface_buffer(zeta), 0, rt_flags | NOUVEAU_BO_OR,
 128                           nv40->nvws->channel->vram->handle,
 129                           nv40->nvws->channel->gart->handle);
 130                 so_method(so, nv40->screen->curie, NV40TCL_ZETA_OFFSET, 1);
 131                 so_reloc (so, nv40_surface_buffer(zeta), zeta->offset, rt_flags |
 132                           NOUVEAU_BO_LOW, 0, 0);
 133                 so_method(so, nv40->screen->curie, NV40TCL_ZETA_PITCH, 1);
 134                 so_data  (so, zeta->stride);
 135         }
 136
 137         so_method(so, nv40->screen->curie, NV40TCL_RT_ENABLE, 1);
 138         so_data  (so, rt_enable);
 139         so_method(so, nv40->screen->curie, NV40TCL_RT_HORIZ, 3);
 140         so_data  (so, (w << 16) | 0);
 141         so_data  (so, (h << 16) | 0);
 142         so_data  (so, rt_format);
 143         so_method(so, nv40->screen->curie, NV40TCL_VIEWPORT_HORIZ, 2);
 144         so_data  (so, (w << 16) | 0);
 145         so_data  (so, (h << 16) | 0);
 146         so_method(so, nv40->screen->curie, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2);
 147         so_data  (so, ((w - 1) << 16) | 0);
 148         so_data  (so, ((h - 1) << 16) | 0);
 149         so_method(so, nv40->screen->curie, 0x1d88, 1);
 150         so_data  (so, (1 << 12) | h);
 151
 152         so_ref(so, &nv40->state.hw[NV40_STATE_FB]);
 153         return TRUE;
 154 }
 155
 156 struct nv40_state_entry nv40_state_framebuffer = {
 157         .validate = nv40_state_framebuffer_validate,
 158         .dirty = {
 159                 .pipe = NV40_NEW_FB,
 160                 .hw = NV40_STATE_FB
 161         }
 162 };