1 #include "nv40_context.h"
2 #include "nouveau/nouveau_util.h"
4 static struct pipe_buffer
*
5 nv40_do_surface_buffer(struct pipe_surface
*surface
)
7 struct nv40_miptree
*mt
= (struct nv40_miptree
*)surface
->texture
;
11 #define nv40_surface_buffer(ps) nouveau_bo(nv40_do_surface_buffer(ps))
14 nv40_state_framebuffer_validate(struct nv40_context
*nv40
)
16 struct nouveau_channel
*chan
= nv40
->screen
->base
.channel
;
17 struct nouveau_grobj
*curie
= nv40
->screen
->curie
;
18 struct pipe_framebuffer_state
*fb
= &nv40
->framebuffer
;
19 struct nv04_surface
*rt
[4], *zeta
;
20 uint32_t rt_enable
, rt_format
;
21 int i
, colour_format
= 0, zeta_format
= 0;
22 struct nouveau_stateobj
*so
= so_new(64, 10);
23 unsigned rt_flags
= NOUVEAU_BO_RDWR
| NOUVEAU_BO_VRAM
;
24 unsigned w
= fb
->width
;
25 unsigned h
= fb
->height
;
28 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
30 assert(colour_format
== fb
->cbufs
[i
]->format
);
32 colour_format
= fb
->cbufs
[i
]->format
;
33 rt_enable
|= (NV40TCL_RT_ENABLE_COLOR0
<< i
);
34 rt
[i
] = (struct nv04_surface
*)fb
->cbufs
[i
];
38 if (rt_enable
& (NV40TCL_RT_ENABLE_COLOR1
| NV40TCL_RT_ENABLE_COLOR2
|
39 NV40TCL_RT_ENABLE_COLOR3
))
40 rt_enable
|= NV40TCL_RT_ENABLE_MRT
;
43 zeta_format
= fb
->zsbuf
->format
;
44 zeta
= (struct nv04_surface
*)fb
->zsbuf
;
47 if (!(rt
[0]->base
.texture
->tex_usage
& NOUVEAU_TEXTURE_USAGE_LINEAR
)) {
48 assert(!(fb
->width
& (fb
->width
- 1)) && !(fb
->height
& (fb
->height
- 1)));
49 for (i
= 1; i
< fb
->nr_cbufs
; i
++)
50 assert(!(rt
[i
]->base
.texture
->tex_usage
& NOUVEAU_TEXTURE_USAGE_LINEAR
));
52 rt_format
= NV40TCL_RT_FORMAT_TYPE_SWIZZLED
|
53 log2i(fb
->width
) << NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT
|
54 log2i(fb
->height
) << NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT
;
57 rt_format
= NV40TCL_RT_FORMAT_TYPE_LINEAR
;
59 switch (colour_format
) {
60 case PIPE_FORMAT_A8R8G8B8_UNORM
:
62 rt_format
|= NV40TCL_RT_FORMAT_COLOR_A8R8G8B8
;
64 case PIPE_FORMAT_R5G6B5_UNORM
:
65 rt_format
|= NV40TCL_RT_FORMAT_COLOR_R5G6B5
;
71 switch (zeta_format
) {
72 case PIPE_FORMAT_Z16_UNORM
:
73 rt_format
|= NV40TCL_RT_FORMAT_ZETA_Z16
;
75 case PIPE_FORMAT_Z24S8_UNORM
:
76 case PIPE_FORMAT_Z24X8_UNORM
:
78 rt_format
|= NV40TCL_RT_FORMAT_ZETA_Z24S8
;
84 if (rt_enable
& NV40TCL_RT_ENABLE_COLOR0
) {
85 so_method(so
, curie
, NV40TCL_DMA_COLOR0
, 1);
86 so_reloc (so
, nv40_surface_buffer(&rt
[0]->base
), 0,
87 rt_flags
| NOUVEAU_BO_OR
,
88 chan
->vram
->handle
, chan
->gart
->handle
);
89 so_method(so
, curie
, NV40TCL_COLOR0_PITCH
, 2);
90 so_data (so
, rt
[0]->pitch
);
91 so_reloc (so
, nv40_surface_buffer(&rt
[0]->base
),
92 rt
[0]->base
.offset
, rt_flags
| NOUVEAU_BO_LOW
,
96 if (rt_enable
& NV40TCL_RT_ENABLE_COLOR1
) {
97 so_method(so
, curie
, NV40TCL_DMA_COLOR1
, 1);
98 so_reloc (so
, nv40_surface_buffer(&rt
[1]->base
), 0,
99 rt_flags
| NOUVEAU_BO_OR
,
100 chan
->vram
->handle
, chan
->gart
->handle
);
101 so_method(so
, curie
, NV40TCL_COLOR1_OFFSET
, 2);
102 so_reloc (so
, nv40_surface_buffer(&rt
[1]->base
),
103 rt
[1]->base
.offset
, rt_flags
| NOUVEAU_BO_LOW
,
105 so_data (so
, rt
[1]->pitch
);
108 if (rt_enable
& NV40TCL_RT_ENABLE_COLOR2
) {
109 so_method(so
, curie
, NV40TCL_DMA_COLOR2
, 1);
110 so_reloc (so
, nv40_surface_buffer(&rt
[2]->base
), 0,
111 rt_flags
| NOUVEAU_BO_OR
,
112 chan
->vram
->handle
, chan
->gart
->handle
);
113 so_method(so
, curie
, NV40TCL_COLOR2_OFFSET
, 1);
114 so_reloc (so
, nv40_surface_buffer(&rt
[2]->base
),
115 rt
[2]->base
.offset
, rt_flags
| NOUVEAU_BO_LOW
,
117 so_method(so
, curie
, NV40TCL_COLOR2_PITCH
, 1);
118 so_data (so
, rt
[2]->pitch
);
121 if (rt_enable
& NV40TCL_RT_ENABLE_COLOR3
) {
122 so_method(so
, curie
, NV40TCL_DMA_COLOR3
, 1);
123 so_reloc (so
, nv40_surface_buffer(&rt
[3]->base
), 0,
124 rt_flags
| NOUVEAU_BO_OR
,
125 chan
->vram
->handle
, chan
->gart
->handle
);
126 so_method(so
, curie
, NV40TCL_COLOR3_OFFSET
, 1);
127 so_reloc (so
, nv40_surface_buffer(&rt
[3]->base
),
128 rt
[3]->base
.offset
, rt_flags
| NOUVEAU_BO_LOW
,
130 so_method(so
, curie
, NV40TCL_COLOR3_PITCH
, 1);
131 so_data (so
, rt
[3]->pitch
);
135 so_method(so
, curie
, NV40TCL_DMA_ZETA
, 1);
136 so_reloc (so
, nv40_surface_buffer(&zeta
->base
), 0,
137 rt_flags
| NOUVEAU_BO_OR
,
138 chan
->vram
->handle
, chan
->gart
->handle
);
139 so_method(so
, curie
, NV40TCL_ZETA_OFFSET
, 1);
140 so_reloc (so
, nv40_surface_buffer(&zeta
->base
),
141 zeta
->base
.offset
, rt_flags
| NOUVEAU_BO_LOW
, 0, 0);
142 so_method(so
, curie
, NV40TCL_ZETA_PITCH
, 1);
143 so_data (so
, zeta
->pitch
);
146 so_method(so
, curie
, NV40TCL_RT_ENABLE
, 1);
147 so_data (so
, rt_enable
);
148 so_method(so
, curie
, NV40TCL_RT_HORIZ
, 3);
149 so_data (so
, (w
<< 16) | 0);
150 so_data (so
, (h
<< 16) | 0);
151 so_data (so
, rt_format
);
152 so_method(so
, curie
, NV40TCL_VIEWPORT_HORIZ
, 2);
153 so_data (so
, (w
<< 16) | 0);
154 so_data (so
, (h
<< 16) | 0);
155 so_method(so
, curie
, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2);
156 so_data (so
, ((w
- 1) << 16) | 0);
157 so_data (so
, ((h
- 1) << 16) | 0);
158 so_method(so
, curie
, 0x1d88, 1);
159 so_data (so
, (1 << 12) | h
);
161 so_ref(so
, &nv40
->state
.hw
[NV40_STATE_FB
]);
166 struct nv40_state_entry nv40_state_framebuffer
= {
167 .validate
= nv40_state_framebuffer_validate
,