src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nv50_context.h"
  27 #include "nv50_screen.h"
  28 #include "nv50_resource.h"
  29
  30 #include "nouveau/nouveau_stateobj.h"
  31
  32 static boolean
  33 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  34                                 enum pipe_format format,
  35                                 enum pipe_texture_target target,
  36                                 unsigned sample_count,
  37                                 unsigned tex_usage, unsigned geom_flags)
  38 {
  39         if (sample_count > 1)
  40                 return FALSE;
  41
  42         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
  43                 switch (format) {
  44                 case PIPE_FORMAT_B8G8R8X8_UNORM:
  45                 case PIPE_FORMAT_B8G8R8A8_UNORM:
  46                 case PIPE_FORMAT_B5G6R5_UNORM:
  47                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  48                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  49                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  50                 case PIPE_FORMAT_R16G16_SNORM:
  51                 case PIPE_FORMAT_R16G16_UNORM:
  52                         return TRUE;
  53                 default:
  54                         break;
  55                 }
  56         } else
  57         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
  58                 switch (format) {
  59                 case PIPE_FORMAT_Z32_FLOAT:
  60                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
  61                 case PIPE_FORMAT_Z24X8_UNORM:
  62                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
  63                         return TRUE;
  64                 default:
  65                         break;
  66                 }
  67         } else {
  68                 if (tex_usage & PIPE_BIND_SAMPLER_VIEW) {
  69                         switch (format) {
  70                         case PIPE_FORMAT_DXT1_RGB:
  71                         case PIPE_FORMAT_DXT1_RGBA:
  72                         case PIPE_FORMAT_DXT3_RGBA:
  73                         case PIPE_FORMAT_DXT5_RGBA:
  74                                 return util_format_s3tc_enabled;
  75                         default:
  76                                 break;
  77                         }
  78                 }
  79                 switch (format) {
  80                 case PIPE_FORMAT_B8G8R8A8_UNORM:
  81                 case PIPE_FORMAT_B8G8R8X8_UNORM:
  82                 case PIPE_FORMAT_B8G8R8A8_SRGB:
  83                 case PIPE_FORMAT_B8G8R8X8_SRGB:
  84                 case PIPE_FORMAT_B5G5R5A1_UNORM:
  85                 case PIPE_FORMAT_B4G4R4A4_UNORM:
  86                 case PIPE_FORMAT_B5G6R5_UNORM:
  87                 case PIPE_FORMAT_L8_UNORM:
  88                 case PIPE_FORMAT_A8_UNORM:
  89                 case PIPE_FORMAT_I8_UNORM:
  90                 case PIPE_FORMAT_L8A8_UNORM:
  91                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
  92                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
  93                 case PIPE_FORMAT_Z32_FLOAT:
  94                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  95                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  96                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  97                 case PIPE_FORMAT_R16G16_SNORM:
  98                 case PIPE_FORMAT_R16G16_UNORM:
  99                         return TRUE;
 100                 default:
 101                         break;
 102                 }
 103         }
 104
 105         return FALSE;
 106 }
 107
 108 static int
 109 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 110 {
 111         switch (param) {
 112         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 113                 return 32;
 114         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 115                 return 32;
 116         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 117                 return 64;
 118         case PIPE_CAP_NPOT_TEXTURES:
 119                 return 1;
 120         case PIPE_CAP_TWO_SIDED_STENCIL:
 121                 return 1;
 122         case PIPE_CAP_GLSL:
 123                 return 1;
 124         case PIPE_CAP_ANISOTROPIC_FILTER:
 125                 return 1;
 126         case PIPE_CAP_POINT_SPRITE:
 127                 return 1;
 128         case PIPE_CAP_MAX_RENDER_TARGETS:
 129                 return 8;
 130         case PIPE_CAP_OCCLUSION_QUERY:
 131                 return 1;
 132         case PIPE_CAP_TIMER_QUERY:
 133                 return 0;
 134         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 135                 return 1;
 136         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 137                 return 13;
 138         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 139                 return 10;
 140         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 141                 return 13;
 142         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 143         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
 144                 return 1;
 145         case PIPE_CAP_TGSI_CONT_SUPPORTED:
 146                 return 1;
 147         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 148                 return 1;
 149         case PIPE_CAP_INDEP_BLEND_ENABLE:
 150                 return 1;
 151         case PIPE_CAP_INDEP_BLEND_FUNC:
 152                 return 0;
 153         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 154         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 155                 return 1;
 156         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 157         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 158                 return 0;
 159         case PIPE_CAP_MAX_VS_INSTRUCTIONS:
 160         case PIPE_CAP_MAX_FS_INSTRUCTIONS:
 161         case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS:
 162         case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS:
 163         case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS:
 164         case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS:
 165         case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS:
 166         case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: /* arbitrary limit */
 167                 return 16384;
 168         case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH:
 169         case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: /* need stack bo */
 170                 return 4;
 171         case PIPE_CAP_MAX_VS_INPUTS:
 172                 return 16;
 173         case PIPE_CAP_MAX_FS_INPUTS: /* 128 / 4 with GP */
 174                 return 64 / 4;
 175         case PIPE_CAP_MAX_VS_CONSTS:
 176         case PIPE_CAP_MAX_FS_CONSTS:
 177                 return 65536 / 16;
 178         case PIPE_CAP_MAX_VS_ADDRS:
 179         case PIPE_CAP_MAX_FS_ADDRS: /* no spilling atm */
 180                 return 1;
 181         case PIPE_CAP_MAX_VS_PREDS:
 182         case PIPE_CAP_MAX_FS_PREDS: /* not yet handled */
 183                 return 0;
 184         case PIPE_CAP_MAX_VS_TEMPS:
 185         case PIPE_CAP_MAX_FS_TEMPS: /* no spilling atm */
 186                 return 128 / 4;
 187         default:
 188                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 189                 return 0;
 190         }
 191 }
 192
 193 static float
 194 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 195 {
 196         switch (param) {
 197         case PIPE_CAP_MAX_LINE_WIDTH:
 198         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 199                 return 10.0;
 200         case PIPE_CAP_MAX_POINT_WIDTH:
 201         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 202                 return 64.0;
 203         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 204                 return 16.0;
 205         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 206                 return 4.0;
 207         default:
 208                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 209                 return 0.0;
 210         }
 211 }
 212
 213 static void
 214 nv50_screen_destroy(struct pipe_screen *pscreen)
 215 {
 216         struct nv50_screen *screen = nv50_screen(pscreen);
 217         unsigned i;
 218
 219         for (i = 0; i < 3; i++) {
 220                 if (screen->constbuf_parm[i])
 221                         nouveau_bo_ref(NULL, &screen->constbuf_parm[i]);
 222         }
 223
 224         if (screen->constbuf_misc[0])
 225                 nouveau_bo_ref(NULL, &screen->constbuf_misc[0]);
 226         if (screen->tic)
 227                 nouveau_bo_ref(NULL, &screen->tic);
 228         if (screen->tsc)
 229                 nouveau_bo_ref(NULL, &screen->tsc);
 230
 231         nouveau_notifier_free(&screen->sync);
 232         nouveau_grobj_free(&screen->tesla);
 233         nouveau_grobj_free(&screen->eng2d);
 234         nouveau_grobj_free(&screen->m2mf);
 235         nouveau_resource_destroy(&screen->immd_heap);
 236         nouveau_screen_fini(&screen->base);
 237         FREE(screen);
 238 }
 239
 240 #define BGN_RELOC(ch, bo, gr, m, n, fl) \
 241    OUT_RELOC(ch, bo, (n << 18) | (gr->subc << 13) | m, fl, 0, 0)
 242
 243 void
 244 nv50_screen_relocs(struct nv50_screen *screen)
 245 {
 246         struct nouveau_channel *chan = screen->base.channel;
 247         struct nouveau_grobj *tesla = screen->tesla;
 248         unsigned i;
 249         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
 250
 251         MARK_RING (chan, 28, 26);
 252
 253         /* cause grobj autobind */
 254         BEGIN_RING(chan, tesla, 0x0100, 1);
 255         OUT_RING  (chan, 0);
 256
 257         BGN_RELOC (chan, screen->tic, tesla, NV50TCL_TIC_ADDRESS_HIGH, 2, rl);
 258         OUT_RELOCh(chan, screen->tic, 0, rl);
 259         OUT_RELOCl(chan, screen->tic, 0, rl);
 260
 261         BGN_RELOC (chan, screen->tsc, tesla, NV50TCL_TSC_ADDRESS_HIGH, 2, rl);
 262         OUT_RELOCh(chan, screen->tsc, 0, rl);
 263         OUT_RELOCl(chan, screen->tsc, 0, rl);
 264
 265         BGN_RELOC (chan, screen->constbuf_misc[0],
 266                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 267         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 268         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 269         OUT_RELOC (chan, screen->constbuf_misc[0],
 270                    (NV50_CB_PMISC << 16) | 0x0200, rl, 0, 0);
 271
 272         BGN_RELOC (chan, screen->constbuf_misc[0],
 273                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 274         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 275         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 276         OUT_RELOC (chan, screen->constbuf_misc[0],
 277                    (NV50_CB_AUX << 16) | 0x0200, rl, 0, 0);
 278
 279         for (i = 0; i < 3; ++i) {
 280                 BGN_RELOC (chan, screen->constbuf_parm[i],
 281                            tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 282                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 283                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 284                 OUT_RELOC (chan, screen->constbuf_parm[i],
 285                            ((NV50_CB_PVP + i) << 16) | 0x0000, rl, 0, 0);
 286         }
 287 }
 288
 289 struct pipe_screen *
 290 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 291 {
 292         struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen);
 293         struct nouveau_channel *chan;
 294         struct pipe_screen *pscreen;
 295         unsigned chipset = dev->chipset;
 296         unsigned tesla_class = 0;
 297         int ret, i;
 298         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 299
 300         if (!screen)
 301                 return NULL;
 302         pscreen = &screen->base.base;
 303
 304         ret = nouveau_screen_init(&screen->base, dev);
 305         if (ret) {
 306                 nv50_screen_destroy(pscreen);
 307                 return NULL;
 308         }
 309         chan = screen->base.channel;
 310
 311         pscreen->winsys = ws;
 312         pscreen->destroy = nv50_screen_destroy;
 313         pscreen->get_param = nv50_screen_get_param;
 314         pscreen->get_paramf = nv50_screen_get_paramf;
 315         pscreen->is_format_supported = nv50_screen_is_format_supported;
 316         pscreen->context_create = nv50_create;
 317
 318         nv50_screen_init_resource_functions(pscreen);
 319
 320         /* DMA engine object */
 321         ret = nouveau_grobj_alloc(chan, 0xbeef5039,
 322                 NV50_MEMORY_TO_MEMORY_FORMAT, &screen->m2mf);
 323         if (ret) {
 324                 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret);
 325                 nv50_screen_destroy(pscreen);
 326                 return NULL;
 327         }
 328
 329         /* 2D object */
 330         ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 331         if (ret) {
 332                 NOUVEAU_ERR("Error creating 2D object: %d\n", ret);
 333                 nv50_screen_destroy(pscreen);
 334                 return NULL;
 335         }
 336
 337         /* 3D object */
 338         switch (chipset & 0xf0) {
 339         case 0x50:
 340                 tesla_class = NV50TCL;
 341                 break;
 342         case 0x80:
 343         case 0x90:
 344                 tesla_class = NV84TCL;
 345                 break;
 346         case 0xa0:
 347                 switch (chipset) {
 348                 case 0xa0:
 349                 case 0xaa:
 350                 case 0xac:
 351                         tesla_class = NVA0TCL;
 352                         break;
 353                 default:
 354                         tesla_class = NVA8TCL;
 355                         break;
 356                 }
 357                 break;
 358         default:
 359                 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset);
 360                 nv50_screen_destroy(pscreen);
 361                 return NULL;
 362         }
 363
 364         ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class,
 365                 &screen->tesla);
 366         if (ret) {
 367                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 368                 nv50_screen_destroy(pscreen);
 369                 return NULL;
 370         }
 371
 372         /* this is necessary for the new RING_3D / statebuffer code */
 373         BIND_RING(chan, screen->tesla, 7);
 374
 375         /* Sync notifier */
 376         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 377         if (ret) {
 378                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 379                 nv50_screen_destroy(pscreen);
 380                 return NULL;
 381         }
 382
 383         /* Static M2MF init */
 384         BEGIN_RING(chan, screen->m2mf,
 385                    NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 386         OUT_RING  (chan, screen->sync->handle);
 387         OUT_RING  (chan, chan->vram->handle);
 388         OUT_RING  (chan, chan->vram->handle);
 389
 390         /* Static 2D init */
 391         BEGIN_RING(chan, screen->eng2d, NV50_2D_DMA_NOTIFY, 4);
 392         OUT_RING  (chan, screen->sync->handle);
 393         OUT_RING  (chan, chan->vram->handle);
 394         OUT_RING  (chan, chan->vram->handle);
 395         OUT_RING  (chan, chan->vram->handle);
 396         BEGIN_RING(chan, screen->eng2d, NV50_2D_OPERATION, 1);
 397         OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 398         BEGIN_RING(chan, screen->eng2d, NV50_2D_CLIP_ENABLE, 1);
 399         OUT_RING  (chan, 0);
 400         BEGIN_RING(chan, screen->eng2d, 0x0888, 1);
 401         OUT_RING  (chan, 1);
 402
 403         /* Static tesla init */
 404         BEGIN_RING(chan, screen->tesla, NV50TCL_COND_MODE, 1);
 405         OUT_RING  (chan, NV50TCL_COND_MODE_ALWAYS);
 406         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
 407         OUT_RING  (chan, screen->sync->handle);
 408         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_ZETA, 11);
 409         for (i = 0; i < 11; i++)
 410                 OUT_RING  (chan, chan->vram->handle);
 411         BEGIN_RING(chan, screen->tesla,
 412                    NV50TCL_DMA_COLOR(0), NV50TCL_DMA_COLOR__SIZE);
 413         for (i = 0; i < NV50TCL_DMA_COLOR__SIZE; i++)
 414                 OUT_RING  (chan, chan->vram->handle);
 415
 416         BEGIN_RING(chan, screen->tesla, NV50TCL_RT_CONTROL, 1);
 417         OUT_RING  (chan, 1);
 418
 419         /* activate all 32 lanes (threads) in a warp */
 420         BEGIN_RING(chan, screen->tesla, NV50TCL_REG_MODE, 1);
 421         OUT_RING  (chan, NV50TCL_REG_MODE_STRIPED);
 422         BEGIN_RING(chan, screen->tesla, 0x1400, 1);
 423         OUT_RING  (chan, 0xf);
 424
 425         /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
 426         for (i = 0; i < 3; ++i) {
 427                 BEGIN_RING(chan, screen->tesla, NV50TCL_TEX_LIMITS(i), 1);
 428                 OUT_RING  (chan, 0x54);
 429         }
 430
 431         /* origin is top left (set to 1 for bottom left) */
 432         BEGIN_RING(chan, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1);
 433         OUT_RING  (chan, 0);
 434         BEGIN_RING(chan, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
 435         OUT_RING  (chan, 8);
 436
 437         /* constant buffers for immediates and VP/FP parameters */
 438         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (32 * 4) * 4,
 439                              &screen->constbuf_misc[0]);
 440         if (ret) {
 441                 nv50_screen_destroy(pscreen);
 442                 return NULL;
 443         }
 444         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 445         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 446         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 447         OUT_RING  (chan, (NV50_CB_PMISC << 16) | 0x0200);
 448         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 449         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 450         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 451         OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 452
 453         for (i = 0; i < 3; i++) {
 454                 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (4096 * 4) * 4,
 455                                      &screen->constbuf_parm[i]);
 456                 if (ret) {
 457                         nv50_screen_destroy(pscreen);
 458                         return NULL;
 459                 }
 460                 BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 461                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 462                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 463                 /* CB_DEF_SET_SIZE value of 0x0000 means 65536 */
 464                 OUT_RING  (chan, ((NV50_CB_PVP + i) << 16) | 0x0000);
 465         }
 466
 467         if (nouveau_resource_init(&screen->immd_heap, 0, 128)) {
 468                 NOUVEAU_ERR("Error initialising shader immediates heap.\n");
 469                 nv50_screen_destroy(pscreen);
 470                 return NULL;
 471         }
 472
 473         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 474                              &screen->tic);
 475         if (ret) {
 476                 nv50_screen_destroy(pscreen);
 477                 return NULL;
 478         }
 479         BEGIN_RING(chan, screen->tesla, NV50TCL_TIC_ADDRESS_HIGH, 3);
 480         OUT_RELOCh(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 481         OUT_RELOCl(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 482         OUT_RING  (chan, 3 * 32 - 1);
 483
 484         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 485                              &screen->tsc);
 486         if (ret) {
 487                 nv50_screen_destroy(pscreen);
 488                 return NULL;
 489         }
 490         BEGIN_RING(chan, screen->tesla, NV50TCL_TSC_ADDRESS_HIGH, 3);
 491         OUT_RELOCh(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 492         OUT_RELOCl(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 493         OUT_RING  (chan, 0); /* ignored if TSC_LINKED (0x1234) == 1 */
 494
 495         /* map constant buffers:
 496          *  B = buffer ID (maybe more than 1 byte)
 497          *  N = CB index used in shader instruction
 498          *  P = program type (0 = VP, 2 = GP, 3 = FP)
 499          * SET_PROGRAM_CB = 0x000BBNP1
 500          */
 501         BEGIN_RING_NI(chan, screen->tesla, NV50TCL_SET_PROGRAM_CB, 8);
 502         /* bind immediate buffer */
 503         OUT_RING  (chan, 0x001 | (NV50_CB_PMISC << 12));
 504         OUT_RING  (chan, 0x021 | (NV50_CB_PMISC << 12));
 505         OUT_RING  (chan, 0x031 | (NV50_CB_PMISC << 12));
 506         /* bind auxiliary constbuf to immediate data bo */
 507         OUT_RING  (chan, 0x201 | (NV50_CB_AUX << 12));
 508         OUT_RING  (chan, 0x221 | (NV50_CB_AUX << 12));
 509         /* bind parameter buffers */
 510         OUT_RING  (chan, 0x101 | (NV50_CB_PVP << 12));
 511         OUT_RING  (chan, 0x121 | (NV50_CB_PGP << 12));
 512         OUT_RING  (chan, 0x131 | (NV50_CB_PFP << 12));
 513
 514         /* Vertex array limits - max them out */
 515         for (i = 0; i < 16; i++) {
 516                 BEGIN_RING(chan, screen->tesla,
 517                            NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
 518                 OUT_RING  (chan, 0x000000ff);
 519                 OUT_RING  (chan, 0xffffffff);
 520         }
 521
 522         BEGIN_RING(chan, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
 523         OUT_RINGf (chan, 0.0f);
 524         OUT_RINGf (chan, 1.0f);
 525
 526         /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
 527         BEGIN_RING(chan, screen->tesla, NV50TCL_LINKED_TSC, 1);
 528         OUT_RING  (chan, 1);
 529
 530         BEGIN_RING(chan, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
 531         OUT_RING  (chan, 1); /* default edgeflag to TRUE */
 532
 533         FIRE_RING (chan);
 534
 535         screen->force_push = debug_get_bool_option("NV50_ALWAYS_PUSH", FALSE);
 536         if(!screen->force_push)
 537                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = NOUVEAU_BO_GART;
 538         return pscreen;
 539 }
 540