src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 extern int nouveau_device_get_param(struct nouveau_device *dev,
  37                                     uint64_t param, uint64_t *value);
  38
  39 static boolean
  40 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (sample_count > 2 && sample_count != 4 && sample_count != 8)
  47       return FALSE;
  48    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  49       return FALSE;
  50
  51    if (!util_format_is_supported(format, bindings))
  52       return FALSE;
  53
  54    switch (format) {
  55    case PIPE_FORMAT_Z16_UNORM:
  56       if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D)
  57          return FALSE;
  58       break;
  59    default:
  60       break;
  61    }
  62
  63    /* transfers & shared are always supported */
  64    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  65                  PIPE_BIND_TRANSFER_WRITE |
  66                  PIPE_BIND_SHARED);
  67
  68    return (nv50_format_table[format].usage & bindings) == bindings;
  69 }
  70
  71 static int
  72 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  73 {
  74    switch (param) {
  75    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  76    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  77       return 32;
  78    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  79       return 64;
  80    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  81       return 13;
  82    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  83       return 10;
  84    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  85       return 13;
  86    case PIPE_CAP_ARRAY_TEXTURES: /* shader support missing */
  87       return 0;
  88    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  89    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  90    case PIPE_CAP_TEXTURE_SWIZZLE:
  91    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  92    case PIPE_CAP_NPOT_TEXTURES:
  93    case PIPE_CAP_ANISOTROPIC_FILTER:
  94       return 1;
  95    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  96       return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
  97    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  98       return 0;
  99    case PIPE_CAP_TWO_SIDED_STENCIL:
 100    case PIPE_CAP_DEPTH_CLAMP:
 101    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 102    case PIPE_CAP_POINT_SPRITE:
 103       return 1;
 104    case PIPE_CAP_GLSL:
 105    case PIPE_CAP_SM3:
 106       return 1;
 107    case PIPE_CAP_MAX_RENDER_TARGETS:
 108       return 8;
 109    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 110       return 1;
 111    case PIPE_CAP_TIMER_QUERY:
 112    case PIPE_CAP_OCCLUSION_QUERY:
 113       return 1;
 114    case PIPE_CAP_STREAM_OUTPUT:
 115       return 0;
 116    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 117    case PIPE_CAP_INDEP_BLEND_ENABLE:
 118       return 1;
 119    case PIPE_CAP_INDEP_BLEND_FUNC:
 120       return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D;
 121    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 122    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 123       return 1;
 124    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 125    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 126       return 0;
 127    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 128       return 0;
 129    case PIPE_CAP_PRIMITIVE_RESTART:
 130    case PIPE_CAP_TGSI_INSTANCEID:
 131    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 132    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 133       return 1;
 134    default:
 135       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 136       return 0;
 137    }
 138 }
 139
 140 static int
 141 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 142                              enum pipe_shader_cap param)
 143 {
 144    switch (shader) {
 145    case PIPE_SHADER_VERTEX:
 146    case PIPE_SHADER_GEOMETRY:
 147    case PIPE_SHADER_FRAGMENT:
 148       break;
 149    default:
 150       return 0;
 151    }
 152
 153    switch (param) {
 154    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 155    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 156    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 157    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 158       return 16384;
 159    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 160       return 4;
 161    case PIPE_SHADER_CAP_MAX_INPUTS:
 162       if (shader == PIPE_SHADER_VERTEX)
 163          return 32;
 164       return 0x300 / 16;
 165    case PIPE_SHADER_CAP_MAX_CONSTS:
 166       return 65536 / 16;
 167    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 168       return 14;
 169    case PIPE_SHADER_CAP_MAX_ADDRS:
 170       return 1;
 171    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 172    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 173       return shader != PIPE_SHADER_FRAGMENT;
 174    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 175    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 176       return 1;
 177    case PIPE_SHADER_CAP_MAX_PREDS:
 178       return 0;
 179    case PIPE_SHADER_CAP_MAX_TEMPS:
 180       return NV50_CAP_MAX_PROGRAM_TEMPS;
 181    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 182       return 1;
 183    case PIPE_SHADER_CAP_SUBROUTINES:
 184       return 0; /* please inline, or provide function declarations */
 185    default:
 186       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 187       return 0;
 188    }
 189 }
 190
 191 static float
 192 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 193 {
 194    switch (param) {
 195    case PIPE_CAP_MAX_LINE_WIDTH:
 196    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 197       return 10.0f;
 198    case PIPE_CAP_MAX_POINT_WIDTH:
 199    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 200       return 64.0f;
 201    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 202       return 16.0f;
 203    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 204       return 4.0f;
 205    default:
 206       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 207       return 0.0f;
 208    }
 209 }
 210
 211 static void
 212 nv50_screen_destroy(struct pipe_screen *pscreen)
 213 {
 214    struct nv50_screen *screen = nv50_screen(pscreen);
 215
 216    if (screen->base.fence.current) {
 217       nouveau_fence_wait(screen->base.fence.current);
 218       nouveau_fence_ref (NULL, &screen->base.fence.current);
 219    }
 220    screen->base.channel->user_private = NULL;
 221
 222    nouveau_bo_ref(NULL, &screen->code);
 223    nouveau_bo_ref(NULL, &screen->tls_bo);
 224    nouveau_bo_ref(NULL, &screen->stack_bo);
 225    nouveau_bo_ref(NULL, &screen->txc);
 226    nouveau_bo_ref(NULL, &screen->uniforms);
 227    nouveau_bo_ref(NULL, &screen->fence.bo);
 228
 229    nouveau_resource_destroy(&screen->vp_code_heap);
 230    nouveau_resource_destroy(&screen->gp_code_heap);
 231    nouveau_resource_destroy(&screen->fp_code_heap);
 232
 233    if (screen->tic.entries)
 234       FREE(screen->tic.entries);
 235
 236    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 237
 238    nouveau_grobj_free(&screen->tesla);
 239    nouveau_grobj_free(&screen->eng2d);
 240    nouveau_grobj_free(&screen->m2mf);
 241
 242    nouveau_notifier_free(&screen->sync);
 243
 244    nouveau_screen_fini(&screen->base);
 245
 246    FREE(screen);
 247 }
 248
 249 static void
 250 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 251 {
 252    struct nv50_screen *screen = nv50_screen(pscreen);
 253    struct nouveau_channel *chan = screen->base.channel;
 254
 255    MARK_RING (chan, 5, 2);
 256    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 257    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 258    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 259    OUT_RING  (chan, sequence);
 260    OUT_RING  (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 261                     NV50_3D_QUERY_GET_UNK4 |
 262                     NV50_3D_QUERY_GET_UNIT_CROP |
 263                     NV50_3D_QUERY_GET_TYPE_QUERY |
 264                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 265                     NV50_3D_QUERY_GET_SHORT);
 266 }
 267
 268 static u32
 269 nv50_screen_fence_update(struct pipe_screen *pscreen)
 270 {
 271    struct nv50_screen *screen = nv50_screen(pscreen);
 272    return screen->fence.map[0];
 273 }
 274
 275 #define FAIL_SCREEN_INIT(str, err)                    \
 276    do {                                               \
 277       NOUVEAU_ERR(str, err);                          \
 278       nv50_screen_destroy(pscreen);                   \
 279       return NULL;                                    \
 280    } while(0)
 281
 282 struct pipe_screen *
 283 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 284 {
 285    struct nv50_screen *screen;
 286    struct nouveau_channel *chan;
 287    struct pipe_screen *pscreen;
 288    uint64_t value;
 289    uint32_t tesla_class;
 290    unsigned stack_size, max_warps, tls_space;
 291    int ret;
 292    unsigned i, base;
 293
 294    screen = CALLOC_STRUCT(nv50_screen);
 295    if (!screen)
 296       return NULL;
 297    pscreen = &screen->base.base;
 298
 299    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 300
 301    ret = nouveau_screen_init(&screen->base, dev);
 302    if (ret)
 303       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 304
 305    chan = screen->base.channel;
 306    chan->user_private = screen;
 307
 308    pscreen->winsys = ws;
 309    pscreen->destroy = nv50_screen_destroy;
 310    pscreen->context_create = nv50_create;
 311    pscreen->is_format_supported = nv50_screen_is_format_supported;
 312    pscreen->get_param = nv50_screen_get_param;
 313    pscreen->get_shader_param = nv50_screen_get_shader_param;
 314    pscreen->get_paramf = nv50_screen_get_paramf;
 315
 316    nv50_screen_init_resource_functions(pscreen);
 317
 318    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 319                         &screen->fence.bo);
 320    if (ret)
 321       goto fail;
 322    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 323    screen->fence.map = screen->fence.bo->map;
 324    nouveau_bo_unmap(screen->fence.bo);
 325    screen->base.fence.emit = nv50_screen_fence_emit;
 326    screen->base.fence.update = nv50_screen_fence_update;
 327
 328    ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 329    if (ret)
 330       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 331
 332    ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
 333    if (ret)
 334       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 335
 336    BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
 337    BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
 338    OUT_RING  (chan, screen->sync->handle);
 339    OUT_RING  (chan, chan->vram->handle);
 340    OUT_RING  (chan, chan->vram->handle);
 341
 342    ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 343    if (ret)
 344       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 345
 346    BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
 347    BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
 348    OUT_RING  (chan, screen->sync->handle);
 349    OUT_RING  (chan, chan->vram->handle);
 350    OUT_RING  (chan, chan->vram->handle);
 351    OUT_RING  (chan, chan->vram->handle);
 352    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 353    OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 354    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 355    OUT_RING  (chan, 0);
 356    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 357    OUT_RING  (chan, 0);
 358    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 359    OUT_RING  (chan, 1);
 360
 361    switch (dev->chipset & 0xf0) {
 362    case 0x50:
 363       tesla_class = NV50_3D;
 364       break;
 365    case 0x80:
 366    case 0x90:
 367       tesla_class = NV84_3D;
 368       break;
 369    case 0xa0:
 370       switch (dev->chipset) {
 371       case 0xa0:
 372       case 0xaa:
 373       case 0xac:
 374          tesla_class = NVA0_3D;
 375          break;
 376       case 0xaf:
 377          tesla_class = NVAF_3D;
 378          break;
 379       default:
 380          tesla_class = NVA3_3D;
 381          break;
 382       }
 383       break;
 384    default:
 385       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 386       break;
 387    }
 388
 389    ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
 390    if (ret)
 391       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 392
 393    BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
 394
 395    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 396    OUT_RING  (chan, NV50_3D_COND_MODE_ALWAYS);
 397
 398    BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
 399    OUT_RING  (chan, screen->sync->handle);
 400    BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
 401    for (i = 0; i < 11; ++i)
 402       OUT_RING(chan, chan->vram->handle);
 403    BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 404    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 405       OUT_RING(chan, chan->vram->handle);
 406
 407    BEGIN_RING(chan, RING_3D(REG_MODE), 1);
 408    OUT_RING  (chan, NV50_3D_REG_MODE_STRIPED);
 409    BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
 410    OUT_RING  (chan, 0xf);
 411
 412    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 413    OUT_RING  (chan, 1);
 414
 415    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 416    OUT_RING  (chan, 0);
 417    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 418    OUT_RING  (chan, 0);
 419    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 420    OUT_RING  (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
 421    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 422    OUT_RING  (chan, 0);
 423    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 424    OUT_RING  (chan, 0);
 425    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 426    OUT_RING  (chan, 1);
 427
 428    if (tesla_class >= NVA0_3D) {
 429       BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1);
 430       OUT_RING  (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 431    }
 432
 433    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 434    OUT_RING  (chan, 0);
 435    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 436    OUT_RING  (chan, 0);
 437    OUT_RING  (chan, 0);
 438    BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 439    OUT_RING  (chan, 0x3f);
 440
 441    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 442                         3 << NV50_CODE_BO_SIZE_LOG2, &screen->code);
 443    if (ret)
 444       goto fail;
 445
 446    nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 447    nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 448    nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 449
 450    base = 1 << NV50_CODE_BO_SIZE_LOG2;
 451
 452    BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
 453    OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 454    OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 455
 456    BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
 457    OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 458    OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 459
 460    BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
 461    OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 462    OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 463
 464    nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 465
 466    max_warps  = util_bitcount(value & 0xffff);
 467    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 468
 469    stack_size = max_warps * 64 * 8;
 470
 471    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
 472                         &screen->stack_bo);
 473    if (ret)
 474       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 475
 476    BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
 477    OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 478    OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 479    OUT_RING  (chan, 4);
 480
 481    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 482
 483    screen->tls_size = tls_space * max_warps * 32;
 484
 485    debug_printf("max_warps = %i, tls_size = %llu KiB\n",
 486                 max_warps, screen->tls_size >> 10);
 487
 488    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
 489                         &screen->tls_bo);
 490    if (ret)
 491       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 492
 493    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
 494    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 495    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 496    OUT_RING  (chan, util_logbase2(tls_space / 8));
 497
 498    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
 499                         &screen->uniforms);
 500    if (ret)
 501       goto fail;
 502
 503    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 504    OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 505    OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 506    OUT_RING  (chan, (NV50_CB_PVP << 16) | 0x0000);
 507
 508    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 509    OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 510    OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 511    OUT_RING  (chan, (NV50_CB_PGP << 16) | 0x0000);
 512
 513    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 514    OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 515    OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 516    OUT_RING  (chan, (NV50_CB_PFP << 16) | 0x0000);
 517
 518    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 519    OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 520    OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 521    OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 522
 523    BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
 524    OUT_RING  (chan, (NV50_CB_PVP << 12) | 0x001);
 525    OUT_RING  (chan, (NV50_CB_PGP << 12) | 0x021);
 526    OUT_RING  (chan, (NV50_CB_PFP << 12) | 0x031);
 527    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf01);
 528    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf21);
 529    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf31);
 530
 531    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
 532                         &screen->txc);
 533    if (ret)
 534       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 535
 536    /* max TIC (bits 4:8) & TSC bindings, per program type */
 537    for (i = 0; i < 3; ++i) {
 538       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 539       OUT_RING  (chan, 0x54);
 540    }
 541
 542    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 543    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 544    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 545    OUT_RING  (chan, NV50_TIC_MAX_ENTRIES - 1);
 546
 547    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 548    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 549    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 550    OUT_RING  (chan, NV50_TSC_MAX_ENTRIES - 1);
 551
 552    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 553    OUT_RING  (chan, 0);
 554
 555    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 556    OUT_RING  (chan, 0);
 557    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 558    OUT_RING  (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 559    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 560    for (i = 0; i < 8 * 2; ++i)
 561       OUT_RING(chan, 0);
 562    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 563    OUT_RING  (chan, 0);
 564
 565    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 566    OUT_RING  (chan, 1);
 567    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 568    OUT_RINGf (chan, 0.0f);
 569    OUT_RINGf (chan, 1.0f);
 570
 571    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 572 #ifdef NV50_SCISSORS_CLIPPING
 573    OUT_RING  (chan, 0x0000);
 574 #else
 575    OUT_RING  (chan, 0x1080);
 576 #endif
 577
 578    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 579    OUT_RING  (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 580
 581    /* We use scissors instead of exact view volume clipping,
 582     * so they're always enabled.
 583     */
 584    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 585    OUT_RING  (chan, 1);
 586    OUT_RING  (chan, 8192 << 16);
 587    OUT_RING  (chan, 8192 << 16);
 588
 589    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 590    OUT_RING  (chan, 1);
 591    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 592    OUT_RING  (chan, NV50_3D_POINT_RASTER_RULES_OGL);
 593    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 594    OUT_RING  (chan, 0x11111111);
 595    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 596    OUT_RING  (chan, 1);
 597
 598    FIRE_RING (chan);
 599
 600    screen->tic.entries = CALLOC(4096, sizeof(void *));
 601    screen->tsc.entries = screen->tic.entries + 2048;
 602
 603    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 604
 605    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 606
 607    return pscreen;
 608
 609 fail:
 610    nv50_screen_destroy(pscreen);
 611    return NULL;
 612 }
 613
 614 void
 615 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
 616 {
 617    struct nouveau_channel *chan = screen->base.channel;
 618
 619    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 620
 621    MARK_RING(chan, 5, 5);
 622    nouveau_bo_validate(chan, screen->code, flags);
 623    nouveau_bo_validate(chan, screen->uniforms, flags);
 624    nouveau_bo_validate(chan, screen->txc, flags);
 625    nouveau_bo_validate(chan, screen->tls_bo, flags);
 626    nouveau_bo_validate(chan, screen->stack_bo, flags);
 627 }
 628
 629 int
 630 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 631 {
 632    int i = screen->tic.next;
 633
 634    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 635       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 636
 637    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 638
 639    if (screen->tic.entries[i])
 640       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 641
 642    screen->tic.entries[i] = entry;
 643    return i;
 644 }
 645
 646 int
 647 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 648 {
 649    int i = screen->tsc.next;
 650
 651    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 652       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 653
 654    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 655
 656    if (screen->tsc.entries[i])
 657       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 658
 659    screen->tsc.entries[i] = entry;
 660    return i;
 661 }