src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nouveau/nouveau_vp3_video.h"
  31
  32 #include "nvc0_context.h"
  33 #include "nvc0_screen.h"
  34
  35 #include "nvc0_graph_macros.h"
  36
  37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39 #endif
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    if (sample_count > 8)
  49       return FALSE;
  50    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  51       return FALSE;
  52
  53    if (!util_format_is_supported(format, bindings))
  54       return FALSE;
  55
  56    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  57       if (util_format_get_blocksizebits(format) == 3 * 32)
  58          return FALSE;
  59
  60    /* transfers & shared are always supported */
  61    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  62                  PIPE_BIND_TRANSFER_WRITE |
  63                  PIPE_BIND_SHARED);
  64
  65    return (nvc0_format_table[format].usage & bindings) == bindings;
  66 }
  67
  68 static int
  69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  70 {
  71    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  72
  73    switch (param) {
  74    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  75       return 16 * 5;
  76    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  77    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  78       return 15;
  79    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  80       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  81    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  82       return 2048;
  83    case PIPE_CAP_MIN_TEXEL_OFFSET:
  84       return -8;
  85    case PIPE_CAP_MAX_TEXEL_OFFSET:
  86       return 7;
  87    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  88    case PIPE_CAP_TEXTURE_SWIZZLE:
  89    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  90    case PIPE_CAP_NPOT_TEXTURES:
  91    case PIPE_CAP_ANISOTROPIC_FILTER:
  92    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  93    case PIPE_CAP_CUBE_MAP_ARRAY:
  94    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  95    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  96       return 1;
  97    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  98       return 65536;
  99    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 100       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 101    case PIPE_CAP_TWO_SIDED_STENCIL:
 102    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 103    case PIPE_CAP_POINT_SPRITE:
 104    case PIPE_CAP_TGSI_TEXCOORD:
 105       return 1;
 106    case PIPE_CAP_SM3:
 107       return 1;
 108    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 109       return 150;
 110    case PIPE_CAP_MAX_RENDER_TARGETS:
 111       return 8;
 112    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 113       return 1;
 114    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 115    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 116    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 117       return 1;
 118    case PIPE_CAP_QUERY_TIMESTAMP:
 119    case PIPE_CAP_QUERY_TIME_ELAPSED:
 120    case PIPE_CAP_OCCLUSION_QUERY:
 121    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 122    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 123       return 1;
 124    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 125       return 4;
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 128       return 128;
 129    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 130    case PIPE_CAP_INDEP_BLEND_ENABLE:
 131    case PIPE_CAP_INDEP_BLEND_FUNC:
 132       return 1;
 133    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 134    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 135       return 1;
 136    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 137    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 138       return 0;
 139    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 140       return 0;
 141    case PIPE_CAP_PRIMITIVE_RESTART:
 142    case PIPE_CAP_TGSI_INSTANCEID:
 143    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 144    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 145    case PIPE_CAP_CONDITIONAL_RENDER:
 146    case PIPE_CAP_TEXTURE_BARRIER:
 147    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 148    case PIPE_CAP_START_INSTANCE:
 149       return 1;
 150    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 151       return 0; /* state trackers will know better */
 152    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 153    case PIPE_CAP_USER_INDEX_BUFFERS:
 154    case PIPE_CAP_USER_VERTEX_BUFFERS:
 155       return 1;
 156    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 157       return 256;
 158    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 159       return 1; /* 256 for binding as RT, but that's not possible in GL */
 160    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 161       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 162    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 163    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 164    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 165       return 0;
 166    case PIPE_CAP_COMPUTE:
 167       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 168    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 169       return 1;
 170    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 171       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 172    case PIPE_CAP_ENDIANNESS:
 173       return PIPE_ENDIAN_LITTLE;
 174    default:
 175       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 176       return 0;
 177    }
 178 }
 179
 180 static int
 181 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 182                              enum pipe_shader_cap param)
 183 {
 184    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 185
 186    switch (shader) {
 187    case PIPE_SHADER_VERTEX:
 188       /*
 189    case PIPE_SHADER_TESSELLATION_CONTROL:
 190    case PIPE_SHADER_TESSELLATION_EVALUATION:
 191       */
 192    case PIPE_SHADER_GEOMETRY:
 193    case PIPE_SHADER_FRAGMENT:
 194       break;
 195    case PIPE_SHADER_COMPUTE:
 196       if (class_3d < NVE4_3D_CLASS)
 197          return 0;
 198       break;
 199    default:
 200       return 0;
 201    }
 202
 203    switch (param) {
 204    case PIPE_SHADER_CAP_PREFERRED_IR:
 205       return PIPE_SHADER_IR_TGSI;
 206    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 207    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 208    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 209    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 210       return 16384;
 211    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 212       return 16;
 213    case PIPE_SHADER_CAP_MAX_INPUTS:
 214       if (shader == PIPE_SHADER_VERTEX)
 215          return 32;
 216       /* NOTE: These only count our slots for GENERIC varyings.
 217        * The address space may be larger, but the actual hard limit seems to be
 218        * less than what the address space layout permits, so don't add TEXCOORD,
 219        * COLOR, etc. here.
 220        */
 221       if (shader == PIPE_SHADER_FRAGMENT)
 222          return 0x1f0 / 16;
 223       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 224        * and excludes 0x60 per-patch inputs.
 225        */
 226       return 0x200 / 16;
 227    case PIPE_SHADER_CAP_MAX_CONSTS:
 228       return 65536 / 16;
 229    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 230       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 231          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 232       return NVC0_MAX_PIPE_CONSTBUFS;
 233    case PIPE_SHADER_CAP_MAX_ADDRS:
 234       return 1;
 235    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 236    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 237       return shader != PIPE_SHADER_FRAGMENT;
 238    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 239    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 240       return 1;
 241    case PIPE_SHADER_CAP_MAX_PREDS:
 242       return 0;
 243    case PIPE_SHADER_CAP_MAX_TEMPS:
 244       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 245    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 246       return 1;
 247    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 248       return 0;
 249    case PIPE_SHADER_CAP_SUBROUTINES:
 250       return 1;
 251    case PIPE_SHADER_CAP_INTEGERS:
 252       return 1;
 253    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 254       return 16; /* would be 32 in linked (OpenGL-style) mode */
 255       /*
 256    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
 257       return 32;
 258       */
 259    default:
 260       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 261       return 0;
 262    }
 263 }
 264
 265 static float
 266 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 267 {
 268    switch (param) {
 269    case PIPE_CAPF_MAX_LINE_WIDTH:
 270    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 271       return 10.0f;
 272    case PIPE_CAPF_MAX_POINT_WIDTH:
 273       return 63.0f;
 274    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 275       return 63.375f;
 276    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 277       return 16.0f;
 278    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 279       return 15.0f;
 280    default:
 281       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 282       return 0.0f;
 283    }
 284 }
 285
 286 static int
 287 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 288                               enum pipe_compute_cap param, void *data)
 289 {
 290    uint64_t *data64 = (uint64_t *)data;
 291    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 292
 293    switch (param) {
 294    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 295       data64[0] = 3;
 296       return 8;
 297    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 298       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 299       data64[1] = 65535;
 300       data64[2] = 65535;
 301       return 24;
 302    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 303       data64[0] = 1024;
 304       data64[1] = 1024;
 305       data64[2] = 64;
 306       return 24;
 307    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 308       data64[0] = 1024;
 309       return 8;
 310    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 311       data64[0] = (uint64_t)1 << 40;
 312       return 8;
 313    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 314       data64[0] = 48 << 10;
 315       return 8;
 316    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 317       data64[0] = 512 << 10;
 318       return 8;
 319    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 320       data64[0] = 4096;
 321       return 8;
 322    default:
 323       return 0;
 324    }
 325 }
 326
 327 static void
 328 nvc0_screen_destroy(struct pipe_screen *pscreen)
 329 {
 330    struct nvc0_screen *screen = nvc0_screen(pscreen);
 331
 332    if (screen->base.fence.current) {
 333       nouveau_fence_wait(screen->base.fence.current);
 334       nouveau_fence_ref(NULL, &screen->base.fence.current);
 335    }
 336    if (screen->base.pushbuf)
 337       screen->base.pushbuf->user_priv = NULL;
 338
 339    if (screen->blitter)
 340       nvc0_blitter_destroy(screen);
 341    if (screen->pm.prog) {
 342       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 343       nvc0_program_destroy(NULL, screen->pm.prog);
 344    }
 345
 346    nouveau_bo_ref(NULL, &screen->text);
 347    nouveau_bo_ref(NULL, &screen->uniform_bo);
 348    nouveau_bo_ref(NULL, &screen->tls);
 349    nouveau_bo_ref(NULL, &screen->txc);
 350    nouveau_bo_ref(NULL, &screen->fence.bo);
 351    nouveau_bo_ref(NULL, &screen->poly_cache);
 352    nouveau_bo_ref(NULL, &screen->parm);
 353
 354    nouveau_heap_destroy(&screen->lib_code);
 355    nouveau_heap_destroy(&screen->text_heap);
 356
 357    FREE(screen->tic.entries);
 358
 359    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 360
 361    nouveau_object_del(&screen->eng3d);
 362    nouveau_object_del(&screen->eng2d);
 363    nouveau_object_del(&screen->m2mf);
 364    nouveau_object_del(&screen->compute);
 365
 366    nouveau_screen_fini(&screen->base);
 367
 368    FREE(screen);
 369 }
 370
 371 static int
 372 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 373                      unsigned size, const uint32_t *data)
 374 {
 375    struct nouveau_pushbuf *push = screen->base.pushbuf;
 376
 377    size /= 4;
 378
 379    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 380    PUSH_DATA (push, (m - 0x3800) / 8);
 381    PUSH_DATA (push, pos);
 382    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 383    PUSH_DATA (push, pos);
 384    PUSH_DATAp(push, data, size);
 385
 386    return pos + size;
 387 }
 388
 389 static void
 390 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 391 {
 392    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 393    PUSH_DATA (push, 0xff);
 394    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 395    PUSH_DATA (push, 0xff);
 396    PUSH_DATA (push, 0xff);
 397    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 398    PUSH_DATA (push, 0xff);
 399    PUSH_DATA (push, 0xff);
 400    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 401    PUSH_DATA (push, 0x3f);
 402
 403    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 404    PUSH_DATA (push, (3 << 16) | 3);
 405    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 406    PUSH_DATA (push, (2 << 16) | 2);
 407    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 408    PUSH_DATA (push, 1);
 409
 410    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 411    PUSH_DATA (push, 0);
 412    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 413    PUSH_DATA (push, 0x10);
 414    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 415    PUSH_DATA (push, 0x10);
 416    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 417    PUSH_DATA (push, 0x10);
 418    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 419    PUSH_DATA (push, 0x10);
 420    PUSH_DATA (push, 0x10);
 421    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 422    PUSH_DATA (push, 0x10);
 423    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 424    PUSH_DATA (push, 0xe);
 425
 426    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 427    PUSH_DATA (push, 1 << 12);
 428    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 429    PUSH_DATA (push, 0);
 430    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 431    PUSH_DATA (push, 3);
 432
 433    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 434    PUSH_DATA (push, 0x3fffff);
 435    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 436    PUSH_DATA (push, 1);
 437    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 438    PUSH_DATA (push, 1);
 439    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 440    PUSH_DATA (push, 3);
 441
 442    if (obj_class >= NVE4_3D_CLASS) {
 443       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 444       PUSH_DATA (push, 1);
 445    }
 446
 447    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 448     * are supposed to do */
 449 }
 450
 451 static void
 452 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 453 {
 454    struct nvc0_screen *screen = nvc0_screen(pscreen);
 455    struct nouveau_pushbuf *push = screen->base.pushbuf;
 456
 457    /* we need to do it after possible flush in MARK_RING */
 458    *sequence = ++screen->base.fence.sequence;
 459
 460    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 461    PUSH_DATAh(push, screen->fence.bo->offset);
 462    PUSH_DATA (push, screen->fence.bo->offset);
 463    PUSH_DATA (push, *sequence);
 464    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 465               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 466 }
 467
 468 static u32
 469 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 470 {
 471    struct nvc0_screen *screen = nvc0_screen(pscreen);
 472    return screen->fence.map[0];
 473 }
 474
 475 static int
 476 nvc0_screen_init_compute(struct nvc0_screen *screen)
 477 {
 478    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 479
 480    switch (screen->base.device->chipset & 0xf0) {
 481    case 0xc0:
 482    case 0xd0:
 483       /* Using COMPUTE has weird effects on 3D state, we need to
 484        * investigate this further before enabling it by default.
 485        */
 486       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
 487          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 488       return 0;
 489    case 0xe0:
 490    case 0xf0:
 491       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 492    default:
 493       return -1;
 494    }
 495 }
 496
 497 boolean
 498 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 499                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 500 {
 501    struct nouveau_bo *bo = NULL;
 502    int ret;
 503    uint64_t size = (lpos + lneg) * 32 + cstack;
 504
 505    if (size >= (1 << 20)) {
 506       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 507       return FALSE;
 508    }
 509
 510    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 511    size  = align(size, 0x8000);
 512    size *= screen->mp_count;
 513
 514    size = align(size, 1 << 17);
 515
 516    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 517                         NULL, &bo);
 518    if (ret) {
 519       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 520       return FALSE;
 521    }
 522    nouveau_bo_ref(NULL, &screen->tls);
 523    screen->tls = bo;
 524    return TRUE;
 525 }
 526
 527 #define FAIL_SCREEN_INIT(str, err)                    \
 528    do {                                               \
 529       NOUVEAU_ERR(str, err);                          \
 530       nvc0_screen_destroy(pscreen);                   \
 531       return NULL;                                    \
 532    } while(0)
 533
 534 struct pipe_screen *
 535 nvc0_screen_create(struct nouveau_device *dev)
 536 {
 537    struct nvc0_screen *screen;
 538    struct pipe_screen *pscreen;
 539    struct nouveau_object *chan;
 540    struct nouveau_pushbuf *push;
 541    uint64_t value;
 542    uint32_t obj_class;
 543    int ret;
 544    unsigned i;
 545    union nouveau_bo_config mm_config;
 546
 547    switch (dev->chipset & ~0xf) {
 548    case 0xc0:
 549    case 0xd0:
 550    case 0xe0:
 551    case 0xf0:
 552       break;
 553    default:
 554       return NULL;
 555    }
 556
 557    screen = CALLOC_STRUCT(nvc0_screen);
 558    if (!screen)
 559       return NULL;
 560    pscreen = &screen->base.base;
 561
 562    ret = nouveau_screen_init(&screen->base, dev);
 563    if (ret) {
 564       nvc0_screen_destroy(pscreen);
 565       return NULL;
 566    }
 567    chan = screen->base.channel;
 568    push = screen->base.pushbuf;
 569    push->user_priv = screen;
 570    push->rsvd_kick = 5;
 571
 572    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 573       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 574    screen->base.sysmem_bindings |=
 575       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 576
 577    pscreen->destroy = nvc0_screen_destroy;
 578    pscreen->context_create = nvc0_create;
 579    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 580    pscreen->get_param = nvc0_screen_get_param;
 581    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 582    pscreen->get_paramf = nvc0_screen_get_paramf;
 583    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 584
 585    nvc0_screen_init_resource_functions(pscreen);
 586
 587    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 588    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 589
 590    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 591                         &screen->fence.bo);
 592    if (ret)
 593       goto fail;
 594    nouveau_bo_map(screen->fence.bo, 0, NULL);
 595    screen->fence.map = screen->fence.bo->map;
 596    screen->base.fence.emit = nvc0_screen_fence_emit;
 597    screen->base.fence.update = nvc0_screen_fence_update;
 598
 599    switch (dev->chipset & 0xf0) {
 600    case 0xf0:
 601       obj_class = NVF0_P2MF_CLASS;
 602       break;
 603    case 0xe0:
 604       obj_class = NVE4_P2MF_CLASS;
 605       break;
 606    default:
 607       obj_class = NVC0_M2MF_CLASS;
 608       break;
 609    }
 610    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 611                             &screen->m2mf);
 612    if (ret)
 613       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 614
 615    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 616    PUSH_DATA (push, screen->m2mf->oclass);
 617    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 618       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 619       PUSH_DATA (push, 0xa0b5);
 620    }
 621
 622    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 623                             &screen->eng2d);
 624    if (ret)
 625       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 626
 627    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 628    PUSH_DATA (push, screen->eng2d->oclass);
 629    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 630    PUSH_DATA (push, 0);
 631    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 632    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 633    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 634    PUSH_DATA (push, 0);
 635    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 636    PUSH_DATA (push, 0);
 637    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 638    PUSH_DATA (push, 0x3f);
 639    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 640    PUSH_DATA (push, 1);
 641
 642    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 643    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 644    PUSH_DATA (push, screen->fence.bo->offset + 16);
 645
 646    switch (dev->chipset & 0xf0) {
 647    case 0xf0:
 648       obj_class = NVF0_3D_CLASS;
 649       break;
 650    case 0xe0:
 651       obj_class = NVE4_3D_CLASS;
 652       break;
 653    case 0xd0:
 654    case 0xc0:
 655    default:
 656       switch (dev->chipset) {
 657       case 0xd9:
 658       case 0xc8:
 659          obj_class = NVC8_3D_CLASS;
 660          break;
 661       case 0xc1:
 662          obj_class = NVC1_3D_CLASS;
 663          break;
 664       default:
 665          obj_class = NVC0_3D_CLASS;
 666          break;
 667       }
 668       break;
 669    }
 670    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 671                             &screen->eng3d);
 672    if (ret)
 673       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 674    screen->base.class_3d = obj_class;
 675
 676    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 677    PUSH_DATA (push, screen->eng3d->oclass);
 678
 679    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 680    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 681
 682    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 683       /* kill shaders after about 1 second (at 100 MHz) */
 684       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 685       PUSH_DATA (push, 0x17);
 686    }
 687
 688    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 689    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 690    for (i = 0; i < 8; ++i)
 691            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 692
 693    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 694    PUSH_DATA (push, 1);
 695
 696    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 697    PUSH_DATA (push, 0);
 698    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 699    PUSH_DATA (push, 0);
 700    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 701    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 702    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 703    PUSH_DATA (push, 0);
 704    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 705    PUSH_DATA (push, 1);
 706    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 707    PUSH_DATA (push, 0);
 708    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 709    PUSH_DATA (push, 1);
 710    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 711    PUSH_DATA (push, 0);
 712    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 713       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 714       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 715    } else {
 716       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 717       PUSH_DATA (push, 15);
 718    }
 719    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 720    PUSH_DATA (push, 8); /* 128 */
 721    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 722    PUSH_DATA (push, 1);
 723    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 724       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 725       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 726    }
 727
 728    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 729
 730    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 731                         &screen->text);
 732    if (ret)
 733       goto fail;
 734
 735    /* XXX: getting a page fault at the end of the code buffer every few
 736     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 737     */
 738    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 739
 740    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 741                         &screen->uniform_bo);
 742    if (ret)
 743       goto fail;
 744
 745    for (i = 0; i < 5; ++i) {
 746       /* TIC and TSC entries for each unit (nve4+ only) */
 747       /* auxiliary constants (6 user clip planes, base instance id) */
 748       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 749       PUSH_DATA (push, 512);
 750       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 751       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 752       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 753       PUSH_DATA (push, (15 << 4) | 1);
 754       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 755          unsigned j;
 756          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 757          PUSH_DATA (push, 0);
 758          for (j = 0; j < 8; ++j)
 759             PUSH_DATA(push, j);
 760       } else {
 761          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 762          PUSH_DATA (push, 0x54);
 763       }
 764    }
 765    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 766    PUSH_DATA (push, 0);
 767
 768    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 769    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 770    PUSH_DATA (push, 256);
 771    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 772    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 773    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 774    PUSH_DATA (push, 0);
 775    PUSH_DATAf(push, 0.0f);
 776    PUSH_DATAf(push, 0.0f);
 777    PUSH_DATAf(push, 0.0f);
 778    PUSH_DATAf(push, 0.0f);
 779    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 780    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 781    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 782
 783    if (dev->drm_version >= 0x01000101) {
 784       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 785       if (ret) {
 786          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 787          goto fail;
 788       }
 789    } else {
 790       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 791          value = (8 << 8) | 4;
 792       else
 793          value = (16 << 8) | 4;
 794    }
 795    screen->mp_count = value >> 8;
 796    screen->mp_count_compute = screen->mp_count;
 797
 798    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 799
 800    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 801    PUSH_DATAh(push, screen->text->offset);
 802    PUSH_DATA (push, screen->text->offset);
 803    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 804    PUSH_DATAh(push, screen->tls->offset);
 805    PUSH_DATA (push, screen->tls->offset);
 806    PUSH_DATA (push, screen->tls->size >> 32);
 807    PUSH_DATA (push, screen->tls->size);
 808    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 809    PUSH_DATA (push, 0);
 810    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 811    PUSH_DATA (push, 0);
 812
 813    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 814                         &screen->poly_cache);
 815    if (ret)
 816       goto fail;
 817
 818    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 819    PUSH_DATAh(push, screen->poly_cache->offset);
 820    PUSH_DATA (push, screen->poly_cache->offset);
 821    PUSH_DATA (push, 3);
 822
 823    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 824                         &screen->txc);
 825    if (ret)
 826       goto fail;
 827
 828    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 829    PUSH_DATAh(push, screen->txc->offset);
 830    PUSH_DATA (push, screen->txc->offset);
 831    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 832
 833    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 834    PUSH_DATAh(push, screen->txc->offset + 65536);
 835    PUSH_DATA (push, screen->txc->offset + 65536);
 836    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 837
 838    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 839    PUSH_DATA (push, 0);
 840    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 841    PUSH_DATA (push, 0);
 842    PUSH_DATA (push, 0);
 843    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 844    PUSH_DATA (push, 0x3f);
 845
 846    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 847    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 848    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 849    for (i = 0; i < 8 * 2; ++i)
 850       PUSH_DATA(push, 0);
 851    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 852    PUSH_DATA (push, 0);
 853    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 854    PUSH_DATA (push, 0);
 855
 856    /* neither scissors, viewport nor stencil mask should affect clears */
 857    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 858    PUSH_DATA (push, 0);
 859
 860    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 861    PUSH_DATA (push, 1);
 862    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
 863    PUSH_DATAf(push, 0.0f);
 864    PUSH_DATAf(push, 1.0f);
 865    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 866    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 867
 868    /* We use scissors instead of exact view volume clipping,
 869     * so they're always enabled.
 870     */
 871    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
 872    PUSH_DATA (push, 1);
 873    PUSH_DATA (push, 8192 << 16);
 874    PUSH_DATA (push, 8192 << 16);
 875
 876 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 877
 878    i = 0;
 879    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
 880    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
 881    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 882    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
 883    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
 884    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 885    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 886
 887    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 888    PUSH_DATA (push, 1);
 889    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 890    PUSH_DATA (push, 1);
 891    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 892    PUSH_DATA (push, 0x40);
 893    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 894    PUSH_DATA (push, 0);
 895    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 896    PUSH_DATA (push, 0x30);
 897    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 898    PUSH_DATA (push, 3);
 899    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 900    PUSH_DATA (push, 0x20);
 901    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 902    PUSH_DATA (push, 0x00);
 903
 904    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 905    PUSH_DATA (push, 0);
 906    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 907    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 908
 909    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 910
 911    if (nvc0_screen_init_compute(screen))
 912       goto fail;
 913
 914    PUSH_KICK (push);
 915
 916    screen->tic.entries = CALLOC(4096, sizeof(void *));
 917    screen->tsc.entries = screen->tic.entries + 2048;
 918
 919    mm_config.nvc0.tile_mode = 0;
 920    mm_config.nvc0.memtype = 0xfe0;
 921    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 922
 923    if (!nvc0_blitter_create(screen))
 924       goto fail;
 925
 926    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 927
 928    return pscreen;
 929
 930 fail:
 931    nvc0_screen_destroy(pscreen);
 932    return NULL;
 933 }
 934
 935 int
 936 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 937 {
 938    int i = screen->tic.next;
 939
 940    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 941       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 942
 943    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 944
 945    if (screen->tic.entries[i])
 946       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 947
 948    screen->tic.entries[i] = entry;
 949    return i;
 950 }
 951
 952 int
 953 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 954 {
 955    int i = screen->tsc.next;
 956
 957    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 958       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 959
 960    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 961
 962    if (screen->tsc.entries[i])
 963       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 964
 965    screen->tsc.entries[i] = entry;
 966    return i;
 967 }