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93a29028617bde5ec0ce43f49a7e43b84695faf0
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nouveau/nouveau_vp3_video.h"
31
32 #include "nvc0_context.h"
33 #include "nvc0_screen.h"
34
35 #include "nvc0_graph_macros.h"
36
37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
39 #endif
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 if (sample_count > 8)
49 return FALSE;
50 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
51 return FALSE;
52
53 if (!util_format_is_supported(format, bindings))
54 return FALSE;
55
56 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
57 if (util_format_get_blocksizebits(format) == 3 * 32)
58 return FALSE;
59
60 /* transfers & shared are always supported */
61 bindings &= ~(PIPE_BIND_TRANSFER_READ |
62 PIPE_BIND_TRANSFER_WRITE |
63 PIPE_BIND_SHARED);
64
65 return (nvc0_format_table[format].usage & bindings) == bindings;
66 }
67
68 static int
69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
70 {
71 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
72
73 switch (param) {
74 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
75 return 16 * 5;
76 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
77 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
78 return 15;
79 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
80 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
81 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
82 return 2048;
83 case PIPE_CAP_MIN_TEXEL_OFFSET:
84 return -8;
85 case PIPE_CAP_MAX_TEXEL_OFFSET:
86 return 7;
87 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
88 case PIPE_CAP_TEXTURE_SWIZZLE:
89 case PIPE_CAP_TEXTURE_SHADOW_MAP:
90 case PIPE_CAP_NPOT_TEXTURES:
91 case PIPE_CAP_ANISOTROPIC_FILTER:
92 case PIPE_CAP_SEAMLESS_CUBE_MAP:
93 case PIPE_CAP_CUBE_MAP_ARRAY:
94 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
95 case PIPE_CAP_TEXTURE_MULTISAMPLE:
96 return 1;
97 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
98 return 65536;
99 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
100 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
101 case PIPE_CAP_TWO_SIDED_STENCIL:
102 case PIPE_CAP_DEPTH_CLIP_DISABLE:
103 case PIPE_CAP_POINT_SPRITE:
104 case PIPE_CAP_TGSI_TEXCOORD:
105 return 1;
106 case PIPE_CAP_SM3:
107 return 1;
108 case PIPE_CAP_GLSL_FEATURE_LEVEL:
109 return 150;
110 case PIPE_CAP_MAX_RENDER_TARGETS:
111 return 8;
112 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
113 return 1;
114 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
115 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
116 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
117 return 1;
118 case PIPE_CAP_QUERY_TIMESTAMP:
119 case PIPE_CAP_QUERY_TIME_ELAPSED:
120 case PIPE_CAP_OCCLUSION_QUERY:
121 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
122 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
123 return 1;
124 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
125 return 4;
126 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
127 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
128 return 128;
129 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
130 case PIPE_CAP_INDEP_BLEND_ENABLE:
131 case PIPE_CAP_INDEP_BLEND_FUNC:
132 return 1;
133 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
134 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
135 return 1;
136 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
137 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
138 return 0;
139 case PIPE_CAP_SHADER_STENCIL_EXPORT:
140 return 0;
141 case PIPE_CAP_PRIMITIVE_RESTART:
142 case PIPE_CAP_TGSI_INSTANCEID:
143 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
144 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
145 case PIPE_CAP_CONDITIONAL_RENDER:
146 case PIPE_CAP_TEXTURE_BARRIER:
147 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
148 case PIPE_CAP_START_INSTANCE:
149 return 1;
150 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
151 return 0; /* state trackers will know better */
152 case PIPE_CAP_USER_CONSTANT_BUFFERS:
153 case PIPE_CAP_USER_INDEX_BUFFERS:
154 case PIPE_CAP_USER_VERTEX_BUFFERS:
155 return 1;
156 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
157 return 256;
158 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
159 return 1; /* 256 for binding as RT, but that's not possible in GL */
160 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
161 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
162 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
163 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
164 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
165 return 0;
166 case PIPE_CAP_COMPUTE:
167 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
168 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
169 return 1;
170 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
171 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
172 case PIPE_CAP_ENDIANNESS:
173 return PIPE_ENDIAN_LITTLE;
174 default:
175 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
176 return 0;
177 }
178 }
179
180 static int
181 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
182 enum pipe_shader_cap param)
183 {
184 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
185
186 switch (shader) {
187 case PIPE_SHADER_VERTEX:
188 /*
189 case PIPE_SHADER_TESSELLATION_CONTROL:
190 case PIPE_SHADER_TESSELLATION_EVALUATION:
191 */
192 case PIPE_SHADER_GEOMETRY:
193 case PIPE_SHADER_FRAGMENT:
194 break;
195 case PIPE_SHADER_COMPUTE:
196 if (class_3d < NVE4_3D_CLASS)
197 return 0;
198 break;
199 default:
200 return 0;
201 }
202
203 switch (param) {
204 case PIPE_SHADER_CAP_PREFERRED_IR:
205 return PIPE_SHADER_IR_TGSI;
206 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
207 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
208 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
209 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
210 return 16384;
211 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
212 return 16;
213 case PIPE_SHADER_CAP_MAX_INPUTS:
214 if (shader == PIPE_SHADER_VERTEX)
215 return 32;
216 /* NOTE: These only count our slots for GENERIC varyings.
217 * The address space may be larger, but the actual hard limit seems to be
218 * less than what the address space layout permits, so don't add TEXCOORD,
219 * COLOR, etc. here.
220 */
221 if (shader == PIPE_SHADER_FRAGMENT)
222 return 0x1f0 / 16;
223 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
224 * and excludes 0x60 per-patch inputs.
225 */
226 return 0x200 / 16;
227 case PIPE_SHADER_CAP_MAX_CONSTS:
228 return 65536 / 16;
229 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
230 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
231 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
232 return NVC0_MAX_PIPE_CONSTBUFS;
233 case PIPE_SHADER_CAP_MAX_ADDRS:
234 return 1;
235 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
236 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
237 return shader != PIPE_SHADER_FRAGMENT;
238 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
239 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
240 return 1;
241 case PIPE_SHADER_CAP_MAX_PREDS:
242 return 0;
243 case PIPE_SHADER_CAP_MAX_TEMPS:
244 return NVC0_CAP_MAX_PROGRAM_TEMPS;
245 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
246 return 1;
247 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
248 return 0;
249 case PIPE_SHADER_CAP_SUBROUTINES:
250 return 1;
251 case PIPE_SHADER_CAP_INTEGERS:
252 return 1;
253 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
254 return 16; /* would be 32 in linked (OpenGL-style) mode */
255 /*
256 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
257 return 32;
258 */
259 default:
260 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
261 return 0;
262 }
263 }
264
265 static float
266 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
267 {
268 switch (param) {
269 case PIPE_CAPF_MAX_LINE_WIDTH:
270 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
271 return 10.0f;
272 case PIPE_CAPF_MAX_POINT_WIDTH:
273 return 63.0f;
274 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
275 return 63.375f;
276 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
277 return 16.0f;
278 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
279 return 15.0f;
280 default:
281 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
282 return 0.0f;
283 }
284 }
285
286 static int
287 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
288 enum pipe_compute_cap param, void *data)
289 {
290 uint64_t *data64 = (uint64_t *)data;
291 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
292
293 switch (param) {
294 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
295 data64[0] = 3;
296 return 8;
297 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
298 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
299 data64[1] = 65535;
300 data64[2] = 65535;
301 return 24;
302 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
303 data64[0] = 1024;
304 data64[1] = 1024;
305 data64[2] = 64;
306 return 24;
307 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
308 data64[0] = 1024;
309 return 8;
310 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
311 data64[0] = (uint64_t)1 << 40;
312 return 8;
313 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
314 data64[0] = 48 << 10;
315 return 8;
316 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
317 data64[0] = 512 << 10;
318 return 8;
319 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
320 data64[0] = 4096;
321 return 8;
322 default:
323 return 0;
324 }
325 }
326
327 static void
328 nvc0_screen_destroy(struct pipe_screen *pscreen)
329 {
330 struct nvc0_screen *screen = nvc0_screen(pscreen);
331
332 if (screen->base.fence.current) {
333 nouveau_fence_wait(screen->base.fence.current);
334 nouveau_fence_ref(NULL, &screen->base.fence.current);
335 }
336 if (screen->base.pushbuf)
337 screen->base.pushbuf->user_priv = NULL;
338
339 if (screen->blitter)
340 nvc0_blitter_destroy(screen);
341 if (screen->pm.prog) {
342 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
343 nvc0_program_destroy(NULL, screen->pm.prog);
344 }
345
346 nouveau_bo_ref(NULL, &screen->text);
347 nouveau_bo_ref(NULL, &screen->uniform_bo);
348 nouveau_bo_ref(NULL, &screen->tls);
349 nouveau_bo_ref(NULL, &screen->txc);
350 nouveau_bo_ref(NULL, &screen->fence.bo);
351 nouveau_bo_ref(NULL, &screen->poly_cache);
352 nouveau_bo_ref(NULL, &screen->parm);
353
354 nouveau_heap_destroy(&screen->lib_code);
355 nouveau_heap_destroy(&screen->text_heap);
356
357 FREE(screen->tic.entries);
358
359 nouveau_mm_destroy(screen->mm_VRAM_fe0);
360
361 nouveau_object_del(&screen->eng3d);
362 nouveau_object_del(&screen->eng2d);
363 nouveau_object_del(&screen->m2mf);
364
365 nouveau_screen_fini(&screen->base);
366
367 FREE(screen);
368 }
369
370 static int
371 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
372 unsigned size, const uint32_t *data)
373 {
374 struct nouveau_pushbuf *push = screen->base.pushbuf;
375
376 size /= 4;
377
378 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
379 PUSH_DATA (push, (m - 0x3800) / 8);
380 PUSH_DATA (push, pos);
381 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
382 PUSH_DATA (push, pos);
383 PUSH_DATAp(push, data, size);
384
385 return pos + size;
386 }
387
388 static void
389 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
390 {
391 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
392 PUSH_DATA (push, 0xff);
393 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
394 PUSH_DATA (push, 0xff);
395 PUSH_DATA (push, 0xff);
396 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
397 PUSH_DATA (push, 0xff);
398 PUSH_DATA (push, 0xff);
399 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
400 PUSH_DATA (push, 0x3f);
401
402 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
403 PUSH_DATA (push, (3 << 16) | 3);
404 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
405 PUSH_DATA (push, (2 << 16) | 2);
406 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
407 PUSH_DATA (push, 1);
408
409 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
410 PUSH_DATA (push, 0);
411 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
412 PUSH_DATA (push, 0x10);
413 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
414 PUSH_DATA (push, 0x10);
415 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
416 PUSH_DATA (push, 0x10);
417 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
418 PUSH_DATA (push, 0x10);
419 PUSH_DATA (push, 0x10);
420 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
421 PUSH_DATA (push, 0x10);
422 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
423 PUSH_DATA (push, 0xe);
424
425 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
426 PUSH_DATA (push, 1 << 12);
427 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
428 PUSH_DATA (push, 0);
429 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
430 PUSH_DATA (push, 3);
431
432 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
433 PUSH_DATA (push, 0x3fffff);
434 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
435 PUSH_DATA (push, 1);
436 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
437 PUSH_DATA (push, 1);
438 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
439 PUSH_DATA (push, 3);
440
441 if (obj_class >= NVE4_3D_CLASS) {
442 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
443 PUSH_DATA (push, 1);
444 }
445
446 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
447 * are supposed to do */
448 }
449
450 static void
451 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
452 {
453 struct nvc0_screen *screen = nvc0_screen(pscreen);
454 struct nouveau_pushbuf *push = screen->base.pushbuf;
455
456 /* we need to do it after possible flush in MARK_RING */
457 *sequence = ++screen->base.fence.sequence;
458
459 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
460 PUSH_DATAh(push, screen->fence.bo->offset);
461 PUSH_DATA (push, screen->fence.bo->offset);
462 PUSH_DATA (push, *sequence);
463 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
464 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
465 }
466
467 static u32
468 nvc0_screen_fence_update(struct pipe_screen *pscreen)
469 {
470 struct nvc0_screen *screen = nvc0_screen(pscreen);
471 return screen->fence.map[0];
472 }
473
474 static int
475 nvc0_screen_init_compute(struct nvc0_screen *screen)
476 {
477 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
478
479 switch (screen->base.device->chipset & 0xf0) {
480 case 0xc0:
481 case 0xd0:
482 /* Using COMPUTE has weird effects on 3D state, we need to
483 * investigate this further before enabling it by default.
484 */
485 if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
486 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
487 return 0;
488 case 0xe0:
489 case 0xf0:
490 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
491 default:
492 return -1;
493 }
494 }
495
496 boolean
497 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
498 uint32_t lpos, uint32_t lneg, uint32_t cstack)
499 {
500 struct nouveau_bo *bo = NULL;
501 int ret;
502 uint64_t size = (lpos + lneg) * 32 + cstack;
503
504 if (size >= (1 << 20)) {
505 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
506 return FALSE;
507 }
508
509 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
510 size = align(size, 0x8000);
511 size *= screen->mp_count;
512
513 size = align(size, 1 << 17);
514
515 ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
516 NULL, &bo);
517 if (ret) {
518 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
519 return FALSE;
520 }
521 nouveau_bo_ref(NULL, &screen->tls);
522 screen->tls = bo;
523 return TRUE;
524 }
525
526 #define FAIL_SCREEN_INIT(str, err) \
527 do { \
528 NOUVEAU_ERR(str, err); \
529 nvc0_screen_destroy(pscreen); \
530 return NULL; \
531 } while(0)
532
533 struct pipe_screen *
534 nvc0_screen_create(struct nouveau_device *dev)
535 {
536 struct nvc0_screen *screen;
537 struct pipe_screen *pscreen;
538 struct nouveau_object *chan;
539 struct nouveau_pushbuf *push;
540 uint64_t value;
541 uint32_t obj_class;
542 int ret;
543 unsigned i;
544 union nouveau_bo_config mm_config;
545
546 switch (dev->chipset & ~0xf) {
547 case 0xc0:
548 case 0xd0:
549 case 0xe0:
550 case 0xf0:
551 break;
552 default:
553 return NULL;
554 }
555
556 screen = CALLOC_STRUCT(nvc0_screen);
557 if (!screen)
558 return NULL;
559 pscreen = &screen->base.base;
560
561 ret = nouveau_screen_init(&screen->base, dev);
562 if (ret) {
563 nvc0_screen_destroy(pscreen);
564 return NULL;
565 }
566 chan = screen->base.channel;
567 push = screen->base.pushbuf;
568 push->user_priv = screen;
569 push->rsvd_kick = 5;
570
571 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
572 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
573 screen->base.sysmem_bindings |=
574 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
575
576 pscreen->destroy = nvc0_screen_destroy;
577 pscreen->context_create = nvc0_create;
578 pscreen->is_format_supported = nvc0_screen_is_format_supported;
579 pscreen->get_param = nvc0_screen_get_param;
580 pscreen->get_shader_param = nvc0_screen_get_shader_param;
581 pscreen->get_paramf = nvc0_screen_get_paramf;
582 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
583
584 nvc0_screen_init_resource_functions(pscreen);
585
586 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
587 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
588
589 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
590 &screen->fence.bo);
591 if (ret)
592 goto fail;
593 nouveau_bo_map(screen->fence.bo, 0, NULL);
594 screen->fence.map = screen->fence.bo->map;
595 screen->base.fence.emit = nvc0_screen_fence_emit;
596 screen->base.fence.update = nvc0_screen_fence_update;
597
598 switch (dev->chipset & 0xf0) {
599 case 0xf0:
600 obj_class = NVF0_P2MF_CLASS;
601 break;
602 case 0xe0:
603 obj_class = NVE4_P2MF_CLASS;
604 break;
605 default:
606 obj_class = NVC0_M2MF_CLASS;
607 break;
608 }
609 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
610 &screen->m2mf);
611 if (ret)
612 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
613
614 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
615 PUSH_DATA (push, screen->m2mf->oclass);
616 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
617 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
618 PUSH_DATA (push, 0xa0b5);
619 }
620
621 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
622 &screen->eng2d);
623 if (ret)
624 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
625
626 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
627 PUSH_DATA (push, screen->eng2d->oclass);
628 BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
629 PUSH_DATA (push, 0);
630 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
631 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
632 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
633 PUSH_DATA (push, 0);
634 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
635 PUSH_DATA (push, 0);
636 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
637 PUSH_DATA (push, 0x3f);
638 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
639 PUSH_DATA (push, 1);
640
641 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
642 PUSH_DATAh(push, screen->fence.bo->offset + 16);
643 PUSH_DATA (push, screen->fence.bo->offset + 16);
644
645 switch (dev->chipset & 0xf0) {
646 case 0xf0:
647 obj_class = NVF0_3D_CLASS;
648 break;
649 case 0xe0:
650 obj_class = NVE4_3D_CLASS;
651 break;
652 case 0xd0:
653 case 0xc0:
654 default:
655 switch (dev->chipset) {
656 case 0xd9:
657 case 0xc8:
658 obj_class = NVC8_3D_CLASS;
659 break;
660 case 0xc1:
661 obj_class = NVC1_3D_CLASS;
662 break;
663 default:
664 obj_class = NVC0_3D_CLASS;
665 break;
666 }
667 break;
668 }
669 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
670 &screen->eng3d);
671 if (ret)
672 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
673 screen->base.class_3d = obj_class;
674
675 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
676 PUSH_DATA (push, screen->eng3d->oclass);
677
678 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
679 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
680
681 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
682 /* kill shaders after about 1 second (at 100 MHz) */
683 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
684 PUSH_DATA (push, 0x17);
685 }
686
687 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
688 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
689 for (i = 0; i < 8; ++i)
690 PUSH_DATA(push, dev->drm_version >= 0x01000101);
691
692 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
693 PUSH_DATA (push, 1);
694
695 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
696 PUSH_DATA (push, 0);
697 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
698 PUSH_DATA (push, 0);
699 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
700 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
701 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
702 PUSH_DATA (push, 0);
703 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
704 PUSH_DATA (push, 1);
705 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
706 PUSH_DATA (push, 0);
707 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
708 PUSH_DATA (push, 1);
709 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
710 PUSH_DATA (push, 0);
711 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
712 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
713 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
714 } else {
715 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
716 PUSH_DATA (push, 15);
717 }
718 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
719 PUSH_DATA (push, 8); /* 128 */
720 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
721 PUSH_DATA (push, 1);
722 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
723 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
724 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
725 }
726
727 nvc0_magic_3d_init(push, screen->eng3d->oclass);
728
729 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
730 &screen->text);
731 if (ret)
732 goto fail;
733
734 /* XXX: getting a page fault at the end of the code buffer every few
735 * launches, don't use the last 256 bytes to work around them - prefetch ?
736 */
737 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
738
739 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
740 &screen->uniform_bo);
741 if (ret)
742 goto fail;
743
744 for (i = 0; i < 5; ++i) {
745 /* TIC and TSC entries for each unit (nve4+ only) */
746 /* auxiliary constants (6 user clip planes, base instance id) */
747 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
748 PUSH_DATA (push, 512);
749 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
750 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
751 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
752 PUSH_DATA (push, (15 << 4) | 1);
753 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
754 unsigned j;
755 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
756 PUSH_DATA (push, 0);
757 for (j = 0; j < 8; ++j)
758 PUSH_DATA(push, j);
759 } else {
760 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
761 PUSH_DATA (push, 0x54);
762 }
763 }
764 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
765 PUSH_DATA (push, 0);
766
767 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
768 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
769 PUSH_DATA (push, 256);
770 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
771 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
772 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
773 PUSH_DATA (push, 0);
774 PUSH_DATAf(push, 0.0f);
775 PUSH_DATAf(push, 0.0f);
776 PUSH_DATAf(push, 0.0f);
777 PUSH_DATAf(push, 0.0f);
778 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
779 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
780 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
781
782 if (dev->drm_version >= 0x01000101) {
783 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
784 if (ret) {
785 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
786 goto fail;
787 }
788 } else {
789 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
790 value = (8 << 8) | 4;
791 else
792 value = (16 << 8) | 4;
793 }
794 screen->mp_count = value >> 8;
795 screen->mp_count_compute = screen->mp_count;
796
797 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
798
799 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
800 PUSH_DATAh(push, screen->text->offset);
801 PUSH_DATA (push, screen->text->offset);
802 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
803 PUSH_DATAh(push, screen->tls->offset);
804 PUSH_DATA (push, screen->tls->offset);
805 PUSH_DATA (push, screen->tls->size >> 32);
806 PUSH_DATA (push, screen->tls->size);
807 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
808 PUSH_DATA (push, 0);
809 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
810 PUSH_DATA (push, 0);
811
812 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
813 &screen->poly_cache);
814 if (ret)
815 goto fail;
816
817 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
818 PUSH_DATAh(push, screen->poly_cache->offset);
819 PUSH_DATA (push, screen->poly_cache->offset);
820 PUSH_DATA (push, 3);
821
822 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
823 &screen->txc);
824 if (ret)
825 goto fail;
826
827 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
828 PUSH_DATAh(push, screen->txc->offset);
829 PUSH_DATA (push, screen->txc->offset);
830 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
831
832 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
833 PUSH_DATAh(push, screen->txc->offset + 65536);
834 PUSH_DATA (push, screen->txc->offset + 65536);
835 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
836
837 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
838 PUSH_DATA (push, 0);
839 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
840 PUSH_DATA (push, 0);
841 PUSH_DATA (push, 0);
842 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
843 PUSH_DATA (push, 0x3f);
844
845 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
846 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
847 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
848 for (i = 0; i < 8 * 2; ++i)
849 PUSH_DATA(push, 0);
850 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
851 PUSH_DATA (push, 0);
852 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
853 PUSH_DATA (push, 0);
854
855 /* neither scissors, viewport nor stencil mask should affect clears */
856 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
857 PUSH_DATA (push, 0);
858
859 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
860 PUSH_DATA (push, 1);
861 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
862 PUSH_DATAf(push, 0.0f);
863 PUSH_DATAf(push, 1.0f);
864 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
865 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
866
867 /* We use scissors instead of exact view volume clipping,
868 * so they're always enabled.
869 */
870 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
871 PUSH_DATA (push, 1);
872 PUSH_DATA (push, 8192 << 16);
873 PUSH_DATA (push, 8192 << 16);
874
875 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
876
877 i = 0;
878 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
879 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
880 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
881 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
882 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
883 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
884 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
885
886 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
887 PUSH_DATA (push, 1);
888 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
889 PUSH_DATA (push, 1);
890 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
891 PUSH_DATA (push, 0x40);
892 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
893 PUSH_DATA (push, 0);
894 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
895 PUSH_DATA (push, 0x30);
896 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
897 PUSH_DATA (push, 3);
898 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
899 PUSH_DATA (push, 0x20);
900 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
901 PUSH_DATA (push, 0x00);
902
903 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
904 PUSH_DATA (push, 0);
905 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
906 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
907
908 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
909
910 if (nvc0_screen_init_compute(screen))
911 goto fail;
912
913 PUSH_KICK (push);
914
915 screen->tic.entries = CALLOC(4096, sizeof(void *));
916 screen->tsc.entries = screen->tic.entries + 2048;
917
918 mm_config.nvc0.tile_mode = 0;
919 mm_config.nvc0.memtype = 0xfe0;
920 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
921
922 if (!nvc0_blitter_create(screen))
923 goto fail;
924
925 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
926
927 return pscreen;
928
929 fail:
930 nvc0_screen_destroy(pscreen);
931 return NULL;
932 }
933
934 int
935 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
936 {
937 int i = screen->tic.next;
938
939 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
940 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
941
942 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
943
944 if (screen->tic.entries[i])
945 nv50_tic_entry(screen->tic.entries[i])->id = -1;
946
947 screen->tic.entries[i] = entry;
948 return i;
949 }
950
951 int
952 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
953 {
954 int i = screen->tsc.next;
955
956 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
957 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
958
959 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
960
961 if (screen->tsc.entries[i])
962 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
963
964 screen->tsc.entries[i] = entry;
965 return i;
966 }