src/gallium/drivers/nvc0/nvc0_state_validate.c

   1
   2 #include "nvc0_context.h"
   3 #include "os/os_time.h"
   4
   5 static void
   6 nvc0_validate_zcull(struct nvc0_context *nvc0)
   7 {
   8     struct nouveau_channel *chan = nvc0->screen->base.channel;
   9     struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
  10     struct nvc0_surface *sf = nvc0_surface(fb->zsbuf);
  11     struct nvc0_miptree *mt = nvc0_miptree(sf->base.texture);
  12     struct nouveau_bo *bo = mt->base.bo;
  13     uint32_t size;
  14     uint32_t offset = align(mt->total_size, 1 << 17);
  15     unsigned width, height;
  16
  17     assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
  18
  19     size = mt->total_size * 2;
  20
  21     height = align(fb->height, 32);
  22     width = fb->width % 224;
  23     if (width)
  24        width = fb->width + (224 - width);
  25     else
  26        width = fb->width;
  27
  28     MARK_RING (chan, 23, 4);
  29     BEGIN_RING(chan, RING_3D_(0x1590), 1); /* ZCULL_REGION_INDEX (bits 0x3f) */
  30     OUT_RING  (chan, 0);
  31     BEGIN_RING(chan, RING_3D_(0x07e8), 2); /* ZCULL_ADDRESS_A_HIGH */
  32     OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  33     OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  34     offset += 1 << 17;
  35     BEGIN_RING(chan, RING_3D_(0x07f0), 2); /* ZCULL_ADDRESS_B_HIGH */
  36     OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  37     OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  38     BEGIN_RING(chan, RING_3D_(0x07e0), 2);
  39     OUT_RING  (chan, size);
  40     OUT_RING  (chan, size >> 16);
  41     BEGIN_RING(chan, RING_3D_(0x15c8), 1); /* bits 0x3 */
  42     OUT_RING  (chan, 2);
  43     BEGIN_RING(chan, RING_3D_(0x07c0), 4); /* ZCULL dimensions */
  44     OUT_RING  (chan, width);
  45     OUT_RING  (chan, height);
  46     OUT_RING  (chan, 1);
  47     OUT_RING  (chan, 0);
  48     BEGIN_RING(chan, RING_3D_(0x15fc), 2);
  49     OUT_RING  (chan, 0); /* bits 0xffff */
  50     OUT_RING  (chan, 0); /* bits 0xffff */
  51     BEGIN_RING(chan, RING_3D_(0x1958), 1);
  52     OUT_RING  (chan, 0); /* bits ~0 */
  53 }
  54
  55 static void
  56 nvc0_validate_fb(struct nvc0_context *nvc0)
  57 {
  58     struct nouveau_channel *chan = nvc0->screen->base.channel;
  59     struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
  60     unsigned i;
  61     boolean serialize = FALSE;
  62
  63     nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_FRAME);
  64
  65     BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
  66     OUT_RING  (chan, (076543210 << 4) | fb->nr_cbufs);
  67     BEGIN_RING(chan, RING_3D(SCREEN_SCISSOR_HORIZ), 2);
  68     OUT_RING  (chan, fb->width << 16);
  69     OUT_RING  (chan, fb->height << 16);
  70
  71     MARK_RING(chan, 9 * fb->nr_cbufs, 2 * fb->nr_cbufs);
  72
  73     for (i = 0; i < fb->nr_cbufs; ++i) {
  74         struct nvc0_miptree *mt = nvc0_miptree(fb->cbufs[i]->texture);
  75         struct nvc0_surface *sf = nvc0_surface(fb->cbufs[i]);
  76         struct nouveau_bo *bo = mt->base.bo;
  77         uint32_t offset = sf->offset;
  78
  79         BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(i)), 8);
  80         OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  81         OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  82         OUT_RING  (chan, sf->width);
  83         OUT_RING  (chan, sf->height);
  84         OUT_RING  (chan, nvc0_format_table[sf->base.format].rt);
  85         OUT_RING  (chan, (mt->layout_3d << 16) |
  86                    mt->level[sf->base.u.tex.level].tile_mode);
  87         OUT_RING  (chan, sf->depth);
  88         OUT_RING  (chan, mt->layer_stride >> 2);
  89
  90         if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
  91            serialize = TRUE;
  92         mt->base.status |=  NOUVEAU_BUFFER_STATUS_GPU_WRITING;
  93         mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
  94
  95         nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
  96                                  NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  97     }
  98
  99     if (fb->zsbuf) {
 100         struct nvc0_miptree *mt = nvc0_miptree(fb->zsbuf->texture);
 101         struct nvc0_surface *sf = nvc0_surface(fb->zsbuf);
 102         struct nouveau_bo *bo = mt->base.bo;
 103         int unk = mt->base.base.target == PIPE_TEXTURE_2D;
 104         uint32_t offset = sf->offset;
 105
 106         MARK_RING (chan, 12, 2);
 107         BEGIN_RING(chan, RING_3D(ZETA_ADDRESS_HIGH), 5);
 108         OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 109         OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 110         OUT_RING  (chan, nvc0_format_table[fb->zsbuf->format].rt);
 111         OUT_RING  (chan, mt->level[sf->base.u.tex.level].tile_mode);
 112         OUT_RING  (chan, mt->layer_stride >> 2);
 113         BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
 114         OUT_RING  (chan, 1);
 115         BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3);
 116         OUT_RING  (chan, sf->width);
 117         OUT_RING  (chan, sf->height);
 118         OUT_RING  (chan, (unk << 16) | sf->depth);
 119
 120         if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
 121            serialize = TRUE;
 122         mt->base.status |=  NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 123         mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
 124
 125         nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
 126                                  NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 127     } else {
 128         BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
 129         OUT_RING  (chan, 0);
 130     }
 131
 132     if (serialize) {
 133        BEGIN_RING(chan, RING_3D(SERIALIZE), 1);
 134        OUT_RING  (chan, 0);
 135     }
 136 }
 137
 138 static void
 139 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
 140 {
 141     struct nouveau_channel *chan = nvc0->screen->base.channel;
 142
 143     BEGIN_RING(chan, RING_3D(BLEND_COLOR(0)), 4);
 144     OUT_RINGf (chan, nvc0->blend_colour.color[0]);
 145     OUT_RINGf (chan, nvc0->blend_colour.color[1]);
 146     OUT_RINGf (chan, nvc0->blend_colour.color[2]);
 147     OUT_RINGf (chan, nvc0->blend_colour.color[3]);
 148 }
 149
 150 static void
 151 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
 152 {
 153     struct nouveau_channel *chan = nvc0->screen->base.channel;
 154
 155     BEGIN_RING(chan, RING_3D(STENCIL_FRONT_FUNC_REF), 1);
 156     OUT_RING  (chan, nvc0->stencil_ref.ref_value[0]);
 157     BEGIN_RING(chan, RING_3D(STENCIL_BACK_FUNC_REF), 1);
 158     OUT_RING  (chan, nvc0->stencil_ref.ref_value[1]);
 159 }
 160
 161 static void
 162 nvc0_validate_stipple(struct nvc0_context *nvc0)
 163 {
 164     struct nouveau_channel *chan = nvc0->screen->base.channel;
 165     unsigned i;
 166
 167     BEGIN_RING(chan, RING_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
 168     for (i = 0; i < 32; ++i)
 169         OUT_RING(chan, util_bswap32(nvc0->stipple.stipple[i]));
 170 }
 171
 172 static void
 173 nvc0_validate_scissor(struct nvc0_context *nvc0)
 174 {
 175     struct nouveau_channel *chan = nvc0->screen->base.channel;
 176     struct pipe_scissor_state *s = &nvc0->scissor;
 177
 178     if (!(nvc0->dirty & NVC0_NEW_SCISSOR) &&
 179         nvc0->rast->pipe.scissor == nvc0->state.scissor)
 180        return;
 181     nvc0->state.scissor = nvc0->rast->pipe.scissor;
 182
 183     BEGIN_RING(chan, RING_3D(SCISSOR_HORIZ(0)), 2);
 184     if (nvc0->rast->pipe.scissor) {
 185        OUT_RING(chan, (s->maxx << 16) | s->minx);
 186        OUT_RING(chan, (s->maxy << 16) | s->miny);
 187     } else {
 188        OUT_RING(chan, (0xffff << 16) | 0);
 189        OUT_RING(chan, (0xffff << 16) | 0);
 190     }
 191 }
 192
 193 static void
 194 nvc0_validate_viewport(struct nvc0_context *nvc0)
 195 {
 196     struct nouveau_channel *chan = nvc0->screen->base.channel;
 197     struct pipe_viewport_state *vp = &nvc0->viewport;
 198     int x, y, w, h;
 199     float zmin, zmax;
 200
 201     BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSLATE_X(0)), 3);
 202     OUT_RINGf (chan, vp->translate[0]);
 203     OUT_RINGf (chan, vp->translate[1]);
 204     OUT_RINGf (chan, vp->translate[2]);
 205     BEGIN_RING(chan, RING_3D(VIEWPORT_SCALE_X(0)), 3);
 206     OUT_RINGf (chan, vp->scale[0]);
 207     OUT_RINGf (chan, vp->scale[1]);
 208     OUT_RINGf (chan, vp->scale[2]);
 209
 210     /* now set the viewport rectangle to viewport dimensions for clipping */
 211
 212     x = (int)(vp->translate[0] - fabsf(vp->scale[0]));
 213     y = (int)(vp->translate[1] - fabsf(vp->scale[1]));
 214     w = (int)fabsf(2.0f * vp->scale[0]);
 215     h = (int)fabsf(2.0f * vp->scale[1]);
 216     zmin = vp->translate[2] - fabsf(vp->scale[2]);
 217     zmax = vp->translate[2] + fabsf(vp->scale[2]);
 218
 219     BEGIN_RING(chan, RING_3D(VIEWPORT_HORIZ(0)), 2);
 220     OUT_RING  (chan, (w << 16) | x);
 221     OUT_RING  (chan, (h << 16) | y);
 222     BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 223     OUT_RINGf (chan, zmin);
 224     OUT_RINGf (chan, zmax);
 225 }
 226
 227 static void
 228 nvc0_validate_clip(struct nvc0_context *nvc0)
 229 {
 230    struct nouveau_channel *chan = nvc0->screen->base.channel;
 231    uint32_t clip;
 232
 233    if (nvc0->clip.depth_clamp) {
 234       clip =
 235          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
 236          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
 237          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
 238          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
 239    } else {
 240       clip = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
 241    }
 242
 243    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 244    OUT_RING  (chan, clip);
 245
 246    if (nvc0->clip.nr) {
 247       struct nouveau_bo *bo = nvc0->screen->uniforms;
 248
 249       MARK_RING (chan, 6 + nvc0->clip.nr * 4, 2);
 250       BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 251       OUT_RING  (chan, 256);
 252       OUT_RELOCh(chan, bo, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 253       OUT_RELOCl(chan, bo, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 254       BEGIN_RING_1I(chan, RING_3D(CB_POS), nvc0->clip.nr * 4 + 1);
 255       OUT_RING  (chan, 0);
 256       OUT_RINGp (chan, &nvc0->clip.ucp[0][0], nvc0->clip.nr * 4);
 257
 258       BEGIN_RING(chan, RING_3D(VP_CLIP_DISTANCE_ENABLE), 1);
 259       OUT_RING  (chan, (1 << nvc0->clip.nr) - 1);
 260    } else {
 261       IMMED_RING(chan, RING_3D(VP_CLIP_DISTANCE_ENABLE), 0);
 262    }
 263 }
 264
 265 static void
 266 nvc0_validate_blend(struct nvc0_context *nvc0)
 267 {
 268    struct nouveau_channel *chan = nvc0->screen->base.channel;
 269
 270    WAIT_RING(chan, nvc0->blend->size);
 271    OUT_RINGp(chan, nvc0->blend->state, nvc0->blend->size);
 272 }
 273
 274 static void
 275 nvc0_validate_zsa(struct nvc0_context *nvc0)
 276 {
 277    struct nouveau_channel *chan = nvc0->screen->base.channel;
 278
 279    WAIT_RING(chan, nvc0->zsa->size);
 280    OUT_RINGp(chan, nvc0->zsa->state, nvc0->zsa->size);
 281 }
 282
 283 static void
 284 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
 285 {
 286    struct nouveau_channel *chan = nvc0->screen->base.channel;
 287
 288    WAIT_RING(chan, nvc0->rast->size);
 289    OUT_RINGp(chan, nvc0->rast->state, nvc0->rast->size);
 290 }
 291
 292 static void
 293 nvc0_validate_sprite_coords(struct nvc0_context *nvc0)
 294 {
 295    struct nouveau_channel *chan = nvc0->screen->base.channel;
 296    uint32_t reg;
 297
 298    if (nvc0->rast->pipe.sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT)
 299       reg = NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT;
 300    else
 301       reg = NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
 302
 303    if (nvc0->rast->pipe.point_quad_rasterization) {
 304       uint32_t en = nvc0->rast->pipe.sprite_coord_enable;
 305
 306       while (en) {
 307          int i = ffs(en) - 1;
 308          en &= ~(1 << i);
 309          if (i >= 0 && i < 8)
 310             reg |= 8 << i;
 311       }
 312    }
 313
 314    BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
 315    OUT_RING  (chan, reg);
 316 }
 317
 318 static void
 319 nvc0_constbufs_validate(struct nvc0_context *nvc0)
 320 {
 321    struct nouveau_channel *chan = nvc0->screen->base.channel;
 322    struct nouveau_bo *bo;
 323    unsigned s;
 324
 325    for (s = 0; s < 5; ++s) {
 326       struct nv04_resource *res;
 327       int i;
 328
 329       while (nvc0->constbuf_dirty[s]) {
 330          unsigned base = 0;
 331          unsigned offset = 0, words = 0;
 332          boolean rebind = TRUE;
 333
 334          i = ffs(nvc0->constbuf_dirty[s]) - 1;
 335          nvc0->constbuf_dirty[s] &= ~(1 << i);
 336
 337          res = nv04_resource(nvc0->constbuf[s][i]);
 338          if (!res) {
 339             BEGIN_RING(chan, RING_3D(CB_BIND(s)), 1);
 340             OUT_RING  (chan, (i << 4) | 0);
 341             if (i == 0)
 342                nvc0->state.uniform_buffer_bound[s] = 0;
 343             continue;
 344          }
 345
 346          if (!nouveau_resource_mapped_by_gpu(&res->base)) {
 347             if (i == 0) {
 348                base = s << 16;
 349                bo = nvc0->screen->uniforms;
 350
 351                if (nvc0->state.uniform_buffer_bound[s] >= res->base.width0)
 352                   rebind = FALSE;
 353                else
 354                   nvc0->state.uniform_buffer_bound[s] =
 355                      align(res->base.width0, 0x100);
 356             } else {
 357                bo = res->bo;
 358             }
 359 #if 0
 360             nvc0_m2mf_push_linear(nvc0, bo, NOUVEAU_BO_VRAM,
 361                                   base, res->base.width0, res->data);
 362             BEGIN_RING(chan, RING_3D_(0x021c), 1);
 363             OUT_RING  (chan, 0x1111);
 364 #else
 365             words = res->base.width0 / 4;
 366 #endif
 367          } else {
 368             bo = res->bo;
 369             if (i == 0)
 370                nvc0->state.uniform_buffer_bound[s] = 0;
 371          }
 372
 373          if (bo != nvc0->screen->uniforms)
 374             nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_CONSTANT, res,
 375                                      NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 376
 377          if (rebind) {
 378             MARK_RING (chan, 4, 2);
 379             BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 380             OUT_RING  (chan, align(res->base.width0, 0x100));
 381             OUT_RELOCh(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 382             OUT_RELOCl(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 383             BEGIN_RING(chan, RING_3D(CB_BIND(s)), 1);
 384             OUT_RING  (chan, (i << 4) | 1);
 385          }
 386
 387          while (words) {
 388             unsigned nr = AVAIL_RING(chan);
 389
 390             if (nr < 16) {
 391                FIRE_RING(chan);
 392                continue;
 393             }
 394             nr = MIN2(MIN2(nr - 6, words), NV04_PFIFO_MAX_PACKET_LEN - 1);
 395
 396             MARK_RING (chan, nr + 5, 2);
 397             BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 398             OUT_RING  (chan, align(res->base.width0, 0x100));
 399             OUT_RELOCh(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 400             OUT_RELOCl(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 401             BEGIN_RING_1I(chan, RING_3D(CB_POS), nr + 1);
 402             OUT_RING  (chan, offset);
 403             OUT_RINGp (chan, &res->data[offset], nr);
 404
 405             offset += nr * 4;
 406             words -= nr;
 407          }
 408       }
 409    }
 410 }
 411
 412 static struct state_validate {
 413     void (*func)(struct nvc0_context *);
 414     uint32_t states;
 415 } validate_list[] = {
 416     { nvc0_validate_fb,            NVC0_NEW_FRAMEBUFFER },
 417     { nvc0_validate_blend,         NVC0_NEW_BLEND },
 418     { nvc0_validate_zsa,           NVC0_NEW_ZSA },
 419     { nvc0_validate_rasterizer,    NVC0_NEW_RASTERIZER },
 420     { nvc0_validate_blend_colour,  NVC0_NEW_BLEND_COLOUR },
 421     { nvc0_validate_stencil_ref,   NVC0_NEW_STENCIL_REF },
 422     { nvc0_validate_stipple,       NVC0_NEW_STIPPLE },
 423     { nvc0_validate_scissor,       NVC0_NEW_SCISSOR | NVC0_NEW_RASTERIZER },
 424     { nvc0_validate_viewport,      NVC0_NEW_VIEWPORT },
 425     { nvc0_validate_clip,          NVC0_NEW_CLIP },
 426     { nvc0_vertprog_validate,      NVC0_NEW_VERTPROG },
 427     { nvc0_tctlprog_validate,      NVC0_NEW_TCTLPROG },
 428     { nvc0_tevlprog_validate,      NVC0_NEW_TEVLPROG },
 429     { nvc0_gmtyprog_validate,      NVC0_NEW_GMTYPROG },
 430     { nvc0_fragprog_validate,      NVC0_NEW_FRAGPROG },
 431     { nvc0_validate_sprite_coords, NVC0_NEW_RASTERIZER | NVC0_NEW_FRAGPROG },
 432     { nvc0_constbufs_validate,     NVC0_NEW_CONSTBUF },
 433     { nvc0_validate_textures,      NVC0_NEW_TEXTURES },
 434     { nvc0_validate_samplers,      NVC0_NEW_SAMPLERS },
 435     { nvc0_vertex_arrays_validate, NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS },
 436     { nvc0_tfb_validate,           NVC0_NEW_TFB | NVC0_NEW_TFB_BUFFERS }
 437 };
 438 #define validate_list_len (sizeof(validate_list) / sizeof(validate_list[0]))
 439
 440 boolean
 441 nvc0_state_validate(struct nvc0_context *nvc0)
 442 {
 443    unsigned i;
 444 #if 0
 445    if (nvc0->screen->cur_ctx != nvc0) /* FIXME: not everything is valid */
 446       nvc0->dirty = 0xffffffff;
 447 #endif
 448    nvc0->screen->cur_ctx = nvc0;
 449
 450    if (nvc0->dirty) {
 451       for (i = 0; i < validate_list_len; ++i) {
 452          struct state_validate *validate = &validate_list[i];
 453
 454          if (nvc0->dirty & validate->states)
 455             validate->func(nvc0);
 456       }
 457       nvc0->dirty = 0;
 458    }
 459
 460    nvc0_bufctx_emit_relocs(nvc0);
 461
 462    return TRUE;
 463 }