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nvc0: sync textures with render targets ourselves
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_state_validate.c
1
2 #include "nvc0_context.h"
3 #include "os/os_time.h"
4
5 static void
6 nvc0_validate_zcull(struct nvc0_context *nvc0)
7 {
8 struct nouveau_channel *chan = nvc0->screen->base.channel;
9 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
10 struct nvc0_surface *sf = nvc0_surface(fb->zsbuf);
11 struct nvc0_miptree *mt = nvc0_miptree(sf->base.texture);
12 struct nouveau_bo *bo = mt->base.bo;
13 uint32_t size;
14 uint32_t offset = align(mt->total_size, 1 << 17);
15 unsigned width, height;
16
17 assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
18
19 size = mt->total_size * 2;
20
21 height = align(fb->height, 32);
22 width = fb->width % 224;
23 if (width)
24 width = fb->width + (224 - width);
25 else
26 width = fb->width;
27
28 MARK_RING (chan, 23, 4);
29 BEGIN_RING(chan, RING_3D_(0x1590), 1); /* ZCULL_REGION_INDEX (bits 0x3f) */
30 OUT_RING (chan, 0);
31 BEGIN_RING(chan, RING_3D_(0x07e8), 2); /* ZCULL_ADDRESS_A_HIGH */
32 OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
33 OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
34 offset += 1 << 17;
35 BEGIN_RING(chan, RING_3D_(0x07f0), 2); /* ZCULL_ADDRESS_B_HIGH */
36 OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
37 OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
38 BEGIN_RING(chan, RING_3D_(0x07e0), 2);
39 OUT_RING (chan, size);
40 OUT_RING (chan, size >> 16);
41 BEGIN_RING(chan, RING_3D_(0x15c8), 1); /* bits 0x3 */
42 OUT_RING (chan, 2);
43 BEGIN_RING(chan, RING_3D_(0x07c0), 4); /* ZCULL dimensions */
44 OUT_RING (chan, width);
45 OUT_RING (chan, height);
46 OUT_RING (chan, 1);
47 OUT_RING (chan, 0);
48 BEGIN_RING(chan, RING_3D_(0x15fc), 2);
49 OUT_RING (chan, 0); /* bits 0xffff */
50 OUT_RING (chan, 0); /* bits 0xffff */
51 BEGIN_RING(chan, RING_3D_(0x1958), 1);
52 OUT_RING (chan, 0); /* bits ~0 */
53 }
54
55 static void
56 nvc0_validate_fb(struct nvc0_context *nvc0)
57 {
58 struct nouveau_channel *chan = nvc0->screen->base.channel;
59 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
60 unsigned i;
61 boolean serialize = FALSE;
62
63 nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_FRAME);
64
65 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
66 OUT_RING (chan, (076543210 << 4) | fb->nr_cbufs);
67 BEGIN_RING(chan, RING_3D(SCREEN_SCISSOR_HORIZ), 2);
68 OUT_RING (chan, fb->width << 16);
69 OUT_RING (chan, fb->height << 16);
70
71 MARK_RING(chan, 9 * fb->nr_cbufs, 2 * fb->nr_cbufs);
72
73 for (i = 0; i < fb->nr_cbufs; ++i) {
74 struct nvc0_miptree *mt = nvc0_miptree(fb->cbufs[i]->texture);
75 struct nvc0_surface *sf = nvc0_surface(fb->cbufs[i]);
76 struct nouveau_bo *bo = mt->base.bo;
77 uint32_t offset = sf->offset;
78
79 BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(i)), 8);
80 OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
81 OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
82 OUT_RING (chan, sf->width);
83 OUT_RING (chan, sf->height);
84 OUT_RING (chan, nvc0_format_table[sf->base.format].rt);
85 OUT_RING (chan, (mt->layout_3d << 16) |
86 mt->level[sf->base.u.tex.level].tile_mode);
87 OUT_RING (chan, sf->depth);
88 OUT_RING (chan, mt->layer_stride >> 2);
89
90 if (mt->base.status & NVC0_BUFFER_STATUS_GPU_READING)
91 serialize = TRUE;
92 mt->base.status |= NVC0_BUFFER_STATUS_GPU_WRITING;
93 mt->base.status &= ~NVC0_BUFFER_STATUS_GPU_READING;
94
95 nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
96 NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
97 }
98
99 if (fb->zsbuf) {
100 struct nvc0_miptree *mt = nvc0_miptree(fb->zsbuf->texture);
101 struct nvc0_surface *sf = nvc0_surface(fb->zsbuf);
102 struct nouveau_bo *bo = mt->base.bo;
103 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
104 uint32_t offset = sf->offset;
105
106 MARK_RING (chan, 12, 2);
107 BEGIN_RING(chan, RING_3D(ZETA_ADDRESS_HIGH), 5);
108 OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
109 OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
110 OUT_RING (chan, nvc0_format_table[fb->zsbuf->format].rt);
111 OUT_RING (chan, mt->level[sf->base.u.tex.level].tile_mode);
112 OUT_RING (chan, mt->layer_stride >> 2);
113 BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
114 OUT_RING (chan, 1);
115 BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3);
116 OUT_RING (chan, sf->width);
117 OUT_RING (chan, sf->height);
118 OUT_RING (chan, (unk << 16) | sf->depth);
119
120 if (mt->base.status & NVC0_BUFFER_STATUS_GPU_READING)
121 serialize = TRUE;
122 mt->base.status |= NVC0_BUFFER_STATUS_GPU_WRITING;
123 mt->base.status &= ~NVC0_BUFFER_STATUS_GPU_READING;
124
125 nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
126 NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
127 } else {
128 BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
129 OUT_RING (chan, 0);
130 }
131
132 if (serialize) {
133 BEGIN_RING(chan, RING_3D(SERIALIZE), 1);
134 OUT_RING (chan, 0);
135 }
136 }
137
138 static void
139 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
140 {
141 struct nouveau_channel *chan = nvc0->screen->base.channel;
142
143 BEGIN_RING(chan, RING_3D(BLEND_COLOR(0)), 4);
144 OUT_RINGf (chan, nvc0->blend_colour.color[0]);
145 OUT_RINGf (chan, nvc0->blend_colour.color[1]);
146 OUT_RINGf (chan, nvc0->blend_colour.color[2]);
147 OUT_RINGf (chan, nvc0->blend_colour.color[3]);
148 }
149
150 static void
151 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
152 {
153 struct nouveau_channel *chan = nvc0->screen->base.channel;
154
155 BEGIN_RING(chan, RING_3D(STENCIL_FRONT_FUNC_REF), 1);
156 OUT_RING (chan, nvc0->stencil_ref.ref_value[0]);
157 BEGIN_RING(chan, RING_3D(STENCIL_BACK_FUNC_REF), 1);
158 OUT_RING (chan, nvc0->stencil_ref.ref_value[1]);
159 }
160
161 static void
162 nvc0_validate_stipple(struct nvc0_context *nvc0)
163 {
164 struct nouveau_channel *chan = nvc0->screen->base.channel;
165 unsigned i;
166
167 BEGIN_RING(chan, RING_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
168 for (i = 0; i < 32; ++i)
169 OUT_RING(chan, util_bswap32(nvc0->stipple.stipple[i]));
170 }
171
172 static void
173 nvc0_validate_scissor(struct nvc0_context *nvc0)
174 {
175 struct nouveau_channel *chan = nvc0->screen->base.channel;
176 struct pipe_scissor_state *s = &nvc0->scissor;
177
178 if (!(nvc0->dirty & NVC0_NEW_SCISSOR) &&
179 nvc0->rast->pipe.scissor == nvc0->state.scissor)
180 return;
181 nvc0->state.scissor = nvc0->rast->pipe.scissor;
182
183 BEGIN_RING(chan, RING_3D(SCISSOR_HORIZ(0)), 2);
184 if (nvc0->rast->pipe.scissor) {
185 OUT_RING(chan, (s->maxx << 16) | s->minx);
186 OUT_RING(chan, (s->maxy << 16) | s->miny);
187 } else {
188 OUT_RING(chan, (0xffff << 16) | 0);
189 OUT_RING(chan, (0xffff << 16) | 0);
190 }
191 }
192
193 static void
194 nvc0_validate_viewport(struct nvc0_context *nvc0)
195 {
196 struct nouveau_channel *chan = nvc0->screen->base.channel;
197 struct pipe_viewport_state *vp = &nvc0->viewport;
198 int x, y, w, h;
199 float zmin, zmax;
200
201 BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSLATE_X(0)), 3);
202 OUT_RINGf (chan, vp->translate[0]);
203 OUT_RINGf (chan, vp->translate[1]);
204 OUT_RINGf (chan, vp->translate[2]);
205 BEGIN_RING(chan, RING_3D(VIEWPORT_SCALE_X(0)), 3);
206 OUT_RINGf (chan, vp->scale[0]);
207 OUT_RINGf (chan, vp->scale[1]);
208 OUT_RINGf (chan, vp->scale[2]);
209
210 /* now set the viewport rectangle to viewport dimensions for clipping */
211
212 x = (int)(vp->translate[0] - fabsf(vp->scale[0]));
213 y = (int)(vp->translate[1] - fabsf(vp->scale[1]));
214 w = (int)fabsf(2.0f * vp->scale[0]);
215 h = (int)fabsf(2.0f * vp->scale[1]);
216 zmin = vp->translate[2] - fabsf(vp->scale[2]);
217 zmax = vp->translate[2] + fabsf(vp->scale[2]);
218
219 BEGIN_RING(chan, RING_3D(VIEWPORT_HORIZ(0)), 2);
220 OUT_RING (chan, (w << 16) | x);
221 OUT_RING (chan, (h << 16) | y);
222 BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
223 OUT_RINGf (chan, zmin);
224 OUT_RINGf (chan, zmax);
225 }
226
227 static void
228 nvc0_validate_clip(struct nvc0_context *nvc0)
229 {
230 struct nouveau_channel *chan = nvc0->screen->base.channel;
231 uint32_t clip;
232
233 if (nvc0->clip.depth_clamp) {
234 clip =
235 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
236 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
237 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
238 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
239 } else {
240 clip = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
241 }
242
243 BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
244 OUT_RING (chan, clip);
245
246 if (nvc0->clip.nr) {
247 struct nouveau_bo *bo = nvc0->screen->uniforms;
248
249 MARK_RING (chan, 6 + nvc0->clip.nr * 4, 2);
250 BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
251 OUT_RING (chan, 256);
252 OUT_RELOCh(chan, bo, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
253 OUT_RELOCl(chan, bo, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
254 BEGIN_RING_1I(chan, RING_3D(CB_POS), nvc0->clip.nr * 4 + 1);
255 OUT_RING (chan, 0);
256 OUT_RINGp (chan, &nvc0->clip.ucp[0][0], nvc0->clip.nr * 4);
257
258 BEGIN_RING(chan, RING_3D(VP_CLIP_DISTANCE_ENABLE), 1);
259 OUT_RING (chan, (1 << nvc0->clip.nr) - 1);
260 } else {
261 IMMED_RING(chan, RING_3D(VP_CLIP_DISTANCE_ENABLE), 0);
262 }
263 }
264
265 static void
266 nvc0_validate_blend(struct nvc0_context *nvc0)
267 {
268 struct nouveau_channel *chan = nvc0->screen->base.channel;
269
270 WAIT_RING(chan, nvc0->blend->size);
271 OUT_RINGp(chan, nvc0->blend->state, nvc0->blend->size);
272 }
273
274 static void
275 nvc0_validate_zsa(struct nvc0_context *nvc0)
276 {
277 struct nouveau_channel *chan = nvc0->screen->base.channel;
278
279 WAIT_RING(chan, nvc0->zsa->size);
280 OUT_RINGp(chan, nvc0->zsa->state, nvc0->zsa->size);
281 }
282
283 static void
284 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
285 {
286 struct nouveau_channel *chan = nvc0->screen->base.channel;
287
288 WAIT_RING(chan, nvc0->rast->size);
289 OUT_RINGp(chan, nvc0->rast->state, nvc0->rast->size);
290 }
291
292 static void
293 nvc0_validate_sprite_coords(struct nvc0_context *nvc0)
294 {
295 struct nouveau_channel *chan = nvc0->screen->base.channel;
296 uint32_t reg;
297
298 if (nvc0->rast->pipe.sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT)
299 reg = NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT;
300 else
301 reg = NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
302
303 if (nvc0->rast->pipe.point_quad_rasterization) {
304 uint32_t en = nvc0->rast->pipe.sprite_coord_enable;
305 int i;
306 struct nvc0_program *prog = nvc0->fragprog;
307
308 while (en) {
309 i = ffs(en) - 1;
310 en &= ~(1 << i);
311 if (prog->fp.in_pos[i] >= 0xc0 && prog->fp.in_pos[i] < 0xe0)
312 reg |= 8 << ((prog->fp.in_pos[i] - 0xc0) / 4);
313 }
314 }
315
316 BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
317 OUT_RING (chan, reg);
318 }
319
320 static void
321 nvc0_constbufs_validate(struct nvc0_context *nvc0)
322 {
323 struct nouveau_channel *chan = nvc0->screen->base.channel;
324 struct nouveau_bo *bo;
325 unsigned s;
326
327 for (s = 0; s < 5; ++s) {
328 struct nvc0_resource *res;
329 int i;
330
331 while (nvc0->constbuf_dirty[s]) {
332 unsigned base = 0;
333 unsigned offset = 0, words = 0;
334 boolean rebind = TRUE;
335
336 i = ffs(nvc0->constbuf_dirty[s]) - 1;
337 nvc0->constbuf_dirty[s] &= ~(1 << i);
338
339 res = nvc0_resource(nvc0->constbuf[s][i]);
340 if (!res) {
341 BEGIN_RING(chan, RING_3D(CB_BIND(s)), 1);
342 OUT_RING (chan, (i << 4) | 0);
343 if (i == 0)
344 nvc0->state.uniform_buffer_bound[s] = 0;
345 continue;
346 }
347
348 if (!nvc0_resource_mapped_by_gpu(&res->base)) {
349 if (i == 0) {
350 base = s << 16;
351 bo = nvc0->screen->uniforms;
352
353 if (nvc0->state.uniform_buffer_bound[s] >= res->base.width0)
354 rebind = FALSE;
355 else
356 nvc0->state.uniform_buffer_bound[s] =
357 align(res->base.width0, 0x100);
358 } else {
359 bo = res->bo;
360 }
361 #if 0
362 nvc0_m2mf_push_linear(nvc0, bo, NOUVEAU_BO_VRAM,
363 base, res->base.width0, res->data);
364 BEGIN_RING(chan, RING_3D_(0x021c), 1);
365 OUT_RING (chan, 0x1111);
366 #else
367 words = res->base.width0 / 4;
368 #endif
369 } else {
370 bo = res->bo;
371 if (i == 0)
372 nvc0->state.uniform_buffer_bound[s] = 0;
373 }
374
375 if (bo != nvc0->screen->uniforms)
376 nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_CONSTANT, res,
377 NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
378
379 if (rebind) {
380 MARK_RING (chan, 4, 2);
381 BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
382 OUT_RING (chan, align(res->base.width0, 0x100));
383 OUT_RELOCh(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
384 OUT_RELOCl(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
385 BEGIN_RING(chan, RING_3D(CB_BIND(s)), 1);
386 OUT_RING (chan, (i << 4) | 1);
387 }
388
389 while (words) {
390 unsigned nr = AVAIL_RING(chan);
391
392 if (nr < 16) {
393 FIRE_RING(chan);
394 continue;
395 }
396 nr = MIN2(MIN2(nr - 6, words), NV04_PFIFO_MAX_PACKET_LEN - 1);
397
398 MARK_RING (chan, nr + 5, 2);
399 BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
400 OUT_RING (chan, align(res->base.width0, 0x100));
401 OUT_RELOCh(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
402 OUT_RELOCl(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
403 BEGIN_RING_1I(chan, RING_3D(CB_POS), nr + 1);
404 OUT_RING (chan, offset);
405 OUT_RINGp (chan, &res->data[offset], nr);
406
407 offset += nr * 4;
408 words -= nr;
409 }
410 }
411 }
412 }
413
414 static struct state_validate {
415 void (*func)(struct nvc0_context *);
416 uint32_t states;
417 } validate_list[] = {
418 { nvc0_validate_fb, NVC0_NEW_FRAMEBUFFER },
419 { nvc0_validate_blend, NVC0_NEW_BLEND },
420 { nvc0_validate_zsa, NVC0_NEW_ZSA },
421 { nvc0_validate_rasterizer, NVC0_NEW_RASTERIZER },
422 { nvc0_validate_blend_colour, NVC0_NEW_BLEND_COLOUR },
423 { nvc0_validate_stencil_ref, NVC0_NEW_STENCIL_REF },
424 { nvc0_validate_stipple, NVC0_NEW_STIPPLE },
425 { nvc0_validate_scissor, NVC0_NEW_SCISSOR | NVC0_NEW_RASTERIZER },
426 { nvc0_validate_viewport, NVC0_NEW_VIEWPORT },
427 { nvc0_validate_clip, NVC0_NEW_CLIP },
428 { nvc0_vertprog_validate, NVC0_NEW_VERTPROG },
429 { nvc0_tctlprog_validate, NVC0_NEW_TCTLPROG },
430 { nvc0_tevlprog_validate, NVC0_NEW_TEVLPROG },
431 { nvc0_gmtyprog_validate, NVC0_NEW_GMTYPROG },
432 { nvc0_fragprog_validate, NVC0_NEW_FRAGPROG },
433 { nvc0_validate_sprite_coords, NVC0_NEW_RASTERIZER | NVC0_NEW_FRAGPROG },
434 { nvc0_constbufs_validate, NVC0_NEW_CONSTBUF },
435 { nvc0_validate_textures, NVC0_NEW_TEXTURES },
436 { nvc0_validate_samplers, NVC0_NEW_SAMPLERS },
437 { nvc0_vertex_arrays_validate, NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS },
438 { nvc0_tfb_validate, NVC0_NEW_TFB | NVC0_NEW_TFB_BUFFERS }
439 };
440 #define validate_list_len (sizeof(validate_list) / sizeof(validate_list[0]))
441
442 boolean
443 nvc0_state_validate(struct nvc0_context *nvc0)
444 {
445 unsigned i;
446 #if 0
447 if (nvc0->screen->cur_ctx != nvc0) /* FIXME: not everything is valid */
448 nvc0->dirty = 0xffffffff;
449 #endif
450 nvc0->screen->cur_ctx = nvc0;
451
452 if (nvc0->dirty) {
453 for (i = 0; i < validate_list_len; ++i) {
454 struct state_validate *validate = &validate_list[i];
455
456 if (nvc0->dirty & validate->states)
457 validate->func(nvc0);
458 }
459 nvc0->dirty = 0;
460 }
461
462 nvc0_bufctx_emit_relocs(nvc0);
463
464 return TRUE;
465 }