src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format_s3tc.h"
   4 #include "util/u_simple_screen.h"
   5
   6 #include "nouveau/nouveau_screen.h"
   7 #include "nouveau/nv_object.xml.h"
   8 #include "nvfx_context.h"
   9 #include "nvfx_screen.h"
  10 #include "nvfx_resource.h"
  11 #include "nvfx_tex.h"
  12
  13 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  14 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  15 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  16
  17 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  18 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  19 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  20
  21 static int
  22 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  23 {
  24         struct nvfx_screen *screen = nvfx_screen(pscreen);
  25
  26         switch (param) {
  27         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  28                 return 16;
  29         case PIPE_CAP_NPOT_TEXTURES:
  30                 return screen->advertise_npot;
  31         case PIPE_CAP_TWO_SIDED_STENCIL:
  32                 return 1;
  33         case PIPE_CAP_GLSL:
  34                 return 1;
  35         case PIPE_CAP_ANISOTROPIC_FILTER:
  36                 return 1;
  37         case PIPE_CAP_POINT_SPRITE:
  38                 return 1;
  39         case PIPE_CAP_MAX_RENDER_TARGETS:
  40                 return screen->use_nv4x ? 4 : 2;
  41         case PIPE_CAP_OCCLUSION_QUERY:
  42                 return 1;
  43         case PIPE_CAP_TIMER_QUERY:
  44                 return 0;
  45         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  46                 return 1;
  47         case PIPE_CAP_TEXTURE_SWIZZLE:
  48                 return 1;
  49         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  50                 return 13;
  51         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  52                 return 10;
  53         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  54                 return 13;
  55         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  56                 return !!screen->use_nv4x;
  57         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  58                 return 1;
  59         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  60                 return 0; /* We have 4 on nv40 - but unsupported currently */
  61         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  62                 return 0;
  63         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64                 return screen->advertise_blend_equation_separate;
  65         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  66                 return 16;
  67         case PIPE_CAP_INDEP_BLEND_ENABLE:
  68                 /* TODO: on nv40 we have separate color masks */
  69                 /* TODO: nv40 mrt blending is probably broken */
  70                 return 0;
  71         case PIPE_CAP_INDEP_BLEND_FUNC:
  72                 return 0;
  73         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  74                 return 0;
  75         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  76         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  77         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  78         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  79                 return 1;
  80         case PIPE_CAP_MAX_FS_INSTRUCTIONS:
  81         case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS:
  82         case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS:
  83         case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS:
  84                 return 4096;
  85         case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH:
  86                 /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
  87                    value (nv30:0/nv40:4) ? */
  88                 return screen->use_nv4x ? 4 : 0;
  89         case PIPE_CAP_MAX_FS_INPUTS:
  90                 return screen->use_nv4x ? 12 : 10;
  91         case PIPE_CAP_MAX_FS_CONSTS:
  92                 return screen->use_nv4x ? 224 : 32;
  93         case PIPE_CAP_MAX_FS_TEMPS:
  94                 return 32;
  95         case PIPE_CAP_MAX_FS_ADDRS:
  96                 return screen->use_nv4x ? 1 : 0;
  97         case PIPE_CAP_MAX_FS_PREDS:
  98                 return 0; /* we could expose these, but nothing uses them */
  99         case PIPE_CAP_MAX_VS_INSTRUCTIONS:
 100         case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS:
 101                 return screen->use_nv4x ? 512 : 256;
 102         case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS:
 103         case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS:
 104                 return screen->use_nv4x ? 512 : 0;
 105         case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH:
 106                 /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 107                    value (nv30:1/nv40:4) ? */
 108                 return screen->use_nv4x ? 4 : 1;
 109         case PIPE_CAP_MAX_VS_INPUTS:
 110                 return 16;
 111         case PIPE_CAP_MAX_VS_CONSTS:
 112                 /* - 6 is for clip planes; Gallium should be fixed to put
 113                  * them in the vertex shader itself, so we don't need to reserve these */
 114                 return (screen->use_nv4x ? 468 : 256) - 6;
 115         case PIPE_CAP_MAX_VS_TEMPS:
 116                 return screen->use_nv4x ? 32 : 13;
 117         case PIPE_CAP_MAX_VS_ADDRS:
 118                 return 2;
 119         case PIPE_CAP_MAX_VS_PREDS:
 120                 return 0; /* we could expose these, but nothing uses them */
 121         case PIPE_CAP_GEOMETRY_SHADER4:
 122                 return 0;
 123         case PIPE_CAP_DEPTH_CLAMP:
 124                 return 0; // TODO: implement depth clamp
 125         default:
 126                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
 127                 return 0;
 128         }
 129 }
 130
 131 static float
 132 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 133 {
 134         struct nvfx_screen *screen = nvfx_screen(pscreen);
 135
 136         switch (param) {
 137         case PIPE_CAP_MAX_LINE_WIDTH:
 138         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 139                 return 10.0;
 140         case PIPE_CAP_MAX_POINT_WIDTH:
 141         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 142                 return 64.0;
 143         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 144                 return screen->use_nv4x ? 16.0 : 8.0;
 145         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 146                 return 15.0;
 147         default:
 148                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 149                 return 0.0;
 150         }
 151 }
 152
 153 static boolean
 154 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 155                                      enum pipe_format format,
 156                                      enum pipe_texture_target target,
 157                                      unsigned sample_count,
 158                                      unsigned bind, unsigned geom_flags)
 159 {
 160         struct nvfx_screen *screen = nvfx_screen(pscreen);
 161
 162          if (sample_count > 1)
 163                 return FALSE;
 164
 165         if (bind & PIPE_BIND_RENDER_TARGET) {
 166                 switch (format) {
 167                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 168                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 169                 case PIPE_FORMAT_B5G6R5_UNORM:
 170                         break;
 171                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 172                         if(!screen->advertise_fp16)
 173                                 return FALSE;
 174                         break;
 175                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 176                         if(!screen->advertise_fp32)
 177                                 return FALSE;
 178                         break;
 179                 default:
 180                         return FALSE;
 181                 }
 182         }
 183
 184         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 185                 switch (format) {
 186                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 187                 case PIPE_FORMAT_X8Z24_UNORM:
 188                 case PIPE_FORMAT_Z16_UNORM:
 189                         break;
 190                 default:
 191                         return FALSE;
 192                 }
 193         }
 194
 195         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 196                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 197                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 198                         return FALSE;
 199                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 200                         return FALSE;
 201                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 202                         return FALSE;
 203                 if(screen->use_nv4x)
 204                 {
 205                         if(tf->fmt[4] < 0)
 206                                 return FALSE;
 207                 }
 208                 else
 209                 {
 210                         if(tf->fmt[0] < 0)
 211                                 return FALSE;
 212                 }
 213         }
 214
 215         // note that we do actually support everything through translate
 216         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 217                 unsigned type = nvfx_vertex_formats[format];
 218                 if(!type)
 219                         return FALSE;
 220         }
 221
 222         if (bind & PIPE_BIND_INDEX_BUFFER) {
 223                 // 8-bit indices supported, but not in hardware index buffer
 224                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 225                         return FALSE;
 226         }
 227
 228         if(bind & PIPE_BIND_STREAM_OUTPUT)
 229                 return FALSE;
 230
 231         return TRUE;
 232 }
 233
 234 static void
 235 nvfx_screen_destroy(struct pipe_screen *pscreen)
 236 {
 237         struct nvfx_screen *screen = nvfx_screen(pscreen);
 238
 239         nouveau_resource_destroy(&screen->vp_exec_heap);
 240         nouveau_resource_destroy(&screen->vp_data_heap);
 241         nouveau_resource_destroy(&screen->query_heap);
 242         nouveau_notifier_free(&screen->query);
 243         nouveau_notifier_free(&screen->sync);
 244         nouveau_grobj_free(&screen->eng3d);
 245         nvfx_screen_surface_takedown(pscreen);
 246
 247         nouveau_screen_fini(&screen->base);
 248
 249         FREE(pscreen);
 250 }
 251
 252 static void nv30_screen_init(struct nvfx_screen *screen)
 253 {
 254         struct nouveau_channel *chan = screen->base.channel;
 255         int i;
 256
 257         /* TODO: perhaps we should do some of this on nv40 too? */
 258         for (i=1; i<8; i++) {
 259                 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1));
 260                 OUT_RING(chan, 0);
 261                 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_VERT(i), 1));
 262                 OUT_RING(chan, 0);
 263         }
 264
 265         OUT_RING(chan, RING_3D(0x220, 1));
 266         OUT_RING(chan, 1);
 267
 268         OUT_RING(chan, RING_3D(0x03b0, 1));
 269         OUT_RING(chan, 0x00100000);
 270         OUT_RING(chan, RING_3D(0x1454, 1));
 271         OUT_RING(chan, 0);
 272         OUT_RING(chan, RING_3D(0x1d80, 1));
 273         OUT_RING(chan, 3);
 274         OUT_RING(chan, RING_3D(0x1450, 1));
 275         OUT_RING(chan, 0x00030004);
 276
 277         /* NEW */
 278         OUT_RING(chan, RING_3D(0x1e98, 1));
 279         OUT_RING(chan, 0);
 280         OUT_RING(chan, RING_3D(0x17e0, 3));
 281         OUT_RING(chan, fui(0.0));
 282         OUT_RING(chan, fui(0.0));
 283         OUT_RING(chan, fui(1.0));
 284         OUT_RING(chan, RING_3D(0x1f80, 16));
 285         for (i=0; i<16; i++) {
 286                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 287         }
 288
 289         OUT_RING(chan, RING_3D(0x120, 3));
 290         OUT_RING(chan, 0);
 291         OUT_RING(chan, 1);
 292         OUT_RING(chan, 2);
 293
 294         OUT_RING(chan, RING_3D(0x1d88, 1));
 295         OUT_RING(chan, 0x00001200);
 296
 297         OUT_RING(chan, RING_3D(NV30_3D_RC_ENABLE, 1));
 298         OUT_RING(chan, 0);
 299
 300         OUT_RING(chan, RING_3D(NV30_3D_DEPTH_RANGE_NEAR, 2));
 301         OUT_RING(chan, fui(0.0));
 302         OUT_RING(chan, fui(1.0));
 303
 304         OUT_RING(chan, RING_3D(NV30_3D_MULTISAMPLE_CONTROL, 1));
 305         OUT_RING(chan, 0xffff0000);
 306
 307         /* enables use of vp rather than fixed-function somehow */
 308         OUT_RING(chan, RING_3D(0x1e94, 1));
 309         OUT_RING(chan, 0x13);
 310 }
 311
 312 static void nv40_screen_init(struct nvfx_screen *screen)
 313 {
 314         struct nouveau_channel *chan = screen->base.channel;
 315
 316         OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 2));
 317         OUT_RING(chan, screen->base.channel->vram->handle);
 318         OUT_RING(chan, screen->base.channel->vram->handle);
 319
 320         OUT_RING(chan, RING_3D(0x1450, 1));
 321         OUT_RING(chan, 0x00000004);
 322
 323         OUT_RING(chan, RING_3D(0x1ea4, 3));
 324         OUT_RING(chan, 0x00000010);
 325         OUT_RING(chan, 0x01000100);
 326         OUT_RING(chan, 0xff800006);
 327
 328         /* vtxprog output routing */
 329         OUT_RING(chan, RING_3D(0x1fc4, 1));
 330         OUT_RING(chan, 0x06144321);
 331         OUT_RING(chan, RING_3D(0x1fc8, 2));
 332         OUT_RING(chan, 0xedcba987);
 333         OUT_RING(chan, 0x0000006f);
 334         OUT_RING(chan, RING_3D(0x1fd0, 1));
 335         OUT_RING(chan, 0x00171615);
 336         OUT_RING(chan, RING_3D(0x1fd4, 1));
 337         OUT_RING(chan, 0x001b1a19);
 338
 339         OUT_RING(chan, RING_3D(0x1ef8, 1));
 340         OUT_RING(chan, 0x0020ffff);
 341         OUT_RING(chan, RING_3D(0x1d64, 1));
 342         OUT_RING(chan, 0x01d300d4);
 343         OUT_RING(chan, RING_3D(0x1e94, 1));
 344         OUT_RING(chan, 0x00000001);
 345
 346         OUT_RING(chan, RING_3D(NV40_3D_MIPMAP_ROUNDING, 1));
 347         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 348 }
 349
 350 static unsigned
 351 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 352 {
 353         int vram_hack_default = 0;
 354         int vram_hack;
 355         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 356         // It may also depend on the specific card or the AGP/PCIe chipset.
 357         if(screen->base.device->chipset == 0x47 /* G70 */
 358                 || screen->base.device->chipset == 0x49 /* G71 */
 359                 || screen->base.device->chipset == 0x46 /* G72 */
 360                 )
 361                 vram_hack_default = 1;
 362         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 363
 364         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 365 }
 366
 367 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 368 {
 369         struct nvfx_screen* screen = chan->user_private;
 370         struct nvfx_context* nvfx = screen->cur_ctx;
 371         if(nvfx)
 372                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 373 }
 374
 375 struct pipe_screen *
 376 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 377 {
 378         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 379         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 380         struct nouveau_channel *chan;
 381         struct pipe_screen *pscreen;
 382         unsigned eng3d_class = 0;
 383         int ret, i;
 384
 385         if (!screen)
 386                 return NULL;
 387
 388         pscreen = &screen->base.base;
 389
 390         ret = nouveau_screen_init(&screen->base, dev);
 391         if (ret) {
 392                 nvfx_screen_destroy(pscreen);
 393                 return NULL;
 394         }
 395         chan = screen->base.channel;
 396         screen->cur_ctx = NULL;
 397         chan->user_private = screen;
 398         chan->flush_notify = nvfx_channel_flush_notify;
 399
 400         pscreen->winsys = ws;
 401         pscreen->destroy = nvfx_screen_destroy;
 402         pscreen->get_param = nvfx_screen_get_param;
 403         pscreen->get_paramf = nvfx_screen_get_paramf;
 404         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 405         pscreen->context_create = nvfx_create;
 406
 407         switch (dev->chipset & 0xf0) {
 408         case 0x30:
 409                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 410                         eng3d_class = NV30_3D;
 411                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 412                         eng3d_class = NV34_3D;
 413                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 414                         eng3d_class = NV35_3D;
 415                 break;
 416         case 0x40:
 417                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 418                         eng3d_class = NV40_3D;
 419                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 420                         eng3d_class = NV44_3D;
 421                 screen->is_nv4x = ~0;
 422                 break;
 423         case 0x60:
 424                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 425                         eng3d_class = NV44_3D;
 426                 screen->is_nv4x = ~0;
 427                 break;
 428         }
 429
 430         if (!eng3d_class) {
 431                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 432                 return NULL;
 433         }
 434
 435         screen->advertise_npot = !!screen->is_nv4x;
 436         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 437         screen->use_nv4x = screen->is_nv4x;
 438
 439         if(screen->is_nv4x) {
 440                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 441                         screen->use_nv4x = 0;
 442                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 443                         screen->advertise_npot = 0;
 444                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 445                         screen->advertise_blend_equation_separate = 0;
 446         }
 447
 448         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 449         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 450
 451         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 452         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 453         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 454
 455         /* We don't advertise these by default because filtering and blending doesn't work as
 456          * it should, due to several restrictions.
 457          * The only exception is fp16 on nv40.
 458          */
 459         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 460         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 461
 462         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 463
 464         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 465         if(eng3d_class == NV40_3D)
 466                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 467
 468         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 469                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 470
 471         nvfx_screen_init_resource_functions(pscreen);
 472
 473         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 474         if (ret) {
 475                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 476                 return FALSE;
 477         }
 478
 479         /* 2D engine setup */
 480         nvfx_screen_surface_init(pscreen);
 481
 482         /* Notifier for sync purposes */
 483         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 484         if (ret) {
 485                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 486                 nvfx_screen_destroy(pscreen);
 487                 return NULL;
 488         }
 489
 490         /* Query objects */
 491         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 492         {
 493                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 494                 if(!ret)
 495                         break;
 496         }
 497
 498         if (ret) {
 499                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 500                 nvfx_screen_destroy(pscreen);
 501                 return NULL;
 502         }
 503
 504         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 505         if (ret) {
 506                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 507                 nvfx_screen_destroy(pscreen);
 508                 return NULL;
 509         }
 510
 511         LIST_INITHEAD(&screen->query_list);
 512
 513         /* Vtxprog resources */
 514         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 515             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 516                 nvfx_screen_destroy(pscreen);
 517                 return NULL;
 518         }
 519
 520         BIND_RING(chan, screen->eng3d, 7);
 521
 522         /* Static eng3d initialisation */
 523         /* note that we just started using the channel, so we must have space in the pushbuffer */
 524         OUT_RING(chan, RING_3D(NV30_3D_DMA_NOTIFY, 1));
 525         OUT_RING(chan, screen->sync->handle);
 526         OUT_RING(chan, RING_3D(NV30_3D_DMA_TEXTURE0, 2));
 527         OUT_RING(chan, chan->vram->handle);
 528         OUT_RING(chan, chan->gart->handle);
 529         OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1));
 530         OUT_RING(chan, chan->vram->handle);
 531         OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 2));
 532         OUT_RING(chan, chan->vram->handle);
 533         OUT_RING(chan, chan->vram->handle);
 534         OUT_RING(chan, RING_3D(NV30_3D_DMA_VTXBUF0, 2));
 535         OUT_RING(chan, chan->vram->handle);
 536         OUT_RING(chan, chan->gart->handle);
 537
 538         OUT_RING(chan, RING_3D(NV30_3D_DMA_FENCE, 2));
 539         OUT_RING(chan, 0);
 540         OUT_RING(chan, screen->query->handle);
 541
 542         OUT_RING(chan, RING_3D(NV30_3D_DMA_UNK1AC, 2));
 543         OUT_RING(chan, chan->vram->handle);
 544         OUT_RING(chan, chan->vram->handle);
 545
 546         if(!screen->is_nv4x)
 547                 nv30_screen_init(screen);
 548         else
 549                 nv40_screen_init(screen);
 550
 551         return pscreen;
 552 }