src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format_s3tc.h"
   4 #include "util/u_simple_screen.h"
   5
   6 #include "nouveau/nouveau_screen.h"
   7
   8 #include "nvfx_context.h"
   9 #include "nvfx_screen.h"
  10 #include "nvfx_resource.h"
  11
  12 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
  13 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
  14 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
  15
  16 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
  17 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
  18 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
  19 * with same number of bits everywhere.
  20 */
  21 struct nouveau_winsys {
  22         struct pipe_winsys base;
  23
  24         struct pipe_screen *pscreen;
  25
  26         struct pipe_surface *front;
  27 };
  28 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  29 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  30 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  31
  32 static int
  33 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  34 {
  35         struct nvfx_screen *screen = nvfx_screen(pscreen);
  36
  37         switch (param) {
  38         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  39                 /* TODO: check this */
  40                 return screen->is_nv4x ? 16 : 8;
  41         case PIPE_CAP_NPOT_TEXTURES:
  42                 return !!screen->is_nv4x;
  43         case PIPE_CAP_TWO_SIDED_STENCIL:
  44                 return 1;
  45         case PIPE_CAP_GLSL:
  46                 return 0;
  47         case PIPE_CAP_ANISOTROPIC_FILTER:
  48                 return 1;
  49         case PIPE_CAP_POINT_SPRITE:
  50                 return 1;
  51         case PIPE_CAP_MAX_RENDER_TARGETS:
  52                 return screen->is_nv4x ? 4 : 2;
  53         case PIPE_CAP_OCCLUSION_QUERY:
  54                 return 1;
  55         case PIPE_CAP_TIMER_QUERY:
  56                 return 0;
  57         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  58                 return 1;
  59         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  60                 return 13;
  61         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  62                 return 10;
  63         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  64                 return 13;
  65         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  66                 return !!screen->is_nv4x;
  67         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  68                 return 1;
  69         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  70                 return 0; /* We have 4 on nv40 - but unsupported currently */
  71         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  72                 return 0;
  73         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  74                 return !!screen->is_nv4x;
  75         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  76                 return 16;
  77         case PIPE_CAP_INDEP_BLEND_ENABLE:
  78                 /* TODO: on nv40 we have separate color masks */
  79                 /* TODO: nv40 mrt blending is probably broken */
  80                 return 0;
  81         case PIPE_CAP_INDEP_BLEND_FUNC:
  82                 return 0;
  83         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  84         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  85                 return 1;
  86         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  87         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  88                 return 0;
  89         case PIPE_CAP_MAX_FS_INSTRUCTIONS:
  90         case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS:
  91         case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS:
  92         case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS:
  93                 return 4096;
  94         case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH:
  95                 /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
  96                    value (nv30:0/nv40:4) ? */
  97                 return screen->is_nv4x ? 4 : 0;
  98         case PIPE_CAP_MAX_FS_INPUTS:
  99                 return 10;
 100         case PIPE_CAP_MAX_FS_CONSTS:
 101                 return screen->is_nv4x ? 224 : 32;
 102         case PIPE_CAP_MAX_FS_TEMPS:
 103                 return 32;
 104         case PIPE_CAP_MAX_FS_ADDRS:
 105                 return screen->is_nv4x ? 1 : 0;
 106         case PIPE_CAP_MAX_FS_PREDS:
 107                 return screen->is_nv4x ? 1 : 0;
 108         case PIPE_CAP_MAX_VS_INSTRUCTIONS:
 109         case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS:
 110                 return screen->is_nv4x ? 512 : 256;
 111         case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS:
 112         case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS:
 113                 return screen->is_nv4x ? 512 : 0;
 114         case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH:
 115                 /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 116                    value (nv30:1/nv40:4) ? */
 117                 return screen->is_nv4x ? 4 : 1;
 118         case PIPE_CAP_MAX_VS_INPUTS:
 119                 return 16;
 120         case PIPE_CAP_MAX_VS_CONSTS:
 121                 return 256;
 122         case PIPE_CAP_MAX_VS_TEMPS:
 123                 return screen->is_nv4x ? 32 : 13;
 124         case PIPE_CAP_MAX_VS_ADDRS:
 125                 return 2;
 126         case PIPE_CAP_MAX_VS_PREDS:
 127                 return screen->is_nv4x ? 1 : 0;
 128         default:
 129                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 130                 return 0;
 131         }
 132 }
 133
 134 static float
 135 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 136 {
 137         struct nvfx_screen *screen = nvfx_screen(pscreen);
 138
 139         switch (param) {
 140         case PIPE_CAP_MAX_LINE_WIDTH:
 141         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 142                 return 10.0;
 143         case PIPE_CAP_MAX_POINT_WIDTH:
 144         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 145                 return 64.0;
 146         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 147                 return screen->is_nv4x ? 16.0 : 8.0;
 148         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 149                 return screen->is_nv4x ? 16.0 : 4.0;
 150         default:
 151                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 152                 return 0.0;
 153         }
 154 }
 155
 156 static boolean
 157 nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 158                                      enum pipe_format format,
 159                                      enum pipe_texture_target target,
 160                                      unsigned tex_usage, unsigned geom_flags)
 161 {
 162         struct nvfx_screen *screen = nvfx_screen(pscreen);
 163         struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
 164
 165         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
 166                 switch (format) {
 167                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 168                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 169                 case PIPE_FORMAT_B5G6R5_UNORM:
 170                         return TRUE;
 171                 default:
 172                         break;
 173                 }
 174         } else
 175         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
 176                 switch (format) {
 177                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 178                 case PIPE_FORMAT_X8Z24_UNORM:
 179                         return TRUE;
 180                 case PIPE_FORMAT_Z16_UNORM:
 181                         /* TODO: this nv30 limitation probably does not exist */
 182                         if (!screen->is_nv4x && front)
 183                                 return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
 184                         return TRUE;
 185                 default:
 186                         break;
 187                 }
 188         } else {
 189                 switch (format) {
 190                 if (tex_usage & PIPE_BIND_SAMPLER_VIEW) {
 191                         switch (format) {
 192                         case PIPE_FORMAT_DXT1_RGB:
 193                         case PIPE_FORMAT_DXT1_RGBA:
 194                         case PIPE_FORMAT_DXT3_RGBA:
 195                         case PIPE_FORMAT_DXT5_RGBA:
 196                                 return util_format_s3tc_enabled;
 197                         default:
 198                                 break;
 199                         }
 200                 }
 201                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 202                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 203                 case PIPE_FORMAT_B5G5R5A1_UNORM:
 204                 case PIPE_FORMAT_B4G4R4A4_UNORM:
 205                 case PIPE_FORMAT_B5G6R5_UNORM:
 206                 case PIPE_FORMAT_L8_UNORM:
 207                 case PIPE_FORMAT_A8_UNORM:
 208                 case PIPE_FORMAT_I8_UNORM:
 209                 case PIPE_FORMAT_L8A8_UNORM:
 210                 case PIPE_FORMAT_Z16_UNORM:
 211                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 212                         return TRUE;
 213                 /* TODO: does nv30 support this? */
 214                 case PIPE_FORMAT_R16_SNORM:
 215                         return !!screen->is_nv4x;
 216                 default:
 217                         break;
 218                 }
 219         }
 220
 221         return FALSE;
 222 }
 223
 224
 225 static void
 226 nvfx_screen_destroy(struct pipe_screen *pscreen)
 227 {
 228         struct nvfx_screen *screen = nvfx_screen(pscreen);
 229
 230         nouveau_resource_destroy(&screen->vp_exec_heap);
 231         nouveau_resource_destroy(&screen->vp_data_heap);
 232         nouveau_resource_destroy(&screen->query_heap);
 233         nouveau_notifier_free(&screen->query);
 234         nouveau_notifier_free(&screen->sync);
 235         nouveau_grobj_free(&screen->eng3d);
 236         nv04_surface_2d_takedown(&screen->eng2d);
 237
 238         nouveau_screen_fini(&screen->base);
 239
 240         FREE(pscreen);
 241 }
 242
 243 static void nv30_screen_init(struct nvfx_screen *screen)
 244 {
 245         struct nouveau_channel *chan = screen->base.channel;
 246         int i;
 247
 248         /* TODO: perhaps we should do some of this on nv40 too? */
 249         for (i=1; i<8; i++) {
 250                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1));
 251                 OUT_RING(chan, 0);
 252                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i), 1));
 253                 OUT_RING(chan, 0);
 254         }
 255
 256         OUT_RING(chan, RING_3D(0x220, 1));
 257         OUT_RING(chan, 1);
 258
 259         OUT_RING(chan, RING_3D(0x03b0, 1));
 260         OUT_RING(chan, 0x00100000);
 261         OUT_RING(chan, RING_3D(0x1454, 1));
 262         OUT_RING(chan, 0);
 263         OUT_RING(chan, RING_3D(0x1d80, 1));
 264         OUT_RING(chan, 3);
 265         OUT_RING(chan, RING_3D(0x1450, 1));
 266         OUT_RING(chan, 0x00030004);
 267
 268         /* NEW */
 269         OUT_RING(chan, RING_3D(0x1e98, 1));
 270         OUT_RING(chan, 0);
 271         OUT_RING(chan, RING_3D(0x17e0, 3));
 272         OUT_RING(chan, fui(0.0));
 273         OUT_RING(chan, fui(0.0));
 274         OUT_RING(chan, fui(1.0));
 275         OUT_RING(chan, RING_3D(0x1f80, 16));
 276         for (i=0; i<16; i++) {
 277                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 278         }
 279
 280         OUT_RING(chan, RING_3D(0x120, 3));
 281         OUT_RING(chan, 0);
 282         OUT_RING(chan, 1);
 283         OUT_RING(chan, 2);
 284
 285         OUT_RING(chan, RING_3D(0x1d88, 1));
 286         OUT_RING(chan, 0x00001200);
 287
 288         OUT_RING(chan, RING_3D(NV34TCL_RC_ENABLE, 1));
 289         OUT_RING(chan, 0);
 290
 291         OUT_RING(chan, RING_3D(NV34TCL_DEPTH_RANGE_NEAR, 2));
 292         OUT_RING(chan, fui(0.0));
 293         OUT_RING(chan, fui(1.0));
 294
 295         OUT_RING(chan, RING_3D(NV34TCL_MULTISAMPLE_CONTROL, 1));
 296         OUT_RING(chan, 0xffff0000);
 297
 298         /* enables use of vp rather than fixed-function somehow */
 299         OUT_RING(chan, RING_3D(0x1e94, 1));
 300         OUT_RING(chan, 0x13);
 301 }
 302
 303 static void nv40_screen_init(struct nvfx_screen *screen)
 304 {
 305         struct nouveau_channel *chan = screen->base.channel;
 306
 307         OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 2));
 308         OUT_RING(chan, screen->base.channel->vram->handle);
 309         OUT_RING(chan, screen->base.channel->vram->handle);
 310
 311         OUT_RING(chan, RING_3D(0x1ea4, 3));
 312         OUT_RING(chan, 0x00000010);
 313         OUT_RING(chan, 0x01000100);
 314         OUT_RING(chan, 0xff800006);
 315
 316         /* vtxprog output routing */
 317         OUT_RING(chan, RING_3D(0x1fc4, 1));
 318         OUT_RING(chan, 0x06144321);
 319         OUT_RING(chan, RING_3D(0x1fc8, 2));
 320         OUT_RING(chan, 0xedcba987);
 321         OUT_RING(chan, 0x00000021);
 322         OUT_RING(chan, RING_3D(0x1fd0, 1));
 323         OUT_RING(chan, 0x00171615);
 324         OUT_RING(chan, RING_3D(0x1fd4, 1));
 325         OUT_RING(chan, 0x001b1a19);
 326
 327         OUT_RING(chan, RING_3D(0x1ef8, 1));
 328         OUT_RING(chan, 0x0020ffff);
 329         OUT_RING(chan, RING_3D(0x1d64, 1));
 330         OUT_RING(chan, 0x00d30000);
 331         OUT_RING(chan, RING_3D(0x1e94, 1));
 332         OUT_RING(chan, 0x00000001);
 333 }
 334
 335 static unsigned
 336 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 337 {
 338         int vram_hack_default = 0;
 339         int vram_hack;
 340         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 341         // It may also depend on the specific card or the AGP/PCIe chipset.
 342         if(screen->base.device->chipset == 0x47 /* G70 */
 343                 || screen->base.device->chipset == 0x49 /* G71 */
 344                 || screen->base.device->chipset == 0x46 /* G72 */
 345                 )
 346                 vram_hack_default = 1;
 347         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 348
 349 #ifdef DEBUG
 350         if(!vram_hack)
 351         {
 352                 fprintf(stderr, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
 353                         "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
 354         }
 355         else
 356         {
 357                 fprintf(stderr, "A performance reducing hack is being used to help avoid graphics corruption.\n"
 358                         "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
 359         }
 360 #endif
 361
 362         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 363 }
 364
 365 struct pipe_screen *
 366 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 367 {
 368         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 369         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 370         struct nouveau_channel *chan;
 371         struct pipe_screen *pscreen;
 372         unsigned eng3d_class = 0;
 373         int ret, i;
 374
 375         if (!screen)
 376                 return NULL;
 377
 378         pscreen = &screen->base.base;
 379
 380         ret = nouveau_screen_init(&screen->base, dev);
 381         if (ret) {
 382                 nvfx_screen_destroy(pscreen);
 383                 return NULL;
 384         }
 385         chan = screen->base.channel;
 386
 387         pscreen->winsys = ws;
 388         pscreen->destroy = nvfx_screen_destroy;
 389         pscreen->get_param = nvfx_screen_get_param;
 390         pscreen->get_paramf = nvfx_screen_get_paramf;
 391         pscreen->is_format_supported = nvfx_screen_surface_format_supported;
 392         pscreen->context_create = nvfx_create;
 393
 394         switch (dev->chipset & 0xf0) {
 395         case 0x30:
 396                 if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 397                         eng3d_class = 0x0397;
 398                 else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 399                         eng3d_class = 0x0697;
 400                 else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 401                         eng3d_class = 0x0497;
 402                 break;
 403         case 0x40:
 404                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 405                         eng3d_class = NV40TCL;
 406                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 407                         eng3d_class = NV44TCL;
 408                 screen->is_nv4x = ~0;
 409                 break;
 410         case 0x60:
 411                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 412                         eng3d_class = NV44TCL;
 413                 screen->is_nv4x = ~0;
 414                 break;
 415         }
 416
 417         if (!eng3d_class) {
 418                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 419                 return NULL;
 420         }
 421
 422         screen->force_swtnl = debug_get_bool_option("NOUVEAU_SWTNL", FALSE);
 423
 424         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 425
 426         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 427         if(eng3d_class == NV40TCL)
 428                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 429
 430         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 431                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 432
 433         nvfx_screen_init_resource_functions(pscreen);
 434
 435         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 436         if (ret) {
 437                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 438                 return FALSE;
 439         }
 440
 441         /* 2D engine setup */
 442         screen->eng2d = nv04_surface_2d_init(&screen->base);
 443         screen->eng2d->buf = nvfx_surface_buffer;
 444
 445         /* Notifier for sync purposes */
 446         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 447         if (ret) {
 448                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 449                 nvfx_screen_destroy(pscreen);
 450                 return NULL;
 451         }
 452
 453         /* Query objects */
 454         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 455         {
 456                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 457                 if(!ret)
 458                         break;
 459         }
 460
 461         if (ret) {
 462                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 463                 nvfx_screen_destroy(pscreen);
 464                 return NULL;
 465         }
 466
 467         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 468         if (ret) {
 469                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 470                 nvfx_screen_destroy(pscreen);
 471                 return NULL;
 472         }
 473
 474         LIST_INITHEAD(&screen->query_list);
 475
 476         /* Vtxprog resources */
 477         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
 478             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 479                 nvfx_screen_destroy(pscreen);
 480                 return NULL;
 481         }
 482
 483         BIND_RING(chan, screen->eng3d, 7);
 484
 485         /* Static eng3d initialisation */
 486         /* note that we just started using the channel, so we must have space in the pushbuffer */
 487         OUT_RING(chan, RING_3D(NV34TCL_DMA_NOTIFY, 1));
 488         OUT_RING(chan, screen->sync->handle);
 489         OUT_RING(chan, RING_3D(NV34TCL_DMA_TEXTURE0, 2));
 490         OUT_RING(chan, chan->vram->handle);
 491         OUT_RING(chan, chan->gart->handle);
 492         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1));
 493         OUT_RING(chan, chan->vram->handle);
 494         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 2));
 495         OUT_RING(chan, chan->vram->handle);
 496         OUT_RING(chan, chan->vram->handle);
 497         OUT_RING(chan, RING_3D(NV34TCL_DMA_VTXBUF0, 2));
 498         OUT_RING(chan, chan->vram->handle);
 499         OUT_RING(chan, chan->gart->handle);
 500
 501         OUT_RING(chan, RING_3D(NV34TCL_DMA_FENCE, 2));
 502         OUT_RING(chan, 0);
 503         OUT_RING(chan, screen->query->handle);
 504
 505         OUT_RING(chan, RING_3D(NV34TCL_DMA_IN_MEMORY7, 2));
 506         OUT_RING(chan, chan->vram->handle);
 507         OUT_RING(chan, chan->vram->handle);
 508
 509         if(!screen->is_nv4x)
 510                 nv30_screen_init(screen);
 511         else
 512                 nv40_screen_init(screen);
 513
 514         return pscreen;
 515 }