src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format_s3tc.h"
   4 #include "util/u_simple_screen.h"
   5
   6 #include "nouveau/nouveau_screen.h"
   7 #include "nouveau/nv_object.xml.h"
   8 #include "nvfx_context.h"
   9 #include "nvfx_screen.h"
  10 #include "nvfx_resource.h"
  11 #include "nvfx_tex.h"
  12
  13 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  14 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  15 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  16
  17 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  18 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  19 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  20
  21 static int
  22 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  23 {
  24         struct nvfx_screen *screen = nvfx_screen(pscreen);
  25
  26         switch (param) {
  27         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  28                 return 16;
  29         case PIPE_CAP_NPOT_TEXTURES:
  30                 return screen->advertise_npot;
  31         case PIPE_CAP_TWO_SIDED_STENCIL:
  32                 return 1;
  33         case PIPE_CAP_GLSL:
  34                 return 1;
  35         case PIPE_CAP_ANISOTROPIC_FILTER:
  36                 return 1;
  37         case PIPE_CAP_POINT_SPRITE:
  38                 return 1;
  39         case PIPE_CAP_MAX_RENDER_TARGETS:
  40                 return screen->use_nv4x ? 4 : 1;
  41         case PIPE_CAP_OCCLUSION_QUERY:
  42                 return 1;
  43         case PIPE_CAP_TIMER_QUERY:
  44                 return 0;
  45         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  46                 return 1;
  47         case PIPE_CAP_TEXTURE_SWIZZLE:
  48                 return 1;
  49         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  50                 return 13;
  51         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  52                 return 10;
  53         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  54                 return 13;
  55         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  56                 return !!screen->use_nv4x;
  57         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  58                 return 1;
  59         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  60                 return 0; /* We have 4 on nv40 - but unsupported currently */
  61         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  62                 return screen->advertise_blend_equation_separate;
  63         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  64                 return 16;
  65         case PIPE_CAP_INDEP_BLEND_ENABLE:
  66                 /* TODO: on nv40 we have separate color masks */
  67                 /* TODO: nv40 mrt blending is probably broken */
  68                 return 0;
  69         case PIPE_CAP_INDEP_BLEND_FUNC:
  70                 return 0;
  71         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  72                 return 0;
  73         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  74         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  75         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  76         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  77                 return 1;
  78         case PIPE_CAP_DEPTH_CLAMP:
  79                 return 0; // TODO: implement depth clamp
  80         case PIPE_CAP_PRIMITIVE_RESTART:
  81                 return 0; // TODO: implement primitive restart
  82         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  83                 return 0;
  84         default:
  85                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  86                 return 0;
  87         }
  88 }
  89
  90 static int
  91 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
  92 {
  93         struct nvfx_screen *screen = nvfx_screen(pscreen);
  94
  95         switch(shader) {
  96         case PIPE_SHADER_FRAGMENT:
  97                 switch(param) {
  98                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
  99                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 100                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 101                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 102                         return 4096;
 103                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 104                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 105                          value (nv30:0/nv40:4) ? */
 106                         return screen->use_nv4x ? 4 : 0;
 107                 case PIPE_SHADER_CAP_MAX_INPUTS:
 108                         return screen->use_nv4x ? 12 : 10;
 109                 case PIPE_SHADER_CAP_MAX_CONSTS:
 110                         return screen->use_nv4x ? 224 : 32;
 111                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 112                     return 1;
 113                 case PIPE_SHADER_CAP_MAX_TEMPS:
 114                         return 32;
 115                 case PIPE_SHADER_CAP_MAX_ADDRS:
 116                         return screen->use_nv4x ? 1 : 0;
 117                 case PIPE_SHADER_CAP_MAX_PREDS:
 118                         return 0; /* we could expose these, but nothing uses them */
 119                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 120                     return 0;
 121                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 122                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 123                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 124                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 125                         return 0;
 126                 case PIPE_SHADER_CAP_SUBROUTINES:
 127                         return screen->use_nv4x ? 1 : 0;
 128                 default:
 129                         break;
 130                 }
 131                 break;
 132         case PIPE_SHADER_VERTEX:
 133                 switch(param) {
 134                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 135                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 136                         return screen->use_nv4x ? 512 : 256;
 137                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 138                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 139                         return screen->use_nv4x ? 512 : 0;
 140                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 141                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 142                          value (nv30:1/nv40:4) ? */
 143                         return screen->use_nv4x ? 4 : 1;
 144                 case PIPE_SHADER_CAP_MAX_INPUTS:
 145                         return 16;
 146                 case PIPE_SHADER_CAP_MAX_CONSTS:
 147                         /* - 6 is for clip planes; Gallium should be fixed to put
 148                          * them in the vertex shader itself, so we don't need to reserve these */
 149                         return (screen->use_nv4x ? 468 : 256) - 6;
 150                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 151                             return 1;
 152                 case PIPE_SHADER_CAP_MAX_TEMPS:
 153                         return screen->use_nv4x ? 32 : 13;
 154                 case PIPE_SHADER_CAP_MAX_ADDRS:
 155                         return 2;
 156                 case PIPE_SHADER_CAP_MAX_PREDS:
 157                         return 0; /* we could expose these, but nothing uses them */
 158                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 159                         return 1;
 160                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 161                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 162                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 163                         return 0;
 164                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 165                         return 1;
 166                 case PIPE_SHADER_CAP_SUBROUTINES:
 167                         return 1;
 168                 default:
 169                         break;
 170                 }
 171                 break;
 172         default:
 173                 break;
 174         }
 175         return 0;
 176 }
 177
 178 static float
 179 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 180 {
 181         struct nvfx_screen *screen = nvfx_screen(pscreen);
 182
 183         switch (param) {
 184         case PIPE_CAP_MAX_LINE_WIDTH:
 185         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 186                 return 10.0;
 187         case PIPE_CAP_MAX_POINT_WIDTH:
 188         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 189                 return 64.0;
 190         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 191                 return screen->use_nv4x ? 16.0 : 8.0;
 192         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 193                 return 15.0;
 194         default:
 195                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 196                 return 0.0;
 197         }
 198 }
 199
 200 static boolean
 201 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 202                                      enum pipe_format format,
 203                                      enum pipe_texture_target target,
 204                                      unsigned sample_count,
 205                                      unsigned bind)
 206 {
 207         struct nvfx_screen *screen = nvfx_screen(pscreen);
 208
 209          if (sample_count > 1)
 210                 return FALSE;
 211
 212         if (bind & PIPE_BIND_RENDER_TARGET) {
 213                 switch (format) {
 214                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 215                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 216                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 217                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 218                 case PIPE_FORMAT_B5G6R5_UNORM:
 219                         break;
 220                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 221                         if(!screen->advertise_fp16)
 222                                 return FALSE;
 223                         break;
 224                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 225                         if(!screen->advertise_fp32)
 226                                 return FALSE;
 227                         break;
 228                 default:
 229                         return FALSE;
 230                 }
 231         }
 232
 233         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 234                 switch (format) {
 235                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 236                 case PIPE_FORMAT_X8Z24_UNORM:
 237                 case PIPE_FORMAT_Z16_UNORM:
 238                         break;
 239                 default:
 240                         return FALSE;
 241                 }
 242         }
 243
 244         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 245                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 246                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 247                         return FALSE;
 248                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 249                         return FALSE;
 250                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 251                         return FALSE;
 252                 if(screen->use_nv4x)
 253                 {
 254                         if(tf->fmt[4] < 0)
 255                                 return FALSE;
 256                 }
 257                 else
 258                 {
 259                         if(tf->fmt[0] < 0)
 260                                 return FALSE;
 261                 }
 262         }
 263
 264         // note that we do actually support everything through translate
 265         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 266                 unsigned type = nvfx_vertex_formats[format];
 267                 if(!type)
 268                         return FALSE;
 269         }
 270
 271         if (bind & PIPE_BIND_INDEX_BUFFER) {
 272                 // 8-bit indices supported, but not in hardware index buffer
 273                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 274                         return FALSE;
 275         }
 276
 277         if(bind & PIPE_BIND_STREAM_OUTPUT)
 278                 return FALSE;
 279
 280         return TRUE;
 281 }
 282
 283 static void
 284 nvfx_screen_destroy(struct pipe_screen *pscreen)
 285 {
 286         struct nvfx_screen *screen = nvfx_screen(pscreen);
 287
 288         nouveau_resource_destroy(&screen->vp_exec_heap);
 289         nouveau_resource_destroy(&screen->vp_data_heap);
 290         nouveau_resource_destroy(&screen->query_heap);
 291         nouveau_notifier_free(&screen->query);
 292         nouveau_notifier_free(&screen->sync);
 293         nouveau_grobj_free(&screen->eng3d);
 294         nvfx_screen_surface_takedown(pscreen);
 295
 296         nouveau_screen_fini(&screen->base);
 297
 298         FREE(pscreen);
 299 }
 300
 301 static void nv30_screen_init(struct nvfx_screen *screen)
 302 {
 303         struct nouveau_channel *chan = screen->base.channel;
 304         struct nouveau_grobj *eng3d = screen->eng3d;
 305         int i;
 306
 307         /* TODO: perhaps we should do some of this on nv40 too? */
 308         for (i=1; i<8; i++) {
 309                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 310                 OUT_RING(chan, 0);
 311                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 312                 OUT_RING(chan, 0);
 313         }
 314
 315         BEGIN_RING(chan, eng3d, 0x220, 1);
 316         OUT_RING(chan, 1);
 317
 318         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 319         OUT_RING(chan, 0x00100000);
 320         BEGIN_RING(chan, eng3d, 0x1454, 1);
 321         OUT_RING(chan, 0);
 322         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 323         OUT_RING(chan, 3);
 324         BEGIN_RING(chan, eng3d, 0x1450, 1);
 325         OUT_RING(chan, 0x00030004);
 326
 327         /* NEW */
 328         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 329         OUT_RING(chan, 0);
 330         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 331         OUT_RING(chan, fui(0.0));
 332         OUT_RING(chan, fui(0.0));
 333         OUT_RING(chan, fui(1.0));
 334         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 335         for (i=0; i<16; i++) {
 336                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 337         }
 338
 339         BEGIN_RING(chan, eng3d, 0x120, 3);
 340         OUT_RING(chan, 0);
 341         OUT_RING(chan, 1);
 342         OUT_RING(chan, 2);
 343
 344         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 345         OUT_RING(chan, 0x00001200);
 346
 347         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 348         OUT_RING(chan, 0);
 349
 350         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 351         OUT_RING(chan, fui(0.0));
 352         OUT_RING(chan, fui(1.0));
 353
 354         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 355         OUT_RING(chan, 0xffff0000);
 356
 357         /* enables use of vp rather than fixed-function somehow */
 358         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 359         OUT_RING(chan, 0x13);
 360 }
 361
 362 static void nv40_screen_init(struct nvfx_screen *screen)
 363 {
 364         struct nouveau_channel *chan = screen->base.channel;
 365         struct nouveau_grobj *eng3d = screen->eng3d;
 366
 367         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 368         OUT_RING(chan, screen->base.channel->vram->handle);
 369         OUT_RING(chan, screen->base.channel->vram->handle);
 370
 371         BEGIN_RING(chan, eng3d, 0x1450, 1);
 372         OUT_RING(chan, 0x00000004);
 373
 374         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 375         OUT_RING(chan, 0x00000010);
 376         OUT_RING(chan, 0x01000100);
 377         OUT_RING(chan, 0xff800006);
 378
 379         /* vtxprog output routing */
 380         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 381         OUT_RING(chan, 0x06144321);
 382         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 383         OUT_RING(chan, 0xedcba987);
 384         OUT_RING(chan, 0x0000006f);
 385         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 386         OUT_RING(chan, 0x00171615);
 387         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 388         OUT_RING(chan, 0x001b1a19);
 389
 390         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 391         OUT_RING(chan, 0x0020ffff);
 392         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 393         OUT_RING(chan, 0x01d300d4);
 394         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 395         OUT_RING(chan, 0x00000001);
 396
 397         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 398         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 399 }
 400
 401 static unsigned
 402 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 403 {
 404         int vram_hack_default = 0;
 405         int vram_hack;
 406         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 407         // It may also depend on the specific card or the AGP/PCIe chipset.
 408         if(screen->base.device->chipset == 0x47 /* G70 */
 409                 || screen->base.device->chipset == 0x49 /* G71 */
 410                 || screen->base.device->chipset == 0x46 /* G72 */
 411                 )
 412                 vram_hack_default = 1;
 413         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 414
 415         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 416 }
 417
 418 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 419 {
 420         struct nvfx_screen* screen = chan->user_private;
 421         struct nvfx_context* nvfx = screen->cur_ctx;
 422         if(nvfx)
 423                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 424 }
 425
 426 struct pipe_screen *
 427 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 428 {
 429         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 430         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 431         struct nouveau_channel *chan;
 432         struct pipe_screen *pscreen;
 433         unsigned eng3d_class = 0;
 434         int ret, i;
 435
 436         if (!screen)
 437                 return NULL;
 438
 439         pscreen = &screen->base.base;
 440
 441         ret = nouveau_screen_init(&screen->base, dev);
 442         if (ret) {
 443                 nvfx_screen_destroy(pscreen);
 444                 return NULL;
 445         }
 446         chan = screen->base.channel;
 447         screen->cur_ctx = NULL;
 448         chan->user_private = screen;
 449         chan->flush_notify = nvfx_channel_flush_notify;
 450
 451         pscreen->winsys = ws;
 452         pscreen->destroy = nvfx_screen_destroy;
 453         pscreen->get_param = nvfx_screen_get_param;
 454         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 455         pscreen->get_paramf = nvfx_screen_get_paramf;
 456         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 457         pscreen->context_create = nvfx_create;
 458
 459         switch (dev->chipset & 0xf0) {
 460         case 0x30:
 461                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 462                         eng3d_class = NV30_3D;
 463                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 464                         eng3d_class = NV34_3D;
 465                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 466                         eng3d_class = NV35_3D;
 467                 break;
 468         case 0x40:
 469                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 470                         eng3d_class = NV40_3D;
 471                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 472                         eng3d_class = NV44_3D;
 473                 screen->is_nv4x = ~0;
 474                 break;
 475         case 0x60:
 476                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 477                         eng3d_class = NV44_3D;
 478                 screen->is_nv4x = ~0;
 479                 break;
 480         }
 481
 482         if (!eng3d_class) {
 483                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 484                 return NULL;
 485         }
 486
 487         screen->advertise_npot = !!screen->is_nv4x;
 488         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 489         screen->use_nv4x = screen->is_nv4x;
 490
 491         if(screen->is_nv4x) {
 492                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 493                         screen->use_nv4x = 0;
 494                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 495                         screen->advertise_npot = 0;
 496                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 497                         screen->advertise_blend_equation_separate = 0;
 498         }
 499
 500         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 501         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 502
 503         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 504         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 505         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 506
 507         /* We don't advertise these by default because filtering and blending doesn't work as
 508          * it should, due to several restrictions.
 509          * The only exception is fp16 on nv40.
 510          */
 511         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 512         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 513
 514         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 515
 516         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 517         if(eng3d_class == NV40_3D)
 518                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 519
 520         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 521                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 522
 523         nvfx_screen_init_resource_functions(pscreen);
 524
 525         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 526         if (ret) {
 527                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 528                 return FALSE;
 529         }
 530
 531         /* 2D engine setup */
 532         nvfx_screen_surface_init(pscreen);
 533
 534         /* Notifier for sync purposes */
 535         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 536         if (ret) {
 537                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 538                 nvfx_screen_destroy(pscreen);
 539                 return NULL;
 540         }
 541
 542         /* Query objects */
 543         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 544         {
 545                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 546                 if(!ret)
 547                         break;
 548         }
 549
 550         if (ret) {
 551                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 552                 nvfx_screen_destroy(pscreen);
 553                 return NULL;
 554         }
 555
 556         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 557         if (ret) {
 558                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 559                 nvfx_screen_destroy(pscreen);
 560                 return NULL;
 561         }
 562
 563         LIST_INITHEAD(&screen->query_list);
 564
 565         /* Vtxprog resources */
 566         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 567             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 568                 nvfx_screen_destroy(pscreen);
 569                 return NULL;
 570         }
 571
 572         BIND_RING(chan, screen->eng3d, 7);
 573
 574         /* Static eng3d initialisation */
 575         /* note that we just started using the channel, so we must have space in the pushbuffer */
 576         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 577         OUT_RING(chan, screen->sync->handle);
 578         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 579         OUT_RING(chan, chan->vram->handle);
 580         OUT_RING(chan, chan->gart->handle);
 581         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 582         OUT_RING(chan, chan->vram->handle);
 583         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 584         OUT_RING(chan, chan->vram->handle);
 585         OUT_RING(chan, chan->vram->handle);
 586         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 587         OUT_RING(chan, chan->vram->handle);
 588         OUT_RING(chan, chan->gart->handle);
 589
 590         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 591         OUT_RING(chan, 0);
 592         OUT_RING(chan, screen->query->handle);
 593
 594         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 595         OUT_RING(chan, chan->vram->handle);
 596         OUT_RING(chan, chan->vram->handle);
 597
 598         if(!screen->is_nv4x)
 599                 nv30_screen_init(screen);
 600         else
 601                 nv40_screen_init(screen);
 602
 603         return pscreen;
 604 }