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nvfx: clean up shader header
[mesa.git] / src / gallium / drivers / nvfx / nvfx_vertprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_dump.h"
9 #include "tgsi/tgsi_util.h"
10
11 #include "nvfx_context.h"
12 #include "nvfx_state.h"
13
14 /* TODO (at least...):
15 * 1. Indexed consts + ARL
16 * 3. NV_vp11, NV_vp2, NV_vp3 features
17 * - extra arith opcodes
18 * - branching
19 * - texture sampling
20 * - indexed attribs
21 * - indexed results
22 * 4. bugs
23 */
24
25 #include "nv30_vertprog.h"
26 #include "nv40_vertprog.h"
27
28 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
29
30 struct nvfx_vpc {
31 struct nvfx_vertex_program *vp;
32
33 struct nvfx_vertex_program_exec *vpi;
34
35 unsigned r_temps;
36 unsigned r_temps_discard;
37 struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
38 struct nvfx_sreg *r_address;
39 struct nvfx_sreg *r_temp;
40
41 struct nvfx_sreg *imm;
42 unsigned nr_imm;
43
44 unsigned hpos_idx;
45 };
46
47 static struct nvfx_sreg
48 temp(struct nvfx_vpc *vpc)
49 {
50 int idx = ffs(~vpc->r_temps) - 1;
51
52 if (idx < 0) {
53 NOUVEAU_ERR("out of temps!!\n");
54 assert(0);
55 return nvfx_sr(NVFXSR_TEMP, 0);
56 }
57
58 vpc->r_temps |= (1 << idx);
59 vpc->r_temps_discard |= (1 << idx);
60 return nvfx_sr(NVFXSR_TEMP, idx);
61 }
62
63 static INLINE void
64 release_temps(struct nvfx_vpc *vpc)
65 {
66 vpc->r_temps &= ~vpc->r_temps_discard;
67 vpc->r_temps_discard = 0;
68 }
69
70 static struct nvfx_sreg
71 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
72 {
73 struct nvfx_vertex_program *vp = vpc->vp;
74 struct nvfx_vertex_program_data *vpd;
75 int idx;
76
77 if (pipe >= 0) {
78 for (idx = 0; idx < vp->nr_consts; idx++) {
79 if (vp->consts[idx].index == pipe)
80 return nvfx_sr(NVFXSR_CONST, idx);
81 }
82 }
83
84 idx = vp->nr_consts++;
85 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
86 vpd = &vp->consts[idx];
87
88 vpd->index = pipe;
89 vpd->value[0] = x;
90 vpd->value[1] = y;
91 vpd->value[2] = z;
92 vpd->value[3] = w;
93 return nvfx_sr(NVFXSR_CONST, idx);
94 }
95
96 #define arith(cc,s,o,d,m,s0,s1,s2) \
97 nvfx_vp_arith(nvfx, (cc), NVFX_VP_INST_SLOT_##s, NVFX_VP_INST_##s##_OP_##o, (d), (m), (s0), (s1), (s2))
98
99 static void
100 emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_sreg src)
101 {
102 struct nvfx_vertex_program *vp = vpc->vp;
103 uint32_t sr = 0;
104
105 switch (src.type) {
106 case NVFXSR_TEMP:
107 sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
108 sr |= (src.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
109 break;
110 case NVFXSR_INPUT:
111 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
112 NVFX_VP(SRC_REG_TYPE_SHIFT));
113 vp->ir |= (1 << src.index);
114 hw[1] |= (src.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
115 break;
116 case NVFXSR_CONST:
117 sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
118 NVFX_VP(SRC_REG_TYPE_SHIFT));
119 assert(vpc->vpi->const_index == -1 ||
120 vpc->vpi->const_index == src.index);
121 vpc->vpi->const_index = src.index;
122 break;
123 case NVFXSR_NONE:
124 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
125 NVFX_VP(SRC_REG_TYPE_SHIFT));
126 break;
127 default:
128 assert(0);
129 }
130
131 if (src.negate)
132 sr |= NVFX_VP(SRC_NEGATE);
133
134 if (src.abs)
135 hw[0] |= (1 << (21 + pos));
136
137 sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
138 (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
139 (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
140 (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
141
142 switch (pos) {
143 case 0:
144 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
145 NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
146 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
147 NVFX_VP(INST_SRC0L_SHIFT);
148 break;
149 case 1:
150 hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
151 break;
152 case 2:
153 hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
154 NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
155 hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
156 NVFX_VP(INST_SRC2L_SHIFT);
157 break;
158 default:
159 assert(0);
160 }
161 }
162
163 static void
164 emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_sreg dst)
165 {
166 struct nvfx_vertex_program *vp = vpc->vp;
167
168 switch (dst.type) {
169 case NVFXSR_TEMP:
170 if(!nvfx->is_nv4x)
171 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
172 else {
173 hw[3] |= NV40_VP_INST_DEST_MASK;
174 if (slot == 0) {
175 hw[0] |= (dst.index <<
176 NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
177 } else {
178 hw[3] |= (dst.index <<
179 NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
180 }
181 }
182 break;
183 case NVFXSR_OUTPUT:
184 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
185 switch (dst.index) {
186 case NVFX_VP_INST_DEST_CLIP(0):
187 vp->or |= (1 << 6);
188 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0;
189 dst.index = NVFX_VP(INST_DEST_FOGC);
190 break;
191 case NVFX_VP_INST_DEST_CLIP(1):
192 vp->or |= (1 << 7);
193 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1;
194 dst.index = NVFX_VP(INST_DEST_FOGC);
195 break;
196 case NVFX_VP_INST_DEST_CLIP(2):
197 vp->or |= (1 << 8);
198 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2;
199 dst.index = NVFX_VP(INST_DEST_FOGC);
200 break;
201 case NVFX_VP_INST_DEST_CLIP(3):
202 vp->or |= (1 << 9);
203 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3;
204 dst.index = NVFX_VP(INST_DEST_PSZ);
205 break;
206 case NVFX_VP_INST_DEST_CLIP(4):
207 vp->or |= (1 << 10);
208 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4;
209 dst.index = NVFX_VP(INST_DEST_PSZ);
210 break;
211 case NVFX_VP_INST_DEST_CLIP(5):
212 vp->or |= (1 << 11);
213 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5;
214 dst.index = NVFX_VP(INST_DEST_PSZ);
215 break;
216 default:
217 if(!nvfx->is_nv4x) {
218 switch (dst.index) {
219 case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
220 case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
221 case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
222 case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
223 case NV30_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
224 case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
225 case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
226 case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
227 case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
228 case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
229 case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
230 case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
231 case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
232 case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
233 }
234 } else {
235 switch (dst.index) {
236 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
237 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
238 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
239 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
240 case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
241 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
242 case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
243 case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
244 case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
245 case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
246 case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
247 case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
248 case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
249 case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
250 }
251 }
252 break;
253 }
254
255 if(!nvfx->is_nv4x) {
256 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
257 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
258
259 /*XXX: no way this is entirely correct, someone needs to
260 * figure out what exactly it is.
261 */
262 hw[3] |= 0x800;
263 } else {
264 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
265 if (slot == 0) {
266 hw[0] |= NV40_VP_INST_VEC_RESULT;
267 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
268 } else {
269 hw[3] |= NV40_VP_INST_SCA_RESULT;
270 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
271 }
272 }
273 break;
274 default:
275 assert(0);
276 }
277 }
278
279 static void
280 nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
281 struct nvfx_sreg dst, int mask,
282 struct nvfx_sreg s0, struct nvfx_sreg s1,
283 struct nvfx_sreg s2)
284 {
285 struct nvfx_vertex_program *vp = vpc->vp;
286 uint32_t *hw;
287
288 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
289 vpc->vpi = &vp->insns[vp->nr_insns - 1];
290 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
291 vpc->vpi->const_index = -1;
292
293 hw = vpc->vpi->data;
294
295 hw[0] |= (NVFX_COND_TR << NVFX_VP(INST_COND_SHIFT));
296 hw[0] |= ((0 << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
297 (1 << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
298 (2 << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
299 (3 << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
300
301 if(!nvfx->is_nv4x) {
302 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
303 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
304 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
305
306 if (dst.type == NVFXSR_OUTPUT) {
307 if (slot)
308 hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
309 else
310 hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
311 } else {
312 if (slot)
313 hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
314 else
315 hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
316 }
317 } else {
318 if (slot == 0) {
319 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
320 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
321 hw[3] |= (mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
322 } else {
323 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
324 hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
325 hw[3] |= (mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
326 }
327 }
328
329 emit_dst(nvfx, vpc, hw, slot, dst);
330 emit_src(nvfx, vpc, hw, 0, s0);
331 emit_src(nvfx, vpc, hw, 1, s1);
332 emit_src(nvfx, vpc, hw, 2, s2);
333 }
334
335 static INLINE struct nvfx_sreg
336 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
337 struct nvfx_sreg src;
338
339 switch (fsrc->Register.File) {
340 case TGSI_FILE_INPUT:
341 src = nvfx_sr(NVFXSR_INPUT, fsrc->Register.Index);
342 break;
343 case TGSI_FILE_CONSTANT:
344 src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
345 break;
346 case TGSI_FILE_IMMEDIATE:
347 src = vpc->imm[fsrc->Register.Index];
348 break;
349 case TGSI_FILE_TEMPORARY:
350 src = vpc->r_temp[fsrc->Register.Index];
351 break;
352 default:
353 NOUVEAU_ERR("bad src file\n");
354 break;
355 }
356
357 src.abs = fsrc->Register.Absolute;
358 src.negate = fsrc->Register.Negate;
359 src.swz[0] = fsrc->Register.SwizzleX;
360 src.swz[1] = fsrc->Register.SwizzleY;
361 src.swz[2] = fsrc->Register.SwizzleZ;
362 src.swz[3] = fsrc->Register.SwizzleW;
363 return src;
364 }
365
366 static INLINE struct nvfx_sreg
367 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
368 struct nvfx_sreg dst;
369
370 switch (fdst->Register.File) {
371 case TGSI_FILE_OUTPUT:
372 dst = vpc->r_result[fdst->Register.Index];
373 break;
374 case TGSI_FILE_TEMPORARY:
375 dst = vpc->r_temp[fdst->Register.Index];
376 break;
377 case TGSI_FILE_ADDRESS:
378 dst = vpc->r_address[fdst->Register.Index];
379 break;
380 default:
381 NOUVEAU_ERR("bad dst file\n");
382 break;
383 }
384
385 return dst;
386 }
387
388 static INLINE int
389 tgsi_mask(uint tgsi)
390 {
391 int mask = 0;
392
393 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
394 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
395 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
396 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
397 return mask;
398 }
399
400 static boolean
401 src_native_swz(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc,
402 struct nvfx_sreg *src)
403 {
404 const struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
405 struct nvfx_sreg tgsi = tgsi_src(vpc, fsrc);
406 uint mask = 0;
407 uint c;
408
409 for (c = 0; c < 4; c++) {
410 switch (tgsi_util_get_full_src_register_swizzle(fsrc, c)) {
411 case TGSI_SWIZZLE_X:
412 case TGSI_SWIZZLE_Y:
413 case TGSI_SWIZZLE_Z:
414 case TGSI_SWIZZLE_W:
415 mask |= tgsi_mask(1 << c);
416 break;
417 default:
418 assert(0);
419 }
420 }
421
422 if (mask == NVFX_VP_MASK_ALL)
423 return TRUE;
424
425 *src = temp(vpc);
426
427 if (mask)
428 arith(vpc, VEC, MOV, *src, mask, tgsi, none, none);
429
430 return FALSE;
431 }
432
433 static boolean
434 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
435 const struct tgsi_full_instruction *finst)
436 {
437 struct nvfx_sreg src[3], dst, tmp;
438 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
439 int mask;
440 int ai = -1, ci = -1, ii = -1;
441 int i;
442
443 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
444 return TRUE;
445
446 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
447 const struct tgsi_full_src_register *fsrc;
448
449 fsrc = &finst->Src[i];
450 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
451 src[i] = tgsi_src(vpc, fsrc);
452 }
453 }
454
455 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
456 const struct tgsi_full_src_register *fsrc;
457
458 fsrc = &finst->Src[i];
459
460 switch (fsrc->Register.File) {
461 case TGSI_FILE_INPUT:
462 case TGSI_FILE_CONSTANT:
463 case TGSI_FILE_TEMPORARY:
464 if (!src_native_swz(nvfx, vpc, fsrc, &src[i]))
465 continue;
466 break;
467 default:
468 break;
469 }
470
471 switch (fsrc->Register.File) {
472 case TGSI_FILE_INPUT:
473 if (ai == -1 || ai == fsrc->Register.Index) {
474 ai = fsrc->Register.Index;
475 src[i] = tgsi_src(vpc, fsrc);
476 } else {
477 src[i] = temp(vpc);
478 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
479 tgsi_src(vpc, fsrc), none, none);
480 }
481 break;
482 case TGSI_FILE_CONSTANT:
483 if ((ci == -1 && ii == -1) ||
484 ci == fsrc->Register.Index) {
485 ci = fsrc->Register.Index;
486 src[i] = tgsi_src(vpc, fsrc);
487 } else {
488 src[i] = temp(vpc);
489 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
490 tgsi_src(vpc, fsrc), none, none);
491 }
492 break;
493 case TGSI_FILE_IMMEDIATE:
494 if ((ci == -1 && ii == -1) ||
495 ii == fsrc->Register.Index) {
496 ii = fsrc->Register.Index;
497 src[i] = tgsi_src(vpc, fsrc);
498 } else {
499 src[i] = temp(vpc);
500 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
501 tgsi_src(vpc, fsrc), none, none);
502 }
503 break;
504 case TGSI_FILE_TEMPORARY:
505 /* handled above */
506 break;
507 default:
508 NOUVEAU_ERR("bad src file\n");
509 return FALSE;
510 }
511 }
512
513 dst = tgsi_dst(vpc, &finst->Dst[0]);
514 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
515
516 switch (finst->Instruction.Opcode) {
517 case TGSI_OPCODE_ABS:
518 arith(vpc, VEC, MOV, dst, mask, abs(src[0]), none, none);
519 break;
520 case TGSI_OPCODE_ADD:
521 arith(vpc, VEC, ADD, dst, mask, src[0], none, src[1]);
522 break;
523 case TGSI_OPCODE_ARL:
524 arith(vpc, VEC, ARL, dst, mask, src[0], none, none);
525 break;
526 case TGSI_OPCODE_DP3:
527 arith(vpc, VEC, DP3, dst, mask, src[0], src[1], none);
528 break;
529 case TGSI_OPCODE_DP4:
530 arith(vpc, VEC, DP4, dst, mask, src[0], src[1], none);
531 break;
532 case TGSI_OPCODE_DPH:
533 arith(vpc, VEC, DPH, dst, mask, src[0], src[1], none);
534 break;
535 case TGSI_OPCODE_DST:
536 arith(vpc, VEC, DST, dst, mask, src[0], src[1], none);
537 break;
538 case TGSI_OPCODE_EX2:
539 arith(vpc, SCA, EX2, dst, mask, none, none, src[0]);
540 break;
541 case TGSI_OPCODE_EXP:
542 arith(vpc, SCA, EXP, dst, mask, none, none, src[0]);
543 break;
544 case TGSI_OPCODE_FLR:
545 arith(vpc, VEC, FLR, dst, mask, src[0], none, none);
546 break;
547 case TGSI_OPCODE_FRC:
548 arith(vpc, VEC, FRC, dst, mask, src[0], none, none);
549 break;
550 case TGSI_OPCODE_LG2:
551 arith(vpc, SCA, LG2, dst, mask, none, none, src[0]);
552 break;
553 case TGSI_OPCODE_LIT:
554 arith(vpc, SCA, LIT, dst, mask, none, none, src[0]);
555 break;
556 case TGSI_OPCODE_LOG:
557 arith(vpc, SCA, LOG, dst, mask, none, none, src[0]);
558 break;
559 case TGSI_OPCODE_MAD:
560 arith(vpc, VEC, MAD, dst, mask, src[0], src[1], src[2]);
561 break;
562 case TGSI_OPCODE_MAX:
563 arith(vpc, VEC, MAX, dst, mask, src[0], src[1], none);
564 break;
565 case TGSI_OPCODE_MIN:
566 arith(vpc, VEC, MIN, dst, mask, src[0], src[1], none);
567 break;
568 case TGSI_OPCODE_MOV:
569 arith(vpc, VEC, MOV, dst, mask, src[0], none, none);
570 break;
571 case TGSI_OPCODE_MUL:
572 arith(vpc, VEC, MUL, dst, mask, src[0], src[1], none);
573 break;
574 case TGSI_OPCODE_POW:
575 tmp = temp(vpc);
576 arith(vpc, SCA, LG2, tmp, NVFX_VP_MASK_X, none, none,
577 swz(src[0], X, X, X, X));
578 arith(vpc, VEC, MUL, tmp, NVFX_VP_MASK_X, swz(tmp, X, X, X, X),
579 swz(src[1], X, X, X, X), none);
580 arith(vpc, SCA, EX2, dst, mask, none, none,
581 swz(tmp, X, X, X, X));
582 break;
583 case TGSI_OPCODE_RCP:
584 arith(vpc, SCA, RCP, dst, mask, none, none, src[0]);
585 break;
586 case TGSI_OPCODE_RET:
587 break;
588 case TGSI_OPCODE_RSQ:
589 arith(vpc, SCA, RSQ, dst, mask, none, none, abs(src[0]));
590 break;
591 case TGSI_OPCODE_SGE:
592 arith(vpc, VEC, SGE, dst, mask, src[0], src[1], none);
593 break;
594 case TGSI_OPCODE_SGT:
595 arith(vpc, VEC, SGT, dst, mask, src[0], src[1], none);
596 break;
597 case TGSI_OPCODE_SLT:
598 arith(vpc, VEC, SLT, dst, mask, src[0], src[1], none);
599 break;
600 case TGSI_OPCODE_SUB:
601 arith(vpc, VEC, ADD, dst, mask, src[0], none, neg(src[1]));
602 break;
603 case TGSI_OPCODE_XPD:
604 tmp = temp(vpc);
605 arith(vpc, VEC, MUL, tmp, mask,
606 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
607 arith(vpc, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W),
608 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
609 neg(tmp));
610 break;
611 default:
612 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
613 return FALSE;
614 }
615
616 release_temps(vpc);
617 return TRUE;
618 }
619
620 static boolean
621 nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
622 const struct tgsi_full_declaration *fdec)
623 {
624 unsigned idx = fdec->Range.First;
625 int hw;
626
627 switch (fdec->Semantic.Name) {
628 case TGSI_SEMANTIC_POSITION:
629 hw = NVFX_VP(INST_DEST_POS);
630 vpc->hpos_idx = idx;
631 break;
632 case TGSI_SEMANTIC_COLOR:
633 if (fdec->Semantic.Index == 0) {
634 hw = NVFX_VP(INST_DEST_COL0);
635 } else
636 if (fdec->Semantic.Index == 1) {
637 hw = NVFX_VP(INST_DEST_COL1);
638 } else {
639 NOUVEAU_ERR("bad colour semantic index\n");
640 return FALSE;
641 }
642 break;
643 case TGSI_SEMANTIC_BCOLOR:
644 if (fdec->Semantic.Index == 0) {
645 hw = NVFX_VP(INST_DEST_BFC0);
646 } else
647 if (fdec->Semantic.Index == 1) {
648 hw = NVFX_VP(INST_DEST_BFC1);
649 } else {
650 NOUVEAU_ERR("bad bcolour semantic index\n");
651 return FALSE;
652 }
653 break;
654 case TGSI_SEMANTIC_FOG:
655 hw = NVFX_VP(INST_DEST_FOGC);
656 break;
657 case TGSI_SEMANTIC_PSIZE:
658 hw = NVFX_VP(INST_DEST_PSZ);
659 break;
660 case TGSI_SEMANTIC_GENERIC:
661 if (fdec->Semantic.Index <= 7) {
662 hw = NVFX_VP(INST_DEST_TC(fdec->Semantic.Index));
663 } else {
664 NOUVEAU_ERR("bad generic semantic index\n");
665 return FALSE;
666 }
667 break;
668 case TGSI_SEMANTIC_EDGEFLAG:
669 /* not really an error just a fallback */
670 NOUVEAU_ERR("cannot handle edgeflag output\n");
671 return FALSE;
672 default:
673 NOUVEAU_ERR("bad output semantic\n");
674 return FALSE;
675 }
676
677 vpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
678 return TRUE;
679 }
680
681 static boolean
682 nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
683 {
684 struct tgsi_parse_context p;
685 int high_temp = -1, high_addr = -1, nr_imm = 0, i;
686
687 tgsi_parse_init(&p, vpc->vp->pipe.tokens);
688 while (!tgsi_parse_end_of_tokens(&p)) {
689 const union tgsi_full_token *tok = &p.FullToken;
690
691 tgsi_parse_token(&p);
692 switch(tok->Token.Type) {
693 case TGSI_TOKEN_TYPE_IMMEDIATE:
694 nr_imm++;
695 break;
696 case TGSI_TOKEN_TYPE_DECLARATION:
697 {
698 const struct tgsi_full_declaration *fdec;
699
700 fdec = &p.FullToken.FullDeclaration;
701 switch (fdec->Declaration.File) {
702 case TGSI_FILE_TEMPORARY:
703 if (fdec->Range.Last > high_temp) {
704 high_temp =
705 fdec->Range.Last;
706 }
707 break;
708 #if 0 /* this would be nice.. except gallium doesn't track it */
709 case TGSI_FILE_ADDRESS:
710 if (fdec->Range.Last > high_addr) {
711 high_addr =
712 fdec->Range.Last;
713 }
714 break;
715 #endif
716 case TGSI_FILE_OUTPUT:
717 if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec))
718 return FALSE;
719 break;
720 default:
721 break;
722 }
723 }
724 break;
725 #if 1 /* yay, parse instructions looking for address regs instead */
726 case TGSI_TOKEN_TYPE_INSTRUCTION:
727 {
728 const struct tgsi_full_instruction *finst;
729 const struct tgsi_full_dst_register *fdst;
730
731 finst = &p.FullToken.FullInstruction;
732 fdst = &finst->Dst[0];
733
734 if (fdst->Register.File == TGSI_FILE_ADDRESS) {
735 if (fdst->Register.Index > high_addr)
736 high_addr = fdst->Register.Index;
737 }
738
739 }
740 break;
741 #endif
742 default:
743 break;
744 }
745 }
746 tgsi_parse_free(&p);
747
748 if (nr_imm) {
749 vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_sreg));
750 assert(vpc->imm);
751 }
752
753 if (++high_temp) {
754 vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
755 for (i = 0; i < high_temp; i++)
756 vpc->r_temp[i] = temp(vpc);
757 }
758
759 if (++high_addr) {
760 vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_sreg));
761 for (i = 0; i < high_addr; i++)
762 vpc->r_address[i] = temp(vpc);
763 }
764
765 vpc->r_temps_discard = 0;
766 return TRUE;
767 }
768
769 static void
770 nvfx_vertprog_translate(struct nvfx_context *nvfx,
771 struct nvfx_vertex_program *vp)
772 {
773 struct tgsi_parse_context parse;
774 struct nvfx_vpc *vpc = NULL;
775 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
776 int i;
777
778 vpc = CALLOC(1, sizeof(struct nvfx_vpc));
779 if (!vpc)
780 return;
781 vpc->vp = vp;
782
783 if (!nvfx_vertprog_prepare(nvfx, vpc)) {
784 FREE(vpc);
785 return;
786 }
787
788 /* Redirect post-transform vertex position to a temp if user clip
789 * planes are enabled. We need to append code to the vtxprog
790 * to handle clip planes later.
791 */
792 if (vp->ucp.nr) {
793 vpc->r_result[vpc->hpos_idx] = temp(vpc);
794 vpc->r_temps_discard = 0;
795 }
796
797 tgsi_parse_init(&parse, vp->pipe.tokens);
798
799 while (!tgsi_parse_end_of_tokens(&parse)) {
800 tgsi_parse_token(&parse);
801
802 switch (parse.FullToken.Token.Type) {
803 case TGSI_TOKEN_TYPE_IMMEDIATE:
804 {
805 const struct tgsi_full_immediate *imm;
806
807 imm = &parse.FullToken.FullImmediate;
808 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
809 assert(imm->Immediate.NrTokens == 4 + 1);
810 vpc->imm[vpc->nr_imm++] =
811 constant(vpc, -1,
812 imm->u[0].Float,
813 imm->u[1].Float,
814 imm->u[2].Float,
815 imm->u[3].Float);
816 }
817 break;
818 case TGSI_TOKEN_TYPE_INSTRUCTION:
819 {
820 const struct tgsi_full_instruction *finst;
821 finst = &parse.FullToken.FullInstruction;
822 if (!nvfx_vertprog_parse_instruction(nvfx, vpc, finst))
823 goto out_err;
824 }
825 break;
826 default:
827 break;
828 }
829 }
830
831 /* Write out HPOS if it was redirected to a temp earlier */
832 if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
833 struct nvfx_sreg hpos = nvfx_sr(NVFXSR_OUTPUT,
834 NVFX_VP(INST_DEST_POS));
835 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
836
837 arith(vpc, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none);
838 }
839
840 /* Insert code to handle user clip planes */
841 for (i = 0; i < vp->ucp.nr; i++) {
842 struct nvfx_sreg cdst = nvfx_sr(NVFXSR_OUTPUT,
843 NVFX_VP_INST_DEST_CLIP(i));
844 struct nvfx_sreg ceqn = constant(vpc, -1,
845 nvfx->clip.ucp[i][0],
846 nvfx->clip.ucp[i][1],
847 nvfx->clip.ucp[i][2],
848 nvfx->clip.ucp[i][3]);
849 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
850 unsigned mask;
851
852 switch (i) {
853 case 0: case 3: mask = NVFX_VP_MASK_Y; break;
854 case 1: case 4: mask = NVFX_VP_MASK_Z; break;
855 case 2: case 5: mask = NVFX_VP_MASK_W; break;
856 default:
857 NOUVEAU_ERR("invalid clip dist #%d\n", i);
858 goto out_err;
859 }
860
861 arith(vpc, VEC, DP4, cdst, mask, htmp, ceqn, none);
862 }
863
864 vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
865 vp->translated = TRUE;
866 out_err:
867 tgsi_parse_free(&parse);
868 if (vpc->r_temp)
869 FREE(vpc->r_temp);
870 if (vpc->r_address)
871 FREE(vpc->r_address);
872 if (vpc->imm)
873 FREE(vpc->imm);
874 FREE(vpc);
875 }
876
877 static boolean
878 nvfx_vertprog_validate(struct nvfx_context *nvfx)
879 {
880 struct pipe_screen *pscreen = nvfx->pipe.screen;
881 struct nvfx_screen *screen = nvfx->screen;
882 struct nouveau_channel *chan = screen->base.channel;
883 struct nouveau_grobj *eng3d = screen->eng3d;
884 struct nvfx_vertex_program *vp;
885 struct pipe_buffer *constbuf;
886 boolean upload_code = FALSE, upload_data = FALSE;
887 int i;
888
889 if (nvfx->render_mode == HW) {
890 vp = nvfx->vertprog;
891 constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
892
893 if ((nvfx->dirty & NVFX_NEW_UCP) ||
894 memcmp(&nvfx->clip, &vp->ucp, sizeof(vp->ucp))) {
895 nvfx_vertprog_destroy(nvfx, vp);
896 memcpy(&vp->ucp, &nvfx->clip, sizeof(vp->ucp));
897 }
898 } else {
899 vp = nvfx->swtnl.vertprog;
900 constbuf = NULL;
901 }
902
903 /* Translate TGSI shader into hw bytecode */
904 if (vp->translated)
905 goto check_gpu_resources;
906
907 nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG;
908 nvfx_vertprog_translate(nvfx, vp);
909 if (!vp->translated) {
910 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
911 return FALSE;
912 }
913
914 check_gpu_resources:
915 /* Allocate hw vtxprog exec slots */
916 if (!vp->exec) {
917 struct nouveau_resource *heap = nvfx->screen->vp_exec_heap;
918 struct nouveau_stateobj *so;
919 uint vplen = vp->nr_insns;
920
921 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
922 while (heap->next && heap->size < vplen) {
923 struct nvfx_vertex_program *evict;
924
925 evict = heap->next->priv;
926 nouveau_resource_free(&evict->exec);
927 }
928
929 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
930 assert(0);
931 }
932
933 so = so_new(3, 4, 0);
934 so_method(so, eng3d, NV34TCL_VP_START_FROM_ID, 1);
935 so_data (so, vp->exec->start);
936 if(nvfx->is_nv4x) {
937 so_method(so, eng3d, NV40TCL_VP_ATTRIB_EN, 2);
938 so_data (so, vp->ir);
939 so_data (so, vp->or);
940 }
941 so_method(so, eng3d, NV34TCL_VP_CLIP_PLANES_ENABLE, 1);
942 so_data (so, vp->clip_ctrl);
943 so_ref(so, &vp->so);
944 so_ref(NULL, &so);
945
946 upload_code = TRUE;
947 }
948
949 /* Allocate hw vtxprog const slots */
950 if (vp->nr_consts && !vp->data) {
951 struct nouveau_resource *heap = nvfx->screen->vp_data_heap;
952
953 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
954 while (heap->next && heap->size < vp->nr_consts) {
955 struct nvfx_vertex_program *evict;
956
957 evict = heap->next->priv;
958 nouveau_resource_free(&evict->data);
959 }
960
961 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
962 assert(0);
963 }
964
965 /*XXX: handle this some day */
966 assert(vp->data->start >= vp->data_start_min);
967
968 upload_data = TRUE;
969 if (vp->data_start != vp->data->start)
970 upload_code = TRUE;
971 }
972
973 /* If exec or data segments moved we need to patch the program to
974 * fixup offsets and register IDs.
975 */
976 if (vp->exec_start != vp->exec->start) {
977 for (i = 0; i < vp->nr_insns; i++) {
978 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
979
980 if (vpi->has_branch_offset) {
981 assert(0);
982 }
983 }
984
985 vp->exec_start = vp->exec->start;
986 }
987
988 if (vp->nr_consts && vp->data_start != vp->data->start) {
989 for (i = 0; i < vp->nr_insns; i++) {
990 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
991
992 if (vpi->const_index >= 0) {
993 vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
994 vpi->data[1] |=
995 (vpi->const_index + vp->data->start) <<
996 NVFX_VP(INST_CONST_SRC_SHIFT);
997
998 }
999 }
1000
1001 vp->data_start = vp->data->start;
1002 }
1003
1004 /* Update + Upload constant values */
1005 if (vp->nr_consts) {
1006 float *map = NULL;
1007
1008 if (constbuf) {
1009 map = pipe_buffer_map(pscreen, constbuf,
1010 PIPE_BUFFER_USAGE_CPU_READ);
1011 }
1012
1013 for (i = 0; i < vp->nr_consts; i++) {
1014 struct nvfx_vertex_program_data *vpd = &vp->consts[i];
1015
1016 if (vpd->index >= 0) {
1017 if (!upload_data &&
1018 !memcmp(vpd->value, &map[vpd->index * 4],
1019 4 * sizeof(float)))
1020 continue;
1021 memcpy(vpd->value, &map[vpd->index * 4],
1022 4 * sizeof(float));
1023 }
1024
1025 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5);
1026 OUT_RING (chan, i + vp->data->start);
1027 OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
1028 }
1029
1030 if (constbuf)
1031 pipe_buffer_unmap(pscreen, constbuf);
1032 }
1033
1034 /* Upload vtxprog */
1035 if (upload_code) {
1036 #if 0
1037 for (i = 0; i < vp->nr_insns; i++) {
1038 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[0]);
1039 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[1]);
1040 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[2]);
1041 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]);
1042 }
1043 #endif
1044 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
1045 OUT_RING (chan, vp->exec->start);
1046 for (i = 0; i < vp->nr_insns; i++) {
1047 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
1048 OUT_RINGp (chan, vp->insns[i].data, 4);
1049 }
1050 }
1051
1052 if (vp->so != nvfx->state.hw[NVFX_STATE_VERTPROG]) {
1053 so_ref(vp->so, &nvfx->state.hw[NVFX_STATE_VERTPROG]);
1054 return TRUE;
1055 }
1056
1057 return FALSE;
1058 }
1059
1060 void
1061 nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
1062 {
1063 vp->translated = FALSE;
1064
1065 if (vp->nr_insns) {
1066 FREE(vp->insns);
1067 vp->insns = NULL;
1068 vp->nr_insns = 0;
1069 }
1070
1071 if (vp->nr_consts) {
1072 FREE(vp->consts);
1073 vp->consts = NULL;
1074 vp->nr_consts = 0;
1075 }
1076
1077 nouveau_resource_free(&vp->exec);
1078 vp->exec_start = 0;
1079 nouveau_resource_free(&vp->data);
1080 vp->data_start = 0;
1081 vp->data_start_min = 0;
1082
1083 vp->ir = vp->or = vp->clip_ctrl = 0;
1084 so_ref(NULL, &vp->so);
1085 }
1086
1087 struct nvfx_state_entry nvfx_state_vertprog = {
1088 .validate = nvfx_vertprog_validate,
1089 .dirty = {
1090 .pipe = NVFX_NEW_VERTPROG | NVFX_NEW_UCP,
1091 .hw = NVFX_STATE_VERTPROG,
1092 }
1093 };