src/gallium/drivers/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Instruction arguments represented as block-local SSA indices, rather than
  71  * registers. Negative values mean unused. */
  72
  73 typedef struct {
  74         int src0;
  75         int src1;
  76         int dest;
  77
  78         /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
  79          * in. Only valid for ALU ops. */
  80         bool inline_constant;
  81 } ssa_args;
  82
  83 /* Generic in-memory data type repesenting a single logical instruction, rather
  84  * than a single instruction group. This is the preferred form for code gen.
  85  * Multiple midgard_insturctions will later be combined during scheduling,
  86  * though this is not represented in this structure.  Its format bridges
  87  * the low-level binary representation with the higher level semantic meaning.
  88  *
  89  * Notably, it allows registers to be specified as block local SSA, for code
  90  * emitted before the register allocation pass.
  91  */
  92
  93 typedef struct midgard_instruction {
  94         /* Must be first for casting */
  95         struct list_head link;
  96
  97         unsigned type; /* ALU, load/store, texture */
  98
  99         /* If the register allocator has not run yet... */
 100         ssa_args ssa_args;
 101
 102         /* Special fields for an ALU instruction */
 103         midgard_reg_info registers;
 104
 105         /* I.e. (1 << alu_bit) */
 106         int unit;
 107
 108         /* When emitting bundle, should this instruction have a break forced
 109          * before it? Used for r31 writes which are valid only within a single
 110          * bundle and *need* to happen as early as possible... this is a hack,
 111          * TODO remove when we have a scheduler */
 112         bool precede_break;
 113
 114         bool has_constants;
 115         float constants[4];
 116         uint16_t inline_constant;
 117         bool has_blend_constant;
 118
 119         bool compact_branch;
 120         bool writeout;
 121         bool prepacked_branch;
 122
 123         union {
 124                 midgard_load_store_word load_store;
 125                 midgard_vector_alu alu;
 126                 midgard_texture_word texture;
 127                 midgard_branch_extended branch_extended;
 128                 uint16_t br_compact;
 129
 130                 /* General branch, rather than packed br_compact. Higher level
 131                  * than the other components */
 132                 midgard_branch branch;
 133         };
 134 } midgard_instruction;
 135
 136 typedef struct midgard_block {
 137         /* Link to next block. Must be first for mir_get_block */
 138         struct list_head link;
 139
 140         /* List of midgard_instructions emitted for the current block */
 141         struct list_head instructions;
 142
 143         bool is_scheduled;
 144
 145         /* List of midgard_bundles emitted (after the scheduler has run) */
 146         struct util_dynarray bundles;
 147
 148         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 149         unsigned quadword_count;
 150
 151         /* Successors: always one forward (the block after us), maybe
 152          * one backwards (for a backward branch). No need for a second
 153          * forward, since graph traversal would get there eventually
 154          * anyway */
 155         struct midgard_block *successors[2];
 156         unsigned nr_successors;
 157
 158         /* The successors pointer form a graph, and in the case of
 159          * complex control flow, this graph has a cycles. To aid
 160          * traversal during liveness analysis, we have a visited?
 161          * boolean for passes to use as they see fit, provided they
 162          * clean up later */
 163         bool visited;
 164 } midgard_block;
 165
 166 typedef struct midgard_bundle {
 167         /* Tag for the overall bundle */
 168         int tag;
 169
 170         /* Instructions contained by the bundle */
 171         int instruction_count;
 172         midgard_instruction instructions[5];
 173
 174         /* Bundle-wide ALU configuration */
 175         int padding;
 176         int control;
 177         bool has_embedded_constants;
 178         float constants[4];
 179         bool has_blend_constant;
 180
 181         uint16_t register_words[8];
 182         int register_words_count;
 183
 184         uint64_t body_words[8];
 185         size_t body_size[8];
 186         int body_words_count;
 187 } midgard_bundle;
 188
 189 typedef struct compiler_context {
 190         nir_shader *nir;
 191         gl_shader_stage stage;
 192
 193         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 194         bool is_blend;
 195
 196         /* Tracking for blend constant patching */
 197         int blend_constant_offset;
 198
 199         /* Current NIR function */
 200         nir_function *func;
 201
 202         /* Unordered list of midgard_blocks */
 203         int block_count;
 204         struct list_head blocks;
 205
 206         midgard_block *initial_block;
 207         midgard_block *previous_source_block;
 208         midgard_block *final_block;
 209
 210         /* List of midgard_instructions emitted for the current block */
 211         midgard_block *current_block;
 212
 213         /* The current "depth" of the loop, for disambiguating breaks/continues
 214          * when using nested loops */
 215         int current_loop_depth;
 216
 217         /* Constants which have been loaded, for later inlining */
 218         struct hash_table_u64 *ssa_constants;
 219
 220         /* SSA indices to be outputted to corresponding varying offset */
 221         struct hash_table_u64 *ssa_varyings;
 222
 223         /* SSA values / registers which have been aliased. Naively, these
 224          * demand a fmov output; instead, we alias them in a later pass to
 225          * avoid the wasted op.
 226          *
 227          * A note on encoding: to avoid dynamic memory management here, rather
 228          * than ampping to a pointer, we map to the source index; the key
 229          * itself is just the destination index. */
 230
 231         struct hash_table_u64 *ssa_to_alias;
 232         struct set *leftover_ssa_to_alias;
 233
 234         /* Actual SSA-to-register for RA */
 235         struct hash_table_u64 *ssa_to_register;
 236
 237         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 238         struct hash_table_u64 *hash_to_temp;
 239         int temp_count;
 240         int max_hash;
 241
 242         /* Just the count of the max register used. Higher count => higher
 243          * register pressure */
 244         int work_registers;
 245
 246         /* Used for cont/last hinting. Increase when a tex op is added.
 247          * Decrease when a tex op is removed. */
 248         int texture_op_count;
 249
 250         /* Mapping of texture register -> SSA index for unaliasing */
 251         int texture_index[2];
 252
 253         /* If any path hits a discard instruction */
 254         bool can_discard;
 255
 256         /* The number of uniforms allowable for the fast path */
 257         int uniform_cutoff;
 258
 259         /* Count of instructions emitted from NIR overall, across all blocks */
 260         int instruction_count;
 261
 262         /* Alpha ref value passed in */
 263         float alpha_ref;
 264
 265         /* The index corresponding to the fragment output */
 266         unsigned fragment_output;
 267
 268         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 269         unsigned sysvals[MAX_SYSVAL_COUNT];
 270         unsigned sysval_count;
 271         struct hash_table_u64 *sysval_to_id;
 272 } compiler_context;
 273
 274 /* Helpers for manipulating the above structures (forming the driver IR) */
 275
 276 /* Append instruction to end of current block */
 277
 278 static inline midgard_instruction *
 279 mir_upload_ins(struct midgard_instruction ins)
 280 {
 281         midgard_instruction *heap = malloc(sizeof(ins));
 282         memcpy(heap, &ins, sizeof(ins));
 283         return heap;
 284 }
 285
 286 static inline void
 287 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 288 {
 289         list_addtail(&(mir_upload_ins(ins))->link, &ctx->current_block->instructions);
 290 }
 291
 292 static inline void
 293 mir_insert_instruction_before(struct midgard_instruction *tag, struct midgard_instruction ins)
 294 {
 295         list_addtail(&(mir_upload_ins(ins))->link, &tag->link);
 296 }
 297
 298 static inline void
 299 mir_remove_instruction(struct midgard_instruction *ins)
 300 {
 301         list_del(&ins->link);
 302 }
 303
 304 static inline midgard_instruction*
 305 mir_prev_op(struct midgard_instruction *ins)
 306 {
 307         return list_last_entry(&(ins->link), midgard_instruction, link);
 308 }
 309
 310 static inline midgard_instruction*
 311 mir_next_op(struct midgard_instruction *ins)
 312 {
 313         return list_first_entry(&(ins->link), midgard_instruction, link);
 314 }
 315
 316 #define mir_foreach_block(ctx, v) \
 317         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 318
 319 #define mir_foreach_block_from(ctx, from, v) \
 320         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 321
 322 /* The following routines are for use before the scheduler has run */
 323
 324 #define mir_foreach_instr(ctx, v) \
 325         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 326
 327 #define mir_foreach_instr_safe(ctx, v) \
 328         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 329
 330 #define mir_foreach_instr_in_block(block, v) \
 331         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 332
 333 #define mir_foreach_instr_in_block_safe(block, v) \
 334         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 335
 336 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 337         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 338
 339 #define mir_foreach_instr_in_block_from(block, v, from) \
 340         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 341
 342 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 343         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 344
 345 #define mir_foreach_bundle_in_block(block, v) \
 346         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 347
 348 static inline midgard_instruction *
 349 mir_last_in_block(struct midgard_block *block)
 350 {
 351         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 352 }
 353
 354 static inline midgard_block *
 355 mir_get_block(compiler_context *ctx, int idx)
 356 {
 357         struct list_head *lst = &ctx->blocks;
 358
 359         while ((idx--) + 1)
 360                 lst = lst->next;
 361
 362         return (struct midgard_block *) lst;
 363 }
 364
 365 /* MIR printing */
 366
 367 void mir_print_instruction(midgard_instruction *ins);
 368 void mir_print_block(midgard_block *block);
 369 void mir_print_shader(compiler_context *ctx);
 370
 371 /* MIR goodies */
 372
 373 static const midgard_vector_alu_src blank_alu_src = {
 374         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 375 };
 376
 377 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 378         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 379 };
 380
 381 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 382         .full = true
 383 };
 384
 385 /* Used for encoding the unused source of 1-op instructions */
 386 static const midgard_vector_alu_src zero_alu_src = { 0 };
 387
 388 /* 'Intrinsic' move for aliasing */
 389
 390 static inline midgard_instruction
 391 v_fmov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 392 {
 393         midgard_instruction ins = {
 394                 .type = TAG_ALU_4,
 395                 .ssa_args = {
 396                         .src0 = SSA_UNUSED_1,
 397                         .src1 = src,
 398                         .dest = dest,
 399                 },
 400                 .alu = {
 401                         .op = midgard_alu_op_fmov,
 402                         .reg_mode = midgard_reg_mode_32,
 403                         .dest_override = midgard_dest_override_none,
 404                         .mask = 0xFF,
 405                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 406                         .src2 = vector_alu_srco_unsigned(mod)
 407                 },
 408         };
 409
 410         return ins;
 411 }
 412
 413 /* Scheduling */
 414
 415 void schedule_program(compiler_context *ctx);
 416
 417 /* Register allocation */
 418
 419 struct ra_graph;
 420
 421 struct ra_graph* allocate_registers(compiler_context *ctx);
 422 void install_registers(compiler_context *ctx, struct ra_graph *g);
 423 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 424
 425 #endif