src/gallium/drivers/panfrost/midgard/helpers.h

   1 /* Author(s):
   2  *  Alyssa Rosenzweig
   3  *
   4  * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #define OP_IS_STORE_VARY(op) (\
  26                 op == midgard_op_store_vary_16 || \
  27                 op == midgard_op_store_vary_32 \
  28         )
  29
  30 #define OP_IS_STORE(op) (\
  31                 OP_IS_STORE_VARY(op) || \
  32                 op == midgard_op_store_cubemap_coords \
  33         )
  34
  35 #define OP_IS_MOVE(op) ( \
  36                 op == midgard_alu_op_fmov || \
  37                 op == midgard_alu_op_imov \
  38         )
  39
  40 /* ALU control words are single bit fields with a lot of space */
  41
  42 #define ALU_ENAB_VEC_MUL  (1 << 17)
  43 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  44 #define ALU_ENAB_VEC_ADD  (1 << 21)
  45 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  46 #define ALU_ENAB_VEC_LUT  (1 << 25)
  47 #define ALU_ENAB_BR_COMPACT (1 << 26)
  48 #define ALU_ENAB_BRANCH   (1 << 27)
  49
  50 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  51
  52 /* Denotes an opcode that takes a vector input with a fixed-number of
  53  * channels, but outputs to only a single output channel, like dot products.
  54  * For these, to determine the effective mask, this quirk can be set. We have
  55  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
  56  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
  57  * make sense (since then why are we quirked?), so that corresponds to "no
  58  * count set" */
  59
  60 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
  61 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
  62
  63 /* For instructions that take a single argument, normally the first argument
  64  * slot is used for the argument and the second slot is a dummy #0 constant.
  65  * However, there are exceptions: instructions like fmov store their argument
  66  * in the _second_ slot and store a dummy r24 in the first slot, designated by
  67  * QUIRK_FLIPPED_R24 */
  68
  69 #define QUIRK_FLIPPED_R24 (1 << 2)
  70
  71 /* Vector-independant shorthands for the above; these numbers are arbitrary and
  72  * not from the ISA. Convert to the above with unit_enum_to_midgard */
  73
  74 #define UNIT_MUL 0
  75 #define UNIT_ADD 1
  76 #define UNIT_LUT 2
  77
  78 /* 4-bit type tags */
  79
  80 #define TAG_TEXTURE_4 0x3
  81 #define TAG_LOAD_STORE_4 0x5
  82 #define TAG_ALU_4 0x8
  83 #define TAG_ALU_8 0x9
  84 #define TAG_ALU_12 0xA
  85 #define TAG_ALU_16 0xB
  86
  87 /* Special register aliases */
  88
  89 #define MAX_WORK_REGISTERS 16
  90
  91 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
  92 #define REGISTER_UNIFORMS 24
  93
  94 #define REGISTER_UNUSED 24
  95 #define REGISTER_CONSTANT 26
  96 #define REGISTER_VARYING_BASE 26
  97 #define REGISTER_OFFSET 27
  98 #define REGISTER_TEXTURE_BASE 28
  99 #define REGISTER_SELECT 31
 100
 101 /* SSA helper aliases to mimic the registers. UNUSED_0 encoded as an inline
 102  * constant. UNUSED_1 encoded as REGISTER_UNUSED */
 103
 104 #define SSA_UNUSED_0 0
 105 #define SSA_UNUSED_1 -2
 106
 107 #define SSA_FIXED_SHIFT 24
 108 #define SSA_FIXED_REGISTER(reg) ((1 + reg) << SSA_FIXED_SHIFT)
 109 #define SSA_REG_FROM_FIXED(reg) ((reg >> SSA_FIXED_SHIFT) - 1)
 110 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 111
 112 /* Swizzle support */
 113
 114 #define SWIZZLE(A, B, C, D) ((D << 6) | (C << 4) | (B << 2) | (A << 0))
 115 #define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
 116 #define COMPONENT_X 0x0
 117 #define COMPONENT_Y 0x1
 118 #define COMPONENT_Z 0x2
 119 #define COMPONENT_W 0x3
 120
 121 /* See ISA notes */
 122
 123 #define LDST_NOP (3)
 124
 125 /* Is this opcode that of an integer (regardless of signedness)? */
 126
 127 static bool
 128 midgard_is_integer_op(int op)
 129 {
 130         switch (op) {
 131         case midgard_alu_op_iadd:
 132         case midgard_alu_op_ishladd:
 133         case midgard_alu_op_isub:
 134         case midgard_alu_op_imul:
 135         case midgard_alu_op_imin:
 136         case midgard_alu_op_umin:
 137         case midgard_alu_op_imax:
 138         case midgard_alu_op_umax:
 139         case midgard_alu_op_iasr:
 140         case midgard_alu_op_ilsr:
 141         case midgard_alu_op_ishl:
 142         case midgard_alu_op_iand:
 143         case midgard_alu_op_ior:
 144         case midgard_alu_op_inot:
 145         case midgard_alu_op_iandnot:
 146         case midgard_alu_op_ixor:
 147         case midgard_alu_op_ilzcnt:
 148         case midgard_alu_op_ibitcount8:
 149         case midgard_alu_op_imov:
 150         case midgard_alu_op_iabs:
 151         case midgard_alu_op_ieq:
 152         case midgard_alu_op_ine:
 153         case midgard_alu_op_ult:
 154         case midgard_alu_op_ule:
 155         case midgard_alu_op_ilt:
 156         case midgard_alu_op_ile:
 157         case midgard_alu_op_iball_eq:
 158         case midgard_alu_op_ball:
 159         case midgard_alu_op_uball_lt:
 160         case midgard_alu_op_uball_lte:
 161         case midgard_alu_op_iball_lt:
 162         case midgard_alu_op_iball_lte:
 163         case midgard_alu_op_ibany_eq:
 164         case midgard_alu_op_ibany_neq:
 165         case midgard_alu_op_ubany_lt:
 166         case midgard_alu_op_ubany_lte:
 167         case midgard_alu_op_ibany_lt:
 168         case midgard_alu_op_ibany_lte:
 169         case midgard_alu_op_i2f:
 170         case midgard_alu_op_u2f:
 171         case midgard_alu_op_icsel:
 172                 return true;
 173
 174         default:
 175                 return false;
 176         }
 177 }
 178
 179 /* Is this unit a branch? */
 180 static bool
 181 midgard_is_branch_unit(unsigned unit)
 182 {
 183         return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
 184 }
 185
 186 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 187  * implemented on some subset of these units (or occassionally all of them).
 188  * This table encodes a bit mask of valid units for each opcode, so the
 189  * scheduler can figure where to plonk the instruction. */
 190
 191 /* Shorthands for each unit */
 192 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 193 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 194 #define UNIT_VADD ALU_ENAB_VEC_ADD
 195 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 196 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 197
 198 /* Shorthands for usual combinations of units */
 199
 200 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 201 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 202 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 203 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 204 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 205 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 206 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 207
 208 static unsigned alu_opcode_props[256] = {
 209         [midgard_alu_op_fadd]            = UNITS_ADD,
 210         [midgard_alu_op_fmul]            = UNITS_MUL | UNIT_VLUT,
 211         [midgard_alu_op_fmin]            = UNITS_MUL | UNITS_ADD,
 212         [midgard_alu_op_fmax]            = UNITS_MUL | UNITS_ADD,
 213         [midgard_alu_op_imin]            = UNITS_MOST,
 214         [midgard_alu_op_imax]            = UNITS_MOST,
 215         [midgard_alu_op_umin]            = UNITS_MOST,
 216         [midgard_alu_op_umax]            = UNITS_MOST,
 217         [midgard_alu_op_fmov]            = UNITS_ALL | QUIRK_FLIPPED_R24,
 218         [midgard_alu_op_fround]          = UNITS_ADD,
 219         [midgard_alu_op_froundeven]      = UNITS_ADD,
 220         [midgard_alu_op_ftrunc]          = UNITS_ADD,
 221         [midgard_alu_op_ffloor]          = UNITS_ADD,
 222         [midgard_alu_op_fceil]           = UNITS_ADD,
 223         [midgard_alu_op_ffma]            = UNIT_VLUT,
 224
 225         /* Though they output a scalar, they need to run on a vector unit
 226          * since they process vectors */
 227         [midgard_alu_op_fdot3]           = UNIT_VMUL | OP_CHANNEL_COUNT(3),
 228         [midgard_alu_op_fdot4]           = UNIT_VMUL | OP_CHANNEL_COUNT(4),
 229
 230         /* Incredibly, iadd can run on vmul, etc */
 231         [midgard_alu_op_iadd]            = UNITS_MOST,
 232         [midgard_alu_op_iabs]            = UNITS_MOST,
 233         [midgard_alu_op_isub]            = UNITS_MOST,
 234         [midgard_alu_op_imul]            = UNITS_MUL,
 235         [midgard_alu_op_imov]            = UNITS_MOST | QUIRK_FLIPPED_R24,
 236
 237         /* For vector comparisons, use ball etc */
 238         [midgard_alu_op_feq]             = UNITS_MOST,
 239         [midgard_alu_op_fne]             = UNITS_MOST,
 240         [midgard_alu_op_fle]             = UNITS_MOST,
 241         [midgard_alu_op_flt]             = UNITS_MOST,
 242         [midgard_alu_op_ieq]             = UNITS_MOST,
 243         [midgard_alu_op_ine]             = UNITS_MOST,
 244         [midgard_alu_op_ilt]             = UNITS_MOST,
 245         [midgard_alu_op_ile]             = UNITS_MOST,
 246         [midgard_alu_op_ule]             = UNITS_MOST,
 247         [midgard_alu_op_ult]             = UNITS_MOST,
 248
 249         [midgard_alu_op_icsel]           = UNITS_ADD,
 250         [midgard_alu_op_fcsel_i]         = UNITS_ADD,
 251         [midgard_alu_op_fcsel]           = UNITS_ADD | UNIT_SMUL,
 252
 253         [midgard_alu_op_frcp]            = UNIT_VLUT,
 254         [midgard_alu_op_frsqrt]          = UNIT_VLUT,
 255         [midgard_alu_op_fsqrt]           = UNIT_VLUT,
 256         [midgard_alu_op_fpow_pt1]        = UNIT_VLUT,
 257         [midgard_alu_op_fexp2]           = UNIT_VLUT,
 258         [midgard_alu_op_flog2]           = UNIT_VLUT,
 259
 260         [midgard_alu_op_f2i]             = UNITS_ADD,
 261         [midgard_alu_op_f2u]             = UNITS_ADD,
 262         [midgard_alu_op_f2u8]            = UNITS_ADD,
 263         [midgard_alu_op_i2f]             = UNITS_ADD,
 264         [midgard_alu_op_u2f]             = UNITS_ADD,
 265
 266         [midgard_alu_op_fsin]            = UNIT_VLUT,
 267         [midgard_alu_op_fcos]            = UNIT_VLUT,
 268
 269         [midgard_alu_op_iand]            = UNITS_ADD, /* XXX: Test case where it's right on smul but not sadd */
 270         [midgard_alu_op_ior]             = UNITS_ADD,
 271         [midgard_alu_op_ixor]            = UNITS_ADD,
 272         [midgard_alu_op_ilzcnt]          = UNITS_ADD,
 273         [midgard_alu_op_ibitcount8]      = UNITS_ADD,
 274         [midgard_alu_op_inot]            = UNITS_MOST,
 275         [midgard_alu_op_ishl]            = UNITS_ADD,
 276         [midgard_alu_op_iasr]            = UNITS_ADD,
 277         [midgard_alu_op_ilsr]            = UNITS_ADD,
 278         [midgard_alu_op_ilsr]            = UNITS_ADD,
 279
 280         [midgard_alu_op_fball_eq]        = UNITS_VECTOR,
 281         [midgard_alu_op_fbany_neq]       = UNITS_VECTOR,
 282         [midgard_alu_op_iball_eq]        = UNITS_VECTOR,
 283         [midgard_alu_op_ibany_neq]       = UNITS_VECTOR
 284 };