2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 /* Successors: always one forward (the block after us), maybe
173 * one backwards (for a backward branch). No need for a second
174 * forward, since graph traversal would get there eventually
176 struct midgard_block
*successors
[2];
177 unsigned nr_successors
;
179 /* The successors pointer form a graph, and in the case of
180 * complex control flow, this graph has a cycles. To aid
181 * traversal during liveness analysis, we have a visited?
182 * boolean for passes to use as they see fit, provided they
188 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
190 block
->successors
[block
->nr_successors
++] = successor
;
191 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
194 /* Helpers to generate midgard_instruction's using macro magic, since every
195 * driver seems to do it that way */
197 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
198 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
200 #define M_LOAD_STORE(name, rname, uname) \
201 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
202 midgard_instruction i = { \
203 .type = TAG_LOAD_STORE_4, \
210 .op = midgard_op_##name, \
212 .swizzle = SWIZZLE_XYZW, \
220 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
221 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
223 const midgard_vector_alu_src blank_alu_src
= {
224 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
227 const midgard_vector_alu_src blank_alu_src_xxxx
= {
228 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
231 const midgard_scalar_alu_src blank_scalar_alu_src
= {
235 /* Used for encoding the unused source of 1-op instructions */
236 const midgard_vector_alu_src zero_alu_src
= { 0 };
238 /* Coerce structs to integer */
241 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
244 memcpy(&u
, &src
, sizeof(src
));
248 static midgard_vector_alu_src
249 vector_alu_from_unsigned(unsigned u
)
251 midgard_vector_alu_src s
;
252 memcpy(&s
, &u
, sizeof(s
));
256 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
257 * the corresponding Midgard source */
259 static midgard_vector_alu_src
260 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
262 if (!src
) return blank_alu_src
;
264 midgard_vector_alu_src alu_src
= {
267 .half
= 0, /* TODO */
268 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
272 /* TODO: sign-extend/zero-extend */
273 alu_src
.mod
= midgard_int_normal
;
275 /* These should have been lowered away */
276 assert(!(src
->abs
|| src
->negate
));
278 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
285 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
288 if (!is_int
&& src
.mod
) return true;
291 for (unsigned c
= 0; c
< 4; ++c
) {
292 if (!(mask
& (1 << c
))) continue;
293 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
299 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
301 static midgard_instruction
302 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
304 midgard_instruction ins
= {
307 .src0
= SSA_UNUSED_1
,
312 .op
= midgard_alu_op_fmov
,
313 .reg_mode
= midgard_reg_mode_full
,
314 .dest_override
= midgard_dest_override_none
,
316 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
317 .src2
= vector_alu_srco_unsigned(mod
)
324 /* load/store instructions have both 32-bit and 16-bit variants, depending on
325 * whether we are using vectors composed of highp or mediump. At the moment, we
326 * don't support half-floats -- this requires changes in other parts of the
327 * compiler -- therefore the 16-bit versions are commented out. */
329 //M_LOAD(load_attr_16);
330 M_LOAD(load_attr_32
);
331 //M_LOAD(load_vary_16);
332 M_LOAD(load_vary_32
);
333 //M_LOAD(load_uniform_16);
334 M_LOAD(load_uniform_32
);
335 M_LOAD(load_color_buffer_8
);
336 //M_STORE(store_vary_16);
337 M_STORE(store_vary_32
);
338 M_STORE(store_cubemap_coords
);
340 static midgard_instruction
341 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
343 midgard_branch_cond branch
= {
351 memcpy(&compact
, &branch
, sizeof(branch
));
353 midgard_instruction ins
= {
355 .unit
= ALU_ENAB_BR_COMPACT
,
356 .prepacked_branch
= true,
357 .compact_branch
= true,
358 .br_compact
= compact
361 if (op
== midgard_jmp_writeout_op_writeout
)
367 static midgard_instruction
368 v_branch(bool conditional
, bool invert
)
370 midgard_instruction ins
= {
372 .unit
= ALU_ENAB_BRANCH
,
373 .compact_branch
= true,
375 .conditional
= conditional
,
376 .invert_conditional
= invert
383 static midgard_branch_extended
384 midgard_create_branch_extended( midgard_condition cond
,
385 midgard_jmp_writeout_op op
,
387 signed quadword_offset
)
389 /* For unclear reasons, the condition code is repeated 8 times */
390 uint16_t duplicated_cond
=
400 midgard_branch_extended branch
= {
402 .dest_tag
= dest_tag
,
403 .offset
= quadword_offset
,
404 .cond
= duplicated_cond
410 typedef struct midgard_bundle
{
411 /* Tag for the overall bundle */
414 /* Instructions contained by the bundle */
415 int instruction_count
;
416 midgard_instruction instructions
[5];
418 /* Bundle-wide ALU configuration */
421 bool has_embedded_constants
;
423 bool has_blend_constant
;
425 uint16_t register_words
[8];
426 int register_words_count
;
428 uint64_t body_words
[8];
430 int body_words_count
;
433 typedef struct compiler_context
{
435 gl_shader_stage stage
;
437 /* Is internally a blend shader? Depends on stage == FRAGMENT */
440 /* Tracking for blend constant patching */
441 int blend_constant_number
;
442 int blend_constant_offset
;
444 /* Current NIR function */
447 /* Unordered list of midgard_blocks */
449 struct list_head blocks
;
451 midgard_block
*initial_block
;
452 midgard_block
*previous_source_block
;
453 midgard_block
*final_block
;
455 /* List of midgard_instructions emitted for the current block */
456 midgard_block
*current_block
;
458 /* The current "depth" of the loop, for disambiguating breaks/continues
459 * when using nested loops */
460 int current_loop_depth
;
462 /* Constants which have been loaded, for later inlining */
463 struct hash_table_u64
*ssa_constants
;
465 /* SSA indices to be outputted to corresponding varying offset */
466 struct hash_table_u64
*ssa_varyings
;
468 /* SSA values / registers which have been aliased. Naively, these
469 * demand a fmov output; instead, we alias them in a later pass to
470 * avoid the wasted op.
472 * A note on encoding: to avoid dynamic memory management here, rather
473 * than ampping to a pointer, we map to the source index; the key
474 * itself is just the destination index. */
476 struct hash_table_u64
*ssa_to_alias
;
477 struct set
*leftover_ssa_to_alias
;
479 /* Actual SSA-to-register for RA */
480 struct hash_table_u64
*ssa_to_register
;
482 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
483 struct hash_table_u64
*hash_to_temp
;
487 /* Just the count of the max register used. Higher count => higher
488 * register pressure */
491 /* Used for cont/last hinting. Increase when a tex op is added.
492 * Decrease when a tex op is removed. */
493 int texture_op_count
;
495 /* Mapping of texture register -> SSA index for unaliasing */
496 int texture_index
[2];
498 /* If any path hits a discard instruction */
501 /* The number of uniforms allowable for the fast path */
504 /* Count of instructions emitted from NIR overall, across all blocks */
505 int instruction_count
;
507 /* Alpha ref value passed in */
510 /* The index corresponding to the fragment output */
511 unsigned fragment_output
;
513 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
514 unsigned sysvals
[MAX_SYSVAL_COUNT
];
515 unsigned sysval_count
;
516 struct hash_table_u64
*sysval_to_id
;
519 /* Append instruction to end of current block */
521 static midgard_instruction
*
522 mir_upload_ins(struct midgard_instruction ins
)
524 midgard_instruction
*heap
= malloc(sizeof(ins
));
525 memcpy(heap
, &ins
, sizeof(ins
));
530 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
532 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
536 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
538 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
542 mir_remove_instruction(struct midgard_instruction
*ins
)
544 list_del(&ins
->link
);
547 static midgard_instruction
*
548 mir_prev_op(struct midgard_instruction
*ins
)
550 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
553 static midgard_instruction
*
554 mir_next_op(struct midgard_instruction
*ins
)
556 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
559 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
560 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
562 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
563 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
564 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
565 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
566 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
567 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
568 #define mir_foreach_instr_in_block_from_rev(block, v, from) list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
571 static midgard_instruction
*
572 mir_last_in_block(struct midgard_block
*block
)
574 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
577 static midgard_block
*
578 mir_get_block(compiler_context
*ctx
, int idx
)
580 struct list_head
*lst
= &ctx
->blocks
;
585 return (struct midgard_block
*) lst
;
588 /* Pretty printer for internal Midgard IR */
591 print_mir_source(int source
)
593 if (source
>= SSA_FIXED_MINIMUM
) {
594 /* Specific register */
595 int reg
= SSA_REG_FROM_FIXED(source
);
597 /* TODO: Moving threshold */
598 if (reg
> 16 && reg
< 24)
599 printf("u%d", 23 - reg
);
603 printf("%d", source
);
608 print_mir_instruction(midgard_instruction
*ins
)
614 midgard_alu_op op
= ins
->alu
.op
;
615 const char *name
= alu_opcode_names
[op
];
618 printf("%d.", ins
->unit
);
620 printf("%s", name
? name
: "??");
624 case TAG_LOAD_STORE_4
: {
625 midgard_load_store_op op
= ins
->load_store
.op
;
626 const char *name
= load_store_opcode_names
[op
];
633 case TAG_TEXTURE_4
: {
642 ssa_args
*args
= &ins
->ssa_args
;
644 printf(" %d, ", args
->dest
);
646 print_mir_source(args
->src0
);
649 if (args
->inline_constant
)
650 printf("#%d", ins
->inline_constant
);
652 print_mir_source(args
->src1
);
654 if (ins
->has_constants
)
655 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
661 print_mir_block(midgard_block
*block
)
665 mir_foreach_instr_in_block(block
, ins
) {
666 print_mir_instruction(ins
);
673 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
675 ins
->has_constants
= true;
676 memcpy(&ins
->constants
, constants
, 16);
678 /* If this is the special blend constant, mark this instruction */
680 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
681 ins
->has_blend_constant
= true;
685 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
687 return glsl_count_attribute_slots(type
, false);
690 /* Lower fdot2 to a vector multiplication followed by channel addition */
692 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
694 if (alu
->op
!= nir_op_fdot2
)
697 b
->cursor
= nir_before_instr(&alu
->instr
);
699 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
700 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
702 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
704 nir_ssa_def
*sum
= nir_fadd(b
,
705 nir_channel(b
, product
, 0),
706 nir_channel(b
, product
, 1));
708 /* Replace the fdot2 with this sum */
709 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
713 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
715 switch (instr
->intrinsic
) {
716 case nir_intrinsic_load_viewport_scale
:
717 return PAN_SYSVAL_VIEWPORT_SCALE
;
718 case nir_intrinsic_load_viewport_offset
:
719 return PAN_SYSVAL_VIEWPORT_OFFSET
;
726 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
730 if (instr
->type
== nir_instr_type_intrinsic
) {
731 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
732 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
738 /* We have a sysval load; check if it's already been assigned */
740 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
743 /* It hasn't -- so assign it now! */
745 unsigned id
= ctx
->sysval_count
++;
746 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
747 ctx
->sysvals
[id
] = sysval
;
751 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
753 ctx
->sysval_count
= 0;
755 nir_foreach_function(function
, shader
) {
756 if (!function
->impl
) continue;
758 nir_foreach_block(block
, function
->impl
) {
759 nir_foreach_instr_safe(instr
, block
) {
760 midgard_nir_assign_sysval_body(ctx
, instr
);
767 midgard_nir_lower_fdot2(nir_shader
*shader
)
769 bool progress
= false;
771 nir_foreach_function(function
, shader
) {
772 if (!function
->impl
) continue;
775 nir_builder
*b
= &_b
;
776 nir_builder_init(b
, function
->impl
);
778 nir_foreach_block(block
, function
->impl
) {
779 nir_foreach_instr_safe(instr
, block
) {
780 if (instr
->type
!= nir_instr_type_alu
) continue;
782 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
783 midgard_nir_lower_fdot2_body(b
, alu
);
789 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
797 optimise_nir(nir_shader
*nir
)
801 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
802 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
804 nir_lower_tex_options lower_tex_options
= {
808 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
813 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
814 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
816 NIR_PASS(progress
, nir
, nir_copy_prop
);
817 NIR_PASS(progress
, nir
, nir_opt_dce
);
818 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
819 NIR_PASS(progress
, nir
, nir_opt_cse
);
820 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
821 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
822 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
823 NIR_PASS(progress
, nir
, nir_opt_undef
);
824 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
827 nir_var_function_temp
);
829 /* TODO: Enable vectorize when merged upstream */
830 // NIR_PASS(progress, nir, nir_opt_vectorize);
833 /* Must be run at the end to prevent creation of fsin/fcos ops */
834 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
839 NIR_PASS(progress
, nir
, nir_opt_dce
);
840 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
841 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
842 NIR_PASS(progress
, nir
, nir_copy_prop
);
845 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
846 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
848 /* Lower mods for float ops only. Integer ops don't support modifiers
849 * (saturate doesn't make sense on integers, neg/abs require dedicated
852 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
853 NIR_PASS(progress
, nir
, nir_copy_prop
);
854 NIR_PASS(progress
, nir
, nir_opt_dce
);
856 /* We implement booleans as 32-bit 0/~0 */
857 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
859 /* Take us out of SSA */
860 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
861 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
863 /* We are a vector architecture; write combine where possible */
864 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
865 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
867 NIR_PASS(progress
, nir
, nir_opt_dce
);
870 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
871 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
872 * r0. See the comments in compiler_context */
875 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
877 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
878 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
881 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
884 unalias_ssa(compiler_context
*ctx
, int dest
)
886 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
887 /* TODO: Remove from leftover or no? */
891 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
893 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
897 midgard_is_pinned(compiler_context
*ctx
, int index
)
899 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
902 /* Do not actually emit a load; instead, cache the constant for inlining */
905 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
907 nir_ssa_def def
= instr
->def
;
909 float *v
= ralloc_array(NULL
, float, 4);
910 nir_const_load_to_arr(v
, instr
, f32
);
911 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
914 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
918 expand_writemask(unsigned mask
)
922 for (int i
= 0; i
< 4; ++i
)
930 squeeze_writemask(unsigned mask
)
934 for (int i
= 0; i
< 4; ++i
)
935 if (mask
& (3 << (2 * i
)))
942 /* Determines effective writemask, taking quirks and expansion into account */
944 effective_writemask(midgard_vector_alu
*alu
)
946 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
949 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
951 /* If there is a fixed channel count, construct the appropriate mask */
954 return (1 << channel_count
) - 1;
956 /* Otherwise, just squeeze the existing mask */
957 return squeeze_writemask(alu
->mask
);
961 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
963 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
966 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
971 /* If no temp is find, allocate one */
972 temp
= ctx
->temp_count
++;
973 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
975 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
981 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
984 return src
->ssa
->index
;
986 assert(!src
->reg
.indirect
);
987 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
992 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
995 return dst
->ssa
.index
;
997 assert(!dst
->reg
.indirect
);
998 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
1003 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
1005 return nir_src_index(ctx
, &src
->src
);
1008 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
1009 * a conditional test) into that register */
1012 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
1014 int condition
= nir_src_index(ctx
, src
);
1016 /* Source to swizzle the desired component into w */
1018 const midgard_vector_alu_src alu_src
= {
1019 .swizzle
= SWIZZLE(component
, component
, component
, component
),
1022 /* There is no boolean move instruction. Instead, we simulate a move by
1023 * ANDing the condition with itself to get it into r31.w */
1025 midgard_instruction ins
= {
1027 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
1031 .dest
= SSA_FIXED_REGISTER(31),
1034 .op
= midgard_alu_op_iand
,
1035 .reg_mode
= midgard_reg_mode_full
,
1036 .dest_override
= midgard_dest_override_none
,
1037 .mask
= (0x3 << 6), /* w */
1038 .src1
= vector_alu_srco_unsigned(alu_src
),
1039 .src2
= vector_alu_srco_unsigned(alu_src
)
1043 emit_mir_instruction(ctx
, ins
);
1046 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1047 * pinning to eliminate this move in all known cases */
1050 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1052 int offset
= nir_src_index(ctx
, src
);
1054 midgard_instruction ins
= {
1057 .src0
= SSA_UNUSED_1
,
1059 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1062 .op
= midgard_alu_op_imov
,
1063 .reg_mode
= midgard_reg_mode_full
,
1064 .dest_override
= midgard_dest_override_none
,
1065 .mask
= (0x3 << 6), /* w */
1066 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1067 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1071 emit_mir_instruction(ctx
, ins
);
1074 #define ALU_CASE(nir, _op) \
1075 case nir_op_##nir: \
1076 op = midgard_alu_op_##_op; \
1080 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1082 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1084 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1085 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1086 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1088 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1089 * supported. A few do not and are commented for now. Also, there are a
1090 * number of NIR ops which Midgard does not support and need to be
1091 * lowered, also TODO. This switch block emits the opcode and calling
1092 * convention of the Midgard instruction; actual packing is done in
1097 switch (instr
->op
) {
1098 ALU_CASE(fadd
, fadd
);
1099 ALU_CASE(fmul
, fmul
);
1100 ALU_CASE(fmin
, fmin
);
1101 ALU_CASE(fmax
, fmax
);
1102 ALU_CASE(imin
, imin
);
1103 ALU_CASE(imax
, imax
);
1104 ALU_CASE(umin
, umin
);
1105 ALU_CASE(umax
, umax
);
1106 ALU_CASE(fmov
, fmov
);
1107 ALU_CASE(ffloor
, ffloor
);
1108 ALU_CASE(fround_even
, froundeven
);
1109 ALU_CASE(ftrunc
, ftrunc
);
1110 ALU_CASE(fceil
, fceil
);
1111 ALU_CASE(fdot3
, fdot3
);
1112 ALU_CASE(fdot4
, fdot4
);
1113 ALU_CASE(iadd
, iadd
);
1114 ALU_CASE(isub
, isub
);
1115 ALU_CASE(imul
, imul
);
1116 ALU_CASE(iabs
, iabs
);
1118 /* XXX: Use fmov, not imov, since imov was causing major
1119 * issues with texture precision? XXX research */
1120 ALU_CASE(imov
, imov
);
1122 ALU_CASE(feq32
, feq
);
1123 ALU_CASE(fne32
, fne
);
1124 ALU_CASE(flt32
, flt
);
1125 ALU_CASE(ieq32
, ieq
);
1126 ALU_CASE(ine32
, ine
);
1127 ALU_CASE(ilt32
, ilt
);
1128 ALU_CASE(ult32
, ult
);
1130 /* We don't have a native b2f32 instruction. Instead, like many
1131 * GPUs, we exploit booleans as 0/~0 for false/true, and
1132 * correspondingly AND
1133 * by 1.0 to do the type conversion. For the moment, prime us
1136 * iand [whatever], #0
1138 * At the end of emit_alu (as MIR), we'll fix-up the constant
1141 ALU_CASE(b2f32
, iand
);
1142 ALU_CASE(b2i32
, iand
);
1144 /* Likewise, we don't have a dedicated f2b32 instruction, but
1145 * we can do a "not equal to 0.0" test. */
1147 ALU_CASE(f2b32
, fne
);
1148 ALU_CASE(i2b32
, ine
);
1150 ALU_CASE(frcp
, frcp
);
1151 ALU_CASE(frsq
, frsqrt
);
1152 ALU_CASE(fsqrt
, fsqrt
);
1153 ALU_CASE(fexp2
, fexp2
);
1154 ALU_CASE(flog2
, flog2
);
1156 ALU_CASE(f2i32
, f2i
);
1157 ALU_CASE(f2u32
, f2u
);
1158 ALU_CASE(i2f32
, i2f
);
1159 ALU_CASE(u2f32
, u2f
);
1161 ALU_CASE(fsin
, fsin
);
1162 ALU_CASE(fcos
, fcos
);
1164 ALU_CASE(iand
, iand
);
1166 ALU_CASE(ixor
, ixor
);
1167 ALU_CASE(inot
, inot
);
1168 ALU_CASE(ishl
, ishl
);
1169 ALU_CASE(ishr
, iasr
);
1170 ALU_CASE(ushr
, ilsr
);
1172 ALU_CASE(b32all_fequal2
, fball_eq
);
1173 ALU_CASE(b32all_fequal3
, fball_eq
);
1174 ALU_CASE(b32all_fequal4
, fball_eq
);
1176 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1177 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1178 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1180 ALU_CASE(b32all_iequal2
, iball_eq
);
1181 ALU_CASE(b32all_iequal3
, iball_eq
);
1182 ALU_CASE(b32all_iequal4
, iball_eq
);
1184 ALU_CASE(b32any_inequal2
, ibany_neq
);
1185 ALU_CASE(b32any_inequal3
, ibany_neq
);
1186 ALU_CASE(b32any_inequal4
, ibany_neq
);
1188 /* For greater-or-equal, we lower to less-or-equal and flip the
1194 case nir_op_uge32
: {
1196 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1197 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1198 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1199 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1202 /* Swap via temporary */
1203 nir_alu_src temp
= instr
->src
[1];
1204 instr
->src
[1] = instr
->src
[0];
1205 instr
->src
[0] = temp
;
1210 case nir_op_b32csel
: {
1211 op
= midgard_alu_op_fcsel
;
1213 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1216 /* Figure out which component the condition is in */
1218 unsigned comp
= instr
->src
[0].swizzle
[0];
1220 /* Make sure NIR isn't throwing a mixed condition at us */
1222 for (unsigned c
= 1; c
< nr_components
; ++c
)
1223 assert(instr
->src
[0].swizzle
[c
] == comp
);
1225 /* Emit the condition into r31.w */
1226 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1228 /* The condition is the first argument; move the other
1229 * arguments up one to be a binary instruction for
1232 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1237 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1242 /* Fetch unit, quirks, etc information */
1243 unsigned opcode_props
= alu_opcode_props
[op
];
1244 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1246 /* Initialise fields common between scalar/vector instructions */
1247 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1249 /* src0 will always exist afaik, but src1 will not for 1-argument
1250 * instructions. The latter can only be fetched if the instruction
1251 * needs it, or else we may segfault. */
1253 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1254 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1256 /* Rather than use the instruction generation helpers, we do it
1257 * ourselves here to avoid the mess */
1259 midgard_instruction ins
= {
1262 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1263 .src1
= quirk_flipped_r24
? src0
: src1
,
1268 nir_alu_src
*nirmods
[2] = { NULL
};
1270 if (nr_inputs
== 2) {
1271 nirmods
[0] = &instr
->src
[0];
1272 nirmods
[1] = &instr
->src
[1];
1273 } else if (nr_inputs
== 1) {
1274 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1279 bool is_int
= midgard_is_integer_op(op
);
1281 midgard_vector_alu alu
= {
1283 .reg_mode
= midgard_reg_mode_full
,
1284 .dest_override
= midgard_dest_override_none
,
1287 /* Writemask only valid for non-SSA NIR */
1288 .mask
= expand_writemask((1 << nr_components
) - 1),
1290 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
1291 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
1294 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1297 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1301 /* Late fixup for emulated instructions */
1303 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1304 /* Presently, our second argument is an inline #0 constant.
1305 * Switch over to an embedded 1.0 constant (that can't fit
1306 * inline, since we're 32-bit, not 16-bit like the inline
1309 ins
.ssa_args
.inline_constant
= false;
1310 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1311 ins
.has_constants
= true;
1313 if (instr
->op
== nir_op_b2f32
) {
1314 ins
.constants
[0] = 1.0f
;
1316 /* Type pun it into place */
1318 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1321 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1322 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1323 ins
.ssa_args
.inline_constant
= false;
1324 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1325 ins
.has_constants
= true;
1326 ins
.constants
[0] = 0.0f
;
1327 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1330 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1331 /* To avoid duplicating the lookup tables (probably), true LUT
1332 * instructions can only operate as if they were scalars. Lower
1333 * them here by changing the component. */
1335 uint8_t original_swizzle
[4];
1336 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1338 for (int i
= 0; i
< nr_components
; ++i
) {
1339 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1341 for (int j
= 0; j
< 4; ++j
)
1342 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1344 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
1345 emit_mir_instruction(ctx
, ins
);
1348 emit_mir_instruction(ctx
, ins
);
1355 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1357 /* TODO: half-floats */
1359 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1360 /* Fast path: For the first 16 uniforms, direct accesses are
1361 * 0-cycle, since they're just a register fetch in the usual
1362 * case. So, we alias the registers while we're still in
1365 int reg_slot
= 23 - offset
;
1366 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1368 /* Otherwise, read from the 'special' UBO to access
1369 * higher-indexed uniforms, at a performance cost. More
1370 * generally, we're emitting a UBO read instruction. */
1372 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1374 /* TODO: Don't split */
1375 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1376 ins
.load_store
.address
= offset
>> 3;
1378 if (indirect_offset
) {
1379 emit_indirect_offset(ctx
, indirect_offset
);
1380 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1382 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1385 emit_mir_instruction(ctx
, ins
);
1390 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1392 /* First, pull out the destination */
1393 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1395 /* Now, figure out which uniform this is */
1396 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1397 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1399 /* Sysvals are prefix uniforms */
1400 unsigned uniform
= ((uintptr_t) val
) - 1;
1402 /* Emit the read itself -- this is never indirect */
1403 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1407 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1409 unsigned offset
, reg
;
1411 switch (instr
->intrinsic
) {
1412 case nir_intrinsic_discard_if
:
1413 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1417 case nir_intrinsic_discard
: {
1418 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1419 struct midgard_instruction discard
= v_branch(conditional
, false);
1420 discard
.branch
.target_type
= TARGET_DISCARD
;
1421 emit_mir_instruction(ctx
, discard
);
1423 ctx
->can_discard
= true;
1427 case nir_intrinsic_load_uniform
:
1428 case nir_intrinsic_load_input
:
1429 offset
= nir_intrinsic_base(instr
);
1431 bool direct
= nir_src_is_const(instr
->src
[0]);
1434 offset
+= nir_src_as_uint(instr
->src
[0]);
1437 reg
= nir_dest_index(ctx
, &instr
->dest
);
1439 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1440 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1441 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1442 /* XXX: Half-floats? */
1443 /* TODO: swizzle, mask */
1445 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1447 midgard_varying_parameter p
= {
1449 .interpolation
= midgard_interp_default
,
1450 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1454 memcpy(&u
, &p
, sizeof(p
));
1455 ins
.load_store
.varying_parameters
= u
;
1458 /* We have the offset totally ready */
1459 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1461 /* We have it partially ready, but we need to
1462 * add in the dynamic index, moved to r27.w */
1463 emit_indirect_offset(ctx
, &instr
->src
[0]);
1464 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1467 emit_mir_instruction(ctx
, ins
);
1468 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1469 /* Constant encoded as a pinned constant */
1471 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1472 ins
.has_constants
= true;
1473 ins
.has_blend_constant
= true;
1474 emit_mir_instruction(ctx
, ins
);
1475 } else if (ctx
->is_blend
) {
1476 /* For blend shaders, a load might be
1477 * translated various ways depending on what
1478 * we're loading. Figure out how this is used */
1480 nir_variable
*out
= NULL
;
1482 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1483 int drvloc
= var
->data
.driver_location
;
1485 if (nir_intrinsic_base(instr
) == drvloc
) {
1493 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1494 /* Source color preloaded to r0 */
1496 midgard_pin_output(ctx
, reg
, 0);
1497 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1498 /* Destination color must be read from framebuffer */
1500 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1501 ins
.load_store
.swizzle
= 0; /* xxxx */
1503 /* Read each component sequentially */
1505 for (int c
= 0; c
< 4; ++c
) {
1506 ins
.load_store
.mask
= (1 << c
);
1507 ins
.load_store
.unknown
= c
;
1508 emit_mir_instruction(ctx
, ins
);
1511 /* vadd.u2f hr2, zext(hr2), #0 */
1513 midgard_vector_alu_src alu_src
= blank_alu_src
;
1514 alu_src
.mod
= midgard_int_zero_extend
;
1515 alu_src
.half
= true;
1517 midgard_instruction u2f
= {
1521 .src1
= SSA_UNUSED_0
,
1523 .inline_constant
= true
1526 .op
= midgard_alu_op_u2f
,
1527 .reg_mode
= midgard_reg_mode_half
,
1528 .dest_override
= midgard_dest_override_none
,
1530 .src1
= vector_alu_srco_unsigned(alu_src
),
1531 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1535 emit_mir_instruction(ctx
, u2f
);
1537 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1541 midgard_instruction fmul
= {
1543 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1547 .src1
= SSA_UNUSED_0
,
1548 .inline_constant
= true
1551 .op
= midgard_alu_op_fmul
,
1552 .reg_mode
= midgard_reg_mode_full
,
1553 .dest_override
= midgard_dest_override_none
,
1554 .outmod
= midgard_outmod_sat
,
1556 .src1
= vector_alu_srco_unsigned(alu_src
),
1557 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1561 emit_mir_instruction(ctx
, fmul
);
1563 DBG("Unknown input in blend shader\n");
1566 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1567 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1568 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1569 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1570 emit_mir_instruction(ctx
, ins
);
1572 DBG("Unknown load\n");
1578 case nir_intrinsic_store_output
:
1579 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1581 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1583 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1585 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1586 /* gl_FragColor is not emitted with load/store
1587 * instructions. Instead, it gets plonked into
1588 * r0 at the end of the shader and we do the
1589 * framebuffer writeout dance. TODO: Defer
1592 midgard_pin_output(ctx
, reg
, 0);
1594 /* Save the index we're writing to for later reference
1595 * in the epilogue */
1597 ctx
->fragment_output
= reg
;
1598 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1599 /* Varyings are written into one of two special
1600 * varying register, r26 or r27. The register itself is selected as the register
1601 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1603 * Normally emitting fmov's is frowned upon,
1604 * but due to unique constraints of
1605 * REGISTER_VARYING, fmov emission + a
1606 * dedicated cleanup pass is the only way to
1607 * guarantee correctness when considering some
1608 * (common) edge cases XXX: FIXME */
1610 /* If this varying corresponds to a constant (why?!),
1611 * emit that now since it won't get picked up by
1612 * hoisting (since there is no corresponding move
1613 * emitted otherwise) */
1615 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1617 if (constant_value
) {
1618 /* Special case: emit the varying write
1619 * directly to r26 (looks funny in asm but it's
1620 * fine) and emit the store _now_. Possibly
1621 * slightly slower, but this is a really stupid
1622 * special case anyway (why on earth would you
1623 * have a constant varying? Your own fault for
1624 * slightly worse perf :P) */
1626 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1627 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1628 emit_mir_instruction(ctx
, ins
);
1630 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1631 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1632 emit_mir_instruction(ctx
, st
);
1634 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1636 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1639 DBG("Unknown store\n");
1645 case nir_intrinsic_load_alpha_ref_float
:
1646 assert(instr
->dest
.is_ssa
);
1648 float ref_value
= ctx
->alpha_ref
;
1650 float *v
= ralloc_array(NULL
, float, 4);
1651 memcpy(v
, &ref_value
, sizeof(float));
1652 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1655 case nir_intrinsic_load_viewport_scale
:
1656 case nir_intrinsic_load_viewport_offset
:
1657 emit_sysval_read(ctx
, instr
);
1661 printf ("Unhandled intrinsic\n");
1668 midgard_tex_format(enum glsl_sampler_dim dim
)
1671 case GLSL_SAMPLER_DIM_2D
:
1672 case GLSL_SAMPLER_DIM_EXTERNAL
:
1675 case GLSL_SAMPLER_DIM_3D
:
1678 case GLSL_SAMPLER_DIM_CUBE
:
1679 return TEXTURE_CUBE
;
1682 DBG("Unknown sampler dim type\n");
1689 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1692 //assert (!instr->sampler);
1693 //assert (!instr->texture_array_size);
1694 assert (instr
->op
== nir_texop_tex
);
1696 /* Allocate registers via a round robin scheme to alternate between the two registers */
1697 int reg
= ctx
->texture_op_count
& 1;
1698 int in_reg
= reg
, out_reg
= reg
;
1700 /* Make room for the reg */
1702 if (ctx
->texture_index
[reg
] > -1)
1703 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1705 int texture_index
= instr
->texture_index
;
1706 int sampler_index
= texture_index
;
1708 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1709 switch (instr
->src
[i
].src_type
) {
1710 case nir_tex_src_coord
: {
1711 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1713 midgard_vector_alu_src alu_src
= blank_alu_src
;
1715 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1717 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1718 /* For cubemaps, we need to load coords into
1719 * special r27, and then use a special ld/st op
1720 * to copy into the texture register */
1722 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1724 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1725 emit_mir_instruction(ctx
, move
);
1727 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1728 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1729 st
.load_store
.mask
= 0x3; /* xy? */
1730 st
.load_store
.swizzle
= alu_src
.swizzle
;
1731 emit_mir_instruction(ctx
, st
);
1734 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1736 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1737 emit_mir_instruction(ctx
, ins
);
1740 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1746 DBG("Unknown source type\n");
1753 /* No helper to build texture words -- we do it all here */
1754 midgard_instruction ins
= {
1755 .type
= TAG_TEXTURE_4
,
1757 .op
= TEXTURE_OP_NORMAL
,
1758 .format
= midgard_tex_format(instr
->sampler_dim
),
1759 .texture_handle
= texture_index
,
1760 .sampler_handle
= sampler_index
,
1762 /* TODO: Don't force xyzw */
1763 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1775 /* Assume we can continue; hint it out later */
1780 /* Set registers to read and write from the same place */
1781 ins
.texture
.in_reg_select
= in_reg
;
1782 ins
.texture
.out_reg_select
= out_reg
;
1784 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1785 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1786 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1787 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1788 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1790 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1791 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1792 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1795 emit_mir_instruction(ctx
, ins
);
1797 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1799 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1800 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1801 ctx
->texture_index
[reg
] = o_index
;
1803 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1804 emit_mir_instruction(ctx
, ins2
);
1806 /* Used for .cont and .last hinting */
1807 ctx
->texture_op_count
++;
1811 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1813 switch (instr
->type
) {
1814 case nir_jump_break
: {
1815 /* Emit a branch out of the loop */
1816 struct midgard_instruction br
= v_branch(false, false);
1817 br
.branch
.target_type
= TARGET_BREAK
;
1818 br
.branch
.target_break
= ctx
->current_loop_depth
;
1819 emit_mir_instruction(ctx
, br
);
1826 DBG("Unknown jump type %d\n", instr
->type
);
1832 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1834 switch (instr
->type
) {
1835 case nir_instr_type_load_const
:
1836 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1839 case nir_instr_type_intrinsic
:
1840 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1843 case nir_instr_type_alu
:
1844 emit_alu(ctx
, nir_instr_as_alu(instr
));
1847 case nir_instr_type_tex
:
1848 emit_tex(ctx
, nir_instr_as_tex(instr
));
1851 case nir_instr_type_jump
:
1852 emit_jump(ctx
, nir_instr_as_jump(instr
));
1855 case nir_instr_type_ssa_undef
:
1860 DBG("Unhandled instruction type\n");
1865 /* Determine the actual hardware from the index based on the RA results or special values */
1868 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1870 if (reg
>= SSA_FIXED_MINIMUM
)
1871 return SSA_REG_FROM_FIXED(reg
);
1874 assert(reg
< maxreg
);
1875 int r
= ra_get_node_reg(g
, reg
);
1876 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1881 /* fmov style unused */
1883 return REGISTER_UNUSED
;
1885 /* lut style unused */
1887 return REGISTER_UNUSED
;
1890 DBG("Unknown SSA register alias %d\n", reg
);
1897 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1899 /* Choose the first available register to minimise reported register pressure */
1901 for (int i
= 0; i
< 16; ++i
) {
1902 if (BITSET_TEST(regs
, i
)) {
1912 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1914 if (ins
->ssa_args
.src0
== src
) return true;
1915 if (ins
->ssa_args
.src1
== src
) return true;
1920 /* Determine if a variable is live in the successors of a block */
1922 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
1924 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
1925 midgard_block
*succ
= bl
->successors
[i
];
1927 /* If we already visited, the value we're seeking
1928 * isn't down this path (or we would have short
1931 if (succ
->visited
) continue;
1933 /* Otherwise (it's visited *now*), check the block */
1935 succ
->visited
= true;
1937 mir_foreach_instr_in_block(succ
, ins
) {
1938 if (midgard_is_live_in_instr(ins
, src
))
1942 /* ...and also, check *its* successors */
1943 if (is_live_after_successors(ctx
, succ
, src
))
1948 /* Welp. We're really not live. */
1954 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1956 /* Check the rest of the block for liveness */
1958 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1959 if (midgard_is_live_in_instr(ins
, src
))
1963 /* Check the rest of the blocks for liveness recursively */
1965 bool succ
= is_live_after_successors(ctx
, block
, src
);
1967 mir_foreach_block(ctx
, block
) {
1968 block
->visited
= false;
1975 allocate_registers(compiler_context
*ctx
)
1977 /* First, initialize the RA */
1978 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1980 /* Create a primary (general purpose) class, as well as special purpose
1981 * pipeline register classes */
1983 int primary_class
= ra_alloc_reg_class(regs
);
1984 int varying_class
= ra_alloc_reg_class(regs
);
1986 /* Add the full set of work registers */
1987 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1988 for (int i
= 0; i
< work_count
; ++i
)
1989 ra_class_add_reg(regs
, primary_class
, i
);
1991 /* Add special registers */
1992 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1993 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1995 /* We're done setting up */
1996 ra_set_finalize(regs
, NULL
);
1998 /* Transform the MIR into squeezed index form */
1999 mir_foreach_block(ctx
, block
) {
2000 mir_foreach_instr_in_block(block
, ins
) {
2001 if (ins
->compact_branch
) continue;
2003 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
2004 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
2005 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
2007 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2008 print_mir_block(block
);
2011 /* Let's actually do register allocation */
2012 int nodes
= ctx
->temp_count
;
2013 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
2015 /* Set everything to the work register class, unless it has somewhere
2018 mir_foreach_block(ctx
, block
) {
2019 mir_foreach_instr_in_block(block
, ins
) {
2020 if (ins
->compact_branch
) continue;
2022 if (ins
->ssa_args
.dest
< 0) continue;
2024 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2026 int class = primary_class
;
2028 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2032 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2033 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2036 unsigned reg
= temp
- 1;
2037 int t
= find_or_allocate_temp(ctx
, index
);
2038 ra_set_node_reg(g
, t
, reg
);
2042 /* Determine liveness */
2044 int *live_start
= malloc(nodes
* sizeof(int));
2045 int *live_end
= malloc(nodes
* sizeof(int));
2047 /* Initialize as non-existent */
2049 for (int i
= 0; i
< nodes
; ++i
) {
2050 live_start
[i
] = live_end
[i
] = -1;
2055 mir_foreach_block(ctx
, block
) {
2056 mir_foreach_instr_in_block(block
, ins
) {
2057 if (ins
->compact_branch
) continue;
2059 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2060 /* If this destination is not yet live, it is now since we just wrote it */
2062 int dest
= ins
->ssa_args
.dest
;
2064 if (live_start
[dest
] == -1)
2065 live_start
[dest
] = d
;
2068 /* Since we just used a source, the source might be
2069 * dead now. Scan the rest of the block for
2070 * invocations, and if there are none, the source dies
2073 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2075 for (int src
= 0; src
< 2; ++src
) {
2076 int s
= sources
[src
];
2078 if (s
< 0) continue;
2080 if (s
>= SSA_FIXED_MINIMUM
) continue;
2082 if (!is_live_after(ctx
, block
, ins
, s
)) {
2091 /* If a node still hasn't been killed, kill it now */
2093 for (int i
= 0; i
< nodes
; ++i
) {
2094 /* live_start == -1 most likely indicates a pinned output */
2096 if (live_end
[i
] == -1)
2100 /* Setup interference between nodes that are live at the same time */
2102 for (int i
= 0; i
< nodes
; ++i
) {
2103 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2104 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2105 ra_add_node_interference(g
, i
, j
);
2109 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2111 if (!ra_allocate(g
)) {
2112 DBG("Error allocating registers\n");
2120 mir_foreach_block(ctx
, block
) {
2121 mir_foreach_instr_in_block(block
, ins
) {
2122 if (ins
->compact_branch
) continue;
2124 ssa_args args
= ins
->ssa_args
;
2126 switch (ins
->type
) {
2128 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
2130 ins
->registers
.src2_imm
= args
.inline_constant
;
2132 if (args
.inline_constant
) {
2133 /* Encode inline 16-bit constant as a vector by default */
2135 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2137 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2139 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2140 ins
->alu
.src2
= imm
<< 2;
2142 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2145 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2149 case TAG_LOAD_STORE_4
: {
2150 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2151 /* TODO: use ssa_args for store_vary */
2152 ins
->load_store
.reg
= 0;
2154 bool has_dest
= args
.dest
>= 0;
2155 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2157 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2170 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2171 * use scalar ALU instructions, for functional or performance reasons. To do
2172 * this, we just demote vector ALU payloads to scalar. */
2175 component_from_mask(unsigned mask
)
2177 for (int c
= 0; c
< 4; ++c
) {
2178 if (mask
& (3 << (2 * c
)))
2187 is_single_component_mask(unsigned mask
)
2191 for (int c
= 0; c
< 4; ++c
)
2192 if (mask
& (3 << (2 * c
)))
2195 return components
== 1;
2198 /* Create a mask of accessed components from a swizzle to figure out vector
2202 swizzle_to_access_mask(unsigned swizzle
)
2204 unsigned component_mask
= 0;
2206 for (int i
= 0; i
< 4; ++i
) {
2207 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2208 component_mask
|= (1 << c
);
2211 return component_mask
;
2215 vector_to_scalar_source(unsigned u
, bool is_int
)
2217 midgard_vector_alu_src v
;
2218 memcpy(&v
, &u
, sizeof(v
));
2220 /* TODO: Integers */
2222 midgard_scalar_alu_src s
= {
2224 .component
= (v
.swizzle
& 3) << 1
2230 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
2231 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
2235 memcpy(&o
, &s
, sizeof(s
));
2237 return o
& ((1 << 6) - 1);
2240 static midgard_scalar_alu
2241 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2243 bool is_int
= midgard_is_integer_op(v
.op
);
2245 /* The output component is from the mask */
2246 midgard_scalar_alu s
= {
2248 .src1
= vector_to_scalar_source(v
.src1
, is_int
),
2249 .src2
= vector_to_scalar_source(v
.src2
, is_int
),
2252 .output_full
= 1, /* TODO: Half */
2253 .output_component
= component_from_mask(v
.mask
) << 1,
2256 /* Inline constant is passed along rather than trying to extract it
2259 if (ins
->ssa_args
.inline_constant
) {
2261 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2262 imm
|= (lower_11
>> 9) & 3;
2263 imm
|= (lower_11
>> 6) & 4;
2264 imm
|= (lower_11
>> 2) & 0x38;
2265 imm
|= (lower_11
& 63) << 6;
2273 /* Midgard prefetches instruction types, so during emission we need to
2274 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2275 * if this is the second to last and the last is an ALU, then it's also 1... */
2277 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2278 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2280 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2281 bytes_emitted += sizeof(type)
2284 emit_binary_vector_instruction(midgard_instruction
*ains
,
2285 uint16_t *register_words
, int *register_words_count
,
2286 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2287 size_t *bytes_emitted
)
2289 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2290 *bytes_emitted
+= sizeof(midgard_reg_info
);
2292 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2293 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2294 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2297 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2298 * mind that we are a vector architecture and we can write to different
2299 * components simultaneously */
2302 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2304 /* Each instruction reads some registers and writes to a register. See
2305 * where the first writes */
2307 /* Figure out where exactly we wrote to */
2308 int source
= first
->ssa_args
.dest
;
2309 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2311 /* As long as the second doesn't read from the first, we're okay */
2312 if (second
->ssa_args
.src0
== source
) {
2313 if (first
->type
== TAG_ALU_4
) {
2314 /* Figure out which components we just read from */
2316 int q
= second
->alu
.src1
;
2317 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2319 /* Check if there are components in common, and fail if so */
2320 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2327 if (second
->ssa_args
.src1
== source
)
2330 /* Otherwise, it's safe in that regard. Another data hazard is both
2331 * writing to the same place, of course */
2333 if (second
->ssa_args
.dest
== source
) {
2334 /* ...but only if the components overlap */
2335 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2337 if (dest_mask
& source_mask
)
2347 midgard_instruction
**segment
, unsigned segment_size
,
2348 midgard_instruction
*ains
)
2350 for (int s
= 0; s
< segment_size
; ++s
)
2351 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2359 /* Schedules, but does not emit, a single basic block. After scheduling, the
2360 * final tag and size of the block are known, which are necessary for branching
2363 static midgard_bundle
2364 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2366 int instructions_emitted
= 0, instructions_consumed
= -1;
2367 midgard_bundle bundle
= { 0 };
2369 uint8_t tag
= ins
->type
;
2371 /* Default to the instruction's tag */
2374 switch (ins
->type
) {
2376 uint32_t control
= 0;
2377 size_t bytes_emitted
= sizeof(control
);
2379 /* TODO: Constant combining */
2380 int index
= 0, last_unit
= 0;
2382 /* Previous instructions, for the purpose of parallelism */
2383 midgard_instruction
*segment
[4] = {0};
2384 int segment_size
= 0;
2386 instructions_emitted
= -1;
2387 midgard_instruction
*pins
= ins
;
2390 midgard_instruction
*ains
= pins
;
2392 /* Advance instruction pointer */
2394 ains
= mir_next_op(pins
);
2398 /* Out-of-work condition */
2399 if ((struct list_head
*) ains
== &block
->instructions
)
2402 /* Ensure that the chain can continue */
2403 if (ains
->type
!= TAG_ALU_4
) break;
2405 /* According to the presentation "The ARM
2406 * Mali-T880 Mobile GPU" from HotChips 27,
2407 * there are two pipeline stages. Branching
2408 * position determined experimentally. Lines
2409 * are executed in parallel:
2412 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2414 * Verify that there are no ordering dependencies here.
2416 * TODO: Allow for parallelism!!!
2419 /* Pick a unit for it if it doesn't force a particular unit */
2421 int unit
= ains
->unit
;
2424 int op
= ains
->alu
.op
;
2425 int units
= alu_opcode_props
[op
];
2427 /* TODO: Promotion of scalars to vectors */
2428 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2431 assert(units
& UNITS_SCALAR
);
2434 if (last_unit
>= UNIT_VADD
) {
2435 if (units
& UNIT_VLUT
)
2440 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2442 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2444 else if (units
& UNIT_VLUT
)
2450 if (last_unit
>= UNIT_VADD
) {
2451 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2453 else if (units
& UNIT_VLUT
)
2458 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2460 else if (units
& UNIT_SMUL
)
2461 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2462 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2469 assert(unit
& units
);
2472 /* Late unit check, this time for encoding (not parallelism) */
2473 if (unit
<= last_unit
) break;
2475 /* Clear the segment */
2476 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2479 if (midgard_has_hazard(segment
, segment_size
, ains
))
2482 /* We're good to go -- emit the instruction */
2485 segment
[segment_size
++] = ains
;
2487 /* Only one set of embedded constants per
2488 * bundle possible; if we have more, we must
2489 * break the chain early, unfortunately */
2491 if (ains
->has_constants
) {
2492 if (bundle
.has_embedded_constants
) {
2493 /* ...but if there are already
2494 * constants but these are the
2495 * *same* constants, we let it
2498 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2501 bundle
.has_embedded_constants
= true;
2502 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2504 /* If this is a blend shader special constant, track it for patching */
2505 if (ains
->has_blend_constant
)
2506 bundle
.has_blend_constant
= true;
2510 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2511 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2512 &bundle
.register_words_count
, bundle
.body_words
,
2513 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2514 } else if (ains
->compact_branch
) {
2515 /* All of r0 has to be written out
2516 * along with the branch writeout.
2519 if (ains
->writeout
) {
2521 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2522 ins
.unit
= UNIT_VMUL
;
2524 control
|= ins
.unit
;
2526 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2527 &bundle
.register_words_count
, bundle
.body_words
,
2528 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2530 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2531 bool written_late
= false;
2532 bool components
[4] = { 0 };
2533 uint16_t register_dep_mask
= 0;
2534 uint16_t written_mask
= 0;
2536 midgard_instruction
*qins
= ins
;
2537 for (int t
= 0; t
< index
; ++t
) {
2538 if (qins
->registers
.out_reg
!= 0) {
2539 /* Mark down writes */
2541 written_mask
|= (1 << qins
->registers
.out_reg
);
2543 /* Mark down the register dependencies for errata check */
2545 if (qins
->registers
.src1_reg
< 16)
2546 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2548 if (qins
->registers
.src2_reg
< 16)
2549 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2551 int mask
= qins
->alu
.mask
;
2553 for (int c
= 0; c
< 4; ++c
)
2554 if (mask
& (0x3 << (2 * c
)))
2555 components
[c
] = true;
2557 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2559 if (qins
->unit
== UNIT_VLUT
)
2560 written_late
= true;
2563 /* Advance instruction pointer */
2564 qins
= mir_next_op(qins
);
2568 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2569 if (register_dep_mask
& written_mask
) {
2570 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2577 /* If even a single component is not written, break it up (conservative check). */
2578 bool breakup
= false;
2580 for (int c
= 0; c
< 4; ++c
)
2587 /* Otherwise, we're free to proceed */
2591 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2592 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2593 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2594 bytes_emitted
+= sizeof(midgard_branch_extended
);
2596 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2597 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2598 bytes_emitted
+= sizeof(ains
->br_compact
);
2601 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2602 bytes_emitted
+= sizeof(midgard_reg_info
);
2604 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2605 bundle
.body_words_count
++;
2606 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2609 /* Defer marking until after writing to allow for break */
2610 control
|= ains
->unit
;
2611 last_unit
= ains
->unit
;
2612 ++instructions_emitted
;
2616 /* Bubble up the number of instructions for skipping */
2617 instructions_consumed
= index
- 1;
2621 /* Pad ALU op to nearest word */
2623 if (bytes_emitted
& 15) {
2624 padding
= 16 - (bytes_emitted
& 15);
2625 bytes_emitted
+= padding
;
2628 /* Constants must always be quadwords */
2629 if (bundle
.has_embedded_constants
)
2630 bytes_emitted
+= 16;
2632 /* Size ALU instruction for tag */
2633 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2634 bundle
.padding
= padding
;
2635 bundle
.control
= bundle
.tag
| control
;
2640 case TAG_LOAD_STORE_4
: {
2641 /* Load store instructions have two words at once. If
2642 * we only have one queued up, we need to NOP pad.
2643 * Otherwise, we store both in succession to save space
2644 * and cycles -- letting them go in parallel -- skip
2645 * the next. The usefulness of this optimisation is
2646 * greatly dependent on the quality of the instruction
2650 midgard_instruction
*next_op
= mir_next_op(ins
);
2652 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2653 /* As the two operate concurrently, make sure
2654 * they are not dependent */
2656 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2657 /* Skip ahead, since it's redundant with the pair */
2658 instructions_consumed
= 1 + (instructions_emitted
++);
2666 /* Texture ops default to single-op-per-bundle scheduling */
2670 /* Copy the instructions into the bundle */
2671 bundle
.instruction_count
= instructions_emitted
+ 1;
2675 midgard_instruction
*uins
= ins
;
2676 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2677 bundle
.instructions
[used_idx
++] = *uins
;
2678 uins
= mir_next_op(uins
);
2681 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2687 quadword_size(int tag
)
2702 case TAG_LOAD_STORE_4
:
2714 /* Schedule a single block by iterating its instruction to create bundles.
2715 * While we go, tally about the bundle sizes to compute the block size. */
2718 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2720 util_dynarray_init(&block
->bundles
, NULL
);
2722 block
->quadword_count
= 0;
2724 mir_foreach_instr_in_block(block
, ins
) {
2726 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2727 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2729 if (bundle
.has_blend_constant
) {
2730 /* TODO: Multiblock? */
2731 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2732 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2736 ins
= mir_next_op(ins
);
2738 block
->quadword_count
+= quadword_size(bundle
.tag
);
2741 block
->is_scheduled
= true;
2745 schedule_program(compiler_context
*ctx
)
2747 allocate_registers(ctx
);
2749 mir_foreach_block(ctx
, block
) {
2750 schedule_block(ctx
, block
);
2754 /* After everything is scheduled, emit whole bundles at a time */
2757 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2759 int lookahead
= next_tag
<< 4;
2761 switch (bundle
->tag
) {
2766 /* Actually emit each component */
2767 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2769 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2770 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2772 /* Emit body words based on the instructions bundled */
2773 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2774 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2776 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2777 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2778 } else if (ins
->compact_branch
) {
2779 /* Dummy move, XXX DRY */
2780 if ((i
== 0) && ins
->writeout
) {
2781 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2782 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2785 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2786 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2788 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2792 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2793 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2797 /* Emit padding (all zero) */
2798 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2800 /* Tack on constants */
2802 if (bundle
->has_embedded_constants
) {
2803 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2804 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2805 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2806 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2812 case TAG_LOAD_STORE_4
: {
2813 /* One or two composing instructions */
2815 uint64_t current64
, next64
= LDST_NOP
;
2817 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2819 if (bundle
->instruction_count
== 2)
2820 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2822 midgard_load_store instruction
= {
2823 .type
= bundle
->tag
,
2824 .next_type
= next_tag
,
2829 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2834 case TAG_TEXTURE_4
: {
2835 /* Texture instructions are easy, since there is no
2836 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2838 midgard_instruction
*ins
= &bundle
->instructions
[0];
2840 ins
->texture
.type
= TAG_TEXTURE_4
;
2841 ins
->texture
.next_type
= next_tag
;
2843 ctx
->texture_op_count
--;
2845 if (!ctx
->texture_op_count
) {
2846 ins
->texture
.cont
= 0;
2847 ins
->texture
.last
= 1;
2850 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2855 DBG("Unknown midgard instruction type\n");
2862 /* ALU instructions can inline or embed constants, which decreases register
2863 * pressure and saves space. */
2865 #define CONDITIONAL_ATTACH(src) { \
2866 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2869 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2870 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2875 inline_alu_constants(compiler_context
*ctx
)
2877 mir_foreach_instr(ctx
, alu
) {
2878 /* Other instructions cannot inline constants */
2879 if (alu
->type
!= TAG_ALU_4
) continue;
2881 /* If there is already a constant here, we can do nothing */
2882 if (alu
->has_constants
) continue;
2884 /* It makes no sense to inline constants on a branch */
2885 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
2887 CONDITIONAL_ATTACH(src0
);
2889 if (!alu
->has_constants
) {
2890 CONDITIONAL_ATTACH(src1
)
2891 } else if (!alu
->inline_constant
) {
2892 /* Corner case: _two_ vec4 constants, for instance with a
2893 * csel. For this case, we can only use a constant
2894 * register for one, we'll have to emit a move for the
2895 * other. Note, if both arguments are constants, then
2896 * necessarily neither argument depends on the value of
2897 * any particular register. As the destination register
2898 * will be wiped, that means we can spill the constant
2899 * to the destination register.
2902 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2903 unsigned scratch
= alu
->ssa_args
.dest
;
2906 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2907 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2909 /* Force a break XXX Defer r31 writes */
2910 ins
.unit
= UNIT_VLUT
;
2912 /* Set the source */
2913 alu
->ssa_args
.src1
= scratch
;
2915 /* Inject us -before- the last instruction which set r31 */
2916 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2922 /* Midgard supports two types of constants, embedded constants (128-bit) and
2923 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2924 * constants can be demoted to inline constants, for space savings and
2925 * sometimes a performance boost */
2928 embedded_to_inline_constant(compiler_context
*ctx
)
2930 mir_foreach_instr(ctx
, ins
) {
2931 if (!ins
->has_constants
) continue;
2933 if (ins
->ssa_args
.inline_constant
) continue;
2935 /* Blend constants must not be inlined by definition */
2936 if (ins
->has_blend_constant
) continue;
2938 /* src1 cannot be an inline constant due to encoding
2939 * restrictions. So, if possible we try to flip the arguments
2942 int op
= ins
->alu
.op
;
2944 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2945 /* Flip based on op. Fallthrough intentional */
2948 /* These ops require an operational change to flip their arguments TODO */
2949 case midgard_alu_op_flt
:
2950 case midgard_alu_op_fle
:
2951 case midgard_alu_op_ilt
:
2952 case midgard_alu_op_ile
:
2953 case midgard_alu_op_fcsel
:
2954 case midgard_alu_op_icsel
:
2955 case midgard_alu_op_isub
:
2956 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2959 /* These ops are commutative and Just Flip */
2960 case midgard_alu_op_fne
:
2961 case midgard_alu_op_fadd
:
2962 case midgard_alu_op_fmul
:
2963 case midgard_alu_op_fmin
:
2964 case midgard_alu_op_fmax
:
2965 case midgard_alu_op_iadd
:
2966 case midgard_alu_op_imul
:
2967 case midgard_alu_op_feq
:
2968 case midgard_alu_op_ieq
:
2969 case midgard_alu_op_ine
:
2970 case midgard_alu_op_iand
:
2971 case midgard_alu_op_ior
:
2972 case midgard_alu_op_ixor
:
2973 /* Flip the SSA numbers */
2974 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2975 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2977 /* And flip the modifiers */
2981 src_temp
= ins
->alu
.src2
;
2982 ins
->alu
.src2
= ins
->alu
.src1
;
2983 ins
->alu
.src1
= src_temp
;
2990 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2991 /* Extract the source information */
2993 midgard_vector_alu_src
*src
;
2994 int q
= ins
->alu
.src2
;
2995 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2998 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2999 int component
= src
->swizzle
& 3;
3001 /* Scale constant appropriately, if we can legally */
3002 uint16_t scaled_constant
= 0;
3004 /* XXX: Check legality */
3005 if (midgard_is_integer_op(op
)) {
3006 /* TODO: Inline integer */
3009 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
3010 scaled_constant
= (uint16_t) iconstants
[component
];
3012 /* Constant overflow after resize */
3013 if (scaled_constant
!= iconstants
[component
])
3016 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
3019 /* We don't know how to handle these with a constant */
3021 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
3022 DBG("Bailing inline constant...\n");
3026 /* Make sure that the constant is not itself a
3027 * vector by checking if all accessed values
3028 * (by the swizzle) are the same. */
3030 uint32_t *cons
= (uint32_t *) ins
->constants
;
3031 uint32_t value
= cons
[component
];
3033 bool is_vector
= false;
3034 unsigned mask
= effective_writemask(&ins
->alu
);
3036 for (int c
= 1; c
< 4; ++c
) {
3037 /* We only care if this component is actually used */
3038 if (!(mask
& (1 << c
)))
3041 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3043 if (test
!= value
) {
3052 /* Get rid of the embedded constant */
3053 ins
->has_constants
= false;
3054 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3055 ins
->ssa_args
.inline_constant
= true;
3056 ins
->inline_constant
= scaled_constant
;
3061 /* Map normal SSA sources to other SSA sources / fixed registers (like
3065 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3067 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3070 /* Remove entry in leftovers to avoid a redunant fmov */
3072 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3075 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3077 /* Assign the alias map */
3083 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
3084 * texture pipeline */
3087 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
3089 bool progress
= false;
3091 mir_foreach_instr_in_block_safe(block
, ins
) {
3092 if (ins
->type
!= TAG_ALU_4
) continue;
3093 if (ins
->compact_branch
) continue;
3095 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3096 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3097 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3099 mir_remove_instruction(ins
);
3107 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
3109 bool progress
= false;
3111 mir_foreach_instr_in_block_safe(block
, ins
) {
3112 if (ins
->type
!= TAG_ALU_4
) continue;
3113 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3115 unsigned from
= ins
->ssa_args
.src1
;
3116 unsigned to
= ins
->ssa_args
.dest
;
3118 /* We only work on pure SSA */
3120 if (to
>= SSA_FIXED_MINIMUM
) continue;
3121 if (from
>= SSA_FIXED_MINIMUM
) continue;
3123 /* Also, if the move has side effects, we're helpless */
3125 midgard_vector_alu_src src
=
3126 vector_alu_from_unsigned(ins
->alu
.src2
);
3127 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
3128 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
3130 if (mir_nontrivial_mod(src
, is_int
, mask
)) continue;
3132 mir_foreach_instr_in_block_from(block
, v
, mir_next_op(ins
)) {
3133 if (v
->ssa_args
.src0
== to
) {
3134 v
->ssa_args
.src0
= from
;
3138 if (v
->ssa_args
.src1
== to
&& !v
->ssa_args
.inline_constant
) {
3139 v
->ssa_args
.src1
= from
;
3148 /* The following passes reorder MIR instructions to enable better scheduling */
3151 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3153 mir_foreach_instr_in_block_safe(block
, ins
) {
3154 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3156 /* We've found a load/store op. Check if next is also load/store. */
3157 midgard_instruction
*next_op
= mir_next_op(ins
);
3158 if (&next_op
->link
!= &block
->instructions
) {
3159 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3160 /* If so, we're done since we're a pair */
3161 ins
= mir_next_op(ins
);
3165 /* Maximum search distance to pair, to avoid register pressure disasters */
3166 int search_distance
= 8;
3168 /* Otherwise, we have an orphaned load/store -- search for another load */
3169 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3170 /* Terminate search if necessary */
3171 if (!(search_distance
--)) break;
3173 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3175 /* Stores cannot be reordered, since they have
3176 * dependencies. For the same reason, indirect
3177 * loads cannot be reordered as their index is
3178 * loaded in r27.w */
3180 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3182 /* It appears the 0x800 bit is set whenever a
3183 * load is direct, unset when it is indirect.
3184 * Skip indirect loads. */
3186 if (!(c
->load_store
.unknown
& 0x800)) continue;
3188 /* We found one! Move it up to pair and remove it from the old location */
3190 mir_insert_instruction_before(ins
, *c
);
3191 mir_remove_instruction(c
);
3199 /* Emit varying stores late */
3202 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3203 /* Iterate in reverse to get the final write, rather than the first */
3205 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3206 /* Check if what we just wrote needs a store */
3207 int idx
= ins
->ssa_args
.dest
;
3208 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3210 if (!varying
) continue;
3214 /* We need to store to the appropriate varying, so emit the
3217 /* TODO: Integrate with special purpose RA (and scheduler?) */
3218 bool high_varying_register
= false;
3220 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3222 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3223 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3225 mir_insert_instruction_before(mir_next_op(ins
), st
);
3226 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3228 /* We no longer need to store this varying */
3229 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3233 /* If there are leftovers after the below pass, emit actual fmov
3234 * instructions for the slow-but-correct path */
3237 emit_leftover_move(compiler_context
*ctx
)
3239 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3240 int base
= ((uintptr_t) leftover
->key
) - 1;
3243 map_ssa_to_alias(ctx
, &mapped
);
3244 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3249 actualise_ssa_to_alias(compiler_context
*ctx
)
3251 mir_foreach_instr(ctx
, ins
) {
3252 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3253 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3256 emit_leftover_move(ctx
);
3260 emit_fragment_epilogue(compiler_context
*ctx
)
3262 /* Special case: writing out constants requires us to include the move
3263 * explicitly now, so shove it into r0 */
3265 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3267 if (constant_value
) {
3268 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3269 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3270 emit_mir_instruction(ctx
, ins
);
3273 /* Perform the actual fragment writeout. We have two writeout/branch
3274 * instructions, forming a loop until writeout is successful as per the
3275 * docs. TODO: gl_FragDepth */
3277 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3278 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3281 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3282 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3283 * with the int8 analogue to the fragment epilogue */
3286 emit_blend_epilogue(compiler_context
*ctx
)
3288 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3290 midgard_instruction scale
= {
3293 .inline_constant
= _mesa_float_to_half(255.0),
3295 .src0
= SSA_FIXED_REGISTER(0),
3296 .src1
= SSA_UNUSED_0
,
3297 .dest
= SSA_FIXED_REGISTER(24),
3298 .inline_constant
= true
3301 .op
= midgard_alu_op_fmul
,
3302 .reg_mode
= midgard_reg_mode_full
,
3303 .dest_override
= midgard_dest_override_lower
,
3305 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3306 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3310 emit_mir_instruction(ctx
, scale
);
3312 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3314 midgard_vector_alu_src alu_src
= blank_alu_src
;
3315 alu_src
.half
= true;
3317 midgard_instruction f2u8
= {
3320 .src0
= SSA_FIXED_REGISTER(24),
3321 .src1
= SSA_UNUSED_0
,
3322 .dest
= SSA_FIXED_REGISTER(0),
3323 .inline_constant
= true
3326 .op
= midgard_alu_op_f2u8
,
3327 .reg_mode
= midgard_reg_mode_half
,
3328 .dest_override
= midgard_dest_override_lower
,
3329 .outmod
= midgard_outmod_pos
,
3331 .src1
= vector_alu_srco_unsigned(alu_src
),
3332 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3336 emit_mir_instruction(ctx
, f2u8
);
3338 /* vmul.imov.quarter r0, r0, r0 */
3340 midgard_instruction imov_8
= {
3343 .src0
= SSA_UNUSED_1
,
3344 .src1
= SSA_FIXED_REGISTER(0),
3345 .dest
= SSA_FIXED_REGISTER(0),
3348 .op
= midgard_alu_op_imov
,
3349 .reg_mode
= midgard_reg_mode_quarter
,
3350 .dest_override
= midgard_dest_override_none
,
3352 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3353 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3357 /* Emit branch epilogue with the 8-bit move as the source */
3359 emit_mir_instruction(ctx
, imov_8
);
3360 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3362 emit_mir_instruction(ctx
, imov_8
);
3363 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3366 static midgard_block
*
3367 emit_block(compiler_context
*ctx
, nir_block
*block
)
3369 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3370 list_addtail(&this_block
->link
, &ctx
->blocks
);
3372 this_block
->is_scheduled
= false;
3375 ctx
->texture_index
[0] = -1;
3376 ctx
->texture_index
[1] = -1;
3378 /* Add us as a successor to the block we are following */
3379 if (ctx
->current_block
)
3380 midgard_block_add_successor(ctx
->current_block
, this_block
);
3382 /* Set up current block */
3383 list_inithead(&this_block
->instructions
);
3384 ctx
->current_block
= this_block
;
3386 nir_foreach_instr(instr
, block
) {
3387 emit_instr(ctx
, instr
);
3388 ++ctx
->instruction_count
;
3391 inline_alu_constants(ctx
);
3392 embedded_to_inline_constant(ctx
);
3394 /* Perform heavylifting for aliasing */
3395 actualise_ssa_to_alias(ctx
);
3397 midgard_emit_store(ctx
, this_block
);
3398 midgard_pair_load_store(ctx
, this_block
);
3400 /* Append fragment shader epilogue (value writeout) */
3401 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3402 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3404 emit_blend_epilogue(ctx
);
3406 emit_fragment_epilogue(ctx
);
3410 if (block
== nir_start_block(ctx
->func
->impl
))
3411 ctx
->initial_block
= this_block
;
3413 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3414 ctx
->final_block
= this_block
;
3416 /* Allow the next control flow to access us retroactively, for
3418 ctx
->current_block
= this_block
;
3420 /* Document the fallthrough chain */
3421 ctx
->previous_source_block
= this_block
;
3426 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3429 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3431 /* Conditional branches expect the condition in r31.w; emit a move for
3432 * that in the _previous_ block (which is the current block). */
3433 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3435 /* Speculatively emit the branch, but we can't fill it in until later */
3436 EMIT(branch
, true, true);
3437 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3439 /* Emit the two subblocks */
3440 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3442 /* Emit a jump from the end of the then block to the end of the else */
3443 EMIT(branch
, false, false);
3444 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3446 /* Emit second block, and check if it's empty */
3448 int else_idx
= ctx
->block_count
;
3449 int count_in
= ctx
->instruction_count
;
3450 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3451 int after_else_idx
= ctx
->block_count
;
3453 /* Now that we have the subblocks emitted, fix up the branches */
3458 if (ctx
->instruction_count
== count_in
) {
3459 /* The else block is empty, so don't emit an exit jump */
3460 mir_remove_instruction(then_exit
);
3461 then_branch
->branch
.target_block
= after_else_idx
;
3463 then_branch
->branch
.target_block
= else_idx
;
3464 then_exit
->branch
.target_block
= after_else_idx
;
3469 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3471 /* Remember where we are */
3472 midgard_block
*start_block
= ctx
->current_block
;
3474 /* Allocate a loop number, growing the current inner loop depth */
3475 int loop_idx
= ++ctx
->current_loop_depth
;
3477 /* Get index from before the body so we can loop back later */
3478 int start_idx
= ctx
->block_count
;
3480 /* Emit the body itself */
3481 emit_cf_list(ctx
, &nloop
->body
);
3483 /* Branch back to loop back */
3484 struct midgard_instruction br_back
= v_branch(false, false);
3485 br_back
.branch
.target_block
= start_idx
;
3486 emit_mir_instruction(ctx
, br_back
);
3488 /* Mark down that branch in the graph. Note that we're really branching
3489 * to the block *after* we started in. TODO: Why doesn't the branch
3490 * itself have an off-by-one then...? */
3491 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
3493 /* Find the index of the block about to follow us (note: we don't add
3494 * one; blocks are 0-indexed so we get a fencepost problem) */
3495 int break_block_idx
= ctx
->block_count
;
3497 /* Fix up the break statements we emitted to point to the right place,
3498 * now that we can allocate a block number for them */
3500 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3501 mir_foreach_instr_in_block(block
, ins
) {
3502 if (ins
->type
!= TAG_ALU_4
) continue;
3503 if (!ins
->compact_branch
) continue;
3504 if (ins
->prepacked_branch
) continue;
3506 /* We found a branch -- check the type to see if we need to do anything */
3507 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3509 /* It's a break! Check if it's our break */
3510 if (ins
->branch
.target_break
!= loop_idx
) continue;
3512 /* Okay, cool, we're breaking out of this loop.
3513 * Rewrite from a break to a goto */
3515 ins
->branch
.target_type
= TARGET_GOTO
;
3516 ins
->branch
.target_block
= break_block_idx
;
3520 /* Now that we've finished emitting the loop, free up the depth again
3521 * so we play nice with recursion amid nested loops */
3522 --ctx
->current_loop_depth
;
3525 static midgard_block
*
3526 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3528 midgard_block
*start_block
= NULL
;
3530 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3531 switch (node
->type
) {
3532 case nir_cf_node_block
: {
3533 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3536 start_block
= block
;
3541 case nir_cf_node_if
:
3542 emit_if(ctx
, nir_cf_node_as_if(node
));
3545 case nir_cf_node_loop
:
3546 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3549 case nir_cf_node_function
:
3558 /* Due to lookahead, we need to report the first tag executed in the command
3559 * stream and in branch targets. An initial block might be empty, so iterate
3560 * until we find one that 'works' */
3563 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3565 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3567 unsigned first_tag
= 0;
3570 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3572 if (initial_bundle
) {
3573 first_tag
= initial_bundle
->tag
;
3577 /* Initial block is empty, try the next block */
3578 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3579 } while(initial_block
!= NULL
);
3586 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3588 struct util_dynarray
*compiled
= &program
->compiled
;
3590 midgard_debug
= debug_get_option_midgard_debug();
3592 compiler_context ictx
= {
3594 .stage
= nir
->info
.stage
,
3596 .is_blend
= is_blend
,
3597 .blend_constant_offset
= -1,
3599 .alpha_ref
= program
->alpha_ref
3602 compiler_context
*ctx
= &ictx
;
3604 /* TODO: Decide this at runtime */
3605 ctx
->uniform_cutoff
= 8;
3607 /* Assign var locations early, so the epilogue can use them if necessary */
3609 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3610 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3611 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3613 /* Initialize at a global (not block) level hash tables */
3615 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3616 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3617 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3618 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3619 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3620 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3621 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3623 /* Record the varying mapping for the command stream's bookkeeping */
3625 struct exec_list
*varyings
=
3626 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3628 nir_foreach_variable(var
, varyings
) {
3629 unsigned loc
= var
->data
.driver_location
;
3630 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3632 for (int c
= 0; c
< sz
; ++c
) {
3633 program
->varyings
[loc
+ c
] = var
->data
.location
;
3637 /* Lower gl_Position pre-optimisation */
3639 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3640 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3642 NIR_PASS_V(nir
, nir_lower_var_copies
);
3643 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3644 NIR_PASS_V(nir
, nir_split_var_copies
);
3645 NIR_PASS_V(nir
, nir_lower_var_copies
);
3646 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3647 NIR_PASS_V(nir
, nir_lower_var_copies
);
3648 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3650 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3652 /* Optimisation passes */
3656 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3657 nir_print_shader(nir
, stdout
);
3660 /* Assign sysvals and counts, now that we're sure
3661 * (post-optimisation) */
3663 midgard_nir_assign_sysvals(ctx
, nir
);
3665 program
->uniform_count
= nir
->num_uniforms
;
3666 program
->sysval_count
= ctx
->sysval_count
;
3667 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3669 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3670 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3672 nir_foreach_function(func
, nir
) {
3676 list_inithead(&ctx
->blocks
);
3677 ctx
->block_count
= 0;
3680 emit_cf_list(ctx
, &func
->impl
->body
);
3681 emit_block(ctx
, func
->impl
->end_block
);
3683 break; /* TODO: Multi-function shaders */
3686 util_dynarray_init(compiled
, NULL
);
3688 /* Peephole optimizations */
3690 mir_foreach_block(ctx
, block
) {
3691 midgard_opt_copy_prop(ctx
, block
);
3692 midgard_opt_dead_code_eliminate(ctx
, block
);
3696 schedule_program(ctx
);
3698 /* Now that all the bundles are scheduled and we can calculate block
3699 * sizes, emit actual branch instructions rather than placeholders */
3701 int br_block_idx
= 0;
3703 mir_foreach_block(ctx
, block
) {
3704 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3705 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3706 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3708 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3710 if (ins
->prepacked_branch
) continue;
3712 /* Parse some basic branch info */
3713 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3714 bool is_conditional
= ins
->branch
.conditional
;
3715 bool is_inverted
= ins
->branch
.invert_conditional
;
3716 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3718 /* Determine the block we're jumping to */
3719 int target_number
= ins
->branch
.target_block
;
3721 /* Report the destination tag. Discards don't need this */
3722 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3724 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3725 int quadword_offset
= 0;
3728 /* Jump to the end of the shader. We
3729 * need to include not only the
3730 * following blocks, but also the
3731 * contents of our current block (since
3732 * discard can come in the middle of
3735 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3737 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3738 quadword_offset
+= quadword_size(bun
->tag
);
3741 mir_foreach_block_from(ctx
, blk
, b
) {
3742 quadword_offset
+= b
->quadword_count
;
3745 } else if (target_number
> br_block_idx
) {
3748 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3749 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3752 quadword_offset
+= blk
->quadword_count
;
3755 /* Jump backwards */
3757 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3758 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3761 quadword_offset
-= blk
->quadword_count
;
3765 /* Unconditional extended branches (far jumps)
3766 * have issues, so we always use a conditional
3767 * branch, setting the condition to always for
3768 * unconditional. For compact unconditional
3769 * branches, cond isn't used so it doesn't
3770 * matter what we pick. */
3772 midgard_condition cond
=
3773 !is_conditional
? midgard_condition_always
:
3774 is_inverted
? midgard_condition_false
:
3775 midgard_condition_true
;
3777 midgard_jmp_writeout_op op
=
3778 is_discard
? midgard_jmp_writeout_op_discard
:
3779 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3780 midgard_jmp_writeout_op_branch_cond
;
3783 midgard_branch_extended branch
=
3784 midgard_create_branch_extended(
3789 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3790 } else if (is_conditional
|| is_discard
) {
3791 midgard_branch_cond branch
= {
3793 .dest_tag
= dest_tag
,
3794 .offset
= quadword_offset
,
3798 assert(branch
.offset
== quadword_offset
);
3800 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3802 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3804 midgard_branch_uncond branch
= {
3806 .dest_tag
= dest_tag
,
3807 .offset
= quadword_offset
,
3811 assert(branch
.offset
== quadword_offset
);
3813 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3821 /* Emit flat binary from the instruction arrays. Iterate each block in
3822 * sequence. Save instruction boundaries such that lookahead tags can
3823 * be assigned easily */
3825 /* Cache _all_ bundles in source order for lookahead across failed branches */
3827 int bundle_count
= 0;
3828 mir_foreach_block(ctx
, block
) {
3829 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3831 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3833 mir_foreach_block(ctx
, block
) {
3834 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3835 source_order_bundles
[bundle_idx
++] = bundle
;
3839 int current_bundle
= 0;
3841 mir_foreach_block(ctx
, block
) {
3842 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3845 if (current_bundle
+ 1 < bundle_count
) {
3846 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3848 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3855 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3859 /* TODO: Free deeper */
3860 //util_dynarray_fini(&block->instructions);
3863 free(source_order_bundles
);
3865 /* Report the very first tag executed */
3866 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3868 /* Deal with off-by-one related to the fencepost problem */
3869 program
->work_register_count
= ctx
->work_registers
+ 1;
3871 program
->can_discard
= ctx
->can_discard
;
3872 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3874 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3876 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3877 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);