2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 /* Successors: always one forward (the block after us), maybe
173 * one backwards (for a backward branch). No need for a second
174 * forward, since graph traversal would get there eventually
176 struct midgard_block
*successors
[2];
177 unsigned nr_successors
;
179 /* The successors pointer form a graph, and in the case of
180 * complex control flow, this graph has a cycles. To aid
181 * traversal during liveness analysis, we have a visited?
182 * boolean for passes to use as they see fit, provided they
188 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
190 block
->successors
[block
->nr_successors
++] = successor
;
191 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
194 /* Helpers to generate midgard_instruction's using macro magic, since every
195 * driver seems to do it that way */
197 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
198 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
200 #define M_LOAD_STORE(name, rname, uname) \
201 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
202 midgard_instruction i = { \
203 .type = TAG_LOAD_STORE_4, \
210 .op = midgard_op_##name, \
212 .swizzle = SWIZZLE_XYZW, \
220 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
221 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
223 const midgard_vector_alu_src blank_alu_src
= {
224 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
227 const midgard_vector_alu_src blank_alu_src_xxxx
= {
228 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
231 const midgard_scalar_alu_src blank_scalar_alu_src
= {
235 /* Used for encoding the unused source of 1-op instructions */
236 const midgard_vector_alu_src zero_alu_src
= { 0 };
238 /* Coerce structs to integer */
241 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
244 memcpy(&u
, &src
, sizeof(src
));
248 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
249 * the corresponding Midgard source */
251 static midgard_vector_alu_src
252 vector_alu_modifiers(nir_alu_src
*src
)
254 if (!src
) return blank_alu_src
;
256 midgard_vector_alu_src alu_src
= {
258 .negate
= src
->negate
,
261 .half
= 0, /* TODO */
262 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
268 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
270 static midgard_instruction
271 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
273 midgard_instruction ins
= {
276 .src0
= SSA_UNUSED_1
,
281 .op
= midgard_alu_op_fmov
,
282 .reg_mode
= midgard_reg_mode_full
,
283 .dest_override
= midgard_dest_override_none
,
285 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
286 .src2
= vector_alu_srco_unsigned(mod
)
293 /* load/store instructions have both 32-bit and 16-bit variants, depending on
294 * whether we are using vectors composed of highp or mediump. At the moment, we
295 * don't support half-floats -- this requires changes in other parts of the
296 * compiler -- therefore the 16-bit versions are commented out. */
298 //M_LOAD(load_attr_16);
299 M_LOAD(load_attr_32
);
300 //M_LOAD(load_vary_16);
301 M_LOAD(load_vary_32
);
302 //M_LOAD(load_uniform_16);
303 M_LOAD(load_uniform_32
);
304 M_LOAD(load_color_buffer_8
);
305 //M_STORE(store_vary_16);
306 M_STORE(store_vary_32
);
307 M_STORE(store_cubemap_coords
);
309 static midgard_instruction
310 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
312 midgard_branch_cond branch
= {
320 memcpy(&compact
, &branch
, sizeof(branch
));
322 midgard_instruction ins
= {
324 .unit
= ALU_ENAB_BR_COMPACT
,
325 .prepacked_branch
= true,
326 .compact_branch
= true,
327 .br_compact
= compact
330 if (op
== midgard_jmp_writeout_op_writeout
)
336 static midgard_instruction
337 v_branch(bool conditional
, bool invert
)
339 midgard_instruction ins
= {
341 .unit
= ALU_ENAB_BRANCH
,
342 .compact_branch
= true,
344 .conditional
= conditional
,
345 .invert_conditional
= invert
352 static midgard_branch_extended
353 midgard_create_branch_extended( midgard_condition cond
,
354 midgard_jmp_writeout_op op
,
356 signed quadword_offset
)
358 /* For unclear reasons, the condition code is repeated 8 times */
359 uint16_t duplicated_cond
=
369 midgard_branch_extended branch
= {
371 .dest_tag
= dest_tag
,
372 .offset
= quadword_offset
,
373 .cond
= duplicated_cond
379 typedef struct midgard_bundle
{
380 /* Tag for the overall bundle */
383 /* Instructions contained by the bundle */
384 int instruction_count
;
385 midgard_instruction instructions
[5];
387 /* Bundle-wide ALU configuration */
390 bool has_embedded_constants
;
392 bool has_blend_constant
;
394 uint16_t register_words
[8];
395 int register_words_count
;
397 uint64_t body_words
[8];
399 int body_words_count
;
402 typedef struct compiler_context
{
404 gl_shader_stage stage
;
406 /* Is internally a blend shader? Depends on stage == FRAGMENT */
409 /* Tracking for blend constant patching */
410 int blend_constant_number
;
411 int blend_constant_offset
;
413 /* Current NIR function */
416 /* Unordered list of midgard_blocks */
418 struct list_head blocks
;
420 midgard_block
*initial_block
;
421 midgard_block
*previous_source_block
;
422 midgard_block
*final_block
;
424 /* List of midgard_instructions emitted for the current block */
425 midgard_block
*current_block
;
427 /* The current "depth" of the loop, for disambiguating breaks/continues
428 * when using nested loops */
429 int current_loop_depth
;
431 /* Constants which have been loaded, for later inlining */
432 struct hash_table_u64
*ssa_constants
;
434 /* SSA indices to be outputted to corresponding varying offset */
435 struct hash_table_u64
*ssa_varyings
;
437 /* SSA values / registers which have been aliased. Naively, these
438 * demand a fmov output; instead, we alias them in a later pass to
439 * avoid the wasted op.
441 * A note on encoding: to avoid dynamic memory management here, rather
442 * than ampping to a pointer, we map to the source index; the key
443 * itself is just the destination index. */
445 struct hash_table_u64
*ssa_to_alias
;
446 struct set
*leftover_ssa_to_alias
;
448 /* Actual SSA-to-register for RA */
449 struct hash_table_u64
*ssa_to_register
;
451 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
452 struct hash_table_u64
*hash_to_temp
;
456 /* Just the count of the max register used. Higher count => higher
457 * register pressure */
460 /* Used for cont/last hinting. Increase when a tex op is added.
461 * Decrease when a tex op is removed. */
462 int texture_op_count
;
464 /* Mapping of texture register -> SSA index for unaliasing */
465 int texture_index
[2];
467 /* If any path hits a discard instruction */
470 /* The number of uniforms allowable for the fast path */
473 /* Count of instructions emitted from NIR overall, across all blocks */
474 int instruction_count
;
476 /* Alpha ref value passed in */
479 /* The index corresponding to the fragment output */
480 unsigned fragment_output
;
482 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
483 unsigned sysvals
[MAX_SYSVAL_COUNT
];
484 unsigned sysval_count
;
485 struct hash_table_u64
*sysval_to_id
;
488 /* Append instruction to end of current block */
490 static midgard_instruction
*
491 mir_upload_ins(struct midgard_instruction ins
)
493 midgard_instruction
*heap
= malloc(sizeof(ins
));
494 memcpy(heap
, &ins
, sizeof(ins
));
499 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
501 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
505 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
507 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
511 mir_remove_instruction(struct midgard_instruction
*ins
)
513 list_del(&ins
->link
);
516 static midgard_instruction
*
517 mir_prev_op(struct midgard_instruction
*ins
)
519 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
522 static midgard_instruction
*
523 mir_next_op(struct midgard_instruction
*ins
)
525 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
528 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
529 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
531 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
532 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
533 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
534 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
535 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
536 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
539 static midgard_instruction
*
540 mir_last_in_block(struct midgard_block
*block
)
542 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
545 static midgard_block
*
546 mir_get_block(compiler_context
*ctx
, int idx
)
548 struct list_head
*lst
= &ctx
->blocks
;
553 return (struct midgard_block
*) lst
;
556 /* Pretty printer for internal Midgard IR */
559 print_mir_source(int source
)
561 if (source
>= SSA_FIXED_MINIMUM
) {
562 /* Specific register */
563 int reg
= SSA_REG_FROM_FIXED(source
);
565 /* TODO: Moving threshold */
566 if (reg
> 16 && reg
< 24)
567 printf("u%d", 23 - reg
);
571 printf("%d", source
);
576 print_mir_instruction(midgard_instruction
*ins
)
582 midgard_alu_op op
= ins
->alu
.op
;
583 const char *name
= alu_opcode_names
[op
];
586 printf("%d.", ins
->unit
);
588 printf("%s", name
? name
: "??");
592 case TAG_LOAD_STORE_4
: {
593 midgard_load_store_op op
= ins
->load_store
.op
;
594 const char *name
= load_store_opcode_names
[op
];
601 case TAG_TEXTURE_4
: {
610 ssa_args
*args
= &ins
->ssa_args
;
612 printf(" %d, ", args
->dest
);
614 print_mir_source(args
->src0
);
617 if (args
->inline_constant
)
618 printf("#%d", ins
->inline_constant
);
620 print_mir_source(args
->src1
);
622 if (ins
->has_constants
)
623 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
629 print_mir_block(midgard_block
*block
)
633 mir_foreach_instr_in_block(block
, ins
) {
634 print_mir_instruction(ins
);
641 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
643 ins
->has_constants
= true;
644 memcpy(&ins
->constants
, constants
, 16);
646 /* If this is the special blend constant, mark this instruction */
648 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
649 ins
->has_blend_constant
= true;
653 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
655 return glsl_count_attribute_slots(type
, false);
658 /* Lower fdot2 to a vector multiplication followed by channel addition */
660 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
662 if (alu
->op
!= nir_op_fdot2
)
665 b
->cursor
= nir_before_instr(&alu
->instr
);
667 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
668 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
670 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
672 nir_ssa_def
*sum
= nir_fadd(b
,
673 nir_channel(b
, product
, 0),
674 nir_channel(b
, product
, 1));
676 /* Replace the fdot2 with this sum */
677 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
681 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
683 switch (instr
->intrinsic
) {
684 case nir_intrinsic_load_viewport_scale
:
685 return PAN_SYSVAL_VIEWPORT_SCALE
;
686 case nir_intrinsic_load_viewport_offset
:
687 return PAN_SYSVAL_VIEWPORT_OFFSET
;
694 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
698 if (instr
->type
== nir_instr_type_intrinsic
) {
699 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
700 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
706 /* We have a sysval load; check if it's already been assigned */
708 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
711 /* It hasn't -- so assign it now! */
713 unsigned id
= ctx
->sysval_count
++;
714 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
715 ctx
->sysvals
[id
] = sysval
;
719 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
721 ctx
->sysval_count
= 0;
723 nir_foreach_function(function
, shader
) {
724 if (!function
->impl
) continue;
726 nir_foreach_block(block
, function
->impl
) {
727 nir_foreach_instr_safe(instr
, block
) {
728 midgard_nir_assign_sysval_body(ctx
, instr
);
735 midgard_nir_lower_fdot2(nir_shader
*shader
)
737 bool progress
= false;
739 nir_foreach_function(function
, shader
) {
740 if (!function
->impl
) continue;
743 nir_builder
*b
= &_b
;
744 nir_builder_init(b
, function
->impl
);
746 nir_foreach_block(block
, function
->impl
) {
747 nir_foreach_instr_safe(instr
, block
) {
748 if (instr
->type
!= nir_instr_type_alu
) continue;
750 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
751 midgard_nir_lower_fdot2_body(b
, alu
);
757 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
765 optimise_nir(nir_shader
*nir
)
769 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
770 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
772 nir_lower_tex_options lower_tex_options
= {
776 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
781 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
782 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
784 NIR_PASS(progress
, nir
, nir_copy_prop
);
785 NIR_PASS(progress
, nir
, nir_opt_dce
);
786 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
787 NIR_PASS(progress
, nir
, nir_opt_cse
);
788 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
789 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
790 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
791 NIR_PASS(progress
, nir
, nir_opt_undef
);
792 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
795 nir_var_function_temp
);
797 /* TODO: Enable vectorize when merged upstream */
798 // NIR_PASS(progress, nir, nir_opt_vectorize);
801 /* Must be run at the end to prevent creation of fsin/fcos ops */
802 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
807 NIR_PASS(progress
, nir
, nir_opt_dce
);
808 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
809 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
810 NIR_PASS(progress
, nir
, nir_copy_prop
);
813 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
814 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
816 /* Lower mods for float ops only. Integer ops don't support modifiers
817 * (saturate doesn't make sense on integers, neg/abs require dedicated
820 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
821 NIR_PASS(progress
, nir
, nir_copy_prop
);
822 NIR_PASS(progress
, nir
, nir_opt_dce
);
824 /* We implement booleans as 32-bit 0/~0 */
825 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
827 /* Take us out of SSA */
828 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
829 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
831 /* We are a vector architecture; write combine where possible */
832 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
833 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
835 NIR_PASS(progress
, nir
, nir_opt_dce
);
838 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
839 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
840 * r0. See the comments in compiler_context */
843 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
845 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
846 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
849 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
852 unalias_ssa(compiler_context
*ctx
, int dest
)
854 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
855 /* TODO: Remove from leftover or no? */
859 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
861 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
865 midgard_is_pinned(compiler_context
*ctx
, int index
)
867 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
870 /* Do not actually emit a load; instead, cache the constant for inlining */
873 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
875 nir_ssa_def def
= instr
->def
;
877 float *v
= ralloc_array(NULL
, float, 4);
878 nir_const_load_to_arr(v
, instr
, f32
);
879 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
882 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
886 expand_writemask(unsigned mask
)
890 for (int i
= 0; i
< 4; ++i
)
898 squeeze_writemask(unsigned mask
)
902 for (int i
= 0; i
< 4; ++i
)
903 if (mask
& (3 << (2 * i
)))
910 /* Determines effective writemask, taking quirks and expansion into account */
912 effective_writemask(midgard_vector_alu
*alu
)
914 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
917 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
919 /* If there is a fixed channel count, construct the appropriate mask */
922 return (1 << channel_count
) - 1;
924 /* Otherwise, just squeeze the existing mask */
925 return squeeze_writemask(alu
->mask
);
929 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
931 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
934 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
939 /* If no temp is find, allocate one */
940 temp
= ctx
->temp_count
++;
941 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
943 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
949 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
952 return src
->ssa
->index
;
954 assert(!src
->reg
.indirect
);
955 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
960 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
963 return dst
->ssa
.index
;
965 assert(!dst
->reg
.indirect
);
966 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
971 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
973 return nir_src_index(ctx
, &src
->src
);
976 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
977 * a conditional test) into that register */
980 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
982 int condition
= nir_src_index(ctx
, src
);
984 /* Source to swizzle the desired component into w */
986 const midgard_vector_alu_src alu_src
= {
987 .swizzle
= SWIZZLE(component
, component
, component
, component
),
990 /* There is no boolean move instruction. Instead, we simulate a move by
991 * ANDing the condition with itself to get it into r31.w */
993 midgard_instruction ins
= {
995 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
999 .dest
= SSA_FIXED_REGISTER(31),
1002 .op
= midgard_alu_op_iand
,
1003 .reg_mode
= midgard_reg_mode_full
,
1004 .dest_override
= midgard_dest_override_none
,
1005 .mask
= (0x3 << 6), /* w */
1006 .src1
= vector_alu_srco_unsigned(alu_src
),
1007 .src2
= vector_alu_srco_unsigned(alu_src
)
1011 emit_mir_instruction(ctx
, ins
);
1014 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1015 * pinning to eliminate this move in all known cases */
1018 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1020 int offset
= nir_src_index(ctx
, src
);
1022 midgard_instruction ins
= {
1025 .src0
= SSA_UNUSED_1
,
1027 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1030 .op
= midgard_alu_op_imov
,
1031 .reg_mode
= midgard_reg_mode_full
,
1032 .dest_override
= midgard_dest_override_none
,
1033 .mask
= (0x3 << 6), /* w */
1034 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1035 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1039 emit_mir_instruction(ctx
, ins
);
1042 #define ALU_CASE(nir, _op) \
1043 case nir_op_##nir: \
1044 op = midgard_alu_op_##_op; \
1048 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1050 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1052 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1053 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1054 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1056 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1057 * supported. A few do not and are commented for now. Also, there are a
1058 * number of NIR ops which Midgard does not support and need to be
1059 * lowered, also TODO. This switch block emits the opcode and calling
1060 * convention of the Midgard instruction; actual packing is done in
1065 switch (instr
->op
) {
1066 ALU_CASE(fadd
, fadd
);
1067 ALU_CASE(fmul
, fmul
);
1068 ALU_CASE(fmin
, fmin
);
1069 ALU_CASE(fmax
, fmax
);
1070 ALU_CASE(imin
, imin
);
1071 ALU_CASE(imax
, imax
);
1072 ALU_CASE(umin
, umin
);
1073 ALU_CASE(umax
, umax
);
1074 ALU_CASE(fmov
, fmov
);
1075 ALU_CASE(ffloor
, ffloor
);
1076 ALU_CASE(fround_even
, froundeven
);
1077 ALU_CASE(ftrunc
, ftrunc
);
1078 ALU_CASE(fceil
, fceil
);
1079 ALU_CASE(fdot3
, fdot3
);
1080 ALU_CASE(fdot4
, fdot4
);
1081 ALU_CASE(iadd
, iadd
);
1082 ALU_CASE(isub
, isub
);
1083 ALU_CASE(imul
, imul
);
1084 ALU_CASE(iabs
, iabs
);
1086 /* XXX: Use fmov, not imov, since imov was causing major
1087 * issues with texture precision? XXX research */
1088 ALU_CASE(imov
, imov
);
1090 ALU_CASE(feq32
, feq
);
1091 ALU_CASE(fne32
, fne
);
1092 ALU_CASE(flt32
, flt
);
1093 ALU_CASE(ieq32
, ieq
);
1094 ALU_CASE(ine32
, ine
);
1095 ALU_CASE(ilt32
, ilt
);
1096 ALU_CASE(ult32
, ult
);
1098 /* We don't have a native b2f32 instruction. Instead, like many
1099 * GPUs, we exploit booleans as 0/~0 for false/true, and
1100 * correspondingly AND
1101 * by 1.0 to do the type conversion. For the moment, prime us
1104 * iand [whatever], #0
1106 * At the end of emit_alu (as MIR), we'll fix-up the constant
1109 ALU_CASE(b2f32
, iand
);
1110 ALU_CASE(b2i32
, iand
);
1112 /* Likewise, we don't have a dedicated f2b32 instruction, but
1113 * we can do a "not equal to 0.0" test. */
1115 ALU_CASE(f2b32
, fne
);
1116 ALU_CASE(i2b32
, ine
);
1118 ALU_CASE(frcp
, frcp
);
1119 ALU_CASE(frsq
, frsqrt
);
1120 ALU_CASE(fsqrt
, fsqrt
);
1121 ALU_CASE(fexp2
, fexp2
);
1122 ALU_CASE(flog2
, flog2
);
1124 ALU_CASE(f2i32
, f2i
);
1125 ALU_CASE(f2u32
, f2u
);
1126 ALU_CASE(i2f32
, i2f
);
1127 ALU_CASE(u2f32
, u2f
);
1129 ALU_CASE(fsin
, fsin
);
1130 ALU_CASE(fcos
, fcos
);
1132 ALU_CASE(iand
, iand
);
1134 ALU_CASE(ixor
, ixor
);
1135 ALU_CASE(inot
, inot
);
1136 ALU_CASE(ishl
, ishl
);
1137 ALU_CASE(ishr
, iasr
);
1138 ALU_CASE(ushr
, ilsr
);
1140 ALU_CASE(b32all_fequal2
, fball_eq
);
1141 ALU_CASE(b32all_fequal3
, fball_eq
);
1142 ALU_CASE(b32all_fequal4
, fball_eq
);
1144 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1145 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1146 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1148 ALU_CASE(b32all_iequal2
, iball_eq
);
1149 ALU_CASE(b32all_iequal3
, iball_eq
);
1150 ALU_CASE(b32all_iequal4
, iball_eq
);
1152 ALU_CASE(b32any_inequal2
, ibany_neq
);
1153 ALU_CASE(b32any_inequal3
, ibany_neq
);
1154 ALU_CASE(b32any_inequal4
, ibany_neq
);
1156 /* For greater-or-equal, we lower to less-or-equal and flip the
1162 case nir_op_uge32
: {
1164 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1165 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1166 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1167 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1170 /* Swap via temporary */
1171 nir_alu_src temp
= instr
->src
[1];
1172 instr
->src
[1] = instr
->src
[0];
1173 instr
->src
[0] = temp
;
1178 case nir_op_b32csel
: {
1179 op
= midgard_alu_op_fcsel
;
1181 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1184 /* Figure out which component the condition is in */
1186 unsigned comp
= instr
->src
[0].swizzle
[0];
1188 /* Make sure NIR isn't throwing a mixed condition at us */
1190 for (unsigned c
= 1; c
< nr_components
; ++c
)
1191 assert(instr
->src
[0].swizzle
[c
] == comp
);
1193 /* Emit the condition into r31.w */
1194 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1196 /* The condition is the first argument; move the other
1197 * arguments up one to be a binary instruction for
1200 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1205 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1210 /* Fetch unit, quirks, etc information */
1211 unsigned opcode_props
= alu_opcode_props
[op
];
1212 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1214 /* Initialise fields common between scalar/vector instructions */
1215 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1217 /* src0 will always exist afaik, but src1 will not for 1-argument
1218 * instructions. The latter can only be fetched if the instruction
1219 * needs it, or else we may segfault. */
1221 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1222 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1224 /* Rather than use the instruction generation helpers, we do it
1225 * ourselves here to avoid the mess */
1227 midgard_instruction ins
= {
1230 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1231 .src1
= quirk_flipped_r24
? src0
: src1
,
1236 nir_alu_src
*nirmods
[2] = { NULL
};
1238 if (nr_inputs
== 2) {
1239 nirmods
[0] = &instr
->src
[0];
1240 nirmods
[1] = &instr
->src
[1];
1241 } else if (nr_inputs
== 1) {
1242 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1247 midgard_vector_alu alu
= {
1249 .reg_mode
= midgard_reg_mode_full
,
1250 .dest_override
= midgard_dest_override_none
,
1253 /* Writemask only valid for non-SSA NIR */
1254 .mask
= expand_writemask((1 << nr_components
) - 1),
1256 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1257 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1260 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1263 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1267 /* Late fixup for emulated instructions */
1269 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1270 /* Presently, our second argument is an inline #0 constant.
1271 * Switch over to an embedded 1.0 constant (that can't fit
1272 * inline, since we're 32-bit, not 16-bit like the inline
1275 ins
.ssa_args
.inline_constant
= false;
1276 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1277 ins
.has_constants
= true;
1279 if (instr
->op
== nir_op_b2f32
) {
1280 ins
.constants
[0] = 1.0f
;
1282 /* Type pun it into place */
1284 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1287 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1288 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1289 ins
.ssa_args
.inline_constant
= false;
1290 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1291 ins
.has_constants
= true;
1292 ins
.constants
[0] = 0.0f
;
1293 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1296 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1297 /* To avoid duplicating the lookup tables (probably), true LUT
1298 * instructions can only operate as if they were scalars. Lower
1299 * them here by changing the component. */
1301 uint8_t original_swizzle
[4];
1302 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1304 for (int i
= 0; i
< nr_components
; ++i
) {
1305 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1307 for (int j
= 0; j
< 4; ++j
)
1308 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1310 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1311 emit_mir_instruction(ctx
, ins
);
1314 emit_mir_instruction(ctx
, ins
);
1321 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1323 /* TODO: half-floats */
1325 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1326 /* Fast path: For the first 16 uniforms, direct accesses are
1327 * 0-cycle, since they're just a register fetch in the usual
1328 * case. So, we alias the registers while we're still in
1331 int reg_slot
= 23 - offset
;
1332 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1334 /* Otherwise, read from the 'special' UBO to access
1335 * higher-indexed uniforms, at a performance cost. More
1336 * generally, we're emitting a UBO read instruction. */
1338 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1340 /* TODO: Don't split */
1341 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1342 ins
.load_store
.address
= offset
>> 3;
1344 if (indirect_offset
) {
1345 emit_indirect_offset(ctx
, indirect_offset
);
1346 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1348 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1351 emit_mir_instruction(ctx
, ins
);
1356 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1358 /* First, pull out the destination */
1359 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1361 /* Now, figure out which uniform this is */
1362 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1363 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1365 /* Sysvals are prefix uniforms */
1366 unsigned uniform
= ((uintptr_t) val
) - 1;
1368 /* Emit the read itself -- this is never indirect */
1369 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1373 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1375 unsigned offset
, reg
;
1377 switch (instr
->intrinsic
) {
1378 case nir_intrinsic_discard_if
:
1379 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1383 case nir_intrinsic_discard
: {
1384 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1385 struct midgard_instruction discard
= v_branch(conditional
, false);
1386 discard
.branch
.target_type
= TARGET_DISCARD
;
1387 emit_mir_instruction(ctx
, discard
);
1389 ctx
->can_discard
= true;
1393 case nir_intrinsic_load_uniform
:
1394 case nir_intrinsic_load_input
:
1395 offset
= nir_intrinsic_base(instr
);
1397 bool direct
= nir_src_is_const(instr
->src
[0]);
1400 offset
+= nir_src_as_uint(instr
->src
[0]);
1403 reg
= nir_dest_index(ctx
, &instr
->dest
);
1405 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1406 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1407 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1408 /* XXX: Half-floats? */
1409 /* TODO: swizzle, mask */
1411 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1413 midgard_varying_parameter p
= {
1415 .interpolation
= midgard_interp_default
,
1416 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1420 memcpy(&u
, &p
, sizeof(p
));
1421 ins
.load_store
.varying_parameters
= u
;
1424 /* We have the offset totally ready */
1425 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1427 /* We have it partially ready, but we need to
1428 * add in the dynamic index, moved to r27.w */
1429 emit_indirect_offset(ctx
, &instr
->src
[0]);
1430 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1433 emit_mir_instruction(ctx
, ins
);
1434 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1435 /* Constant encoded as a pinned constant */
1437 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1438 ins
.has_constants
= true;
1439 ins
.has_blend_constant
= true;
1440 emit_mir_instruction(ctx
, ins
);
1441 } else if (ctx
->is_blend
) {
1442 /* For blend shaders, a load might be
1443 * translated various ways depending on what
1444 * we're loading. Figure out how this is used */
1446 nir_variable
*out
= NULL
;
1448 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1449 int drvloc
= var
->data
.driver_location
;
1451 if (nir_intrinsic_base(instr
) == drvloc
) {
1459 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1460 /* Source color preloaded to r0 */
1462 midgard_pin_output(ctx
, reg
, 0);
1463 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1464 /* Destination color must be read from framebuffer */
1466 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1467 ins
.load_store
.swizzle
= 0; /* xxxx */
1469 /* Read each component sequentially */
1471 for (int c
= 0; c
< 4; ++c
) {
1472 ins
.load_store
.mask
= (1 << c
);
1473 ins
.load_store
.unknown
= c
;
1474 emit_mir_instruction(ctx
, ins
);
1477 /* vadd.u2f hr2, abs(hr2), #0 */
1479 midgard_vector_alu_src alu_src
= blank_alu_src
;
1481 alu_src
.half
= true;
1483 midgard_instruction u2f
= {
1487 .src1
= SSA_UNUSED_0
,
1489 .inline_constant
= true
1492 .op
= midgard_alu_op_u2f
,
1493 .reg_mode
= midgard_reg_mode_half
,
1494 .dest_override
= midgard_dest_override_none
,
1496 .src1
= vector_alu_srco_unsigned(alu_src
),
1497 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1501 emit_mir_instruction(ctx
, u2f
);
1503 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1505 alu_src
.abs
= false;
1507 midgard_instruction fmul
= {
1509 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1513 .src1
= SSA_UNUSED_0
,
1514 .inline_constant
= true
1517 .op
= midgard_alu_op_fmul
,
1518 .reg_mode
= midgard_reg_mode_full
,
1519 .dest_override
= midgard_dest_override_none
,
1520 .outmod
= midgard_outmod_sat
,
1522 .src1
= vector_alu_srco_unsigned(alu_src
),
1523 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1527 emit_mir_instruction(ctx
, fmul
);
1529 DBG("Unknown input in blend shader\n");
1532 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1533 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1534 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1535 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1536 emit_mir_instruction(ctx
, ins
);
1538 DBG("Unknown load\n");
1544 case nir_intrinsic_store_output
:
1545 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1547 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1549 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1551 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1552 /* gl_FragColor is not emitted with load/store
1553 * instructions. Instead, it gets plonked into
1554 * r0 at the end of the shader and we do the
1555 * framebuffer writeout dance. TODO: Defer
1558 midgard_pin_output(ctx
, reg
, 0);
1560 /* Save the index we're writing to for later reference
1561 * in the epilogue */
1563 ctx
->fragment_output
= reg
;
1564 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1565 /* Varyings are written into one of two special
1566 * varying register, r26 or r27. The register itself is selected as the register
1567 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1569 * Normally emitting fmov's is frowned upon,
1570 * but due to unique constraints of
1571 * REGISTER_VARYING, fmov emission + a
1572 * dedicated cleanup pass is the only way to
1573 * guarantee correctness when considering some
1574 * (common) edge cases XXX: FIXME */
1576 /* If this varying corresponds to a constant (why?!),
1577 * emit that now since it won't get picked up by
1578 * hoisting (since there is no corresponding move
1579 * emitted otherwise) */
1581 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1583 if (constant_value
) {
1584 /* Special case: emit the varying write
1585 * directly to r26 (looks funny in asm but it's
1586 * fine) and emit the store _now_. Possibly
1587 * slightly slower, but this is a really stupid
1588 * special case anyway (why on earth would you
1589 * have a constant varying? Your own fault for
1590 * slightly worse perf :P) */
1592 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1593 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1594 emit_mir_instruction(ctx
, ins
);
1596 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1597 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1598 emit_mir_instruction(ctx
, st
);
1600 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1602 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1605 DBG("Unknown store\n");
1611 case nir_intrinsic_load_alpha_ref_float
:
1612 assert(instr
->dest
.is_ssa
);
1614 float ref_value
= ctx
->alpha_ref
;
1616 float *v
= ralloc_array(NULL
, float, 4);
1617 memcpy(v
, &ref_value
, sizeof(float));
1618 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1621 case nir_intrinsic_load_viewport_scale
:
1622 case nir_intrinsic_load_viewport_offset
:
1623 emit_sysval_read(ctx
, instr
);
1627 printf ("Unhandled intrinsic\n");
1634 midgard_tex_format(enum glsl_sampler_dim dim
)
1637 case GLSL_SAMPLER_DIM_2D
:
1638 case GLSL_SAMPLER_DIM_EXTERNAL
:
1641 case GLSL_SAMPLER_DIM_3D
:
1644 case GLSL_SAMPLER_DIM_CUBE
:
1645 return TEXTURE_CUBE
;
1648 DBG("Unknown sampler dim type\n");
1655 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1658 //assert (!instr->sampler);
1659 //assert (!instr->texture_array_size);
1660 assert (instr
->op
== nir_texop_tex
);
1662 /* Allocate registers via a round robin scheme to alternate between the two registers */
1663 int reg
= ctx
->texture_op_count
& 1;
1664 int in_reg
= reg
, out_reg
= reg
;
1666 /* Make room for the reg */
1668 if (ctx
->texture_index
[reg
] > -1)
1669 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1671 int texture_index
= instr
->texture_index
;
1672 int sampler_index
= texture_index
;
1674 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1675 switch (instr
->src
[i
].src_type
) {
1676 case nir_tex_src_coord
: {
1677 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1679 midgard_vector_alu_src alu_src
= blank_alu_src
;
1681 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1683 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1684 /* For cubemaps, we need to load coords into
1685 * special r27, and then use a special ld/st op
1686 * to copy into the texture register */
1688 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1690 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1691 emit_mir_instruction(ctx
, move
);
1693 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1694 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1695 st
.load_store
.mask
= 0x3; /* xy? */
1696 st
.load_store
.swizzle
= alu_src
.swizzle
;
1697 emit_mir_instruction(ctx
, st
);
1700 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1702 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1703 emit_mir_instruction(ctx
, ins
);
1706 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1712 DBG("Unknown source type\n");
1719 /* No helper to build texture words -- we do it all here */
1720 midgard_instruction ins
= {
1721 .type
= TAG_TEXTURE_4
,
1723 .op
= TEXTURE_OP_NORMAL
,
1724 .format
= midgard_tex_format(instr
->sampler_dim
),
1725 .texture_handle
= texture_index
,
1726 .sampler_handle
= sampler_index
,
1728 /* TODO: Don't force xyzw */
1729 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1741 /* Assume we can continue; hint it out later */
1746 /* Set registers to read and write from the same place */
1747 ins
.texture
.in_reg_select
= in_reg
;
1748 ins
.texture
.out_reg_select
= out_reg
;
1750 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1751 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1752 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1753 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1754 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1756 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1757 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1758 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1761 emit_mir_instruction(ctx
, ins
);
1763 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1765 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1766 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1767 ctx
->texture_index
[reg
] = o_index
;
1769 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1770 emit_mir_instruction(ctx
, ins2
);
1772 /* Used for .cont and .last hinting */
1773 ctx
->texture_op_count
++;
1777 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1779 switch (instr
->type
) {
1780 case nir_jump_break
: {
1781 /* Emit a branch out of the loop */
1782 struct midgard_instruction br
= v_branch(false, false);
1783 br
.branch
.target_type
= TARGET_BREAK
;
1784 br
.branch
.target_break
= ctx
->current_loop_depth
;
1785 emit_mir_instruction(ctx
, br
);
1792 DBG("Unknown jump type %d\n", instr
->type
);
1798 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1800 switch (instr
->type
) {
1801 case nir_instr_type_load_const
:
1802 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1805 case nir_instr_type_intrinsic
:
1806 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1809 case nir_instr_type_alu
:
1810 emit_alu(ctx
, nir_instr_as_alu(instr
));
1813 case nir_instr_type_tex
:
1814 emit_tex(ctx
, nir_instr_as_tex(instr
));
1817 case nir_instr_type_jump
:
1818 emit_jump(ctx
, nir_instr_as_jump(instr
));
1821 case nir_instr_type_ssa_undef
:
1826 DBG("Unhandled instruction type\n");
1831 /* Determine the actual hardware from the index based on the RA results or special values */
1834 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1836 if (reg
>= SSA_FIXED_MINIMUM
)
1837 return SSA_REG_FROM_FIXED(reg
);
1840 assert(reg
< maxreg
);
1841 int r
= ra_get_node_reg(g
, reg
);
1842 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1847 /* fmov style unused */
1849 return REGISTER_UNUSED
;
1851 /* lut style unused */
1853 return REGISTER_UNUSED
;
1856 DBG("Unknown SSA register alias %d\n", reg
);
1863 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1865 /* Choose the first available register to minimise reported register pressure */
1867 for (int i
= 0; i
< 16; ++i
) {
1868 if (BITSET_TEST(regs
, i
)) {
1878 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1880 if (ins
->ssa_args
.src0
== src
) return true;
1881 if (ins
->ssa_args
.src1
== src
) return true;
1886 /* Determine if a variable is live in the successors of a block */
1888 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
1890 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
1891 midgard_block
*succ
= bl
->successors
[i
];
1893 /* If we already visited, the value we're seeking
1894 * isn't down this path (or we would have short
1897 if (succ
->visited
) continue;
1899 /* Otherwise (it's visited *now*), check the block */
1901 succ
->visited
= true;
1903 mir_foreach_instr_in_block(succ
, ins
) {
1904 if (midgard_is_live_in_instr(ins
, src
))
1908 /* ...and also, check *its* successors */
1909 if (is_live_after_successors(ctx
, succ
, src
))
1914 /* Welp. We're really not live. */
1920 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1922 /* Check the rest of the block for liveness */
1924 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1925 if (midgard_is_live_in_instr(ins
, src
))
1929 /* Check the rest of the blocks for liveness recursively */
1931 bool succ
= is_live_after_successors(ctx
, block
, src
);
1933 mir_foreach_block(ctx
, block
) {
1934 block
->visited
= false;
1941 allocate_registers(compiler_context
*ctx
)
1943 /* First, initialize the RA */
1944 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1946 /* Create a primary (general purpose) class, as well as special purpose
1947 * pipeline register classes */
1949 int primary_class
= ra_alloc_reg_class(regs
);
1950 int varying_class
= ra_alloc_reg_class(regs
);
1952 /* Add the full set of work registers */
1953 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1954 for (int i
= 0; i
< work_count
; ++i
)
1955 ra_class_add_reg(regs
, primary_class
, i
);
1957 /* Add special registers */
1958 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1959 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1961 /* We're done setting up */
1962 ra_set_finalize(regs
, NULL
);
1964 /* Transform the MIR into squeezed index form */
1965 mir_foreach_block(ctx
, block
) {
1966 mir_foreach_instr_in_block(block
, ins
) {
1967 if (ins
->compact_branch
) continue;
1969 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1970 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1971 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1973 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1974 print_mir_block(block
);
1977 /* Let's actually do register allocation */
1978 int nodes
= ctx
->temp_count
;
1979 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1981 /* Set everything to the work register class, unless it has somewhere
1984 mir_foreach_block(ctx
, block
) {
1985 mir_foreach_instr_in_block(block
, ins
) {
1986 if (ins
->compact_branch
) continue;
1988 if (ins
->ssa_args
.dest
< 0) continue;
1990 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1992 int class = primary_class
;
1994 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1998 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1999 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2002 unsigned reg
= temp
- 1;
2003 int t
= find_or_allocate_temp(ctx
, index
);
2004 ra_set_node_reg(g
, t
, reg
);
2008 /* Determine liveness */
2010 int *live_start
= malloc(nodes
* sizeof(int));
2011 int *live_end
= malloc(nodes
* sizeof(int));
2013 /* Initialize as non-existent */
2015 for (int i
= 0; i
< nodes
; ++i
) {
2016 live_start
[i
] = live_end
[i
] = -1;
2021 mir_foreach_block(ctx
, block
) {
2022 mir_foreach_instr_in_block(block
, ins
) {
2023 if (ins
->compact_branch
) continue;
2025 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2026 /* If this destination is not yet live, it is now since we just wrote it */
2028 int dest
= ins
->ssa_args
.dest
;
2030 if (live_start
[dest
] == -1)
2031 live_start
[dest
] = d
;
2034 /* Since we just used a source, the source might be
2035 * dead now. Scan the rest of the block for
2036 * invocations, and if there are none, the source dies
2039 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2041 for (int src
= 0; src
< 2; ++src
) {
2042 int s
= sources
[src
];
2044 if (s
< 0) continue;
2046 if (s
>= SSA_FIXED_MINIMUM
) continue;
2048 if (!is_live_after(ctx
, block
, ins
, s
)) {
2057 /* If a node still hasn't been killed, kill it now */
2059 for (int i
= 0; i
< nodes
; ++i
) {
2060 /* live_start == -1 most likely indicates a pinned output */
2062 if (live_end
[i
] == -1)
2066 /* Setup interference between nodes that are live at the same time */
2068 for (int i
= 0; i
< nodes
; ++i
) {
2069 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2070 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2071 ra_add_node_interference(g
, i
, j
);
2075 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2077 if (!ra_allocate(g
)) {
2078 DBG("Error allocating registers\n");
2086 mir_foreach_block(ctx
, block
) {
2087 mir_foreach_instr_in_block(block
, ins
) {
2088 if (ins
->compact_branch
) continue;
2090 ssa_args args
= ins
->ssa_args
;
2092 switch (ins
->type
) {
2094 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
2096 ins
->registers
.src2_imm
= args
.inline_constant
;
2098 if (args
.inline_constant
) {
2099 /* Encode inline 16-bit constant as a vector by default */
2101 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2103 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2105 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2106 ins
->alu
.src2
= imm
<< 2;
2108 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2111 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2115 case TAG_LOAD_STORE_4
: {
2116 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2117 /* TODO: use ssa_args for store_vary */
2118 ins
->load_store
.reg
= 0;
2120 bool has_dest
= args
.dest
>= 0;
2121 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2123 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2136 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2137 * use scalar ALU instructions, for functional or performance reasons. To do
2138 * this, we just demote vector ALU payloads to scalar. */
2141 component_from_mask(unsigned mask
)
2143 for (int c
= 0; c
< 4; ++c
) {
2144 if (mask
& (3 << (2 * c
)))
2153 is_single_component_mask(unsigned mask
)
2157 for (int c
= 0; c
< 4; ++c
)
2158 if (mask
& (3 << (2 * c
)))
2161 return components
== 1;
2164 /* Create a mask of accessed components from a swizzle to figure out vector
2168 swizzle_to_access_mask(unsigned swizzle
)
2170 unsigned component_mask
= 0;
2172 for (int i
= 0; i
< 4; ++i
) {
2173 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2174 component_mask
|= (1 << c
);
2177 return component_mask
;
2181 vector_to_scalar_source(unsigned u
)
2183 midgard_vector_alu_src v
;
2184 memcpy(&v
, &u
, sizeof(v
));
2186 midgard_scalar_alu_src s
= {
2190 .component
= (v
.swizzle
& 3) << 1
2194 memcpy(&o
, &s
, sizeof(s
));
2196 return o
& ((1 << 6) - 1);
2199 static midgard_scalar_alu
2200 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2202 /* The output component is from the mask */
2203 midgard_scalar_alu s
= {
2205 .src1
= vector_to_scalar_source(v
.src1
),
2206 .src2
= vector_to_scalar_source(v
.src2
),
2209 .output_full
= 1, /* TODO: Half */
2210 .output_component
= component_from_mask(v
.mask
) << 1,
2213 /* Inline constant is passed along rather than trying to extract it
2216 if (ins
->ssa_args
.inline_constant
) {
2218 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2219 imm
|= (lower_11
>> 9) & 3;
2220 imm
|= (lower_11
>> 6) & 4;
2221 imm
|= (lower_11
>> 2) & 0x38;
2222 imm
|= (lower_11
& 63) << 6;
2230 /* Midgard prefetches instruction types, so during emission we need to
2231 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2232 * if this is the second to last and the last is an ALU, then it's also 1... */
2234 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2235 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2237 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2238 bytes_emitted += sizeof(type)
2241 emit_binary_vector_instruction(midgard_instruction
*ains
,
2242 uint16_t *register_words
, int *register_words_count
,
2243 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2244 size_t *bytes_emitted
)
2246 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2247 *bytes_emitted
+= sizeof(midgard_reg_info
);
2249 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2250 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2251 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2254 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2255 * mind that we are a vector architecture and we can write to different
2256 * components simultaneously */
2259 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2261 /* Each instruction reads some registers and writes to a register. See
2262 * where the first writes */
2264 /* Figure out where exactly we wrote to */
2265 int source
= first
->ssa_args
.dest
;
2266 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2268 /* As long as the second doesn't read from the first, we're okay */
2269 if (second
->ssa_args
.src0
== source
) {
2270 if (first
->type
== TAG_ALU_4
) {
2271 /* Figure out which components we just read from */
2273 int q
= second
->alu
.src1
;
2274 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2276 /* Check if there are components in common, and fail if so */
2277 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2284 if (second
->ssa_args
.src1
== source
)
2287 /* Otherwise, it's safe in that regard. Another data hazard is both
2288 * writing to the same place, of course */
2290 if (second
->ssa_args
.dest
== source
) {
2291 /* ...but only if the components overlap */
2292 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2294 if (dest_mask
& source_mask
)
2304 midgard_instruction
**segment
, unsigned segment_size
,
2305 midgard_instruction
*ains
)
2307 for (int s
= 0; s
< segment_size
; ++s
)
2308 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2316 /* Schedules, but does not emit, a single basic block. After scheduling, the
2317 * final tag and size of the block are known, which are necessary for branching
2320 static midgard_bundle
2321 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2323 int instructions_emitted
= 0, instructions_consumed
= -1;
2324 midgard_bundle bundle
= { 0 };
2326 uint8_t tag
= ins
->type
;
2328 /* Default to the instruction's tag */
2331 switch (ins
->type
) {
2333 uint32_t control
= 0;
2334 size_t bytes_emitted
= sizeof(control
);
2336 /* TODO: Constant combining */
2337 int index
= 0, last_unit
= 0;
2339 /* Previous instructions, for the purpose of parallelism */
2340 midgard_instruction
*segment
[4] = {0};
2341 int segment_size
= 0;
2343 instructions_emitted
= -1;
2344 midgard_instruction
*pins
= ins
;
2347 midgard_instruction
*ains
= pins
;
2349 /* Advance instruction pointer */
2351 ains
= mir_next_op(pins
);
2355 /* Out-of-work condition */
2356 if ((struct list_head
*) ains
== &block
->instructions
)
2359 /* Ensure that the chain can continue */
2360 if (ains
->type
!= TAG_ALU_4
) break;
2362 /* According to the presentation "The ARM
2363 * Mali-T880 Mobile GPU" from HotChips 27,
2364 * there are two pipeline stages. Branching
2365 * position determined experimentally. Lines
2366 * are executed in parallel:
2369 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2371 * Verify that there are no ordering dependencies here.
2373 * TODO: Allow for parallelism!!!
2376 /* Pick a unit for it if it doesn't force a particular unit */
2378 int unit
= ains
->unit
;
2381 int op
= ains
->alu
.op
;
2382 int units
= alu_opcode_props
[op
];
2384 /* TODO: Promotion of scalars to vectors */
2385 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2388 assert(units
& UNITS_SCALAR
);
2391 if (last_unit
>= UNIT_VADD
) {
2392 if (units
& UNIT_VLUT
)
2397 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2399 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2401 else if (units
& UNIT_VLUT
)
2407 if (last_unit
>= UNIT_VADD
) {
2408 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2410 else if (units
& UNIT_VLUT
)
2415 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2417 else if (units
& UNIT_SMUL
)
2418 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2419 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2426 assert(unit
& units
);
2429 /* Late unit check, this time for encoding (not parallelism) */
2430 if (unit
<= last_unit
) break;
2432 /* Clear the segment */
2433 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2436 if (midgard_has_hazard(segment
, segment_size
, ains
))
2439 /* We're good to go -- emit the instruction */
2442 segment
[segment_size
++] = ains
;
2444 /* Only one set of embedded constants per
2445 * bundle possible; if we have more, we must
2446 * break the chain early, unfortunately */
2448 if (ains
->has_constants
) {
2449 if (bundle
.has_embedded_constants
) {
2450 /* ...but if there are already
2451 * constants but these are the
2452 * *same* constants, we let it
2455 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2458 bundle
.has_embedded_constants
= true;
2459 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2461 /* If this is a blend shader special constant, track it for patching */
2462 if (ains
->has_blend_constant
)
2463 bundle
.has_blend_constant
= true;
2467 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2468 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2469 &bundle
.register_words_count
, bundle
.body_words
,
2470 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2471 } else if (ains
->compact_branch
) {
2472 /* All of r0 has to be written out
2473 * along with the branch writeout.
2476 if (ains
->writeout
) {
2478 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2479 ins
.unit
= UNIT_VMUL
;
2481 control
|= ins
.unit
;
2483 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2484 &bundle
.register_words_count
, bundle
.body_words
,
2485 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2487 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2488 bool written_late
= false;
2489 bool components
[4] = { 0 };
2490 uint16_t register_dep_mask
= 0;
2491 uint16_t written_mask
= 0;
2493 midgard_instruction
*qins
= ins
;
2494 for (int t
= 0; t
< index
; ++t
) {
2495 if (qins
->registers
.out_reg
!= 0) {
2496 /* Mark down writes */
2498 written_mask
|= (1 << qins
->registers
.out_reg
);
2500 /* Mark down the register dependencies for errata check */
2502 if (qins
->registers
.src1_reg
< 16)
2503 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2505 if (qins
->registers
.src2_reg
< 16)
2506 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2508 int mask
= qins
->alu
.mask
;
2510 for (int c
= 0; c
< 4; ++c
)
2511 if (mask
& (0x3 << (2 * c
)))
2512 components
[c
] = true;
2514 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2516 if (qins
->unit
== UNIT_VLUT
)
2517 written_late
= true;
2520 /* Advance instruction pointer */
2521 qins
= mir_next_op(qins
);
2525 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2526 if (register_dep_mask
& written_mask
) {
2527 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2534 /* If even a single component is not written, break it up (conservative check). */
2535 bool breakup
= false;
2537 for (int c
= 0; c
< 4; ++c
)
2544 /* Otherwise, we're free to proceed */
2548 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2549 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2550 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2551 bytes_emitted
+= sizeof(midgard_branch_extended
);
2553 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2554 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2555 bytes_emitted
+= sizeof(ains
->br_compact
);
2558 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2559 bytes_emitted
+= sizeof(midgard_reg_info
);
2561 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2562 bundle
.body_words_count
++;
2563 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2566 /* Defer marking until after writing to allow for break */
2567 control
|= ains
->unit
;
2568 last_unit
= ains
->unit
;
2569 ++instructions_emitted
;
2573 /* Bubble up the number of instructions for skipping */
2574 instructions_consumed
= index
- 1;
2578 /* Pad ALU op to nearest word */
2580 if (bytes_emitted
& 15) {
2581 padding
= 16 - (bytes_emitted
& 15);
2582 bytes_emitted
+= padding
;
2585 /* Constants must always be quadwords */
2586 if (bundle
.has_embedded_constants
)
2587 bytes_emitted
+= 16;
2589 /* Size ALU instruction for tag */
2590 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2591 bundle
.padding
= padding
;
2592 bundle
.control
= bundle
.tag
| control
;
2597 case TAG_LOAD_STORE_4
: {
2598 /* Load store instructions have two words at once. If
2599 * we only have one queued up, we need to NOP pad.
2600 * Otherwise, we store both in succession to save space
2601 * and cycles -- letting them go in parallel -- skip
2602 * the next. The usefulness of this optimisation is
2603 * greatly dependent on the quality of the instruction
2607 midgard_instruction
*next_op
= mir_next_op(ins
);
2609 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2610 /* As the two operate concurrently, make sure
2611 * they are not dependent */
2613 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2614 /* Skip ahead, since it's redundant with the pair */
2615 instructions_consumed
= 1 + (instructions_emitted
++);
2623 /* Texture ops default to single-op-per-bundle scheduling */
2627 /* Copy the instructions into the bundle */
2628 bundle
.instruction_count
= instructions_emitted
+ 1;
2632 midgard_instruction
*uins
= ins
;
2633 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2634 bundle
.instructions
[used_idx
++] = *uins
;
2635 uins
= mir_next_op(uins
);
2638 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2644 quadword_size(int tag
)
2659 case TAG_LOAD_STORE_4
:
2671 /* Schedule a single block by iterating its instruction to create bundles.
2672 * While we go, tally about the bundle sizes to compute the block size. */
2675 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2677 util_dynarray_init(&block
->bundles
, NULL
);
2679 block
->quadword_count
= 0;
2681 mir_foreach_instr_in_block(block
, ins
) {
2683 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2684 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2686 if (bundle
.has_blend_constant
) {
2687 /* TODO: Multiblock? */
2688 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2689 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2693 ins
= mir_next_op(ins
);
2695 block
->quadword_count
+= quadword_size(bundle
.tag
);
2698 block
->is_scheduled
= true;
2702 schedule_program(compiler_context
*ctx
)
2704 allocate_registers(ctx
);
2706 mir_foreach_block(ctx
, block
) {
2707 schedule_block(ctx
, block
);
2711 /* After everything is scheduled, emit whole bundles at a time */
2714 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2716 int lookahead
= next_tag
<< 4;
2718 switch (bundle
->tag
) {
2723 /* Actually emit each component */
2724 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2726 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2727 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2729 /* Emit body words based on the instructions bundled */
2730 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2731 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2733 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2734 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2735 } else if (ins
->compact_branch
) {
2736 /* Dummy move, XXX DRY */
2737 if ((i
== 0) && ins
->writeout
) {
2738 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2739 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2742 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2743 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2745 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2749 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2750 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2754 /* Emit padding (all zero) */
2755 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2757 /* Tack on constants */
2759 if (bundle
->has_embedded_constants
) {
2760 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2761 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2762 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2763 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2769 case TAG_LOAD_STORE_4
: {
2770 /* One or two composing instructions */
2772 uint64_t current64
, next64
= LDST_NOP
;
2774 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2776 if (bundle
->instruction_count
== 2)
2777 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2779 midgard_load_store instruction
= {
2780 .type
= bundle
->tag
,
2781 .next_type
= next_tag
,
2786 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2791 case TAG_TEXTURE_4
: {
2792 /* Texture instructions are easy, since there is no
2793 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2795 midgard_instruction
*ins
= &bundle
->instructions
[0];
2797 ins
->texture
.type
= TAG_TEXTURE_4
;
2798 ins
->texture
.next_type
= next_tag
;
2800 ctx
->texture_op_count
--;
2802 if (!ctx
->texture_op_count
) {
2803 ins
->texture
.cont
= 0;
2804 ins
->texture
.last
= 1;
2807 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2812 DBG("Unknown midgard instruction type\n");
2819 /* ALU instructions can inline or embed constants, which decreases register
2820 * pressure and saves space. */
2822 #define CONDITIONAL_ATTACH(src) { \
2823 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2826 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2827 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2832 inline_alu_constants(compiler_context
*ctx
)
2834 mir_foreach_instr(ctx
, alu
) {
2835 /* Other instructions cannot inline constants */
2836 if (alu
->type
!= TAG_ALU_4
) continue;
2838 /* If there is already a constant here, we can do nothing */
2839 if (alu
->has_constants
) continue;
2841 /* It makes no sense to inline constants on a branch */
2842 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
2844 CONDITIONAL_ATTACH(src0
);
2846 if (!alu
->has_constants
) {
2847 CONDITIONAL_ATTACH(src1
)
2848 } else if (!alu
->inline_constant
) {
2849 /* Corner case: _two_ vec4 constants, for instance with a
2850 * csel. For this case, we can only use a constant
2851 * register for one, we'll have to emit a move for the
2852 * other. Note, if both arguments are constants, then
2853 * necessarily neither argument depends on the value of
2854 * any particular register. As the destination register
2855 * will be wiped, that means we can spill the constant
2856 * to the destination register.
2859 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2860 unsigned scratch
= alu
->ssa_args
.dest
;
2863 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2864 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2866 /* Force a break XXX Defer r31 writes */
2867 ins
.unit
= UNIT_VLUT
;
2869 /* Set the source */
2870 alu
->ssa_args
.src1
= scratch
;
2872 /* Inject us -before- the last instruction which set r31 */
2873 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2879 /* Midgard supports two types of constants, embedded constants (128-bit) and
2880 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2881 * constants can be demoted to inline constants, for space savings and
2882 * sometimes a performance boost */
2885 embedded_to_inline_constant(compiler_context
*ctx
)
2887 mir_foreach_instr(ctx
, ins
) {
2888 if (!ins
->has_constants
) continue;
2890 if (ins
->ssa_args
.inline_constant
) continue;
2892 /* Blend constants must not be inlined by definition */
2893 if (ins
->has_blend_constant
) continue;
2895 /* src1 cannot be an inline constant due to encoding
2896 * restrictions. So, if possible we try to flip the arguments
2899 int op
= ins
->alu
.op
;
2901 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2902 /* Flip based on op. Fallthrough intentional */
2905 /* These ops require an operational change to flip their arguments TODO */
2906 case midgard_alu_op_flt
:
2907 case midgard_alu_op_fle
:
2908 case midgard_alu_op_ilt
:
2909 case midgard_alu_op_ile
:
2910 case midgard_alu_op_fcsel
:
2911 case midgard_alu_op_icsel
:
2912 case midgard_alu_op_isub
:
2913 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2916 /* These ops are commutative and Just Flip */
2917 case midgard_alu_op_fne
:
2918 case midgard_alu_op_fadd
:
2919 case midgard_alu_op_fmul
:
2920 case midgard_alu_op_fmin
:
2921 case midgard_alu_op_fmax
:
2922 case midgard_alu_op_iadd
:
2923 case midgard_alu_op_imul
:
2924 case midgard_alu_op_feq
:
2925 case midgard_alu_op_ieq
:
2926 case midgard_alu_op_ine
:
2927 case midgard_alu_op_iand
:
2928 case midgard_alu_op_ior
:
2929 case midgard_alu_op_ixor
:
2930 /* Flip the SSA numbers */
2931 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2932 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2934 /* And flip the modifiers */
2938 src_temp
= ins
->alu
.src2
;
2939 ins
->alu
.src2
= ins
->alu
.src1
;
2940 ins
->alu
.src1
= src_temp
;
2947 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2948 /* Extract the source information */
2950 midgard_vector_alu_src
*src
;
2951 int q
= ins
->alu
.src2
;
2952 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2955 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2956 int component
= src
->swizzle
& 3;
2958 /* Scale constant appropriately, if we can legally */
2959 uint16_t scaled_constant
= 0;
2961 /* XXX: Check legality */
2962 if (midgard_is_integer_op(op
)) {
2963 /* TODO: Inline integer */
2966 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2967 scaled_constant
= (uint16_t) iconstants
[component
];
2969 /* Constant overflow after resize */
2970 if (scaled_constant
!= iconstants
[component
])
2973 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2976 /* We don't know how to handle these with a constant */
2978 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2979 DBG("Bailing inline constant...\n");
2983 /* Make sure that the constant is not itself a
2984 * vector by checking if all accessed values
2985 * (by the swizzle) are the same. */
2987 uint32_t *cons
= (uint32_t *) ins
->constants
;
2988 uint32_t value
= cons
[component
];
2990 bool is_vector
= false;
2991 unsigned mask
= effective_writemask(&ins
->alu
);
2993 for (int c
= 1; c
< 4; ++c
) {
2994 /* We only care if this component is actually used */
2995 if (!(mask
& (1 << c
)))
2998 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3000 if (test
!= value
) {
3009 /* Get rid of the embedded constant */
3010 ins
->has_constants
= false;
3011 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3012 ins
->ssa_args
.inline_constant
= true;
3013 ins
->inline_constant
= scaled_constant
;
3018 /* Map normal SSA sources to other SSA sources / fixed registers (like
3022 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3024 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3027 /* Remove entry in leftovers to avoid a redunant fmov */
3029 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3032 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3034 /* Assign the alias map */
3040 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
3041 * texture pipeline */
3044 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
3046 mir_foreach_instr_in_block_safe(block
, ins
) {
3047 if (ins
->type
!= TAG_ALU_4
) continue;
3048 if (ins
->compact_branch
) continue;
3050 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3051 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3052 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3054 mir_remove_instruction(ins
);
3058 /* The following passes reorder MIR instructions to enable better scheduling */
3061 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3063 mir_foreach_instr_in_block_safe(block
, ins
) {
3064 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3066 /* We've found a load/store op. Check if next is also load/store. */
3067 midgard_instruction
*next_op
= mir_next_op(ins
);
3068 if (&next_op
->link
!= &block
->instructions
) {
3069 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3070 /* If so, we're done since we're a pair */
3071 ins
= mir_next_op(ins
);
3075 /* Maximum search distance to pair, to avoid register pressure disasters */
3076 int search_distance
= 8;
3078 /* Otherwise, we have an orphaned load/store -- search for another load */
3079 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3080 /* Terminate search if necessary */
3081 if (!(search_distance
--)) break;
3083 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3085 /* Stores cannot be reordered, since they have
3086 * dependencies. For the same reason, indirect
3087 * loads cannot be reordered as their index is
3088 * loaded in r27.w */
3090 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3092 /* It appears the 0x800 bit is set whenever a
3093 * load is direct, unset when it is indirect.
3094 * Skip indirect loads. */
3096 if (!(c
->load_store
.unknown
& 0x800)) continue;
3098 /* We found one! Move it up to pair and remove it from the old location */
3100 mir_insert_instruction_before(ins
, *c
);
3101 mir_remove_instruction(c
);
3109 /* Emit varying stores late */
3112 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3113 /* Iterate in reverse to get the final write, rather than the first */
3115 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3116 /* Check if what we just wrote needs a store */
3117 int idx
= ins
->ssa_args
.dest
;
3118 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3120 if (!varying
) continue;
3124 /* We need to store to the appropriate varying, so emit the
3127 /* TODO: Integrate with special purpose RA (and scheduler?) */
3128 bool high_varying_register
= false;
3130 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3132 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3133 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3135 mir_insert_instruction_before(mir_next_op(ins
), st
);
3136 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3138 /* We no longer need to store this varying */
3139 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3143 /* If there are leftovers after the below pass, emit actual fmov
3144 * instructions for the slow-but-correct path */
3147 emit_leftover_move(compiler_context
*ctx
)
3149 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3150 int base
= ((uintptr_t) leftover
->key
) - 1;
3153 map_ssa_to_alias(ctx
, &mapped
);
3154 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3159 actualise_ssa_to_alias(compiler_context
*ctx
)
3161 mir_foreach_instr(ctx
, ins
) {
3162 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3163 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3166 emit_leftover_move(ctx
);
3170 emit_fragment_epilogue(compiler_context
*ctx
)
3172 /* Special case: writing out constants requires us to include the move
3173 * explicitly now, so shove it into r0 */
3175 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3177 if (constant_value
) {
3178 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3179 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3180 emit_mir_instruction(ctx
, ins
);
3183 /* Perform the actual fragment writeout. We have two writeout/branch
3184 * instructions, forming a loop until writeout is successful as per the
3185 * docs. TODO: gl_FragDepth */
3187 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3188 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3191 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3192 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3193 * with the int8 analogue to the fragment epilogue */
3196 emit_blend_epilogue(compiler_context
*ctx
)
3198 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3200 midgard_instruction scale
= {
3203 .inline_constant
= _mesa_float_to_half(255.0),
3205 .src0
= SSA_FIXED_REGISTER(0),
3206 .src1
= SSA_UNUSED_0
,
3207 .dest
= SSA_FIXED_REGISTER(24),
3208 .inline_constant
= true
3211 .op
= midgard_alu_op_fmul
,
3212 .reg_mode
= midgard_reg_mode_full
,
3213 .dest_override
= midgard_dest_override_lower
,
3215 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3216 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3220 emit_mir_instruction(ctx
, scale
);
3222 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3224 midgard_vector_alu_src alu_src
= blank_alu_src
;
3225 alu_src
.half
= true;
3227 midgard_instruction f2u8
= {
3230 .src0
= SSA_FIXED_REGISTER(24),
3231 .src1
= SSA_UNUSED_0
,
3232 .dest
= SSA_FIXED_REGISTER(0),
3233 .inline_constant
= true
3236 .op
= midgard_alu_op_f2u8
,
3237 .reg_mode
= midgard_reg_mode_half
,
3238 .dest_override
= midgard_dest_override_lower
,
3239 .outmod
= midgard_outmod_pos
,
3241 .src1
= vector_alu_srco_unsigned(alu_src
),
3242 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3246 emit_mir_instruction(ctx
, f2u8
);
3248 /* vmul.imov.quarter r0, r0, r0 */
3250 midgard_instruction imov_8
= {
3253 .src0
= SSA_UNUSED_1
,
3254 .src1
= SSA_FIXED_REGISTER(0),
3255 .dest
= SSA_FIXED_REGISTER(0),
3258 .op
= midgard_alu_op_imov
,
3259 .reg_mode
= midgard_reg_mode_quarter
,
3260 .dest_override
= midgard_dest_override_none
,
3262 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3263 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3267 /* Emit branch epilogue with the 8-bit move as the source */
3269 emit_mir_instruction(ctx
, imov_8
);
3270 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3272 emit_mir_instruction(ctx
, imov_8
);
3273 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3276 static midgard_block
*
3277 emit_block(compiler_context
*ctx
, nir_block
*block
)
3279 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3280 list_addtail(&this_block
->link
, &ctx
->blocks
);
3282 this_block
->is_scheduled
= false;
3285 ctx
->texture_index
[0] = -1;
3286 ctx
->texture_index
[1] = -1;
3288 /* Add us as a successor to the block we are following */
3289 if (ctx
->current_block
)
3290 midgard_block_add_successor(ctx
->current_block
, this_block
);
3292 /* Set up current block */
3293 list_inithead(&this_block
->instructions
);
3294 ctx
->current_block
= this_block
;
3296 nir_foreach_instr(instr
, block
) {
3297 emit_instr(ctx
, instr
);
3298 ++ctx
->instruction_count
;
3301 inline_alu_constants(ctx
);
3302 embedded_to_inline_constant(ctx
);
3304 /* Perform heavylifting for aliasing */
3305 actualise_ssa_to_alias(ctx
);
3307 midgard_emit_store(ctx
, this_block
);
3308 midgard_pair_load_store(ctx
, this_block
);
3310 /* Append fragment shader epilogue (value writeout) */
3311 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3312 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3314 emit_blend_epilogue(ctx
);
3316 emit_fragment_epilogue(ctx
);
3320 if (block
== nir_start_block(ctx
->func
->impl
))
3321 ctx
->initial_block
= this_block
;
3323 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3324 ctx
->final_block
= this_block
;
3326 /* Allow the next control flow to access us retroactively, for
3328 ctx
->current_block
= this_block
;
3330 /* Document the fallthrough chain */
3331 ctx
->previous_source_block
= this_block
;
3336 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3339 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3341 /* Conditional branches expect the condition in r31.w; emit a move for
3342 * that in the _previous_ block (which is the current block). */
3343 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3345 /* Speculatively emit the branch, but we can't fill it in until later */
3346 EMIT(branch
, true, true);
3347 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3349 /* Emit the two subblocks */
3350 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3352 /* Emit a jump from the end of the then block to the end of the else */
3353 EMIT(branch
, false, false);
3354 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3356 /* Emit second block, and check if it's empty */
3358 int else_idx
= ctx
->block_count
;
3359 int count_in
= ctx
->instruction_count
;
3360 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3361 int after_else_idx
= ctx
->block_count
;
3363 /* Now that we have the subblocks emitted, fix up the branches */
3368 if (ctx
->instruction_count
== count_in
) {
3369 /* The else block is empty, so don't emit an exit jump */
3370 mir_remove_instruction(then_exit
);
3371 then_branch
->branch
.target_block
= after_else_idx
;
3373 then_branch
->branch
.target_block
= else_idx
;
3374 then_exit
->branch
.target_block
= after_else_idx
;
3379 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3381 /* Remember where we are */
3382 midgard_block
*start_block
= ctx
->current_block
;
3384 /* Allocate a loop number, growing the current inner loop depth */
3385 int loop_idx
= ++ctx
->current_loop_depth
;
3387 /* Get index from before the body so we can loop back later */
3388 int start_idx
= ctx
->block_count
;
3390 /* Emit the body itself */
3391 emit_cf_list(ctx
, &nloop
->body
);
3393 /* Branch back to loop back */
3394 struct midgard_instruction br_back
= v_branch(false, false);
3395 br_back
.branch
.target_block
= start_idx
;
3396 emit_mir_instruction(ctx
, br_back
);
3398 /* Mark down that branch in the graph. Note that we're really branching
3399 * to the block *after* we started in. TODO: Why doesn't the branch
3400 * itself have an off-by-one then...? */
3401 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
3403 /* Find the index of the block about to follow us (note: we don't add
3404 * one; blocks are 0-indexed so we get a fencepost problem) */
3405 int break_block_idx
= ctx
->block_count
;
3407 /* Fix up the break statements we emitted to point to the right place,
3408 * now that we can allocate a block number for them */
3410 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3411 mir_foreach_instr_in_block(block
, ins
) {
3412 if (ins
->type
!= TAG_ALU_4
) continue;
3413 if (!ins
->compact_branch
) continue;
3414 if (ins
->prepacked_branch
) continue;
3416 /* We found a branch -- check the type to see if we need to do anything */
3417 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3419 /* It's a break! Check if it's our break */
3420 if (ins
->branch
.target_break
!= loop_idx
) continue;
3422 /* Okay, cool, we're breaking out of this loop.
3423 * Rewrite from a break to a goto */
3425 ins
->branch
.target_type
= TARGET_GOTO
;
3426 ins
->branch
.target_block
= break_block_idx
;
3430 /* Now that we've finished emitting the loop, free up the depth again
3431 * so we play nice with recursion amid nested loops */
3432 --ctx
->current_loop_depth
;
3435 static midgard_block
*
3436 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3438 midgard_block
*start_block
= NULL
;
3440 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3441 switch (node
->type
) {
3442 case nir_cf_node_block
: {
3443 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3446 start_block
= block
;
3451 case nir_cf_node_if
:
3452 emit_if(ctx
, nir_cf_node_as_if(node
));
3455 case nir_cf_node_loop
:
3456 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3459 case nir_cf_node_function
:
3468 /* Due to lookahead, we need to report the first tag executed in the command
3469 * stream and in branch targets. An initial block might be empty, so iterate
3470 * until we find one that 'works' */
3473 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3475 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3477 unsigned first_tag
= 0;
3480 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3482 if (initial_bundle
) {
3483 first_tag
= initial_bundle
->tag
;
3487 /* Initial block is empty, try the next block */
3488 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3489 } while(initial_block
!= NULL
);
3496 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3498 struct util_dynarray
*compiled
= &program
->compiled
;
3500 midgard_debug
= debug_get_option_midgard_debug();
3502 compiler_context ictx
= {
3504 .stage
= nir
->info
.stage
,
3506 .is_blend
= is_blend
,
3507 .blend_constant_offset
= -1,
3509 .alpha_ref
= program
->alpha_ref
3512 compiler_context
*ctx
= &ictx
;
3514 /* TODO: Decide this at runtime */
3515 ctx
->uniform_cutoff
= 8;
3517 /* Assign var locations early, so the epilogue can use them if necessary */
3519 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3520 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3521 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3523 /* Initialize at a global (not block) level hash tables */
3525 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3526 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3527 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3528 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3529 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3530 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3531 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3533 /* Record the varying mapping for the command stream's bookkeeping */
3535 struct exec_list
*varyings
=
3536 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3538 nir_foreach_variable(var
, varyings
) {
3539 unsigned loc
= var
->data
.driver_location
;
3540 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3542 for (int c
= 0; c
< sz
; ++c
) {
3543 program
->varyings
[loc
+ c
] = var
->data
.location
;
3547 /* Lower gl_Position pre-optimisation */
3549 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3550 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3552 NIR_PASS_V(nir
, nir_lower_var_copies
);
3553 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3554 NIR_PASS_V(nir
, nir_split_var_copies
);
3555 NIR_PASS_V(nir
, nir_lower_var_copies
);
3556 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3557 NIR_PASS_V(nir
, nir_lower_var_copies
);
3558 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3560 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3562 /* Optimisation passes */
3566 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3567 nir_print_shader(nir
, stdout
);
3570 /* Assign sysvals and counts, now that we're sure
3571 * (post-optimisation) */
3573 midgard_nir_assign_sysvals(ctx
, nir
);
3575 program
->uniform_count
= nir
->num_uniforms
;
3576 program
->sysval_count
= ctx
->sysval_count
;
3577 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3579 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3580 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3582 nir_foreach_function(func
, nir
) {
3586 list_inithead(&ctx
->blocks
);
3587 ctx
->block_count
= 0;
3590 emit_cf_list(ctx
, &func
->impl
->body
);
3591 emit_block(ctx
, func
->impl
->end_block
);
3593 break; /* TODO: Multi-function shaders */
3596 util_dynarray_init(compiled
, NULL
);
3598 /* Peephole optimizations */
3600 mir_foreach_block(ctx
, block
) {
3601 midgard_opt_dead_code_eliminate(ctx
, block
);
3605 schedule_program(ctx
);
3607 /* Now that all the bundles are scheduled and we can calculate block
3608 * sizes, emit actual branch instructions rather than placeholders */
3610 int br_block_idx
= 0;
3612 mir_foreach_block(ctx
, block
) {
3613 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3614 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3615 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3617 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3619 if (ins
->prepacked_branch
) continue;
3621 /* Parse some basic branch info */
3622 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3623 bool is_conditional
= ins
->branch
.conditional
;
3624 bool is_inverted
= ins
->branch
.invert_conditional
;
3625 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3627 /* Determine the block we're jumping to */
3628 int target_number
= ins
->branch
.target_block
;
3630 /* Report the destination tag. Discards don't need this */
3631 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3633 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3634 int quadword_offset
= 0;
3637 /* Jump to the end of the shader. We
3638 * need to include not only the
3639 * following blocks, but also the
3640 * contents of our current block (since
3641 * discard can come in the middle of
3644 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3646 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3647 quadword_offset
+= quadword_size(bun
->tag
);
3650 mir_foreach_block_from(ctx
, blk
, b
) {
3651 quadword_offset
+= b
->quadword_count
;
3654 } else if (target_number
> br_block_idx
) {
3657 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3658 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3661 quadword_offset
+= blk
->quadword_count
;
3664 /* Jump backwards */
3666 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3667 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3670 quadword_offset
-= blk
->quadword_count
;
3674 /* Unconditional extended branches (far jumps)
3675 * have issues, so we always use a conditional
3676 * branch, setting the condition to always for
3677 * unconditional. For compact unconditional
3678 * branches, cond isn't used so it doesn't
3679 * matter what we pick. */
3681 midgard_condition cond
=
3682 !is_conditional
? midgard_condition_always
:
3683 is_inverted
? midgard_condition_false
:
3684 midgard_condition_true
;
3686 midgard_jmp_writeout_op op
=
3687 is_discard
? midgard_jmp_writeout_op_discard
:
3688 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3689 midgard_jmp_writeout_op_branch_cond
;
3692 midgard_branch_extended branch
=
3693 midgard_create_branch_extended(
3698 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3699 } else if (is_conditional
|| is_discard
) {
3700 midgard_branch_cond branch
= {
3702 .dest_tag
= dest_tag
,
3703 .offset
= quadword_offset
,
3707 assert(branch
.offset
== quadword_offset
);
3709 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3711 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3713 midgard_branch_uncond branch
= {
3715 .dest_tag
= dest_tag
,
3716 .offset
= quadword_offset
,
3720 assert(branch
.offset
== quadword_offset
);
3722 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3730 /* Emit flat binary from the instruction arrays. Iterate each block in
3731 * sequence. Save instruction boundaries such that lookahead tags can
3732 * be assigned easily */
3734 /* Cache _all_ bundles in source order for lookahead across failed branches */
3736 int bundle_count
= 0;
3737 mir_foreach_block(ctx
, block
) {
3738 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3740 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3742 mir_foreach_block(ctx
, block
) {
3743 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3744 source_order_bundles
[bundle_idx
++] = bundle
;
3748 int current_bundle
= 0;
3750 mir_foreach_block(ctx
, block
) {
3751 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3754 if (current_bundle
+ 1 < bundle_count
) {
3755 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3757 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3764 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3768 /* TODO: Free deeper */
3769 //util_dynarray_fini(&block->instructions);
3772 free(source_order_bundles
);
3774 /* Report the very first tag executed */
3775 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3777 /* Deal with off-by-one related to the fencepost problem */
3778 program
->work_register_count
= ctx
->work_registers
+ 1;
3780 program
->can_discard
= ctx
->can_discard
;
3781 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3783 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3785 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3786 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);