2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 /* Successors: always one forward (the block after us), maybe
173 * one backwards (for a backward branch). No need for a second
174 * forward, since graph traversal would get there eventually
176 struct midgard_block
*successors
[2];
177 unsigned nr_successors
;
179 /* The successors pointer form a graph, and in the case of
180 * complex control flow, this graph has a cycles. To aid
181 * traversal during liveness analysis, we have a visited?
182 * boolean for passes to use as they see fit, provided they
188 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
190 block
->successors
[block
->nr_successors
++] = successor
;
191 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
194 /* Helpers to generate midgard_instruction's using macro magic, since every
195 * driver seems to do it that way */
197 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
198 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
200 #define M_LOAD_STORE(name, rname, uname) \
201 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
202 midgard_instruction i = { \
203 .type = TAG_LOAD_STORE_4, \
210 .op = midgard_op_##name, \
212 .swizzle = SWIZZLE_XYZW, \
220 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
221 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
223 const midgard_vector_alu_src blank_alu_src
= {
224 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
227 const midgard_vector_alu_src blank_alu_src_xxxx
= {
228 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
231 const midgard_scalar_alu_src blank_scalar_alu_src
= {
235 /* Used for encoding the unused source of 1-op instructions */
236 const midgard_vector_alu_src zero_alu_src
= { 0 };
238 /* Coerce structs to integer */
241 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
244 memcpy(&u
, &src
, sizeof(src
));
248 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
249 * the corresponding Midgard source */
251 static midgard_vector_alu_src
252 vector_alu_modifiers(nir_alu_src
*src
)
254 if (!src
) return blank_alu_src
;
256 midgard_vector_alu_src alu_src
= {
258 .negate
= src
->negate
,
261 .half
= 0, /* TODO */
262 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
268 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
270 static midgard_instruction
271 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
273 midgard_instruction ins
= {
276 .src0
= SSA_UNUSED_1
,
281 .op
= midgard_alu_op_fmov
,
282 .reg_mode
= midgard_reg_mode_full
,
283 .dest_override
= midgard_dest_override_none
,
285 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
286 .src2
= vector_alu_srco_unsigned(mod
)
293 /* load/store instructions have both 32-bit and 16-bit variants, depending on
294 * whether we are using vectors composed of highp or mediump. At the moment, we
295 * don't support half-floats -- this requires changes in other parts of the
296 * compiler -- therefore the 16-bit versions are commented out. */
298 //M_LOAD(load_attr_16);
299 M_LOAD(load_attr_32
);
300 //M_LOAD(load_vary_16);
301 M_LOAD(load_vary_32
);
302 //M_LOAD(load_uniform_16);
303 M_LOAD(load_uniform_32
);
304 M_LOAD(load_color_buffer_8
);
305 //M_STORE(store_vary_16);
306 M_STORE(store_vary_32
);
307 M_STORE(store_cubemap_coords
);
309 static midgard_instruction
310 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
312 midgard_branch_cond branch
= {
320 memcpy(&compact
, &branch
, sizeof(branch
));
322 midgard_instruction ins
= {
324 .unit
= ALU_ENAB_BR_COMPACT
,
325 .prepacked_branch
= true,
326 .compact_branch
= true,
327 .br_compact
= compact
330 if (op
== midgard_jmp_writeout_op_writeout
)
336 static midgard_instruction
337 v_branch(bool conditional
, bool invert
)
339 midgard_instruction ins
= {
341 .unit
= ALU_ENAB_BRANCH
,
342 .compact_branch
= true,
344 .conditional
= conditional
,
345 .invert_conditional
= invert
352 static midgard_branch_extended
353 midgard_create_branch_extended( midgard_condition cond
,
354 midgard_jmp_writeout_op op
,
356 signed quadword_offset
)
358 /* For unclear reasons, the condition code is repeated 8 times */
359 uint16_t duplicated_cond
=
369 midgard_branch_extended branch
= {
371 .dest_tag
= dest_tag
,
372 .offset
= quadword_offset
,
373 .cond
= duplicated_cond
379 typedef struct midgard_bundle
{
380 /* Tag for the overall bundle */
383 /* Instructions contained by the bundle */
384 int instruction_count
;
385 midgard_instruction instructions
[5];
387 /* Bundle-wide ALU configuration */
390 bool has_embedded_constants
;
392 bool has_blend_constant
;
394 uint16_t register_words
[8];
395 int register_words_count
;
397 uint64_t body_words
[8];
399 int body_words_count
;
402 typedef struct compiler_context
{
404 gl_shader_stage stage
;
406 /* Is internally a blend shader? Depends on stage == FRAGMENT */
409 /* Tracking for blend constant patching */
410 int blend_constant_number
;
411 int blend_constant_offset
;
413 /* Current NIR function */
416 /* Unordered list of midgard_blocks */
418 struct list_head blocks
;
420 midgard_block
*initial_block
;
421 midgard_block
*previous_source_block
;
422 midgard_block
*final_block
;
424 /* List of midgard_instructions emitted for the current block */
425 midgard_block
*current_block
;
427 /* The index corresponding to the current loop, e.g. for breaks/contineus */
430 /* Constants which have been loaded, for later inlining */
431 struct hash_table_u64
*ssa_constants
;
433 /* SSA indices to be outputted to corresponding varying offset */
434 struct hash_table_u64
*ssa_varyings
;
436 /* SSA values / registers which have been aliased. Naively, these
437 * demand a fmov output; instead, we alias them in a later pass to
438 * avoid the wasted op.
440 * A note on encoding: to avoid dynamic memory management here, rather
441 * than ampping to a pointer, we map to the source index; the key
442 * itself is just the destination index. */
444 struct hash_table_u64
*ssa_to_alias
;
445 struct set
*leftover_ssa_to_alias
;
447 /* Actual SSA-to-register for RA */
448 struct hash_table_u64
*ssa_to_register
;
450 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
451 struct hash_table_u64
*hash_to_temp
;
455 /* Just the count of the max register used. Higher count => higher
456 * register pressure */
459 /* Used for cont/last hinting. Increase when a tex op is added.
460 * Decrease when a tex op is removed. */
461 int texture_op_count
;
463 /* Mapping of texture register -> SSA index for unaliasing */
464 int texture_index
[2];
466 /* If any path hits a discard instruction */
469 /* The number of uniforms allowable for the fast path */
472 /* Count of instructions emitted from NIR overall, across all blocks */
473 int instruction_count
;
475 /* Alpha ref value passed in */
478 /* The index corresponding to the fragment output */
479 unsigned fragment_output
;
481 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
482 unsigned sysvals
[MAX_SYSVAL_COUNT
];
483 unsigned sysval_count
;
484 struct hash_table_u64
*sysval_to_id
;
487 /* Append instruction to end of current block */
489 static midgard_instruction
*
490 mir_upload_ins(struct midgard_instruction ins
)
492 midgard_instruction
*heap
= malloc(sizeof(ins
));
493 memcpy(heap
, &ins
, sizeof(ins
));
498 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
500 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
504 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
506 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
510 mir_remove_instruction(struct midgard_instruction
*ins
)
512 list_del(&ins
->link
);
515 static midgard_instruction
*
516 mir_prev_op(struct midgard_instruction
*ins
)
518 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
521 static midgard_instruction
*
522 mir_next_op(struct midgard_instruction
*ins
)
524 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
527 static midgard_block
*
528 mir_next_block(struct midgard_block
*blk
)
530 return list_first_entry(&(blk
->link
), midgard_block
, link
);
534 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
535 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
537 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
538 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
539 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
540 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
541 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
542 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
545 static midgard_instruction
*
546 mir_last_in_block(struct midgard_block
*block
)
548 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
551 static midgard_block
*
552 mir_get_block(compiler_context
*ctx
, int idx
)
554 struct list_head
*lst
= &ctx
->blocks
;
559 return (struct midgard_block
*) lst
;
562 /* Pretty printer for internal Midgard IR */
565 print_mir_source(int source
)
567 if (source
>= SSA_FIXED_MINIMUM
) {
568 /* Specific register */
569 int reg
= SSA_REG_FROM_FIXED(source
);
571 /* TODO: Moving threshold */
572 if (reg
> 16 && reg
< 24)
573 printf("u%d", 23 - reg
);
577 printf("%d", source
);
582 print_mir_instruction(midgard_instruction
*ins
)
588 midgard_alu_op op
= ins
->alu
.op
;
589 const char *name
= alu_opcode_names
[op
];
592 printf("%d.", ins
->unit
);
594 printf("%s", name
? name
: "??");
598 case TAG_LOAD_STORE_4
: {
599 midgard_load_store_op op
= ins
->load_store
.op
;
600 const char *name
= load_store_opcode_names
[op
];
607 case TAG_TEXTURE_4
: {
616 ssa_args
*args
= &ins
->ssa_args
;
618 printf(" %d, ", args
->dest
);
620 print_mir_source(args
->src0
);
623 if (args
->inline_constant
)
624 printf("#%d", ins
->inline_constant
);
626 print_mir_source(args
->src1
);
628 if (ins
->has_constants
)
629 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
635 print_mir_block(midgard_block
*block
)
639 mir_foreach_instr_in_block(block
, ins
) {
640 print_mir_instruction(ins
);
649 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
651 ins
->has_constants
= true;
652 memcpy(&ins
->constants
, constants
, 16);
654 /* If this is the special blend constant, mark this instruction */
656 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
657 ins
->has_blend_constant
= true;
661 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
663 return glsl_count_attribute_slots(type
, false);
666 /* Lower fdot2 to a vector multiplication followed by channel addition */
668 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
670 if (alu
->op
!= nir_op_fdot2
)
673 b
->cursor
= nir_before_instr(&alu
->instr
);
675 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
676 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
678 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
680 nir_ssa_def
*sum
= nir_fadd(b
,
681 nir_channel(b
, product
, 0),
682 nir_channel(b
, product
, 1));
684 /* Replace the fdot2 with this sum */
685 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
689 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
691 switch (instr
->intrinsic
) {
692 case nir_intrinsic_load_viewport_scale
:
693 return PAN_SYSVAL_VIEWPORT_SCALE
;
694 case nir_intrinsic_load_viewport_offset
:
695 return PAN_SYSVAL_VIEWPORT_OFFSET
;
702 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
706 if (instr
->type
== nir_instr_type_intrinsic
) {
707 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
708 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
714 /* We have a sysval load; check if it's already been assigned */
716 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
719 /* It hasn't -- so assign it now! */
721 unsigned id
= ctx
->sysval_count
++;
722 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
723 ctx
->sysvals
[id
] = sysval
;
727 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
729 ctx
->sysval_count
= 0;
731 nir_foreach_function(function
, shader
) {
732 if (!function
->impl
) continue;
734 nir_foreach_block(block
, function
->impl
) {
735 nir_foreach_instr_safe(instr
, block
) {
736 midgard_nir_assign_sysval_body(ctx
, instr
);
743 midgard_nir_lower_fdot2(nir_shader
*shader
)
745 bool progress
= false;
747 nir_foreach_function(function
, shader
) {
748 if (!function
->impl
) continue;
751 nir_builder
*b
= &_b
;
752 nir_builder_init(b
, function
->impl
);
754 nir_foreach_block(block
, function
->impl
) {
755 nir_foreach_instr_safe(instr
, block
) {
756 if (instr
->type
!= nir_instr_type_alu
) continue;
758 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
759 midgard_nir_lower_fdot2_body(b
, alu
);
765 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
773 optimise_nir(nir_shader
*nir
)
777 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
778 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
780 nir_lower_tex_options lower_tex_options
= {
784 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
789 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
790 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
792 NIR_PASS(progress
, nir
, nir_copy_prop
);
793 NIR_PASS(progress
, nir
, nir_opt_dce
);
794 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
795 NIR_PASS(progress
, nir
, nir_opt_cse
);
796 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
797 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
798 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
799 NIR_PASS(progress
, nir
, nir_opt_undef
);
800 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
803 nir_var_function_temp
);
805 /* TODO: Enable vectorize when merged upstream */
806 // NIR_PASS(progress, nir, nir_opt_vectorize);
809 /* Must be run at the end to prevent creation of fsin/fcos ops */
810 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
815 NIR_PASS(progress
, nir
, nir_opt_dce
);
816 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
817 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
818 NIR_PASS(progress
, nir
, nir_copy_prop
);
821 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
822 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
824 /* Lower mods for float ops only. Integer ops don't support modifiers
825 * (saturate doesn't make sense on integers, neg/abs require dedicated
828 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
829 NIR_PASS(progress
, nir
, nir_copy_prop
);
830 NIR_PASS(progress
, nir
, nir_opt_dce
);
832 /* We implement booleans as 32-bit 0/~0 */
833 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
835 /* Take us out of SSA */
836 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
837 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
839 /* We are a vector architecture; write combine where possible */
840 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
841 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
843 NIR_PASS(progress
, nir
, nir_opt_dce
);
846 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
847 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
848 * r0. See the comments in compiler_context */
851 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
853 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
854 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
857 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
860 unalias_ssa(compiler_context
*ctx
, int dest
)
862 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
863 /* TODO: Remove from leftover or no? */
867 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
869 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
873 midgard_is_pinned(compiler_context
*ctx
, int index
)
875 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
878 /* Do not actually emit a load; instead, cache the constant for inlining */
881 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
883 nir_ssa_def def
= instr
->def
;
885 float *v
= ralloc_array(NULL
, float, 4);
886 nir_const_load_to_arr(v
, instr
, f32
);
887 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
890 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
894 expand_writemask(unsigned mask
)
898 for (int i
= 0; i
< 4; ++i
)
906 squeeze_writemask(unsigned mask
)
910 for (int i
= 0; i
< 4; ++i
)
911 if (mask
& (3 << (2 * i
)))
918 /* Determines effective writemask, taking quirks and expansion into account */
920 effective_writemask(midgard_vector_alu
*alu
)
922 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
925 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
927 /* If there is a fixed channel count, construct the appropriate mask */
930 return (1 << channel_count
) - 1;
932 /* Otherwise, just squeeze the existing mask */
933 return squeeze_writemask(alu
->mask
);
937 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
939 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
942 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
947 /* If no temp is find, allocate one */
948 temp
= ctx
->temp_count
++;
949 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
951 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
957 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
960 return src
->ssa
->index
;
962 assert(!src
->reg
.indirect
);
963 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
968 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
971 return dst
->ssa
.index
;
973 assert(!dst
->reg
.indirect
);
974 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
979 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
981 return nir_src_index(ctx
, &src
->src
);
984 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
985 * a conditional test) into that register */
988 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
990 int condition
= nir_src_index(ctx
, src
);
992 /* Source to swizzle the desired component into w */
994 const midgard_vector_alu_src alu_src
= {
995 .swizzle
= SWIZZLE(component
, component
, component
, component
),
998 /* There is no boolean move instruction. Instead, we simulate a move by
999 * ANDing the condition with itself to get it into r31.w */
1001 midgard_instruction ins
= {
1003 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
1007 .dest
= SSA_FIXED_REGISTER(31),
1010 .op
= midgard_alu_op_iand
,
1011 .reg_mode
= midgard_reg_mode_full
,
1012 .dest_override
= midgard_dest_override_none
,
1013 .mask
= (0x3 << 6), /* w */
1014 .src1
= vector_alu_srco_unsigned(alu_src
),
1015 .src2
= vector_alu_srco_unsigned(alu_src
)
1019 emit_mir_instruction(ctx
, ins
);
1022 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1023 * pinning to eliminate this move in all known cases */
1026 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1028 int offset
= nir_src_index(ctx
, src
);
1030 midgard_instruction ins
= {
1033 .src0
= SSA_UNUSED_1
,
1035 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1038 .op
= midgard_alu_op_imov
,
1039 .reg_mode
= midgard_reg_mode_full
,
1040 .dest_override
= midgard_dest_override_none
,
1041 .mask
= (0x3 << 6), /* w */
1042 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1043 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1047 emit_mir_instruction(ctx
, ins
);
1050 #define ALU_CASE(nir, _op) \
1051 case nir_op_##nir: \
1052 op = midgard_alu_op_##_op; \
1056 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1058 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1060 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1061 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1062 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1064 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1065 * supported. A few do not and are commented for now. Also, there are a
1066 * number of NIR ops which Midgard does not support and need to be
1067 * lowered, also TODO. This switch block emits the opcode and calling
1068 * convention of the Midgard instruction; actual packing is done in
1073 switch (instr
->op
) {
1074 ALU_CASE(fadd
, fadd
);
1075 ALU_CASE(fmul
, fmul
);
1076 ALU_CASE(fmin
, fmin
);
1077 ALU_CASE(fmax
, fmax
);
1078 ALU_CASE(imin
, imin
);
1079 ALU_CASE(imax
, imax
);
1080 ALU_CASE(umin
, umin
);
1081 ALU_CASE(umax
, umax
);
1082 ALU_CASE(fmov
, fmov
);
1083 ALU_CASE(ffloor
, ffloor
);
1084 ALU_CASE(fround_even
, froundeven
);
1085 ALU_CASE(ftrunc
, ftrunc
);
1086 ALU_CASE(fceil
, fceil
);
1087 ALU_CASE(fdot3
, fdot3
);
1088 ALU_CASE(fdot4
, fdot4
);
1089 ALU_CASE(iadd
, iadd
);
1090 ALU_CASE(isub
, isub
);
1091 ALU_CASE(imul
, imul
);
1092 ALU_CASE(iabs
, iabs
);
1094 /* XXX: Use fmov, not imov, since imov was causing major
1095 * issues with texture precision? XXX research */
1096 ALU_CASE(imov
, fmov
);
1098 ALU_CASE(feq32
, feq
);
1099 ALU_CASE(fne32
, fne
);
1100 ALU_CASE(flt32
, flt
);
1101 ALU_CASE(ieq32
, ieq
);
1102 ALU_CASE(ine32
, ine
);
1103 ALU_CASE(ilt32
, ilt
);
1104 ALU_CASE(ult32
, ult
);
1106 /* We don't have a native b2f32 instruction. Instead, like many
1107 * GPUs, we exploit booleans as 0/~0 for false/true, and
1108 * correspondingly AND
1109 * by 1.0 to do the type conversion. For the moment, prime us
1112 * iand [whatever], #0
1114 * At the end of emit_alu (as MIR), we'll fix-up the constant
1117 ALU_CASE(b2f32
, iand
);
1118 ALU_CASE(b2i32
, iand
);
1120 /* Likewise, we don't have a dedicated f2b32 instruction, but
1121 * we can do a "not equal to 0.0" test. */
1123 ALU_CASE(f2b32
, fne
);
1124 ALU_CASE(i2b32
, ine
);
1126 ALU_CASE(frcp
, frcp
);
1127 ALU_CASE(frsq
, frsqrt
);
1128 ALU_CASE(fsqrt
, fsqrt
);
1129 ALU_CASE(fexp2
, fexp2
);
1130 ALU_CASE(flog2
, flog2
);
1132 ALU_CASE(f2i32
, f2i
);
1133 ALU_CASE(f2u32
, f2u
);
1134 ALU_CASE(i2f32
, i2f
);
1135 ALU_CASE(u2f32
, u2f
);
1137 ALU_CASE(fsin
, fsin
);
1138 ALU_CASE(fcos
, fcos
);
1140 ALU_CASE(iand
, iand
);
1142 ALU_CASE(ixor
, ixor
);
1143 ALU_CASE(inot
, inot
);
1144 ALU_CASE(ishl
, ishl
);
1145 ALU_CASE(ishr
, iasr
);
1146 ALU_CASE(ushr
, ilsr
);
1148 ALU_CASE(b32all_fequal2
, fball_eq
);
1149 ALU_CASE(b32all_fequal3
, fball_eq
);
1150 ALU_CASE(b32all_fequal4
, fball_eq
);
1152 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1153 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1154 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1156 ALU_CASE(b32all_iequal2
, iball_eq
);
1157 ALU_CASE(b32all_iequal3
, iball_eq
);
1158 ALU_CASE(b32all_iequal4
, iball_eq
);
1160 ALU_CASE(b32any_inequal2
, ibany_neq
);
1161 ALU_CASE(b32any_inequal3
, ibany_neq
);
1162 ALU_CASE(b32any_inequal4
, ibany_neq
);
1164 /* For greater-or-equal, we lower to less-or-equal and flip the
1170 case nir_op_uge32
: {
1172 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1173 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1174 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1175 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1178 /* Swap via temporary */
1179 nir_alu_src temp
= instr
->src
[1];
1180 instr
->src
[1] = instr
->src
[0];
1181 instr
->src
[0] = temp
;
1186 case nir_op_b32csel
: {
1187 op
= midgard_alu_op_fcsel
;
1189 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1192 /* Figure out which component the condition is in */
1194 unsigned comp
= instr
->src
[0].swizzle
[0];
1196 /* Make sure NIR isn't throwing a mixed condition at us */
1198 for (unsigned c
= 1; c
< nr_components
; ++c
)
1199 assert(instr
->src
[0].swizzle
[c
] == comp
);
1201 /* Emit the condition into r31.w */
1202 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1204 /* The condition is the first argument; move the other
1205 * arguments up one to be a binary instruction for
1208 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1213 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1218 /* Fetch unit, quirks, etc information */
1219 unsigned opcode_props
= alu_opcode_props
[op
];
1220 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1222 /* Initialise fields common between scalar/vector instructions */
1223 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1225 /* src0 will always exist afaik, but src1 will not for 1-argument
1226 * instructions. The latter can only be fetched if the instruction
1227 * needs it, or else we may segfault. */
1229 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1230 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1232 /* Rather than use the instruction generation helpers, we do it
1233 * ourselves here to avoid the mess */
1235 midgard_instruction ins
= {
1238 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1239 .src1
= quirk_flipped_r24
? src0
: src1
,
1244 nir_alu_src
*nirmods
[2] = { NULL
};
1246 if (nr_inputs
== 2) {
1247 nirmods
[0] = &instr
->src
[0];
1248 nirmods
[1] = &instr
->src
[1];
1249 } else if (nr_inputs
== 1) {
1250 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1255 midgard_vector_alu alu
= {
1257 .reg_mode
= midgard_reg_mode_full
,
1258 .dest_override
= midgard_dest_override_none
,
1261 /* Writemask only valid for non-SSA NIR */
1262 .mask
= expand_writemask((1 << nr_components
) - 1),
1264 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1265 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1268 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1271 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1275 /* Late fixup for emulated instructions */
1277 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1278 /* Presently, our second argument is an inline #0 constant.
1279 * Switch over to an embedded 1.0 constant (that can't fit
1280 * inline, since we're 32-bit, not 16-bit like the inline
1283 ins
.ssa_args
.inline_constant
= false;
1284 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1285 ins
.has_constants
= true;
1287 if (instr
->op
== nir_op_b2f32
) {
1288 ins
.constants
[0] = 1.0f
;
1290 /* Type pun it into place */
1292 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1295 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1296 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1297 ins
.ssa_args
.inline_constant
= false;
1298 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1299 ins
.has_constants
= true;
1300 ins
.constants
[0] = 0.0f
;
1301 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1304 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1305 /* To avoid duplicating the lookup tables (probably), true LUT
1306 * instructions can only operate as if they were scalars. Lower
1307 * them here by changing the component. */
1309 uint8_t original_swizzle
[4];
1310 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1312 for (int i
= 0; i
< nr_components
; ++i
) {
1313 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1315 for (int j
= 0; j
< 4; ++j
)
1316 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1318 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1319 emit_mir_instruction(ctx
, ins
);
1322 emit_mir_instruction(ctx
, ins
);
1329 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1331 /* TODO: half-floats */
1333 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1334 /* Fast path: For the first 16 uniforms, direct accesses are
1335 * 0-cycle, since they're just a register fetch in the usual
1336 * case. So, we alias the registers while we're still in
1339 int reg_slot
= 23 - offset
;
1340 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1342 /* Otherwise, read from the 'special' UBO to access
1343 * higher-indexed uniforms, at a performance cost. More
1344 * generally, we're emitting a UBO read instruction. */
1346 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1348 /* TODO: Don't split */
1349 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1350 ins
.load_store
.address
= offset
>> 3;
1352 if (indirect_offset
) {
1353 emit_indirect_offset(ctx
, indirect_offset
);
1354 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1356 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1359 emit_mir_instruction(ctx
, ins
);
1364 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1366 /* First, pull out the destination */
1367 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1369 /* Now, figure out which uniform this is */
1370 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1371 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1373 /* Sysvals are prefix uniforms */
1374 unsigned uniform
= ((uintptr_t) val
) - 1;
1376 /* Emit the read itself -- this is never indirect */
1377 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1381 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1383 unsigned offset
, reg
;
1385 switch (instr
->intrinsic
) {
1386 case nir_intrinsic_discard_if
:
1387 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1391 case nir_intrinsic_discard
: {
1392 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1393 struct midgard_instruction discard
= v_branch(conditional
, false);
1394 discard
.branch
.target_type
= TARGET_DISCARD
;
1395 emit_mir_instruction(ctx
, discard
);
1397 ctx
->can_discard
= true;
1401 case nir_intrinsic_load_uniform
:
1402 case nir_intrinsic_load_input
:
1403 offset
= nir_intrinsic_base(instr
);
1405 bool direct
= nir_src_is_const(instr
->src
[0]);
1408 offset
+= nir_src_as_uint(instr
->src
[0]);
1411 reg
= nir_dest_index(ctx
, &instr
->dest
);
1413 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1414 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1415 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1416 /* XXX: Half-floats? */
1417 /* TODO: swizzle, mask */
1419 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1421 midgard_varying_parameter p
= {
1423 .interpolation
= midgard_interp_default
,
1424 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1428 memcpy(&u
, &p
, sizeof(p
));
1429 ins
.load_store
.varying_parameters
= u
;
1432 /* We have the offset totally ready */
1433 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1435 /* We have it partially ready, but we need to
1436 * add in the dynamic index, moved to r27.w */
1437 emit_indirect_offset(ctx
, &instr
->src
[0]);
1438 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1441 emit_mir_instruction(ctx
, ins
);
1442 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1443 /* Constant encoded as a pinned constant */
1445 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1446 ins
.has_constants
= true;
1447 ins
.has_blend_constant
= true;
1448 emit_mir_instruction(ctx
, ins
);
1449 } else if (ctx
->is_blend
) {
1450 /* For blend shaders, a load might be
1451 * translated various ways depending on what
1452 * we're loading. Figure out how this is used */
1454 nir_variable
*out
= NULL
;
1456 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1457 int drvloc
= var
->data
.driver_location
;
1459 if (nir_intrinsic_base(instr
) == drvloc
) {
1467 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1468 /* Source color preloaded to r0 */
1470 midgard_pin_output(ctx
, reg
, 0);
1471 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1472 /* Destination color must be read from framebuffer */
1474 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1475 ins
.load_store
.swizzle
= 0; /* xxxx */
1477 /* Read each component sequentially */
1479 for (int c
= 0; c
< 4; ++c
) {
1480 ins
.load_store
.mask
= (1 << c
);
1481 ins
.load_store
.unknown
= c
;
1482 emit_mir_instruction(ctx
, ins
);
1485 /* vadd.u2f hr2, abs(hr2), #0 */
1487 midgard_vector_alu_src alu_src
= blank_alu_src
;
1489 alu_src
.half
= true;
1491 midgard_instruction u2f
= {
1495 .src1
= SSA_UNUSED_0
,
1497 .inline_constant
= true
1500 .op
= midgard_alu_op_u2f
,
1501 .reg_mode
= midgard_reg_mode_half
,
1502 .dest_override
= midgard_dest_override_none
,
1504 .src1
= vector_alu_srco_unsigned(alu_src
),
1505 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1509 emit_mir_instruction(ctx
, u2f
);
1511 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1513 alu_src
.abs
= false;
1515 midgard_instruction fmul
= {
1517 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1521 .src1
= SSA_UNUSED_0
,
1522 .inline_constant
= true
1525 .op
= midgard_alu_op_fmul
,
1526 .reg_mode
= midgard_reg_mode_full
,
1527 .dest_override
= midgard_dest_override_none
,
1528 .outmod
= midgard_outmod_sat
,
1530 .src1
= vector_alu_srco_unsigned(alu_src
),
1531 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1535 emit_mir_instruction(ctx
, fmul
);
1537 DBG("Unknown input in blend shader\n");
1540 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1541 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1542 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1543 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1544 emit_mir_instruction(ctx
, ins
);
1546 DBG("Unknown load\n");
1552 case nir_intrinsic_store_output
:
1553 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1555 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1557 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1559 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1560 /* gl_FragColor is not emitted with load/store
1561 * instructions. Instead, it gets plonked into
1562 * r0 at the end of the shader and we do the
1563 * framebuffer writeout dance. TODO: Defer
1566 midgard_pin_output(ctx
, reg
, 0);
1568 /* Save the index we're writing to for later reference
1569 * in the epilogue */
1571 ctx
->fragment_output
= reg
;
1572 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1573 /* Varyings are written into one of two special
1574 * varying register, r26 or r27. The register itself is selected as the register
1575 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1577 * Normally emitting fmov's is frowned upon,
1578 * but due to unique constraints of
1579 * REGISTER_VARYING, fmov emission + a
1580 * dedicated cleanup pass is the only way to
1581 * guarantee correctness when considering some
1582 * (common) edge cases XXX: FIXME */
1584 /* If this varying corresponds to a constant (why?!),
1585 * emit that now since it won't get picked up by
1586 * hoisting (since there is no corresponding move
1587 * emitted otherwise) */
1589 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1591 if (constant_value
) {
1592 /* Special case: emit the varying write
1593 * directly to r26 (looks funny in asm but it's
1594 * fine) and emit the store _now_. Possibly
1595 * slightly slower, but this is a really stupid
1596 * special case anyway (why on earth would you
1597 * have a constant varying? Your own fault for
1598 * slightly worse perf :P) */
1600 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1601 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1602 emit_mir_instruction(ctx
, ins
);
1604 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1605 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1606 emit_mir_instruction(ctx
, st
);
1608 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1610 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1613 DBG("Unknown store\n");
1619 case nir_intrinsic_load_alpha_ref_float
:
1620 assert(instr
->dest
.is_ssa
);
1622 float ref_value
= ctx
->alpha_ref
;
1624 float *v
= ralloc_array(NULL
, float, 4);
1625 memcpy(v
, &ref_value
, sizeof(float));
1626 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1629 case nir_intrinsic_load_viewport_scale
:
1630 case nir_intrinsic_load_viewport_offset
:
1631 emit_sysval_read(ctx
, instr
);
1635 printf ("Unhandled intrinsic\n");
1642 midgard_tex_format(enum glsl_sampler_dim dim
)
1645 case GLSL_SAMPLER_DIM_2D
:
1646 case GLSL_SAMPLER_DIM_EXTERNAL
:
1649 case GLSL_SAMPLER_DIM_3D
:
1652 case GLSL_SAMPLER_DIM_CUBE
:
1653 return TEXTURE_CUBE
;
1656 DBG("Unknown sampler dim type\n");
1663 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1666 //assert (!instr->sampler);
1667 //assert (!instr->texture_array_size);
1668 assert (instr
->op
== nir_texop_tex
);
1670 /* Allocate registers via a round robin scheme to alternate between the two registers */
1671 int reg
= ctx
->texture_op_count
& 1;
1672 int in_reg
= reg
, out_reg
= reg
;
1674 /* Make room for the reg */
1676 if (ctx
->texture_index
[reg
] > -1)
1677 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1679 int texture_index
= instr
->texture_index
;
1680 int sampler_index
= texture_index
;
1682 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1683 switch (instr
->src
[i
].src_type
) {
1684 case nir_tex_src_coord
: {
1685 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1687 midgard_vector_alu_src alu_src
= blank_alu_src
;
1689 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1691 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1692 /* For cubemaps, we need to load coords into
1693 * special r27, and then use a special ld/st op
1694 * to copy into the texture register */
1696 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1698 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1699 emit_mir_instruction(ctx
, move
);
1701 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1702 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1703 st
.load_store
.mask
= 0x3; /* xy? */
1704 st
.load_store
.swizzle
= alu_src
.swizzle
;
1705 emit_mir_instruction(ctx
, st
);
1708 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1710 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1711 emit_mir_instruction(ctx
, ins
);
1714 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1720 DBG("Unknown source type\n");
1727 /* No helper to build texture words -- we do it all here */
1728 midgard_instruction ins
= {
1729 .type
= TAG_TEXTURE_4
,
1731 .op
= TEXTURE_OP_NORMAL
,
1732 .format
= midgard_tex_format(instr
->sampler_dim
),
1733 .texture_handle
= texture_index
,
1734 .sampler_handle
= sampler_index
,
1736 /* TODO: Don't force xyzw */
1737 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1749 /* Assume we can continue; hint it out later */
1754 /* Set registers to read and write from the same place */
1755 ins
.texture
.in_reg_select
= in_reg
;
1756 ins
.texture
.out_reg_select
= out_reg
;
1758 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1759 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1760 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1761 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1762 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1764 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1765 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1766 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1769 emit_mir_instruction(ctx
, ins
);
1771 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1773 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1774 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1775 ctx
->texture_index
[reg
] = o_index
;
1777 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1778 emit_mir_instruction(ctx
, ins2
);
1780 /* Used for .cont and .last hinting */
1781 ctx
->texture_op_count
++;
1785 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1787 switch (instr
->type
) {
1788 case nir_jump_break
: {
1789 /* Emit a branch out of the loop */
1790 struct midgard_instruction br
= v_branch(false, false);
1791 br
.branch
.target_type
= TARGET_BREAK
;
1792 br
.branch
.target_break
= ctx
->current_loop
;
1793 emit_mir_instruction(ctx
, br
);
1800 DBG("Unknown jump type %d\n", instr
->type
);
1806 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1808 switch (instr
->type
) {
1809 case nir_instr_type_load_const
:
1810 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1813 case nir_instr_type_intrinsic
:
1814 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1817 case nir_instr_type_alu
:
1818 emit_alu(ctx
, nir_instr_as_alu(instr
));
1821 case nir_instr_type_tex
:
1822 emit_tex(ctx
, nir_instr_as_tex(instr
));
1825 case nir_instr_type_jump
:
1826 emit_jump(ctx
, nir_instr_as_jump(instr
));
1829 case nir_instr_type_ssa_undef
:
1834 DBG("Unhandled instruction type\n");
1839 /* Determine the actual hardware from the index based on the RA results or special values */
1842 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1844 if (reg
>= SSA_FIXED_MINIMUM
)
1845 return SSA_REG_FROM_FIXED(reg
);
1848 assert(reg
< maxreg
);
1849 int r
= ra_get_node_reg(g
, reg
);
1850 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1855 /* fmov style unused */
1857 return REGISTER_UNUSED
;
1859 /* lut style unused */
1861 return REGISTER_UNUSED
;
1864 DBG("Unknown SSA register alias %d\n", reg
);
1871 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1873 /* Choose the first available register to minimise reported register pressure */
1875 for (int i
= 0; i
< 16; ++i
) {
1876 if (BITSET_TEST(regs
, i
)) {
1886 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1888 if (ins
->ssa_args
.src0
== src
) return true;
1889 if (ins
->ssa_args
.src1
== src
) return true;
1894 /* Determine if a variable is live in the successors of a block */
1896 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
1898 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
1899 midgard_block
*succ
= bl
->successors
[i
];
1901 /* If we already visited, the value we're seeking
1902 * isn't down this path (or we would have short
1905 if (succ
->visited
) continue;
1907 /* Otherwise (it's visited *now*), check the block */
1909 succ
->visited
= true;
1911 mir_foreach_instr_in_block(succ
, ins
) {
1912 if (midgard_is_live_in_instr(ins
, src
))
1916 /* ...and also, check *its* successors */
1917 if (is_live_after_successors(ctx
, succ
, src
))
1922 /* Welp. We're really not live. */
1928 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1930 /* Check the rest of the block for liveness */
1932 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1933 if (midgard_is_live_in_instr(ins
, src
))
1937 /* Check the rest of the blocks for liveness recursively */
1939 bool succ
= is_live_after_successors(ctx
, block
, src
);
1941 mir_foreach_block(ctx
, block
) {
1942 block
->visited
= false;
1949 allocate_registers(compiler_context
*ctx
)
1951 /* First, initialize the RA */
1952 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1954 /* Create a primary (general purpose) class, as well as special purpose
1955 * pipeline register classes */
1957 int primary_class
= ra_alloc_reg_class(regs
);
1958 int varying_class
= ra_alloc_reg_class(regs
);
1960 /* Add the full set of work registers */
1961 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1962 for (int i
= 0; i
< work_count
; ++i
)
1963 ra_class_add_reg(regs
, primary_class
, i
);
1965 /* Add special registers */
1966 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1967 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1969 /* We're done setting up */
1970 ra_set_finalize(regs
, NULL
);
1972 /* Transform the MIR into squeezed index form */
1973 mir_foreach_block(ctx
, block
) {
1974 mir_foreach_instr_in_block(block
, ins
) {
1975 if (ins
->compact_branch
) continue;
1977 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1978 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1979 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1981 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1982 print_mir_block(block
);
1985 /* Let's actually do register allocation */
1986 int nodes
= ctx
->temp_count
;
1987 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1989 /* Set everything to the work register class, unless it has somewhere
1992 mir_foreach_block(ctx
, block
) {
1993 mir_foreach_instr_in_block(block
, ins
) {
1994 if (ins
->compact_branch
) continue;
1996 if (ins
->ssa_args
.dest
< 0) continue;
1998 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2000 int class = primary_class
;
2002 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2006 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2007 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2010 unsigned reg
= temp
- 1;
2011 int t
= find_or_allocate_temp(ctx
, index
);
2012 ra_set_node_reg(g
, t
, reg
);
2016 /* Determine liveness */
2018 int *live_start
= malloc(nodes
* sizeof(int));
2019 int *live_end
= malloc(nodes
* sizeof(int));
2021 /* Initialize as non-existent */
2023 for (int i
= 0; i
< nodes
; ++i
) {
2024 live_start
[i
] = live_end
[i
] = -1;
2029 mir_foreach_block(ctx
, block
) {
2030 mir_foreach_instr_in_block(block
, ins
) {
2031 if (ins
->compact_branch
) continue;
2033 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2034 /* If this destination is not yet live, it is now since we just wrote it */
2036 int dest
= ins
->ssa_args
.dest
;
2038 if (live_start
[dest
] == -1)
2039 live_start
[dest
] = d
;
2042 /* Since we just used a source, the source might be
2043 * dead now. Scan the rest of the block for
2044 * invocations, and if there are none, the source dies
2047 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2049 for (int src
= 0; src
< 2; ++src
) {
2050 int s
= sources
[src
];
2052 if (s
< 0) continue;
2054 if (s
>= SSA_FIXED_MINIMUM
) continue;
2056 if (!is_live_after(ctx
, block
, ins
, s
)) {
2065 /* If a node still hasn't been killed, kill it now */
2067 for (int i
= 0; i
< nodes
; ++i
) {
2068 /* live_start == -1 most likely indicates a pinned output */
2070 if (live_end
[i
] == -1)
2074 /* Setup interference between nodes that are live at the same time */
2076 for (int i
= 0; i
< nodes
; ++i
) {
2077 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2078 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2079 ra_add_node_interference(g
, i
, j
);
2083 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2085 if (!ra_allocate(g
)) {
2086 DBG("Error allocating registers\n");
2094 mir_foreach_block(ctx
, block
) {
2095 mir_foreach_instr_in_block(block
, ins
) {
2096 if (ins
->compact_branch
) continue;
2098 ssa_args args
= ins
->ssa_args
;
2100 switch (ins
->type
) {
2102 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
2104 ins
->registers
.src2_imm
= args
.inline_constant
;
2106 if (args
.inline_constant
) {
2107 /* Encode inline 16-bit constant as a vector by default */
2109 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2111 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2113 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2114 ins
->alu
.src2
= imm
<< 2;
2116 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2119 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2123 case TAG_LOAD_STORE_4
: {
2124 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2125 /* TODO: use ssa_args for store_vary */
2126 ins
->load_store
.reg
= 0;
2128 bool has_dest
= args
.dest
>= 0;
2129 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2131 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2144 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2145 * use scalar ALU instructions, for functional or performance reasons. To do
2146 * this, we just demote vector ALU payloads to scalar. */
2149 component_from_mask(unsigned mask
)
2151 for (int c
= 0; c
< 4; ++c
) {
2152 if (mask
& (3 << (2 * c
)))
2161 is_single_component_mask(unsigned mask
)
2165 for (int c
= 0; c
< 4; ++c
)
2166 if (mask
& (3 << (2 * c
)))
2169 return components
== 1;
2172 /* Create a mask of accessed components from a swizzle to figure out vector
2176 swizzle_to_access_mask(unsigned swizzle
)
2178 unsigned component_mask
= 0;
2180 for (int i
= 0; i
< 4; ++i
) {
2181 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2182 component_mask
|= (1 << c
);
2185 return component_mask
;
2189 vector_to_scalar_source(unsigned u
)
2191 midgard_vector_alu_src v
;
2192 memcpy(&v
, &u
, sizeof(v
));
2194 midgard_scalar_alu_src s
= {
2198 .component
= (v
.swizzle
& 3) << 1
2202 memcpy(&o
, &s
, sizeof(s
));
2204 return o
& ((1 << 6) - 1);
2207 static midgard_scalar_alu
2208 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2210 /* The output component is from the mask */
2211 midgard_scalar_alu s
= {
2213 .src1
= vector_to_scalar_source(v
.src1
),
2214 .src2
= vector_to_scalar_source(v
.src2
),
2217 .output_full
= 1, /* TODO: Half */
2218 .output_component
= component_from_mask(v
.mask
) << 1,
2221 /* Inline constant is passed along rather than trying to extract it
2224 if (ins
->ssa_args
.inline_constant
) {
2226 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2227 imm
|= (lower_11
>> 9) & 3;
2228 imm
|= (lower_11
>> 6) & 4;
2229 imm
|= (lower_11
>> 2) & 0x38;
2230 imm
|= (lower_11
& 63) << 6;
2238 /* Midgard prefetches instruction types, so during emission we need to
2239 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2240 * if this is the second to last and the last is an ALU, then it's also 1... */
2242 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2243 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2245 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2246 bytes_emitted += sizeof(type)
2249 emit_binary_vector_instruction(midgard_instruction
*ains
,
2250 uint16_t *register_words
, int *register_words_count
,
2251 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2252 size_t *bytes_emitted
)
2254 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2255 *bytes_emitted
+= sizeof(midgard_reg_info
);
2257 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2258 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2259 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2262 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2263 * mind that we are a vector architecture and we can write to different
2264 * components simultaneously */
2267 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2269 /* Each instruction reads some registers and writes to a register. See
2270 * where the first writes */
2272 /* Figure out where exactly we wrote to */
2273 int source
= first
->ssa_args
.dest
;
2274 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2276 /* As long as the second doesn't read from the first, we're okay */
2277 if (second
->ssa_args
.src0
== source
) {
2278 if (first
->type
== TAG_ALU_4
) {
2279 /* Figure out which components we just read from */
2281 int q
= second
->alu
.src1
;
2282 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2284 /* Check if there are components in common, and fail if so */
2285 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2292 if (second
->ssa_args
.src1
== source
)
2295 /* Otherwise, it's safe in that regard. Another data hazard is both
2296 * writing to the same place, of course */
2298 if (second
->ssa_args
.dest
== source
) {
2299 /* ...but only if the components overlap */
2300 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2302 if (dest_mask
& source_mask
)
2312 midgard_instruction
**segment
, unsigned segment_size
,
2313 midgard_instruction
*ains
)
2315 for (int s
= 0; s
< segment_size
; ++s
)
2316 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2324 /* Schedules, but does not emit, a single basic block. After scheduling, the
2325 * final tag and size of the block are known, which are necessary for branching
2328 static midgard_bundle
2329 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2331 int instructions_emitted
= 0, instructions_consumed
= -1;
2332 midgard_bundle bundle
= { 0 };
2334 uint8_t tag
= ins
->type
;
2336 /* Default to the instruction's tag */
2339 switch (ins
->type
) {
2341 uint32_t control
= 0;
2342 size_t bytes_emitted
= sizeof(control
);
2344 /* TODO: Constant combining */
2345 int index
= 0, last_unit
= 0;
2347 /* Previous instructions, for the purpose of parallelism */
2348 midgard_instruction
*segment
[4] = {0};
2349 int segment_size
= 0;
2351 instructions_emitted
= -1;
2352 midgard_instruction
*pins
= ins
;
2355 midgard_instruction
*ains
= pins
;
2357 /* Advance instruction pointer */
2359 ains
= mir_next_op(pins
);
2363 /* Out-of-work condition */
2364 if ((struct list_head
*) ains
== &block
->instructions
)
2367 /* Ensure that the chain can continue */
2368 if (ains
->type
!= TAG_ALU_4
) break;
2370 /* According to the presentation "The ARM
2371 * Mali-T880 Mobile GPU" from HotChips 27,
2372 * there are two pipeline stages. Branching
2373 * position determined experimentally. Lines
2374 * are executed in parallel:
2377 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2379 * Verify that there are no ordering dependencies here.
2381 * TODO: Allow for parallelism!!!
2384 /* Pick a unit for it if it doesn't force a particular unit */
2386 int unit
= ains
->unit
;
2389 int op
= ains
->alu
.op
;
2390 int units
= alu_opcode_props
[op
];
2392 /* TODO: Promotion of scalars to vectors */
2393 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2396 assert(units
& UNITS_SCALAR
);
2399 if (last_unit
>= UNIT_VADD
) {
2400 if (units
& UNIT_VLUT
)
2405 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2407 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2409 else if (units
& UNIT_VLUT
)
2415 if (last_unit
>= UNIT_VADD
) {
2416 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2418 else if (units
& UNIT_VLUT
)
2423 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2425 else if (units
& UNIT_SMUL
)
2426 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2427 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2434 assert(unit
& units
);
2437 /* Late unit check, this time for encoding (not parallelism) */
2438 if (unit
<= last_unit
) break;
2440 /* Clear the segment */
2441 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2444 if (midgard_has_hazard(segment
, segment_size
, ains
))
2447 /* We're good to go -- emit the instruction */
2450 segment
[segment_size
++] = ains
;
2452 /* Only one set of embedded constants per
2453 * bundle possible; if we have more, we must
2454 * break the chain early, unfortunately */
2456 if (ains
->has_constants
) {
2457 if (bundle
.has_embedded_constants
) {
2458 /* ...but if there are already
2459 * constants but these are the
2460 * *same* constants, we let it
2463 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2466 bundle
.has_embedded_constants
= true;
2467 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2469 /* If this is a blend shader special constant, track it for patching */
2470 if (ains
->has_blend_constant
)
2471 bundle
.has_blend_constant
= true;
2475 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2476 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2477 &bundle
.register_words_count
, bundle
.body_words
,
2478 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2479 } else if (ains
->compact_branch
) {
2480 /* All of r0 has to be written out
2481 * along with the branch writeout.
2484 if (ains
->writeout
) {
2486 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2487 ins
.unit
= UNIT_VMUL
;
2489 control
|= ins
.unit
;
2491 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2492 &bundle
.register_words_count
, bundle
.body_words
,
2493 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2495 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2496 bool written_late
= false;
2497 bool components
[4] = { 0 };
2498 uint16_t register_dep_mask
= 0;
2499 uint16_t written_mask
= 0;
2501 midgard_instruction
*qins
= ins
;
2502 for (int t
= 0; t
< index
; ++t
) {
2503 if (qins
->registers
.out_reg
!= 0) {
2504 /* Mark down writes */
2506 written_mask
|= (1 << qins
->registers
.out_reg
);
2508 /* Mark down the register dependencies for errata check */
2510 if (qins
->registers
.src1_reg
< 16)
2511 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2513 if (qins
->registers
.src2_reg
< 16)
2514 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2516 int mask
= qins
->alu
.mask
;
2518 for (int c
= 0; c
< 4; ++c
)
2519 if (mask
& (0x3 << (2 * c
)))
2520 components
[c
] = true;
2522 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2524 if (qins
->unit
== UNIT_VLUT
)
2525 written_late
= true;
2528 /* Advance instruction pointer */
2529 qins
= mir_next_op(qins
);
2533 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2534 if (register_dep_mask
& written_mask
) {
2535 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2542 /* If even a single component is not written, break it up (conservative check). */
2543 bool breakup
= false;
2545 for (int c
= 0; c
< 4; ++c
)
2552 /* Otherwise, we're free to proceed */
2556 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2557 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2558 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2559 bytes_emitted
+= sizeof(midgard_branch_extended
);
2561 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2562 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2563 bytes_emitted
+= sizeof(ains
->br_compact
);
2566 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2567 bytes_emitted
+= sizeof(midgard_reg_info
);
2569 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2570 bundle
.body_words_count
++;
2571 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2574 /* Defer marking until after writing to allow for break */
2575 control
|= ains
->unit
;
2576 last_unit
= ains
->unit
;
2577 ++instructions_emitted
;
2581 /* Bubble up the number of instructions for skipping */
2582 instructions_consumed
= index
- 1;
2586 /* Pad ALU op to nearest word */
2588 if (bytes_emitted
& 15) {
2589 padding
= 16 - (bytes_emitted
& 15);
2590 bytes_emitted
+= padding
;
2593 /* Constants must always be quadwords */
2594 if (bundle
.has_embedded_constants
)
2595 bytes_emitted
+= 16;
2597 /* Size ALU instruction for tag */
2598 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2599 bundle
.padding
= padding
;
2600 bundle
.control
= bundle
.tag
| control
;
2605 case TAG_LOAD_STORE_4
: {
2606 /* Load store instructions have two words at once. If
2607 * we only have one queued up, we need to NOP pad.
2608 * Otherwise, we store both in succession to save space
2609 * and cycles -- letting them go in parallel -- skip
2610 * the next. The usefulness of this optimisation is
2611 * greatly dependent on the quality of the instruction
2615 midgard_instruction
*next_op
= mir_next_op(ins
);
2617 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2618 /* As the two operate concurrently, make sure
2619 * they are not dependent */
2621 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2622 /* Skip ahead, since it's redundant with the pair */
2623 instructions_consumed
= 1 + (instructions_emitted
++);
2631 /* Texture ops default to single-op-per-bundle scheduling */
2635 /* Copy the instructions into the bundle */
2636 bundle
.instruction_count
= instructions_emitted
+ 1;
2640 midgard_instruction
*uins
= ins
;
2641 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2642 bundle
.instructions
[used_idx
++] = *uins
;
2643 uins
= mir_next_op(uins
);
2646 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2652 quadword_size(int tag
)
2667 case TAG_LOAD_STORE_4
:
2679 /* Schedule a single block by iterating its instruction to create bundles.
2680 * While we go, tally about the bundle sizes to compute the block size. */
2683 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2685 util_dynarray_init(&block
->bundles
, NULL
);
2687 block
->quadword_count
= 0;
2689 mir_foreach_instr_in_block(block
, ins
) {
2691 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2692 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2694 if (bundle
.has_blend_constant
) {
2695 /* TODO: Multiblock? */
2696 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2697 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2701 ins
= mir_next_op(ins
);
2703 block
->quadword_count
+= quadword_size(bundle
.tag
);
2706 block
->is_scheduled
= true;
2710 schedule_program(compiler_context
*ctx
)
2712 allocate_registers(ctx
);
2714 mir_foreach_block(ctx
, block
) {
2715 schedule_block(ctx
, block
);
2719 /* After everything is scheduled, emit whole bundles at a time */
2722 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2724 int lookahead
= next_tag
<< 4;
2726 switch (bundle
->tag
) {
2731 /* Actually emit each component */
2732 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2734 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2735 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2737 /* Emit body words based on the instructions bundled */
2738 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2739 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2741 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2742 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2743 } else if (ins
->compact_branch
) {
2744 /* Dummy move, XXX DRY */
2745 if ((i
== 0) && ins
->writeout
) {
2746 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2747 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2750 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2751 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2753 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2757 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2758 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2762 /* Emit padding (all zero) */
2763 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2765 /* Tack on constants */
2767 if (bundle
->has_embedded_constants
) {
2768 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2769 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2770 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2771 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2777 case TAG_LOAD_STORE_4
: {
2778 /* One or two composing instructions */
2780 uint64_t current64
, next64
= LDST_NOP
;
2782 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2784 if (bundle
->instruction_count
== 2)
2785 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2787 midgard_load_store instruction
= {
2788 .type
= bundle
->tag
,
2789 .next_type
= next_tag
,
2794 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2799 case TAG_TEXTURE_4
: {
2800 /* Texture instructions are easy, since there is no
2801 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2803 midgard_instruction
*ins
= &bundle
->instructions
[0];
2805 ins
->texture
.type
= TAG_TEXTURE_4
;
2806 ins
->texture
.next_type
= next_tag
;
2808 ctx
->texture_op_count
--;
2810 if (!ctx
->texture_op_count
) {
2811 ins
->texture
.cont
= 0;
2812 ins
->texture
.last
= 1;
2815 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2820 DBG("Unknown midgard instruction type\n");
2827 /* ALU instructions can inline or embed constants, which decreases register
2828 * pressure and saves space. */
2830 #define CONDITIONAL_ATTACH(src) { \
2831 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2834 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2835 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2840 inline_alu_constants(compiler_context
*ctx
)
2842 mir_foreach_instr(ctx
, alu
) {
2843 /* Other instructions cannot inline constants */
2844 if (alu
->type
!= TAG_ALU_4
) continue;
2846 /* If there is already a constant here, we can do nothing */
2847 if (alu
->has_constants
) continue;
2849 /* It makes no sense to inline constants on a branch */
2850 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
2852 CONDITIONAL_ATTACH(src0
);
2854 if (!alu
->has_constants
) {
2855 CONDITIONAL_ATTACH(src1
)
2856 } else if (!alu
->inline_constant
) {
2857 /* Corner case: _two_ vec4 constants, for instance with a
2858 * csel. For this case, we can only use a constant
2859 * register for one, we'll have to emit a move for the
2860 * other. Note, if both arguments are constants, then
2861 * necessarily neither argument depends on the value of
2862 * any particular register. As the destination register
2863 * will be wiped, that means we can spill the constant
2864 * to the destination register.
2867 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2868 unsigned scratch
= alu
->ssa_args
.dest
;
2871 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2872 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2874 /* Force a break XXX Defer r31 writes */
2875 ins
.unit
= UNIT_VLUT
;
2877 /* Set the source */
2878 alu
->ssa_args
.src1
= scratch
;
2880 /* Inject us -before- the last instruction which set r31 */
2881 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2887 /* Midgard supports two types of constants, embedded constants (128-bit) and
2888 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2889 * constants can be demoted to inline constants, for space savings and
2890 * sometimes a performance boost */
2893 embedded_to_inline_constant(compiler_context
*ctx
)
2895 mir_foreach_instr(ctx
, ins
) {
2896 if (!ins
->has_constants
) continue;
2898 if (ins
->ssa_args
.inline_constant
) continue;
2900 /* Blend constants must not be inlined by definition */
2901 if (ins
->has_blend_constant
) continue;
2903 /* src1 cannot be an inline constant due to encoding
2904 * restrictions. So, if possible we try to flip the arguments
2907 int op
= ins
->alu
.op
;
2909 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2910 /* Flip based on op. Fallthrough intentional */
2913 /* These ops require an operational change to flip their arguments TODO */
2914 case midgard_alu_op_flt
:
2915 case midgard_alu_op_fle
:
2916 case midgard_alu_op_ilt
:
2917 case midgard_alu_op_ile
:
2918 case midgard_alu_op_fcsel
:
2919 case midgard_alu_op_icsel
:
2920 case midgard_alu_op_isub
:
2921 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2924 /* These ops are commutative and Just Flip */
2925 case midgard_alu_op_fne
:
2926 case midgard_alu_op_fadd
:
2927 case midgard_alu_op_fmul
:
2928 case midgard_alu_op_fmin
:
2929 case midgard_alu_op_fmax
:
2930 case midgard_alu_op_iadd
:
2931 case midgard_alu_op_imul
:
2932 case midgard_alu_op_feq
:
2933 case midgard_alu_op_ieq
:
2934 case midgard_alu_op_ine
:
2935 case midgard_alu_op_iand
:
2936 case midgard_alu_op_ior
:
2937 case midgard_alu_op_ixor
:
2938 /* Flip the SSA numbers */
2939 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2940 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2942 /* And flip the modifiers */
2946 src_temp
= ins
->alu
.src2
;
2947 ins
->alu
.src2
= ins
->alu
.src1
;
2948 ins
->alu
.src1
= src_temp
;
2955 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2956 /* Extract the source information */
2958 midgard_vector_alu_src
*src
;
2959 int q
= ins
->alu
.src2
;
2960 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2963 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2964 int component
= src
->swizzle
& 3;
2966 /* Scale constant appropriately, if we can legally */
2967 uint16_t scaled_constant
= 0;
2969 /* XXX: Check legality */
2970 if (midgard_is_integer_op(op
)) {
2971 /* TODO: Inline integer */
2974 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2975 scaled_constant
= (uint16_t) iconstants
[component
];
2977 /* Constant overflow after resize */
2978 if (scaled_constant
!= iconstants
[component
])
2981 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2984 /* We don't know how to handle these with a constant */
2986 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2987 DBG("Bailing inline constant...\n");
2991 /* Make sure that the constant is not itself a
2992 * vector by checking if all accessed values
2993 * (by the swizzle) are the same. */
2995 uint32_t *cons
= (uint32_t *) ins
->constants
;
2996 uint32_t value
= cons
[component
];
2998 bool is_vector
= false;
2999 unsigned mask
= effective_writemask(&ins
->alu
);
3001 for (int c
= 1; c
< 4; ++c
) {
3002 /* We only care if this component is actually used */
3003 if (!(mask
& (1 << c
)))
3006 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3008 if (test
!= value
) {
3017 /* Get rid of the embedded constant */
3018 ins
->has_constants
= false;
3019 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3020 ins
->ssa_args
.inline_constant
= true;
3021 ins
->inline_constant
= scaled_constant
;
3026 /* Map normal SSA sources to other SSA sources / fixed registers (like
3030 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3032 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3035 /* Remove entry in leftovers to avoid a redunant fmov */
3037 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3040 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3042 /* Assign the alias map */
3048 #define AS_SRC(to, u) \
3049 int q##to = ins->alu.src2; \
3050 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
3052 /* Removing unused moves is necessary to clean up the texture pipeline results.
3054 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
3057 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
3059 mir_foreach_instr_in_block_safe(block
, ins
) {
3060 if (ins
->type
!= TAG_ALU_4
) continue;
3062 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
3064 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3066 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3068 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3070 mir_remove_instruction(ins
);
3074 /* The following passes reorder MIR instructions to enable better scheduling */
3077 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3079 mir_foreach_instr_in_block_safe(block
, ins
) {
3080 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3082 /* We've found a load/store op. Check if next is also load/store. */
3083 midgard_instruction
*next_op
= mir_next_op(ins
);
3084 if (&next_op
->link
!= &block
->instructions
) {
3085 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3086 /* If so, we're done since we're a pair */
3087 ins
= mir_next_op(ins
);
3091 /* Maximum search distance to pair, to avoid register pressure disasters */
3092 int search_distance
= 8;
3094 /* Otherwise, we have an orphaned load/store -- search for another load */
3095 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3096 /* Terminate search if necessary */
3097 if (!(search_distance
--)) break;
3099 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3101 /* Stores cannot be reordered, since they have
3102 * dependencies. For the same reason, indirect
3103 * loads cannot be reordered as their index is
3104 * loaded in r27.w */
3106 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3108 /* It appears the 0x800 bit is set whenever a
3109 * load is direct, unset when it is indirect.
3110 * Skip indirect loads. */
3112 if (!(c
->load_store
.unknown
& 0x800)) continue;
3114 /* We found one! Move it up to pair and remove it from the old location */
3116 mir_insert_instruction_before(ins
, *c
);
3117 mir_remove_instruction(c
);
3125 /* Emit varying stores late */
3128 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3129 /* Iterate in reverse to get the final write, rather than the first */
3131 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3132 /* Check if what we just wrote needs a store */
3133 int idx
= ins
->ssa_args
.dest
;
3134 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3136 if (!varying
) continue;
3140 /* We need to store to the appropriate varying, so emit the
3143 /* TODO: Integrate with special purpose RA (and scheduler?) */
3144 bool high_varying_register
= false;
3146 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3148 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3149 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3151 mir_insert_instruction_before(mir_next_op(ins
), st
);
3152 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3154 /* We no longer need to store this varying */
3155 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3159 /* If there are leftovers after the below pass, emit actual fmov
3160 * instructions for the slow-but-correct path */
3163 emit_leftover_move(compiler_context
*ctx
)
3165 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3166 int base
= ((uintptr_t) leftover
->key
) - 1;
3169 map_ssa_to_alias(ctx
, &mapped
);
3170 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3175 actualise_ssa_to_alias(compiler_context
*ctx
)
3177 mir_foreach_instr(ctx
, ins
) {
3178 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3179 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3182 emit_leftover_move(ctx
);
3186 emit_fragment_epilogue(compiler_context
*ctx
)
3188 /* Special case: writing out constants requires us to include the move
3189 * explicitly now, so shove it into r0 */
3191 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3193 if (constant_value
) {
3194 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3195 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3196 emit_mir_instruction(ctx
, ins
);
3199 /* Perform the actual fragment writeout. We have two writeout/branch
3200 * instructions, forming a loop until writeout is successful as per the
3201 * docs. TODO: gl_FragDepth */
3203 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3204 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3207 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3208 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3209 * with the int8 analogue to the fragment epilogue */
3212 emit_blend_epilogue(compiler_context
*ctx
)
3214 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3216 midgard_instruction scale
= {
3219 .inline_constant
= _mesa_float_to_half(255.0),
3221 .src0
= SSA_FIXED_REGISTER(0),
3222 .src1
= SSA_UNUSED_0
,
3223 .dest
= SSA_FIXED_REGISTER(24),
3224 .inline_constant
= true
3227 .op
= midgard_alu_op_fmul
,
3228 .reg_mode
= midgard_reg_mode_full
,
3229 .dest_override
= midgard_dest_override_lower
,
3231 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3232 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3236 emit_mir_instruction(ctx
, scale
);
3238 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3240 midgard_vector_alu_src alu_src
= blank_alu_src
;
3241 alu_src
.half
= true;
3243 midgard_instruction f2u8
= {
3246 .src0
= SSA_FIXED_REGISTER(24),
3247 .src1
= SSA_UNUSED_0
,
3248 .dest
= SSA_FIXED_REGISTER(0),
3249 .inline_constant
= true
3252 .op
= midgard_alu_op_f2u8
,
3253 .reg_mode
= midgard_reg_mode_half
,
3254 .dest_override
= midgard_dest_override_lower
,
3255 .outmod
= midgard_outmod_pos
,
3257 .src1
= vector_alu_srco_unsigned(alu_src
),
3258 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3262 emit_mir_instruction(ctx
, f2u8
);
3264 /* vmul.imov.quarter r0, r0, r0 */
3266 midgard_instruction imov_8
= {
3269 .src0
= SSA_UNUSED_1
,
3270 .src1
= SSA_FIXED_REGISTER(0),
3271 .dest
= SSA_FIXED_REGISTER(0),
3274 .op
= midgard_alu_op_imov
,
3275 .reg_mode
= midgard_reg_mode_quarter
,
3276 .dest_override
= midgard_dest_override_none
,
3278 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3279 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3283 /* Emit branch epilogue with the 8-bit move as the source */
3285 emit_mir_instruction(ctx
, imov_8
);
3286 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3288 emit_mir_instruction(ctx
, imov_8
);
3289 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3292 static midgard_block
*
3293 emit_block(compiler_context
*ctx
, nir_block
*block
)
3295 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3296 list_addtail(&this_block
->link
, &ctx
->blocks
);
3298 this_block
->is_scheduled
= false;
3301 ctx
->texture_index
[0] = -1;
3302 ctx
->texture_index
[1] = -1;
3304 /* Add us as a successor to the block we are following */
3305 if (ctx
->current_block
)
3306 midgard_block_add_successor(ctx
->current_block
, this_block
);
3308 /* Set up current block */
3309 list_inithead(&this_block
->instructions
);
3310 ctx
->current_block
= this_block
;
3312 nir_foreach_instr(instr
, block
) {
3313 emit_instr(ctx
, instr
);
3314 ++ctx
->instruction_count
;
3317 inline_alu_constants(ctx
);
3318 embedded_to_inline_constant(ctx
);
3320 /* Perform heavylifting for aliasing */
3321 actualise_ssa_to_alias(ctx
);
3323 midgard_emit_store(ctx
, this_block
);
3324 midgard_eliminate_orphan_moves(ctx
, this_block
);
3325 midgard_pair_load_store(ctx
, this_block
);
3327 /* Append fragment shader epilogue (value writeout) */
3328 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3329 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3331 emit_blend_epilogue(ctx
);
3333 emit_fragment_epilogue(ctx
);
3337 if (block
== nir_start_block(ctx
->func
->impl
))
3338 ctx
->initial_block
= this_block
;
3340 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3341 ctx
->final_block
= this_block
;
3343 /* Allow the next control flow to access us retroactively, for
3345 ctx
->current_block
= this_block
;
3347 /* Document the fallthrough chain */
3348 ctx
->previous_source_block
= this_block
;
3353 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3356 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3358 /* Conditional branches expect the condition in r31.w; emit a move for
3359 * that in the _previous_ block (which is the current block). */
3360 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3362 /* Speculatively emit the branch, but we can't fill it in until later */
3363 EMIT(branch
, true, true);
3364 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3366 /* Emit the two subblocks */
3367 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3369 /* Emit a jump from the end of the then block to the end of the else */
3370 EMIT(branch
, false, false);
3371 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3373 /* Emit second block, and check if it's empty */
3375 int else_idx
= ctx
->block_count
;
3376 int count_in
= ctx
->instruction_count
;
3377 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3378 int after_else_idx
= ctx
->block_count
;
3380 /* Now that we have the subblocks emitted, fix up the branches */
3385 if (ctx
->instruction_count
== count_in
) {
3386 /* The else block is empty, so don't emit an exit jump */
3387 mir_remove_instruction(then_exit
);
3388 then_branch
->branch
.target_block
= after_else_idx
;
3390 then_branch
->branch
.target_block
= else_idx
;
3391 then_exit
->branch
.target_block
= after_else_idx
;
3396 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3398 /* Remember where we are */
3399 midgard_block
*start_block
= ctx
->current_block
;
3401 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3402 * single current_loop variable, maybe we need a stack */
3404 int loop_idx
= ++ctx
->current_loop
;
3406 /* Get index from before the body so we can loop back later */
3407 int start_idx
= ctx
->block_count
;
3409 /* Emit the body itself */
3410 emit_cf_list(ctx
, &nloop
->body
);
3412 /* Branch back to loop back */
3413 struct midgard_instruction br_back
= v_branch(false, false);
3414 br_back
.branch
.target_block
= start_idx
;
3415 emit_mir_instruction(ctx
, br_back
);
3417 /* Mark down that branch in the graph */
3418 midgard_block_add_successor(ctx
->current_block
, start_block
);
3420 /* Find the index of the block about to follow us (note: we don't add
3421 * one; blocks are 0-indexed so we get a fencepost problem) */
3422 int break_block_idx
= ctx
->block_count
;
3424 /* Fix up the break statements we emitted to point to the right place,
3425 * now that we can allocate a block number for them */
3427 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3428 mir_foreach_instr_in_block(block
, ins
) {
3429 if (ins
->type
!= TAG_ALU_4
) continue;
3430 if (!ins
->compact_branch
) continue;
3431 if (ins
->prepacked_branch
) continue;
3433 /* We found a branch -- check the type to see if we need to do anything */
3434 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3436 /* It's a break! Check if it's our break */
3437 if (ins
->branch
.target_break
!= loop_idx
) continue;
3439 /* Okay, cool, we're breaking out of this loop.
3440 * Rewrite from a break to a goto */
3442 ins
->branch
.target_type
= TARGET_GOTO
;
3443 ins
->branch
.target_block
= break_block_idx
;
3448 static midgard_block
*
3449 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3451 midgard_block
*start_block
= NULL
;
3453 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3454 switch (node
->type
) {
3455 case nir_cf_node_block
: {
3456 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3459 start_block
= block
;
3464 case nir_cf_node_if
:
3465 emit_if(ctx
, nir_cf_node_as_if(node
));
3468 case nir_cf_node_loop
:
3469 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3472 case nir_cf_node_function
:
3481 /* Due to lookahead, we need to report the first tag executed in the command
3482 * stream and in branch targets. An initial block might be empty, so iterate
3483 * until we find one that 'works' */
3486 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3488 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3490 unsigned first_tag
= 0;
3493 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3495 if (initial_bundle
) {
3496 first_tag
= initial_bundle
->tag
;
3500 /* Initial block is empty, try the next block */
3501 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3502 } while(initial_block
!= NULL
);
3509 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3511 struct util_dynarray
*compiled
= &program
->compiled
;
3513 midgard_debug
= debug_get_option_midgard_debug();
3515 compiler_context ictx
= {
3517 .stage
= nir
->info
.stage
,
3519 .is_blend
= is_blend
,
3520 .blend_constant_offset
= -1,
3522 .alpha_ref
= program
->alpha_ref
3525 compiler_context
*ctx
= &ictx
;
3527 /* TODO: Decide this at runtime */
3528 ctx
->uniform_cutoff
= 8;
3530 /* Assign var locations early, so the epilogue can use them if necessary */
3532 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3533 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3534 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3536 /* Initialize at a global (not block) level hash tables */
3538 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3539 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3540 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3541 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3542 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3543 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3544 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3546 /* Record the varying mapping for the command stream's bookkeeping */
3548 struct exec_list
*varyings
=
3549 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3551 nir_foreach_variable(var
, varyings
) {
3552 unsigned loc
= var
->data
.driver_location
;
3553 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3555 for (int c
= 0; c
< sz
; ++c
) {
3556 program
->varyings
[loc
+ c
] = var
->data
.location
;
3560 /* Lower gl_Position pre-optimisation */
3562 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3563 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3565 NIR_PASS_V(nir
, nir_lower_var_copies
);
3566 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3567 NIR_PASS_V(nir
, nir_split_var_copies
);
3568 NIR_PASS_V(nir
, nir_lower_var_copies
);
3569 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3570 NIR_PASS_V(nir
, nir_lower_var_copies
);
3571 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3573 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3575 /* Optimisation passes */
3579 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3580 nir_print_shader(nir
, stdout
);
3583 /* Assign sysvals and counts, now that we're sure
3584 * (post-optimisation) */
3586 midgard_nir_assign_sysvals(ctx
, nir
);
3588 program
->uniform_count
= nir
->num_uniforms
;
3589 program
->sysval_count
= ctx
->sysval_count
;
3590 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3592 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3593 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3595 nir_foreach_function(func
, nir
) {
3599 list_inithead(&ctx
->blocks
);
3600 ctx
->block_count
= 0;
3603 emit_cf_list(ctx
, &func
->impl
->body
);
3604 emit_block(ctx
, func
->impl
->end_block
);
3606 break; /* TODO: Multi-function shaders */
3609 util_dynarray_init(compiled
, NULL
);
3612 schedule_program(ctx
);
3614 /* Now that all the bundles are scheduled and we can calculate block
3615 * sizes, emit actual branch instructions rather than placeholders */
3617 int br_block_idx
= 0;
3619 mir_foreach_block(ctx
, block
) {
3620 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3621 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3622 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3624 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3626 if (ins
->prepacked_branch
) continue;
3628 /* Parse some basic branch info */
3629 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3630 bool is_conditional
= ins
->branch
.conditional
;
3631 bool is_inverted
= ins
->branch
.invert_conditional
;
3632 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3634 /* Determine the block we're jumping to */
3635 int target_number
= ins
->branch
.target_block
;
3637 /* Report the destination tag. Discards don't need this */
3638 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3640 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3641 int quadword_offset
= 0;
3644 /* Jump to the end of the shader. We
3645 * need to include not only the
3646 * following blocks, but also the
3647 * contents of our current block (since
3648 * discard can come in the middle of
3651 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3653 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3654 quadword_offset
+= quadword_size(bun
->tag
);
3657 mir_foreach_block_from(ctx
, blk
, b
) {
3658 quadword_offset
+= b
->quadword_count
;
3661 } else if (target_number
> br_block_idx
) {
3664 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3665 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3668 quadword_offset
+= blk
->quadword_count
;
3671 /* Jump backwards */
3673 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3674 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3677 quadword_offset
-= blk
->quadword_count
;
3681 /* Unconditional extended branches (far jumps)
3682 * have issues, so we always use a conditional
3683 * branch, setting the condition to always for
3684 * unconditional. For compact unconditional
3685 * branches, cond isn't used so it doesn't
3686 * matter what we pick. */
3688 midgard_condition cond
=
3689 !is_conditional
? midgard_condition_always
:
3690 is_inverted
? midgard_condition_false
:
3691 midgard_condition_true
;
3693 midgard_jmp_writeout_op op
=
3694 is_discard
? midgard_jmp_writeout_op_discard
:
3695 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3696 midgard_jmp_writeout_op_branch_cond
;
3699 midgard_branch_extended branch
=
3700 midgard_create_branch_extended(
3705 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3706 } else if (is_conditional
|| is_discard
) {
3707 midgard_branch_cond branch
= {
3709 .dest_tag
= dest_tag
,
3710 .offset
= quadword_offset
,
3714 assert(branch
.offset
== quadword_offset
);
3716 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3718 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3720 midgard_branch_uncond branch
= {
3722 .dest_tag
= dest_tag
,
3723 .offset
= quadword_offset
,
3727 assert(branch
.offset
== quadword_offset
);
3729 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3737 /* Emit flat binary from the instruction arrays. Iterate each block in
3738 * sequence. Save instruction boundaries such that lookahead tags can
3739 * be assigned easily */
3741 /* Cache _all_ bundles in source order for lookahead across failed branches */
3743 int bundle_count
= 0;
3744 mir_foreach_block(ctx
, block
) {
3745 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3747 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3749 mir_foreach_block(ctx
, block
) {
3750 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3751 source_order_bundles
[bundle_idx
++] = bundle
;
3755 int current_bundle
= 0;
3757 mir_foreach_block(ctx
, block
) {
3758 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3761 if (current_bundle
+ 1 < bundle_count
) {
3762 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3764 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3771 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3775 /* TODO: Free deeper */
3776 //util_dynarray_fini(&block->instructions);
3779 free(source_order_bundles
);
3781 /* Report the very first tag executed */
3782 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3784 /* Deal with off-by-one related to the fencepost problem */
3785 program
->work_register_count
= ctx
->work_registers
+ 1;
3787 program
->can_discard
= ctx
->can_discard
;
3788 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3790 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3792 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3793 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);