2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "mesa/state_tracker/st_glsl_types.h"
36 #include "compiler/nir_types.h"
37 #include "main/imports.h"
38 #include "compiler/nir/nir_builder.h"
39 #include "util/half_float.h"
40 #include "util/register_allocate.h"
41 #include "util/u_debug.h"
42 #include "util/u_dynarray.h"
43 #include "util/list.h"
44 #include "main/mtypes.h"
47 #include "midgard_nir.h"
48 #include "midgard_compile.h"
51 #include "disassemble.h"
53 static const struct debug_named_value debug_options
[] = {
54 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
61 int midgard_debug
= 0;
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
68 /* Instruction arguments represented as block-local SSA indices, rather than
69 * registers. Negative values mean unused. */
76 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
77 * in. Only valid for ALU ops. */
81 /* Forward declare so midgard_branch can reference */
84 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
85 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
86 * instruction is actually a discard op. */
89 #define TARGET_BREAK 1
90 #define TARGET_CONTINUE 2
91 #define TARGET_DISCARD 3
93 typedef struct midgard_branch
{
94 /* If conditional, the condition is specified in r31.w */
97 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
98 bool invert_conditional
;
100 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
101 unsigned target_type
;
103 /* The actual target */
111 /* Generic in-memory data type repesenting a single logical instruction, rather
112 * than a single instruction group. This is the preferred form for code gen.
113 * Multiple midgard_insturctions will later be combined during scheduling,
114 * though this is not represented in this structure. Its format bridges
115 * the low-level binary representation with the higher level semantic meaning.
117 * Notably, it allows registers to be specified as block local SSA, for code
118 * emitted before the register allocation pass.
121 typedef struct midgard_instruction
{
122 /* Must be first for casting */
123 struct list_head link
;
125 unsigned type
; /* ALU, load/store, texture */
127 /* If the register allocator has not run yet... */
130 /* Special fields for an ALU instruction */
131 midgard_reg_info registers
;
133 /* I.e. (1 << alu_bit) */
138 uint16_t inline_constant
;
139 bool has_blend_constant
;
143 bool prepacked_branch
;
146 midgard_load_store_word load_store
;
147 midgard_vector_alu alu
;
148 midgard_texture_word texture
;
149 midgard_branch_extended branch_extended
;
152 /* General branch, rather than packed br_compact. Higher level
153 * than the other components */
154 midgard_branch branch
;
156 } midgard_instruction
;
158 typedef struct midgard_block
{
159 /* Link to next block. Must be first for mir_get_block */
160 struct list_head link
;
162 /* List of midgard_instructions emitted for the current block */
163 struct list_head instructions
;
167 /* List of midgard_bundles emitted (after the scheduler has run) */
168 struct util_dynarray bundles
;
170 /* Number of quadwords _actually_ emitted, as determined after scheduling */
171 unsigned quadword_count
;
173 struct midgard_block
*next_fallthrough
;
176 /* Helpers to generate midgard_instruction's using macro magic, since every
177 * driver seems to do it that way */
179 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
180 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
182 #define M_LOAD_STORE(name, rname, uname) \
183 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
184 midgard_instruction i = { \
185 .type = TAG_LOAD_STORE_4, \
192 .op = midgard_op_##name, \
194 .swizzle = SWIZZLE_XYZW, \
202 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
203 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
205 const midgard_vector_alu_src blank_alu_src
= {
206 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
209 const midgard_vector_alu_src blank_alu_src_xxxx
= {
210 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
213 const midgard_scalar_alu_src blank_scalar_alu_src
= {
217 /* Used for encoding the unused source of 1-op instructions */
218 const midgard_vector_alu_src zero_alu_src
= { 0 };
220 /* Coerce structs to integer */
223 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
226 memcpy(&u
, &src
, sizeof(src
));
230 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
231 * the corresponding Midgard source */
233 static midgard_vector_alu_src
234 vector_alu_modifiers(nir_alu_src
*src
)
236 if (!src
) return blank_alu_src
;
238 midgard_vector_alu_src alu_src
= {
240 .negate
= src
->negate
,
243 .half
= 0, /* TODO */
244 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
250 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
252 static midgard_instruction
253 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
255 midgard_instruction ins
= {
258 .src0
= SSA_UNUSED_1
,
263 .op
= midgard_alu_op_fmov
,
264 .reg_mode
= midgard_reg_mode_full
,
265 .dest_override
= midgard_dest_override_none
,
267 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
268 .src2
= vector_alu_srco_unsigned(mod
)
275 /* load/store instructions have both 32-bit and 16-bit variants, depending on
276 * whether we are using vectors composed of highp or mediump. At the moment, we
277 * don't support half-floats -- this requires changes in other parts of the
278 * compiler -- therefore the 16-bit versions are commented out. */
280 //M_LOAD(load_attr_16);
281 M_LOAD(load_attr_32
);
282 //M_LOAD(load_vary_16);
283 M_LOAD(load_vary_32
);
284 //M_LOAD(load_uniform_16);
285 M_LOAD(load_uniform_32
);
286 M_LOAD(load_color_buffer_8
);
287 //M_STORE(store_vary_16);
288 M_STORE(store_vary_32
);
289 M_STORE(store_cubemap_coords
);
291 static midgard_instruction
292 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
294 midgard_branch_cond branch
= {
302 memcpy(&compact
, &branch
, sizeof(branch
));
304 midgard_instruction ins
= {
306 .unit
= ALU_ENAB_BR_COMPACT
,
307 .prepacked_branch
= true,
308 .compact_branch
= true,
309 .br_compact
= compact
312 if (op
== midgard_jmp_writeout_op_writeout
)
318 static midgard_instruction
319 v_branch(bool conditional
, bool invert
)
321 midgard_instruction ins
= {
323 .unit
= ALU_ENAB_BRANCH
,
324 .compact_branch
= true,
326 .conditional
= conditional
,
327 .invert_conditional
= invert
334 static midgard_branch_extended
335 midgard_create_branch_extended( midgard_condition cond
,
336 midgard_jmp_writeout_op op
,
338 signed quadword_offset
)
340 /* For unclear reasons, the condition code is repeated 8 times */
341 uint16_t duplicated_cond
=
351 midgard_branch_extended branch
= {
353 .dest_tag
= dest_tag
,
354 .offset
= quadword_offset
,
355 .cond
= duplicated_cond
361 typedef struct midgard_bundle
{
362 /* Tag for the overall bundle */
365 /* Instructions contained by the bundle */
366 int instruction_count
;
367 midgard_instruction instructions
[5];
369 /* Bundle-wide ALU configuration */
372 bool has_embedded_constants
;
374 bool has_blend_constant
;
376 uint16_t register_words
[8];
377 int register_words_count
;
379 uint64_t body_words
[8];
381 int body_words_count
;
384 typedef struct compiler_context
{
386 gl_shader_stage stage
;
388 /* Is internally a blend shader? Depends on stage == FRAGMENT */
391 /* Tracking for blend constant patching */
392 int blend_constant_number
;
393 int blend_constant_offset
;
395 /* Current NIR function */
398 /* Unordered list of midgard_blocks */
400 struct list_head blocks
;
402 midgard_block
*initial_block
;
403 midgard_block
*previous_source_block
;
404 midgard_block
*final_block
;
406 /* List of midgard_instructions emitted for the current block */
407 midgard_block
*current_block
;
409 /* The index corresponding to the current loop, e.g. for breaks/contineus */
412 /* Constants which have been loaded, for later inlining */
413 struct hash_table_u64
*ssa_constants
;
415 /* SSA indices to be outputted to corresponding varying offset */
416 struct hash_table_u64
*ssa_varyings
;
418 /* SSA values / registers which have been aliased. Naively, these
419 * demand a fmov output; instead, we alias them in a later pass to
420 * avoid the wasted op.
422 * A note on encoding: to avoid dynamic memory management here, rather
423 * than ampping to a pointer, we map to the source index; the key
424 * itself is just the destination index. */
426 struct hash_table_u64
*ssa_to_alias
;
427 struct set
*leftover_ssa_to_alias
;
429 /* Actual SSA-to-register for RA */
430 struct hash_table_u64
*ssa_to_register
;
432 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
433 struct hash_table_u64
*hash_to_temp
;
437 /* Just the count of the max register used. Higher count => higher
438 * register pressure */
441 /* Used for cont/last hinting. Increase when a tex op is added.
442 * Decrease when a tex op is removed. */
443 int texture_op_count
;
445 /* Mapping of texture register -> SSA index for unaliasing */
446 int texture_index
[2];
448 /* If any path hits a discard instruction */
451 /* The number of uniforms allowable for the fast path */
454 /* Count of instructions emitted from NIR overall, across all blocks */
455 int instruction_count
;
457 /* Alpha ref value passed in */
460 /* The index corresponding to the fragment output */
461 unsigned fragment_output
;
463 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
464 unsigned sysvals
[MAX_SYSVAL_COUNT
];
465 unsigned sysval_count
;
466 struct hash_table_u64
*sysval_to_id
;
469 /* Append instruction to end of current block */
471 static midgard_instruction
*
472 mir_upload_ins(struct midgard_instruction ins
)
474 midgard_instruction
*heap
= malloc(sizeof(ins
));
475 memcpy(heap
, &ins
, sizeof(ins
));
480 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
482 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
486 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
488 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
492 mir_remove_instruction(struct midgard_instruction
*ins
)
494 list_del(&ins
->link
);
497 static midgard_instruction
*
498 mir_prev_op(struct midgard_instruction
*ins
)
500 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
503 static midgard_instruction
*
504 mir_next_op(struct midgard_instruction
*ins
)
506 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
509 static midgard_block
*
510 mir_next_block(struct midgard_block
*blk
)
512 return list_first_entry(&(blk
->link
), midgard_block
, link
);
516 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
517 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
519 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
520 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
521 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
522 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
523 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
524 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
527 static midgard_instruction
*
528 mir_last_in_block(struct midgard_block
*block
)
530 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
533 static midgard_block
*
534 mir_get_block(compiler_context
*ctx
, int idx
)
536 struct list_head
*lst
= &ctx
->blocks
;
541 return (struct midgard_block
*) lst
;
544 /* Pretty printer for internal Midgard IR */
547 print_mir_source(int source
)
549 if (source
>= SSA_FIXED_MINIMUM
) {
550 /* Specific register */
551 int reg
= SSA_REG_FROM_FIXED(source
);
553 /* TODO: Moving threshold */
554 if (reg
> 16 && reg
< 24)
555 printf("u%d", 23 - reg
);
559 printf("%d", source
);
564 print_mir_instruction(midgard_instruction
*ins
)
570 midgard_alu_op op
= ins
->alu
.op
;
571 const char *name
= alu_opcode_names
[op
];
574 printf("%d.", ins
->unit
);
576 printf("%s", name
? name
: "??");
580 case TAG_LOAD_STORE_4
: {
581 midgard_load_store_op op
= ins
->load_store
.op
;
582 const char *name
= load_store_opcode_names
[op
];
589 case TAG_TEXTURE_4
: {
598 ssa_args
*args
= &ins
->ssa_args
;
600 printf(" %d, ", args
->dest
);
602 print_mir_source(args
->src0
);
605 if (args
->inline_constant
)
606 printf("#%d", ins
->inline_constant
);
608 print_mir_source(args
->src1
);
610 if (ins
->has_constants
)
611 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
617 print_mir_block(midgard_block
*block
)
621 mir_foreach_instr_in_block(block
, ins
) {
622 print_mir_instruction(ins
);
631 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
633 ins
->has_constants
= true;
634 memcpy(&ins
->constants
, constants
, 16);
636 /* If this is the special blend constant, mark this instruction */
638 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
639 ins
->has_blend_constant
= true;
643 glsl_type_size(const struct glsl_type
*type
)
645 return glsl_count_attribute_slots(type
, false);
649 uniform_type_size(const struct glsl_type
*type
)
651 return st_glsl_storage_type_size(type
, false);
654 /* Lower fdot2 to a vector multiplication followed by channel addition */
656 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
658 if (alu
->op
!= nir_op_fdot2
)
661 b
->cursor
= nir_before_instr(&alu
->instr
);
663 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
664 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
666 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
668 nir_ssa_def
*sum
= nir_fadd(b
,
669 nir_channel(b
, product
, 0),
670 nir_channel(b
, product
, 1));
672 /* Replace the fdot2 with this sum */
673 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
677 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
679 switch (instr
->intrinsic
) {
680 case nir_intrinsic_load_viewport_scale
:
681 return PAN_SYSVAL_VIEWPORT_SCALE
;
682 case nir_intrinsic_load_viewport_offset
:
683 return PAN_SYSVAL_VIEWPORT_OFFSET
;
690 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
694 if (instr
->type
== nir_instr_type_intrinsic
) {
695 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
696 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
702 /* We have a sysval load; check if it's already been assigned */
704 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
707 /* It hasn't -- so assign it now! */
709 unsigned id
= ctx
->sysval_count
++;
710 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
711 ctx
->sysvals
[id
] = sysval
;
715 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
717 ctx
->sysval_count
= 0;
719 nir_foreach_function(function
, shader
) {
720 if (!function
->impl
) continue;
722 nir_foreach_block(block
, function
->impl
) {
723 nir_foreach_instr_safe(instr
, block
) {
724 midgard_nir_assign_sysval_body(ctx
, instr
);
731 midgard_nir_lower_fdot2(nir_shader
*shader
)
733 bool progress
= false;
735 nir_foreach_function(function
, shader
) {
736 if (!function
->impl
) continue;
739 nir_builder
*b
= &_b
;
740 nir_builder_init(b
, function
->impl
);
742 nir_foreach_block(block
, function
->impl
) {
743 nir_foreach_instr_safe(instr
, block
) {
744 if (instr
->type
!= nir_instr_type_alu
) continue;
746 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
747 midgard_nir_lower_fdot2_body(b
, alu
);
753 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
761 optimise_nir(nir_shader
*nir
)
765 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
766 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
768 nir_lower_tex_options lower_tex_options
= {
772 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
777 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
778 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
779 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
781 NIR_PASS(progress
, nir
, nir_copy_prop
);
782 NIR_PASS(progress
, nir
, nir_opt_dce
);
783 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
784 NIR_PASS(progress
, nir
, nir_opt_cse
);
785 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
786 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
787 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
788 NIR_PASS(progress
, nir
, nir_opt_undef
);
789 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
792 nir_var_function_temp
);
794 /* TODO: Enable vectorize when merged upstream */
795 // NIR_PASS(progress, nir, nir_opt_vectorize);
798 /* Must be run at the end to prevent creation of fsin/fcos ops */
799 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
804 NIR_PASS(progress
, nir
, nir_opt_dce
);
805 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
806 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
807 NIR_PASS(progress
, nir
, nir_copy_prop
);
810 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
811 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
813 /* Lower mods for float ops only. Integer ops don't support modifiers
814 * (saturate doesn't make sense on integers, neg/abs require dedicated
817 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
818 NIR_PASS(progress
, nir
, nir_copy_prop
);
819 NIR_PASS(progress
, nir
, nir_opt_dce
);
821 /* We implement booleans as 32-bit 0/~0 */
822 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
824 /* Take us out of SSA */
825 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
826 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
828 /* We are a vector architecture; write combine where possible */
829 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
830 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
832 NIR_PASS(progress
, nir
, nir_opt_dce
);
835 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
836 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
837 * r0. See the comments in compiler_context */
840 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
842 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
843 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
846 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
849 unalias_ssa(compiler_context
*ctx
, int dest
)
851 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
852 /* TODO: Remove from leftover or no? */
856 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
858 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
862 midgard_is_pinned(compiler_context
*ctx
, int index
)
864 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
867 /* Do not actually emit a load; instead, cache the constant for inlining */
870 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
872 nir_ssa_def def
= instr
->def
;
874 float *v
= ralloc_array(NULL
, float, 4);
875 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
876 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
879 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
883 expand_writemask(unsigned mask
)
887 for (int i
= 0; i
< 4; ++i
)
895 squeeze_writemask(unsigned mask
)
899 for (int i
= 0; i
< 4; ++i
)
900 if (mask
& (3 << (2 * i
)))
907 /* Determines effective writemask, taking quirks and expansion into account */
909 effective_writemask(midgard_vector_alu
*alu
)
911 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
914 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
916 /* If there is a fixed channel count, construct the appropriate mask */
919 return (1 << channel_count
) - 1;
921 /* Otherwise, just squeeze the existing mask */
922 return squeeze_writemask(alu
->mask
);
926 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
928 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
931 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
936 /* If no temp is find, allocate one */
937 temp
= ctx
->temp_count
++;
938 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
940 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
946 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
949 return src
->ssa
->index
;
951 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
955 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
958 return dst
->ssa
.index
;
960 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
964 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
966 return nir_src_index(ctx
, &src
->src
);
969 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
970 * a conditional test) into that register */
973 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
975 /* XXX: Force component correct */
976 int condition
= nir_src_index(ctx
, src
);
978 /* There is no boolean move instruction. Instead, we simulate a move by
979 * ANDing the condition with itself to get it into r31.w */
981 midgard_instruction ins
= {
983 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
987 .dest
= SSA_FIXED_REGISTER(31),
990 .op
= midgard_alu_op_iand
,
991 .reg_mode
= midgard_reg_mode_full
,
992 .dest_override
= midgard_dest_override_none
,
993 .mask
= (0x3 << 6), /* w */
994 .src1
= vector_alu_srco_unsigned(blank_alu_src_xxxx
),
995 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
999 emit_mir_instruction(ctx
, ins
);
1002 #define ALU_CASE(nir, _op) \
1003 case nir_op_##nir: \
1004 op = midgard_alu_op_##_op; \
1008 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1010 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1012 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1013 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1014 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1016 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1017 * supported. A few do not and are commented for now. Also, there are a
1018 * number of NIR ops which Midgard does not support and need to be
1019 * lowered, also TODO. This switch block emits the opcode and calling
1020 * convention of the Midgard instruction; actual packing is done in
1025 switch (instr
->op
) {
1026 ALU_CASE(fadd
, fadd
);
1027 ALU_CASE(fmul
, fmul
);
1028 ALU_CASE(fmin
, fmin
);
1029 ALU_CASE(fmax
, fmax
);
1030 ALU_CASE(imin
, imin
);
1031 ALU_CASE(imax
, imax
);
1032 ALU_CASE(fmov
, fmov
);
1033 ALU_CASE(ffloor
, ffloor
);
1034 ALU_CASE(fround_even
, froundeven
);
1035 ALU_CASE(ftrunc
, ftrunc
);
1036 ALU_CASE(fceil
, fceil
);
1037 ALU_CASE(fdot3
, fdot3
);
1038 ALU_CASE(fdot4
, fdot4
);
1039 ALU_CASE(iadd
, iadd
);
1040 ALU_CASE(isub
, isub
);
1041 ALU_CASE(imul
, imul
);
1042 ALU_CASE(iabs
, iabs
);
1044 /* XXX: Use fmov, not imov, since imov was causing major
1045 * issues with texture precision? XXX research */
1046 ALU_CASE(imov
, fmov
);
1048 ALU_CASE(feq32
, feq
);
1049 ALU_CASE(fne32
, fne
);
1050 ALU_CASE(flt32
, flt
);
1051 ALU_CASE(ieq32
, ieq
);
1052 ALU_CASE(ine32
, ine
);
1053 ALU_CASE(ilt32
, ilt
);
1054 ALU_CASE(ult32
, ult
);
1056 /* We don't have a native b2f32 instruction. Instead, like many
1057 * GPUs, we exploit booleans as 0/~0 for false/true, and
1058 * correspondingly AND
1059 * by 1.0 to do the type conversion. For the moment, prime us
1062 * iand [whatever], #0
1064 * At the end of emit_alu (as MIR), we'll fix-up the constant
1067 ALU_CASE(b2f32
, iand
);
1068 ALU_CASE(b2i32
, iand
);
1070 /* Likewise, we don't have a dedicated f2b32 instruction, but
1071 * we can do a "not equal to 0.0" test. */
1073 ALU_CASE(f2b32
, fne
);
1074 ALU_CASE(i2b32
, ine
);
1076 ALU_CASE(frcp
, frcp
);
1077 ALU_CASE(frsq
, frsqrt
);
1078 ALU_CASE(fsqrt
, fsqrt
);
1079 ALU_CASE(fexp2
, fexp2
);
1080 ALU_CASE(flog2
, flog2
);
1082 ALU_CASE(f2i32
, f2i
);
1083 ALU_CASE(f2u32
, f2u
);
1084 ALU_CASE(i2f32
, i2f
);
1085 ALU_CASE(u2f32
, u2f
);
1087 ALU_CASE(fsin
, fsin
);
1088 ALU_CASE(fcos
, fcos
);
1090 ALU_CASE(iand
, iand
);
1092 ALU_CASE(ixor
, ixor
);
1093 ALU_CASE(inot
, inot
);
1094 ALU_CASE(ishl
, ishl
);
1095 ALU_CASE(ishr
, iasr
);
1096 ALU_CASE(ushr
, ilsr
);
1098 ALU_CASE(b32all_fequal2
, fball_eq
);
1099 ALU_CASE(b32all_fequal3
, fball_eq
);
1100 ALU_CASE(b32all_fequal4
, fball_eq
);
1102 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1103 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1104 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1106 ALU_CASE(b32all_iequal2
, iball_eq
);
1107 ALU_CASE(b32all_iequal3
, iball_eq
);
1108 ALU_CASE(b32all_iequal4
, iball_eq
);
1110 ALU_CASE(b32any_inequal2
, ibany_neq
);
1111 ALU_CASE(b32any_inequal3
, ibany_neq
);
1112 ALU_CASE(b32any_inequal4
, ibany_neq
);
1114 /* For greater-or-equal, we lower to less-or-equal and flip the
1120 case nir_op_uge32
: {
1122 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1123 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1124 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1125 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1128 /* Swap via temporary */
1129 nir_alu_src temp
= instr
->src
[1];
1130 instr
->src
[1] = instr
->src
[0];
1131 instr
->src
[0] = temp
;
1136 case nir_op_b32csel
: {
1137 op
= midgard_alu_op_fcsel
;
1139 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1142 emit_condition(ctx
, &instr
->src
[0].src
, false);
1144 /* The condition is the first argument; move the other
1145 * arguments up one to be a binary instruction for
1148 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1153 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1158 /* Fetch unit, quirks, etc information */
1159 unsigned opcode_props
= alu_opcode_props
[op
];
1160 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1162 /* Initialise fields common between scalar/vector instructions */
1163 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1165 /* src0 will always exist afaik, but src1 will not for 1-argument
1166 * instructions. The latter can only be fetched if the instruction
1167 * needs it, or else we may segfault. */
1169 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1170 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1172 /* Rather than use the instruction generation helpers, we do it
1173 * ourselves here to avoid the mess */
1175 midgard_instruction ins
= {
1178 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1179 .src1
= quirk_flipped_r24
? src0
: src1
,
1184 nir_alu_src
*nirmods
[2] = { NULL
};
1186 if (nr_inputs
== 2) {
1187 nirmods
[0] = &instr
->src
[0];
1188 nirmods
[1] = &instr
->src
[1];
1189 } else if (nr_inputs
== 1) {
1190 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1195 midgard_vector_alu alu
= {
1197 .reg_mode
= midgard_reg_mode_full
,
1198 .dest_override
= midgard_dest_override_none
,
1201 /* Writemask only valid for non-SSA NIR */
1202 .mask
= expand_writemask((1 << nr_components
) - 1),
1204 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1205 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1208 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1211 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1215 /* Late fixup for emulated instructions */
1217 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1218 /* Presently, our second argument is an inline #0 constant.
1219 * Switch over to an embedded 1.0 constant (that can't fit
1220 * inline, since we're 32-bit, not 16-bit like the inline
1223 ins
.ssa_args
.inline_constant
= false;
1224 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1225 ins
.has_constants
= true;
1227 if (instr
->op
== nir_op_b2f32
) {
1228 ins
.constants
[0] = 1.0f
;
1230 /* Type pun it into place */
1232 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1235 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1236 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1237 ins
.ssa_args
.inline_constant
= false;
1238 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1239 ins
.has_constants
= true;
1240 ins
.constants
[0] = 0.0f
;
1241 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1244 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1245 /* To avoid duplicating the lookup tables (probably), true LUT
1246 * instructions can only operate as if they were scalars. Lower
1247 * them here by changing the component. */
1249 uint8_t original_swizzle
[4];
1250 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1252 for (int i
= 0; i
< nr_components
; ++i
) {
1253 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1255 for (int j
= 0; j
< 4; ++j
)
1256 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1258 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1259 emit_mir_instruction(ctx
, ins
);
1262 emit_mir_instruction(ctx
, ins
);
1269 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
)
1271 /* TODO: half-floats */
1273 if (offset
< ctx
->uniform_cutoff
) {
1274 /* Fast path: For the first 16 uniform,
1275 * accesses are 0-cycle, since they're
1276 * just a register fetch in the usual
1277 * case. So, we alias the registers
1278 * while we're still in SSA-space */
1280 int reg_slot
= 23 - offset
;
1281 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1283 /* Otherwise, read from the 'special'
1284 * UBO to access higher-indexed
1285 * uniforms, at a performance cost */
1287 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1289 /* TODO: Don't split */
1290 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1291 ins
.load_store
.address
= offset
>> 3;
1293 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1294 emit_mir_instruction(ctx
, ins
);
1299 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1301 /* First, pull out the destination */
1302 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1304 /* Now, figure out which uniform this is */
1305 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1306 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1308 /* Sysvals are prefix uniforms */
1309 unsigned uniform
= ((uintptr_t) val
) - 1;
1311 emit_uniform_read(ctx
, dest
, uniform
);
1315 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1317 unsigned offset
, reg
;
1319 switch (instr
->intrinsic
) {
1320 case nir_intrinsic_discard_if
:
1321 emit_condition(ctx
, &instr
->src
[0], true);
1325 case nir_intrinsic_discard
: {
1326 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1327 struct midgard_instruction discard
= v_branch(conditional
, false);
1328 discard
.branch
.target_type
= TARGET_DISCARD
;
1329 emit_mir_instruction(ctx
, discard
);
1331 ctx
->can_discard
= true;
1335 case nir_intrinsic_load_uniform
:
1336 case nir_intrinsic_load_input
:
1337 assert(nir_src_is_const(instr
->src
[0]) && "no indirect inputs");
1339 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[0]);
1341 reg
= nir_dest_index(ctx
, &instr
->dest
);
1343 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1344 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
);
1345 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1346 /* XXX: Half-floats? */
1347 /* TODO: swizzle, mask */
1349 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1351 midgard_varying_parameter p
= {
1353 .interpolation
= midgard_interp_default
,
1354 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1358 memcpy(&u
, &p
, sizeof(p
));
1359 ins
.load_store
.varying_parameters
= u
;
1361 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1362 emit_mir_instruction(ctx
, ins
);
1363 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1364 /* Constant encoded as a pinned constant */
1366 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1367 ins
.has_constants
= true;
1368 ins
.has_blend_constant
= true;
1369 emit_mir_instruction(ctx
, ins
);
1370 } else if (ctx
->is_blend
) {
1371 /* For blend shaders, a load might be
1372 * translated various ways depending on what
1373 * we're loading. Figure out how this is used */
1375 nir_variable
*out
= NULL
;
1377 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1378 int drvloc
= var
->data
.driver_location
;
1380 if (nir_intrinsic_base(instr
) == drvloc
) {
1388 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1389 /* Source color preloaded to r0 */
1391 midgard_pin_output(ctx
, reg
, 0);
1392 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1393 /* Destination color must be read from framebuffer */
1395 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1396 ins
.load_store
.swizzle
= 0; /* xxxx */
1398 /* Read each component sequentially */
1400 for (int c
= 0; c
< 4; ++c
) {
1401 ins
.load_store
.mask
= (1 << c
);
1402 ins
.load_store
.unknown
= c
;
1403 emit_mir_instruction(ctx
, ins
);
1406 /* vadd.u2f hr2, abs(hr2), #0 */
1408 midgard_vector_alu_src alu_src
= blank_alu_src
;
1410 alu_src
.half
= true;
1412 midgard_instruction u2f
= {
1416 .src1
= SSA_UNUSED_0
,
1418 .inline_constant
= true
1421 .op
= midgard_alu_op_u2f
,
1422 .reg_mode
= midgard_reg_mode_half
,
1423 .dest_override
= midgard_dest_override_none
,
1425 .src1
= vector_alu_srco_unsigned(alu_src
),
1426 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1430 emit_mir_instruction(ctx
, u2f
);
1432 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1434 alu_src
.abs
= false;
1436 midgard_instruction fmul
= {
1438 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1442 .src1
= SSA_UNUSED_0
,
1443 .inline_constant
= true
1446 .op
= midgard_alu_op_fmul
,
1447 .reg_mode
= midgard_reg_mode_full
,
1448 .dest_override
= midgard_dest_override_none
,
1449 .outmod
= midgard_outmod_sat
,
1451 .src1
= vector_alu_srco_unsigned(alu_src
),
1452 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1456 emit_mir_instruction(ctx
, fmul
);
1458 DBG("Unknown input in blend shader\n");
1461 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1462 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1463 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1464 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1465 emit_mir_instruction(ctx
, ins
);
1467 DBG("Unknown load\n");
1473 case nir_intrinsic_store_output
:
1474 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1476 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1478 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1480 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1481 /* gl_FragColor is not emitted with load/store
1482 * instructions. Instead, it gets plonked into
1483 * r0 at the end of the shader and we do the
1484 * framebuffer writeout dance. TODO: Defer
1487 midgard_pin_output(ctx
, reg
, 0);
1489 /* Save the index we're writing to for later reference
1490 * in the epilogue */
1492 ctx
->fragment_output
= reg
;
1493 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1494 /* Varyings are written into one of two special
1495 * varying register, r26 or r27. The register itself is selected as the register
1496 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1498 * Normally emitting fmov's is frowned upon,
1499 * but due to unique constraints of
1500 * REGISTER_VARYING, fmov emission + a
1501 * dedicated cleanup pass is the only way to
1502 * guarantee correctness when considering some
1503 * (common) edge cases XXX: FIXME */
1505 /* If this varying corresponds to a constant (why?!),
1506 * emit that now since it won't get picked up by
1507 * hoisting (since there is no corresponding move
1508 * emitted otherwise) */
1510 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1512 if (constant_value
) {
1513 /* Special case: emit the varying write
1514 * directly to r26 (looks funny in asm but it's
1515 * fine) and emit the store _now_. Possibly
1516 * slightly slower, but this is a really stupid
1517 * special case anyway (why on earth would you
1518 * have a constant varying? Your own fault for
1519 * slightly worse perf :P) */
1521 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1522 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1523 emit_mir_instruction(ctx
, ins
);
1525 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1526 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1527 emit_mir_instruction(ctx
, st
);
1529 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1531 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1534 DBG("Unknown store\n");
1540 case nir_intrinsic_load_alpha_ref_float
:
1541 assert(instr
->dest
.is_ssa
);
1543 float ref_value
= ctx
->alpha_ref
;
1545 float *v
= ralloc_array(NULL
, float, 4);
1546 memcpy(v
, &ref_value
, sizeof(float));
1547 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1550 case nir_intrinsic_load_viewport_scale
:
1551 case nir_intrinsic_load_viewport_offset
:
1552 emit_sysval_read(ctx
, instr
);
1556 printf ("Unhandled intrinsic\n");
1563 midgard_tex_format(enum glsl_sampler_dim dim
)
1566 case GLSL_SAMPLER_DIM_2D
:
1567 case GLSL_SAMPLER_DIM_EXTERNAL
:
1570 case GLSL_SAMPLER_DIM_3D
:
1573 case GLSL_SAMPLER_DIM_CUBE
:
1574 return TEXTURE_CUBE
;
1577 DBG("Unknown sampler dim type\n");
1584 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1587 //assert (!instr->sampler);
1588 //assert (!instr->texture_array_size);
1589 assert (instr
->op
== nir_texop_tex
);
1591 /* Allocate registers via a round robin scheme to alternate between the two registers */
1592 int reg
= ctx
->texture_op_count
& 1;
1593 int in_reg
= reg
, out_reg
= reg
;
1595 /* Make room for the reg */
1597 if (ctx
->texture_index
[reg
] > -1)
1598 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1600 int texture_index
= instr
->texture_index
;
1601 int sampler_index
= texture_index
;
1603 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1604 switch (instr
->src
[i
].src_type
) {
1605 case nir_tex_src_coord
: {
1606 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1608 midgard_vector_alu_src alu_src
= blank_alu_src
;
1610 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1612 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1613 /* For cubemaps, we need to load coords into
1614 * special r27, and then use a special ld/st op
1615 * to copy into the texture register */
1617 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1619 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1620 emit_mir_instruction(ctx
, move
);
1622 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1623 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1624 st
.load_store
.mask
= 0x3; /* xy? */
1625 st
.load_store
.swizzle
= alu_src
.swizzle
;
1626 emit_mir_instruction(ctx
, st
);
1629 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1631 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1632 emit_mir_instruction(ctx
, ins
);
1635 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1641 DBG("Unknown source type\n");
1648 /* No helper to build texture words -- we do it all here */
1649 midgard_instruction ins
= {
1650 .type
= TAG_TEXTURE_4
,
1652 .op
= TEXTURE_OP_NORMAL
,
1653 .format
= midgard_tex_format(instr
->sampler_dim
),
1654 .texture_handle
= texture_index
,
1655 .sampler_handle
= sampler_index
,
1657 /* TODO: Don't force xyzw */
1658 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1670 /* Assume we can continue; hint it out later */
1675 /* Set registers to read and write from the same place */
1676 ins
.texture
.in_reg_select
= in_reg
;
1677 ins
.texture
.out_reg_select
= out_reg
;
1679 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1680 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1681 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1682 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1683 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1685 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1686 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1687 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1690 emit_mir_instruction(ctx
, ins
);
1692 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1694 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1695 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1696 ctx
->texture_index
[reg
] = o_index
;
1698 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1699 emit_mir_instruction(ctx
, ins2
);
1701 /* Used for .cont and .last hinting */
1702 ctx
->texture_op_count
++;
1706 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1708 switch (instr
->type
) {
1709 case nir_jump_break
: {
1710 /* Emit a branch out of the loop */
1711 struct midgard_instruction br
= v_branch(false, false);
1712 br
.branch
.target_type
= TARGET_BREAK
;
1713 br
.branch
.target_break
= ctx
->current_loop
;
1714 emit_mir_instruction(ctx
, br
);
1721 DBG("Unknown jump type %d\n", instr
->type
);
1727 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1729 switch (instr
->type
) {
1730 case nir_instr_type_load_const
:
1731 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1734 case nir_instr_type_intrinsic
:
1735 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1738 case nir_instr_type_alu
:
1739 emit_alu(ctx
, nir_instr_as_alu(instr
));
1742 case nir_instr_type_tex
:
1743 emit_tex(ctx
, nir_instr_as_tex(instr
));
1746 case nir_instr_type_jump
:
1747 emit_jump(ctx
, nir_instr_as_jump(instr
));
1750 case nir_instr_type_ssa_undef
:
1755 DBG("Unhandled instruction type\n");
1760 /* Determine the actual hardware from the index based on the RA results or special values */
1763 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1765 if (reg
>= SSA_FIXED_MINIMUM
)
1766 return SSA_REG_FROM_FIXED(reg
);
1769 assert(reg
< maxreg
);
1770 int r
= ra_get_node_reg(g
, reg
);
1771 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1776 /* fmov style unused */
1778 return REGISTER_UNUSED
;
1780 /* lut style unused */
1782 return REGISTER_UNUSED
;
1785 DBG("Unknown SSA register alias %d\n", reg
);
1792 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1794 /* Choose the first available register to minimise reported register pressure */
1796 for (int i
= 0; i
< 16; ++i
) {
1797 if (BITSET_TEST(regs
, i
)) {
1807 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1809 if (ins
->ssa_args
.src0
== src
) return true;
1810 if (ins
->ssa_args
.src1
== src
) return true;
1816 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1818 /* Check the rest of the block for liveness */
1819 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1820 if (midgard_is_live_in_instr(ins
, src
))
1824 /* Check the rest of the blocks for liveness */
1825 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1826 mir_foreach_instr_in_block(b
, ins
) {
1827 if (midgard_is_live_in_instr(ins
, src
))
1832 /* TODO: How does control flow interact in complex shaders? */
1838 allocate_registers(compiler_context
*ctx
)
1840 /* First, initialize the RA */
1841 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1843 /* Create a primary (general purpose) class, as well as special purpose
1844 * pipeline register classes */
1846 int primary_class
= ra_alloc_reg_class(regs
);
1847 int varying_class
= ra_alloc_reg_class(regs
);
1849 /* Add the full set of work registers */
1850 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1851 for (int i
= 0; i
< work_count
; ++i
)
1852 ra_class_add_reg(regs
, primary_class
, i
);
1854 /* Add special registers */
1855 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1856 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1858 /* We're done setting up */
1859 ra_set_finalize(regs
, NULL
);
1861 /* Transform the MIR into squeezed index form */
1862 mir_foreach_block(ctx
, block
) {
1863 mir_foreach_instr_in_block(block
, ins
) {
1864 if (ins
->compact_branch
) continue;
1866 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1867 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1868 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1870 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1871 print_mir_block(block
);
1874 /* Let's actually do register allocation */
1875 int nodes
= ctx
->temp_count
;
1876 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1878 /* Set everything to the work register class, unless it has somewhere
1881 mir_foreach_block(ctx
, block
) {
1882 mir_foreach_instr_in_block(block
, ins
) {
1883 if (ins
->compact_branch
) continue;
1885 if (ins
->ssa_args
.dest
< 0) continue;
1887 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1889 int class = primary_class
;
1891 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1895 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1896 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1899 unsigned reg
= temp
- 1;
1900 int t
= find_or_allocate_temp(ctx
, index
);
1901 ra_set_node_reg(g
, t
, reg
);
1905 /* Determine liveness */
1907 int *live_start
= malloc(nodes
* sizeof(int));
1908 int *live_end
= malloc(nodes
* sizeof(int));
1910 /* Initialize as non-existent */
1912 for (int i
= 0; i
< nodes
; ++i
) {
1913 live_start
[i
] = live_end
[i
] = -1;
1918 mir_foreach_block(ctx
, block
) {
1919 mir_foreach_instr_in_block(block
, ins
) {
1920 if (ins
->compact_branch
) continue;
1922 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1923 /* If this destination is not yet live, it is now since we just wrote it */
1925 int dest
= ins
->ssa_args
.dest
;
1927 if (live_start
[dest
] == -1)
1928 live_start
[dest
] = d
;
1931 /* Since we just used a source, the source might be
1932 * dead now. Scan the rest of the block for
1933 * invocations, and if there are none, the source dies
1936 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1938 for (int src
= 0; src
< 2; ++src
) {
1939 int s
= sources
[src
];
1941 if (s
< 0) continue;
1943 if (s
>= SSA_FIXED_MINIMUM
) continue;
1945 if (!is_live_after(ctx
, block
, ins
, s
)) {
1954 /* If a node still hasn't been killed, kill it now */
1956 for (int i
= 0; i
< nodes
; ++i
) {
1957 /* live_start == -1 most likely indicates a pinned output */
1959 if (live_end
[i
] == -1)
1963 /* Setup interference between nodes that are live at the same time */
1965 for (int i
= 0; i
< nodes
; ++i
) {
1966 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1967 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1968 ra_add_node_interference(g
, i
, j
);
1972 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1974 if (!ra_allocate(g
)) {
1975 DBG("Error allocating registers\n");
1983 mir_foreach_block(ctx
, block
) {
1984 mir_foreach_instr_in_block(block
, ins
) {
1985 if (ins
->compact_branch
) continue;
1987 ssa_args args
= ins
->ssa_args
;
1989 switch (ins
->type
) {
1991 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1993 ins
->registers
.src2_imm
= args
.inline_constant
;
1995 if (args
.inline_constant
) {
1996 /* Encode inline 16-bit constant as a vector by default */
1998 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2000 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2002 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2003 ins
->alu
.src2
= imm
<< 2;
2005 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2008 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2012 case TAG_LOAD_STORE_4
: {
2013 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2014 /* TODO: use ssa_args for store_vary */
2015 ins
->load_store
.reg
= 0;
2017 bool has_dest
= args
.dest
>= 0;
2018 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2020 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2033 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2034 * use scalar ALU instructions, for functional or performance reasons. To do
2035 * this, we just demote vector ALU payloads to scalar. */
2038 component_from_mask(unsigned mask
)
2040 for (int c
= 0; c
< 4; ++c
) {
2041 if (mask
& (3 << (2 * c
)))
2050 is_single_component_mask(unsigned mask
)
2054 for (int c
= 0; c
< 4; ++c
)
2055 if (mask
& (3 << (2 * c
)))
2058 return components
== 1;
2061 /* Create a mask of accessed components from a swizzle to figure out vector
2065 swizzle_to_access_mask(unsigned swizzle
)
2067 unsigned component_mask
= 0;
2069 for (int i
= 0; i
< 4; ++i
) {
2070 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2071 component_mask
|= (1 << c
);
2074 return component_mask
;
2078 vector_to_scalar_source(unsigned u
)
2080 midgard_vector_alu_src v
;
2081 memcpy(&v
, &u
, sizeof(v
));
2083 midgard_scalar_alu_src s
= {
2087 .component
= (v
.swizzle
& 3) << 1
2091 memcpy(&o
, &s
, sizeof(s
));
2093 return o
& ((1 << 6) - 1);
2096 static midgard_scalar_alu
2097 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2099 /* The output component is from the mask */
2100 midgard_scalar_alu s
= {
2102 .src1
= vector_to_scalar_source(v
.src1
),
2103 .src2
= vector_to_scalar_source(v
.src2
),
2106 .output_full
= 1, /* TODO: Half */
2107 .output_component
= component_from_mask(v
.mask
) << 1,
2110 /* Inline constant is passed along rather than trying to extract it
2113 if (ins
->ssa_args
.inline_constant
) {
2115 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2116 imm
|= (lower_11
>> 9) & 3;
2117 imm
|= (lower_11
>> 6) & 4;
2118 imm
|= (lower_11
>> 2) & 0x38;
2119 imm
|= (lower_11
& 63) << 6;
2127 /* Midgard prefetches instruction types, so during emission we need to
2128 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2129 * if this is the second to last and the last is an ALU, then it's also 1... */
2131 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2132 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2134 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2135 bytes_emitted += sizeof(type)
2138 emit_binary_vector_instruction(midgard_instruction
*ains
,
2139 uint16_t *register_words
, int *register_words_count
,
2140 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2141 size_t *bytes_emitted
)
2143 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2144 *bytes_emitted
+= sizeof(midgard_reg_info
);
2146 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2147 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2148 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2151 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2152 * mind that we are a vector architecture and we can write to different
2153 * components simultaneously */
2156 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2158 /* Each instruction reads some registers and writes to a register. See
2159 * where the first writes */
2161 /* Figure out where exactly we wrote to */
2162 int source
= first
->ssa_args
.dest
;
2163 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2165 /* As long as the second doesn't read from the first, we're okay */
2166 if (second
->ssa_args
.src0
== source
) {
2167 if (first
->type
== TAG_ALU_4
) {
2168 /* Figure out which components we just read from */
2170 int q
= second
->alu
.src1
;
2171 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2173 /* Check if there are components in common, and fail if so */
2174 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2181 if (second
->ssa_args
.src1
== source
)
2184 /* Otherwise, it's safe in that regard. Another data hazard is both
2185 * writing to the same place, of course */
2187 if (second
->ssa_args
.dest
== source
) {
2188 /* ...but only if the components overlap */
2189 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2191 if (dest_mask
& source_mask
)
2201 midgard_instruction
**segment
, unsigned segment_size
,
2202 midgard_instruction
*ains
)
2204 for (int s
= 0; s
< segment_size
; ++s
)
2205 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2213 /* Schedules, but does not emit, a single basic block. After scheduling, the
2214 * final tag and size of the block are known, which are necessary for branching
2217 static midgard_bundle
2218 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2220 int instructions_emitted
= 0, instructions_consumed
= -1;
2221 midgard_bundle bundle
= { 0 };
2223 uint8_t tag
= ins
->type
;
2225 /* Default to the instruction's tag */
2228 switch (ins
->type
) {
2230 uint32_t control
= 0;
2231 size_t bytes_emitted
= sizeof(control
);
2233 /* TODO: Constant combining */
2234 int index
= 0, last_unit
= 0;
2236 /* Previous instructions, for the purpose of parallelism */
2237 midgard_instruction
*segment
[4] = {0};
2238 int segment_size
= 0;
2240 instructions_emitted
= -1;
2241 midgard_instruction
*pins
= ins
;
2244 midgard_instruction
*ains
= pins
;
2246 /* Advance instruction pointer */
2248 ains
= mir_next_op(pins
);
2252 /* Out-of-work condition */
2253 if ((struct list_head
*) ains
== &block
->instructions
)
2256 /* Ensure that the chain can continue */
2257 if (ains
->type
!= TAG_ALU_4
) break;
2259 /* According to the presentation "The ARM
2260 * Mali-T880 Mobile GPU" from HotChips 27,
2261 * there are two pipeline stages. Branching
2262 * position determined experimentally. Lines
2263 * are executed in parallel:
2266 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2268 * Verify that there are no ordering dependencies here.
2270 * TODO: Allow for parallelism!!!
2273 /* Pick a unit for it if it doesn't force a particular unit */
2275 int unit
= ains
->unit
;
2278 int op
= ains
->alu
.op
;
2279 int units
= alu_opcode_props
[op
];
2281 /* TODO: Promotion of scalars to vectors */
2282 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2285 assert(units
& UNITS_SCALAR
);
2288 if (last_unit
>= UNIT_VADD
) {
2289 if (units
& UNIT_VLUT
)
2294 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2296 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2298 else if (units
& UNIT_VLUT
)
2304 if (last_unit
>= UNIT_VADD
) {
2305 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2307 else if (units
& UNIT_VLUT
)
2312 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2314 else if (units
& UNIT_SMUL
)
2315 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2316 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2323 assert(unit
& units
);
2326 /* Late unit check, this time for encoding (not parallelism) */
2327 if (unit
<= last_unit
) break;
2329 /* Clear the segment */
2330 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2333 if (midgard_has_hazard(segment
, segment_size
, ains
))
2336 /* We're good to go -- emit the instruction */
2339 segment
[segment_size
++] = ains
;
2341 /* Only one set of embedded constants per
2342 * bundle possible; if we have more, we must
2343 * break the chain early, unfortunately */
2345 if (ains
->has_constants
) {
2346 if (bundle
.has_embedded_constants
) {
2347 /* ...but if there are already
2348 * constants but these are the
2349 * *same* constants, we let it
2352 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2355 bundle
.has_embedded_constants
= true;
2356 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2358 /* If this is a blend shader special constant, track it for patching */
2359 if (ains
->has_blend_constant
)
2360 bundle
.has_blend_constant
= true;
2364 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2365 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2366 &bundle
.register_words_count
, bundle
.body_words
,
2367 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2368 } else if (ains
->compact_branch
) {
2369 /* All of r0 has to be written out
2370 * along with the branch writeout.
2373 if (ains
->writeout
) {
2375 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2376 ins
.unit
= UNIT_VMUL
;
2378 control
|= ins
.unit
;
2380 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2381 &bundle
.register_words_count
, bundle
.body_words
,
2382 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2384 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2385 bool written_late
= false;
2386 bool components
[4] = { 0 };
2387 uint16_t register_dep_mask
= 0;
2388 uint16_t written_mask
= 0;
2390 midgard_instruction
*qins
= ins
;
2391 for (int t
= 0; t
< index
; ++t
) {
2392 if (qins
->registers
.out_reg
!= 0) {
2393 /* Mark down writes */
2395 written_mask
|= (1 << qins
->registers
.out_reg
);
2397 /* Mark down the register dependencies for errata check */
2399 if (qins
->registers
.src1_reg
< 16)
2400 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2402 if (qins
->registers
.src2_reg
< 16)
2403 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2405 int mask
= qins
->alu
.mask
;
2407 for (int c
= 0; c
< 4; ++c
)
2408 if (mask
& (0x3 << (2 * c
)))
2409 components
[c
] = true;
2411 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2413 if (qins
->unit
== UNIT_VLUT
)
2414 written_late
= true;
2417 /* Advance instruction pointer */
2418 qins
= mir_next_op(qins
);
2422 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2423 if (register_dep_mask
& written_mask
) {
2424 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2431 /* If even a single component is not written, break it up (conservative check). */
2432 bool breakup
= false;
2434 for (int c
= 0; c
< 4; ++c
)
2441 /* Otherwise, we're free to proceed */
2445 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2446 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2447 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2448 bytes_emitted
+= sizeof(midgard_branch_extended
);
2450 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2451 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2452 bytes_emitted
+= sizeof(ains
->br_compact
);
2455 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2456 bytes_emitted
+= sizeof(midgard_reg_info
);
2458 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2459 bundle
.body_words_count
++;
2460 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2463 /* Defer marking until after writing to allow for break */
2464 control
|= ains
->unit
;
2465 last_unit
= ains
->unit
;
2466 ++instructions_emitted
;
2470 /* Bubble up the number of instructions for skipping */
2471 instructions_consumed
= index
- 1;
2475 /* Pad ALU op to nearest word */
2477 if (bytes_emitted
& 15) {
2478 padding
= 16 - (bytes_emitted
& 15);
2479 bytes_emitted
+= padding
;
2482 /* Constants must always be quadwords */
2483 if (bundle
.has_embedded_constants
)
2484 bytes_emitted
+= 16;
2486 /* Size ALU instruction for tag */
2487 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2488 bundle
.padding
= padding
;
2489 bundle
.control
= bundle
.tag
| control
;
2494 case TAG_LOAD_STORE_4
: {
2495 /* Load store instructions have two words at once. If
2496 * we only have one queued up, we need to NOP pad.
2497 * Otherwise, we store both in succession to save space
2498 * and cycles -- letting them go in parallel -- skip
2499 * the next. The usefulness of this optimisation is
2500 * greatly dependent on the quality of the instruction
2504 midgard_instruction
*next_op
= mir_next_op(ins
);
2506 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2507 /* As the two operate concurrently, make sure
2508 * they are not dependent */
2510 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2511 /* Skip ahead, since it's redundant with the pair */
2512 instructions_consumed
= 1 + (instructions_emitted
++);
2520 /* Texture ops default to single-op-per-bundle scheduling */
2524 /* Copy the instructions into the bundle */
2525 bundle
.instruction_count
= instructions_emitted
+ 1;
2529 midgard_instruction
*uins
= ins
;
2530 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2531 bundle
.instructions
[used_idx
++] = *uins
;
2532 uins
= mir_next_op(uins
);
2535 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2541 quadword_size(int tag
)
2556 case TAG_LOAD_STORE_4
:
2568 /* Schedule a single block by iterating its instruction to create bundles.
2569 * While we go, tally about the bundle sizes to compute the block size. */
2572 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2574 util_dynarray_init(&block
->bundles
, NULL
);
2576 block
->quadword_count
= 0;
2578 mir_foreach_instr_in_block(block
, ins
) {
2580 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2581 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2583 if (bundle
.has_blend_constant
) {
2584 /* TODO: Multiblock? */
2585 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2586 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2590 ins
= mir_next_op(ins
);
2592 block
->quadword_count
+= quadword_size(bundle
.tag
);
2595 block
->is_scheduled
= true;
2599 schedule_program(compiler_context
*ctx
)
2601 allocate_registers(ctx
);
2603 mir_foreach_block(ctx
, block
) {
2604 schedule_block(ctx
, block
);
2608 /* After everything is scheduled, emit whole bundles at a time */
2611 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2613 int lookahead
= next_tag
<< 4;
2615 switch (bundle
->tag
) {
2620 /* Actually emit each component */
2621 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2623 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2624 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2626 /* Emit body words based on the instructions bundled */
2627 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2628 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2630 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2631 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2632 } else if (ins
->compact_branch
) {
2633 /* Dummy move, XXX DRY */
2634 if ((i
== 0) && ins
->writeout
) {
2635 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2636 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2639 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2640 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2642 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2646 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2647 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2651 /* Emit padding (all zero) */
2652 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2654 /* Tack on constants */
2656 if (bundle
->has_embedded_constants
) {
2657 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2658 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2659 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2660 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2666 case TAG_LOAD_STORE_4
: {
2667 /* One or two composing instructions */
2669 uint64_t current64
, next64
= LDST_NOP
;
2671 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2673 if (bundle
->instruction_count
== 2)
2674 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2676 midgard_load_store instruction
= {
2677 .type
= bundle
->tag
,
2678 .next_type
= next_tag
,
2683 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2688 case TAG_TEXTURE_4
: {
2689 /* Texture instructions are easy, since there is no
2690 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2692 midgard_instruction
*ins
= &bundle
->instructions
[0];
2694 ins
->texture
.type
= TAG_TEXTURE_4
;
2695 ins
->texture
.next_type
= next_tag
;
2697 ctx
->texture_op_count
--;
2699 if (!ctx
->texture_op_count
) {
2700 ins
->texture
.cont
= 0;
2701 ins
->texture
.last
= 1;
2704 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2709 DBG("Unknown midgard instruction type\n");
2716 /* ALU instructions can inline or embed constants, which decreases register
2717 * pressure and saves space. */
2719 #define CONDITIONAL_ATTACH(src) { \
2720 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2723 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2724 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2729 inline_alu_constants(compiler_context
*ctx
)
2731 mir_foreach_instr(ctx
, alu
) {
2732 /* Other instructions cannot inline constants */
2733 if (alu
->type
!= TAG_ALU_4
) continue;
2735 /* If there is already a constant here, we can do nothing */
2736 if (alu
->has_constants
) continue;
2738 CONDITIONAL_ATTACH(src0
);
2740 if (!alu
->has_constants
) {
2741 CONDITIONAL_ATTACH(src1
)
2742 } else if (!alu
->inline_constant
) {
2743 /* Corner case: _two_ vec4 constants, for instance with a
2744 * csel. For this case, we can only use a constant
2745 * register for one, we'll have to emit a move for the
2746 * other. Note, if both arguments are constants, then
2747 * necessarily neither argument depends on the value of
2748 * any particular register. As the destination register
2749 * will be wiped, that means we can spill the constant
2750 * to the destination register.
2753 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2754 unsigned scratch
= alu
->ssa_args
.dest
;
2757 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2758 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2760 /* Force a break XXX Defer r31 writes */
2761 ins
.unit
= UNIT_VLUT
;
2763 /* Set the source */
2764 alu
->ssa_args
.src1
= scratch
;
2766 /* Inject us -before- the last instruction which set r31 */
2767 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2773 /* Midgard supports two types of constants, embedded constants (128-bit) and
2774 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2775 * constants can be demoted to inline constants, for space savings and
2776 * sometimes a performance boost */
2779 embedded_to_inline_constant(compiler_context
*ctx
)
2781 mir_foreach_instr(ctx
, ins
) {
2782 if (!ins
->has_constants
) continue;
2784 if (ins
->ssa_args
.inline_constant
) continue;
2786 /* Blend constants must not be inlined by definition */
2787 if (ins
->has_blend_constant
) continue;
2789 /* src1 cannot be an inline constant due to encoding
2790 * restrictions. So, if possible we try to flip the arguments
2793 int op
= ins
->alu
.op
;
2795 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2796 /* Flip based on op. Fallthrough intentional */
2799 /* These ops require an operational change to flip their arguments TODO */
2800 case midgard_alu_op_flt
:
2801 case midgard_alu_op_fle
:
2802 case midgard_alu_op_ilt
:
2803 case midgard_alu_op_ile
:
2804 case midgard_alu_op_fcsel
:
2805 case midgard_alu_op_icsel
:
2806 case midgard_alu_op_isub
:
2807 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2810 /* These ops are commutative and Just Flip */
2811 case midgard_alu_op_fne
:
2812 case midgard_alu_op_fadd
:
2813 case midgard_alu_op_fmul
:
2814 case midgard_alu_op_fmin
:
2815 case midgard_alu_op_fmax
:
2816 case midgard_alu_op_iadd
:
2817 case midgard_alu_op_imul
:
2818 case midgard_alu_op_feq
:
2819 case midgard_alu_op_ieq
:
2820 case midgard_alu_op_ine
:
2821 case midgard_alu_op_iand
:
2822 case midgard_alu_op_ior
:
2823 case midgard_alu_op_ixor
:
2824 /* Flip the SSA numbers */
2825 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2826 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2828 /* And flip the modifiers */
2832 src_temp
= ins
->alu
.src2
;
2833 ins
->alu
.src2
= ins
->alu
.src1
;
2834 ins
->alu
.src1
= src_temp
;
2841 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2842 /* Extract the source information */
2844 midgard_vector_alu_src
*src
;
2845 int q
= ins
->alu
.src2
;
2846 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2849 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2850 int component
= src
->swizzle
& 3;
2852 /* Scale constant appropriately, if we can legally */
2853 uint16_t scaled_constant
= 0;
2855 /* XXX: Check legality */
2856 if (midgard_is_integer_op(op
)) {
2857 /* TODO: Inline integer */
2860 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2861 scaled_constant
= (uint16_t) iconstants
[component
];
2863 /* Constant overflow after resize */
2864 if (scaled_constant
!= iconstants
[component
])
2867 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2870 /* We don't know how to handle these with a constant */
2872 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2873 DBG("Bailing inline constant...\n");
2877 /* Make sure that the constant is not itself a
2878 * vector by checking if all accessed values
2879 * (by the swizzle) are the same. */
2881 uint32_t *cons
= (uint32_t *) ins
->constants
;
2882 uint32_t value
= cons
[component
];
2884 bool is_vector
= false;
2885 unsigned mask
= effective_writemask(&ins
->alu
);
2887 for (int c
= 1; c
< 4; ++c
) {
2888 /* We only care if this component is actually used */
2889 if (!(mask
& (1 << c
)))
2892 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2894 if (test
!= value
) {
2903 /* Get rid of the embedded constant */
2904 ins
->has_constants
= false;
2905 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2906 ins
->ssa_args
.inline_constant
= true;
2907 ins
->inline_constant
= scaled_constant
;
2912 /* Map normal SSA sources to other SSA sources / fixed registers (like
2916 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2918 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2921 /* Remove entry in leftovers to avoid a redunant fmov */
2923 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2926 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2928 /* Assign the alias map */
2934 #define AS_SRC(to, u) \
2935 int q##to = ins->alu.src2; \
2936 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2938 /* Removing unused moves is necessary to clean up the texture pipeline results.
2940 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2943 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2945 mir_foreach_instr_in_block_safe(block
, ins
) {
2946 if (ins
->type
!= TAG_ALU_4
) continue;
2948 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2950 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2952 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2954 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2956 mir_remove_instruction(ins
);
2960 /* The following passes reorder MIR instructions to enable better scheduling */
2963 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2965 mir_foreach_instr_in_block_safe(block
, ins
) {
2966 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2968 /* We've found a load/store op. Check if next is also load/store. */
2969 midgard_instruction
*next_op
= mir_next_op(ins
);
2970 if (&next_op
->link
!= &block
->instructions
) {
2971 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2972 /* If so, we're done since we're a pair */
2973 ins
= mir_next_op(ins
);
2977 /* Maximum search distance to pair, to avoid register pressure disasters */
2978 int search_distance
= 8;
2980 /* Otherwise, we have an orphaned load/store -- search for another load */
2981 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2982 /* Terminate search if necessary */
2983 if (!(search_distance
--)) break;
2985 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2987 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2989 /* We found one! Move it up to pair and remove it from the old location */
2991 mir_insert_instruction_before(ins
, *c
);
2992 mir_remove_instruction(c
);
3000 /* Emit varying stores late */
3003 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3004 /* Iterate in reverse to get the final write, rather than the first */
3006 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3007 /* Check if what we just wrote needs a store */
3008 int idx
= ins
->ssa_args
.dest
;
3009 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3011 if (!varying
) continue;
3015 /* We need to store to the appropriate varying, so emit the
3018 /* TODO: Integrate with special purpose RA (and scheduler?) */
3019 bool high_varying_register
= false;
3021 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3023 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3024 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3026 mir_insert_instruction_before(mir_next_op(ins
), st
);
3027 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3029 /* We no longer need to store this varying */
3030 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3034 /* If there are leftovers after the below pass, emit actual fmov
3035 * instructions for the slow-but-correct path */
3038 emit_leftover_move(compiler_context
*ctx
)
3040 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3041 int base
= ((uintptr_t) leftover
->key
) - 1;
3044 map_ssa_to_alias(ctx
, &mapped
);
3045 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3050 actualise_ssa_to_alias(compiler_context
*ctx
)
3052 mir_foreach_instr(ctx
, ins
) {
3053 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3054 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3057 emit_leftover_move(ctx
);
3060 /* Vertex shaders do not write gl_Position as is; instead, they write a
3061 * transformed screen space position as a varying. See section 12.5 "Coordinate
3062 * Transformation" of the ES 3.2 full specification for details.
3064 * This transformation occurs early on, as NIR and prior to optimisation, in
3065 * order to take advantage of NIR optimisation passes of the transform itself.
3069 write_transformed_position(nir_builder
*b
, nir_src input_point_src
)
3071 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
3072 nir_ssa_def
*scale
= nir_load_viewport_scale(b
);
3073 nir_ssa_def
*offset
= nir_load_viewport_offset(b
);
3075 /* World space to normalised device coordinates to screen space */
3077 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
3078 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
3079 nir_ssa_def
*screen
= nir_fadd(b
, nir_fmul(b
, ndc_point
, scale
), offset
);
3081 /* gl_Position will be written out in screenspace xyz, with w set to
3082 * the reciprocal we computed earlier. The transformed w component is
3083 * then used for perspective-correct varying interpolation. The
3084 * transformed w component must preserve its original sign; this is
3085 * used in depth clipping computations */
3087 nir_ssa_def
*screen_space
= nir_vec4(b
,
3088 nir_channel(b
, screen
, 0),
3089 nir_channel(b
, screen
, 1),
3090 nir_channel(b
, screen
, 2),
3093 /* Finally, write out the transformed values to the varying */
3095 nir_intrinsic_instr
*store
;
3096 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
3097 store
->num_components
= 4;
3098 nir_intrinsic_set_base(store
, 0);
3099 nir_intrinsic_set_write_mask(store
, 0xf);
3100 store
->src
[0].ssa
= screen_space
;
3101 store
->src
[0].is_ssa
= true;
3102 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
3103 nir_builder_instr_insert(b
, &store
->instr
);
3107 transform_position_writes(nir_shader
*shader
)
3109 nir_foreach_function(func
, shader
) {
3110 nir_foreach_block(block
, func
->impl
) {
3111 nir_foreach_instr_safe(instr
, block
) {
3112 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
3114 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
3115 nir_variable
*out
= NULL
;
3117 switch (intr
->intrinsic
) {
3118 case nir_intrinsic_store_output
:
3119 /* already had i/o lowered.. lookup the matching output var: */
3120 nir_foreach_variable(var
, &shader
->outputs
) {
3121 int drvloc
= var
->data
.driver_location
;
3123 if (nir_intrinsic_base(intr
) == drvloc
) {
3137 if (out
->data
.mode
!= nir_var_shader_out
)
3140 if (out
->data
.location
!= VARYING_SLOT_POS
)
3144 nir_builder_init(&b
, func
->impl
);
3145 b
.cursor
= nir_before_instr(instr
);
3147 write_transformed_position(&b
, intr
->src
[0]);
3148 nir_instr_remove(instr
);
3155 emit_fragment_epilogue(compiler_context
*ctx
)
3157 /* Special case: writing out constants requires us to include the move
3158 * explicitly now, so shove it into r0 */
3160 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3162 if (constant_value
) {
3163 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3164 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3165 emit_mir_instruction(ctx
, ins
);
3168 /* Perform the actual fragment writeout. We have two writeout/branch
3169 * instructions, forming a loop until writeout is successful as per the
3170 * docs. TODO: gl_FragDepth */
3172 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3173 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3176 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3177 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3178 * with the int8 analogue to the fragment epilogue */
3181 emit_blend_epilogue(compiler_context
*ctx
)
3183 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3185 midgard_instruction scale
= {
3188 .inline_constant
= _mesa_float_to_half(255.0),
3190 .src0
= SSA_FIXED_REGISTER(0),
3191 .src1
= SSA_UNUSED_0
,
3192 .dest
= SSA_FIXED_REGISTER(24),
3193 .inline_constant
= true
3196 .op
= midgard_alu_op_fmul
,
3197 .reg_mode
= midgard_reg_mode_full
,
3198 .dest_override
= midgard_dest_override_lower
,
3200 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3201 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3205 emit_mir_instruction(ctx
, scale
);
3207 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3209 midgard_vector_alu_src alu_src
= blank_alu_src
;
3210 alu_src
.half
= true;
3212 midgard_instruction f2u8
= {
3215 .src0
= SSA_FIXED_REGISTER(24),
3216 .src1
= SSA_UNUSED_0
,
3217 .dest
= SSA_FIXED_REGISTER(0),
3218 .inline_constant
= true
3221 .op
= midgard_alu_op_f2u8
,
3222 .reg_mode
= midgard_reg_mode_half
,
3223 .dest_override
= midgard_dest_override_lower
,
3224 .outmod
= midgard_outmod_pos
,
3226 .src1
= vector_alu_srco_unsigned(alu_src
),
3227 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3231 emit_mir_instruction(ctx
, f2u8
);
3233 /* vmul.imov.quarter r0, r0, r0 */
3235 midgard_instruction imov_8
= {
3238 .src0
= SSA_UNUSED_1
,
3239 .src1
= SSA_FIXED_REGISTER(0),
3240 .dest
= SSA_FIXED_REGISTER(0),
3243 .op
= midgard_alu_op_imov
,
3244 .reg_mode
= midgard_reg_mode_quarter
,
3245 .dest_override
= midgard_dest_override_none
,
3247 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3248 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3252 /* Emit branch epilogue with the 8-bit move as the source */
3254 emit_mir_instruction(ctx
, imov_8
);
3255 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3257 emit_mir_instruction(ctx
, imov_8
);
3258 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3261 static midgard_block
*
3262 emit_block(compiler_context
*ctx
, nir_block
*block
)
3264 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3265 list_addtail(&this_block
->link
, &ctx
->blocks
);
3267 this_block
->is_scheduled
= false;
3270 ctx
->texture_index
[0] = -1;
3271 ctx
->texture_index
[1] = -1;
3273 /* Set up current block */
3274 list_inithead(&this_block
->instructions
);
3275 ctx
->current_block
= this_block
;
3277 nir_foreach_instr(instr
, block
) {
3278 emit_instr(ctx
, instr
);
3279 ++ctx
->instruction_count
;
3282 inline_alu_constants(ctx
);
3283 embedded_to_inline_constant(ctx
);
3285 /* Perform heavylifting for aliasing */
3286 actualise_ssa_to_alias(ctx
);
3288 midgard_emit_store(ctx
, this_block
);
3289 midgard_eliminate_orphan_moves(ctx
, this_block
);
3290 midgard_pair_load_store(ctx
, this_block
);
3292 /* Append fragment shader epilogue (value writeout) */
3293 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3294 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3296 emit_blend_epilogue(ctx
);
3298 emit_fragment_epilogue(ctx
);
3302 /* Fallthrough save */
3303 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3305 if (block
== nir_start_block(ctx
->func
->impl
))
3306 ctx
->initial_block
= this_block
;
3308 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3309 ctx
->final_block
= this_block
;
3311 /* Allow the next control flow to access us retroactively, for
3313 ctx
->current_block
= this_block
;
3315 /* Document the fallthrough chain */
3316 ctx
->previous_source_block
= this_block
;
3321 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3324 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3326 /* Conditional branches expect the condition in r31.w; emit a move for
3327 * that in the _previous_ block (which is the current block). */
3328 emit_condition(ctx
, &nif
->condition
, true);
3330 /* Speculatively emit the branch, but we can't fill it in until later */
3331 EMIT(branch
, true, true);
3332 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3334 /* Emit the two subblocks */
3335 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3337 /* Emit a jump from the end of the then block to the end of the else */
3338 EMIT(branch
, false, false);
3339 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3341 /* Emit second block, and check if it's empty */
3343 int else_idx
= ctx
->block_count
;
3344 int count_in
= ctx
->instruction_count
;
3345 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3346 int after_else_idx
= ctx
->block_count
;
3348 /* Now that we have the subblocks emitted, fix up the branches */
3353 if (ctx
->instruction_count
== count_in
) {
3354 /* The else block is empty, so don't emit an exit jump */
3355 mir_remove_instruction(then_exit
);
3356 then_branch
->branch
.target_block
= after_else_idx
;
3358 then_branch
->branch
.target_block
= else_idx
;
3359 then_exit
->branch
.target_block
= after_else_idx
;
3364 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3366 /* Remember where we are */
3367 midgard_block
*start_block
= ctx
->current_block
;
3369 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3370 * single current_loop variable, maybe we need a stack */
3372 int loop_idx
= ++ctx
->current_loop
;
3374 /* Get index from before the body so we can loop back later */
3375 int start_idx
= ctx
->block_count
;
3377 /* Emit the body itself */
3378 emit_cf_list(ctx
, &nloop
->body
);
3380 /* Branch back to loop back */
3381 struct midgard_instruction br_back
= v_branch(false, false);
3382 br_back
.branch
.target_block
= start_idx
;
3383 emit_mir_instruction(ctx
, br_back
);
3385 /* Find the index of the block about to follow us (note: we don't add
3386 * one; blocks are 0-indexed so we get a fencepost problem) */
3387 int break_block_idx
= ctx
->block_count
;
3389 /* Fix up the break statements we emitted to point to the right place,
3390 * now that we can allocate a block number for them */
3392 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3393 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3394 print_mir_block(block
);
3395 mir_foreach_instr_in_block(block
, ins
) {
3396 if (ins
->type
!= TAG_ALU_4
) continue;
3397 if (!ins
->compact_branch
) continue;
3398 if (ins
->prepacked_branch
) continue;
3400 /* We found a branch -- check the type to see if we need to do anything */
3401 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3403 /* It's a break! Check if it's our break */
3404 if (ins
->branch
.target_break
!= loop_idx
) continue;
3406 /* Okay, cool, we're breaking out of this loop.
3407 * Rewrite from a break to a goto */
3409 ins
->branch
.target_type
= TARGET_GOTO
;
3410 ins
->branch
.target_block
= break_block_idx
;
3415 static midgard_block
*
3416 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3418 midgard_block
*start_block
= NULL
;
3420 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3421 switch (node
->type
) {
3422 case nir_cf_node_block
: {
3423 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3426 start_block
= block
;
3431 case nir_cf_node_if
:
3432 emit_if(ctx
, nir_cf_node_as_if(node
));
3435 case nir_cf_node_loop
:
3436 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3439 case nir_cf_node_function
:
3448 /* Due to lookahead, we need to report the first tag executed in the command
3449 * stream and in branch targets. An initial block might be empty, so iterate
3450 * until we find one that 'works' */
3453 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3455 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3457 unsigned first_tag
= 0;
3460 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3462 if (initial_bundle
) {
3463 first_tag
= initial_bundle
->tag
;
3467 /* Initial block is empty, try the next block */
3468 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3469 } while(initial_block
!= NULL
);
3476 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3478 struct util_dynarray
*compiled
= &program
->compiled
;
3480 midgard_debug
= debug_get_option_midgard_debug();
3482 compiler_context ictx
= {
3484 .stage
= nir
->info
.stage
,
3486 .is_blend
= is_blend
,
3487 .blend_constant_offset
= -1,
3489 .alpha_ref
= program
->alpha_ref
3492 compiler_context
*ctx
= &ictx
;
3494 /* TODO: Decide this at runtime */
3495 ctx
->uniform_cutoff
= 8;
3497 /* Assign var locations early, so the epilogue can use them if necessary */
3499 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3500 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3501 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, uniform_type_size
);
3503 /* Initialize at a global (not block) level hash tables */
3505 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3506 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3507 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3508 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3509 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3510 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3511 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3513 /* Record the varying mapping for the command stream's bookkeeping */
3515 struct exec_list
*varyings
=
3516 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3518 nir_foreach_variable(var
, varyings
) {
3519 unsigned loc
= var
->data
.driver_location
;
3520 program
->varyings
[loc
] = var
->data
.location
;
3523 /* Lower vars -- not I/O -- before epilogue */
3525 NIR_PASS_V(nir
, nir_lower_var_copies
);
3526 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3527 NIR_PASS_V(nir
, nir_split_var_copies
);
3528 NIR_PASS_V(nir
, nir_lower_var_copies
);
3529 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3530 NIR_PASS_V(nir
, nir_lower_var_copies
);
3531 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3533 NIR_PASS_V(nir
, nir_lower_io
, nir_var_uniform
, uniform_type_size
, 0);
3534 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
& ~nir_var_uniform
, glsl_type_size
, 0);
3536 /* Append vertex epilogue before optimisation, so the epilogue itself
3539 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3540 transform_position_writes(nir
);
3542 /* Optimisation passes */
3546 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3547 nir_print_shader(nir
, stdout
);
3550 /* Assign sysvals and counts, now that we're sure
3551 * (post-optimisation) */
3553 midgard_nir_assign_sysvals(ctx
, nir
);
3555 program
->uniform_count
= nir
->num_uniforms
;
3556 program
->sysval_count
= ctx
->sysval_count
;
3557 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3559 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3560 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3562 nir_foreach_function(func
, nir
) {
3566 list_inithead(&ctx
->blocks
);
3567 ctx
->block_count
= 0;
3570 emit_cf_list(ctx
, &func
->impl
->body
);
3571 emit_block(ctx
, func
->impl
->end_block
);
3573 break; /* TODO: Multi-function shaders */
3576 util_dynarray_init(compiled
, NULL
);
3579 schedule_program(ctx
);
3581 /* Now that all the bundles are scheduled and we can calculate block
3582 * sizes, emit actual branch instructions rather than placeholders */
3584 int br_block_idx
= 0;
3586 mir_foreach_block(ctx
, block
) {
3587 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3588 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3589 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3591 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3593 if (ins
->prepacked_branch
) continue;
3595 /* Parse some basic branch info */
3596 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3597 bool is_conditional
= ins
->branch
.conditional
;
3598 bool is_inverted
= ins
->branch
.invert_conditional
;
3599 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3601 /* Determine the block we're jumping to */
3602 int target_number
= ins
->branch
.target_block
;
3604 /* Report the destination tag. Discards don't need this */
3605 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3607 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3608 int quadword_offset
= 0;
3611 /* Jump to the end of the shader. We
3612 * need to include not only the
3613 * following blocks, but also the
3614 * contents of our current block (since
3615 * discard can come in the middle of
3618 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3620 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3621 quadword_offset
+= quadword_size(bun
->tag
);
3624 mir_foreach_block_from(ctx
, blk
, b
) {
3625 quadword_offset
+= b
->quadword_count
;
3628 } else if (target_number
> br_block_idx
) {
3631 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3632 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3635 quadword_offset
+= blk
->quadword_count
;
3638 /* Jump backwards */
3640 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3641 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3644 quadword_offset
-= blk
->quadword_count
;
3648 /* Unconditional extended branches (far jumps)
3649 * have issues, so we always use a conditional
3650 * branch, setting the condition to always for
3651 * unconditional. For compact unconditional
3652 * branches, cond isn't used so it doesn't
3653 * matter what we pick. */
3655 midgard_condition cond
=
3656 !is_conditional
? midgard_condition_always
:
3657 is_inverted
? midgard_condition_false
:
3658 midgard_condition_true
;
3660 midgard_jmp_writeout_op op
=
3661 is_discard
? midgard_jmp_writeout_op_discard
:
3662 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3663 midgard_jmp_writeout_op_branch_cond
;
3666 midgard_branch_extended branch
=
3667 midgard_create_branch_extended(
3672 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3673 } else if (is_conditional
|| is_discard
) {
3674 midgard_branch_cond branch
= {
3676 .dest_tag
= dest_tag
,
3677 .offset
= quadword_offset
,
3681 assert(branch
.offset
== quadword_offset
);
3683 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3685 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3687 midgard_branch_uncond branch
= {
3689 .dest_tag
= dest_tag
,
3690 .offset
= quadword_offset
,
3694 assert(branch
.offset
== quadword_offset
);
3696 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3704 /* Emit flat binary from the instruction arrays. Iterate each block in
3705 * sequence. Save instruction boundaries such that lookahead tags can
3706 * be assigned easily */
3708 /* Cache _all_ bundles in source order for lookahead across failed branches */
3710 int bundle_count
= 0;
3711 mir_foreach_block(ctx
, block
) {
3712 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3714 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3716 mir_foreach_block(ctx
, block
) {
3717 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3718 source_order_bundles
[bundle_idx
++] = bundle
;
3722 int current_bundle
= 0;
3724 mir_foreach_block(ctx
, block
) {
3725 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3728 if (current_bundle
+ 1 < bundle_count
) {
3729 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3731 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3738 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3742 /* TODO: Free deeper */
3743 //util_dynarray_fini(&block->instructions);
3746 free(source_order_bundles
);
3748 /* Report the very first tag executed */
3749 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3751 /* Deal with off-by-one related to the fencepost problem */
3752 program
->work_register_count
= ctx
->work_registers
+ 1;
3754 program
->can_discard
= ctx
->can_discard
;
3755 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3757 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3759 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3760 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);