2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "compiler/glsl/glsl_to_nir.h"
34 #include "compiler/nir_types.h"
35 #include "main/imports.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/register_allocate.h"
39 #include "util/u_dynarray.h"
40 #include "util/list.h"
41 #include "main/mtypes.h"
44 #include "midgard_nir.h"
45 #include "midgard_compile.h"
48 #include "disassemble.h"
50 /* Instruction arguments represented as block-local SSA indices, rather than
51 * registers. Negative values mean unused. */
58 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
59 * in. Only valid for ALU ops. */
63 /* Forward declare so midgard_branch can reference */
66 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
67 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
68 * instruction is actually a discard op. */
71 #define TARGET_BREAK 1
72 #define TARGET_CONTINUE 2
73 #define TARGET_DISCARD 3
75 typedef struct midgard_branch
{
76 /* If conditional, the condition is specified in r31.w */
79 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
80 bool invert_conditional
;
82 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
85 /* The actual target */
93 /* Generic in-memory data type repesenting a single logical instruction, rather
94 * than a single instruction group. This is the preferred form for code gen.
95 * Multiple midgard_insturctions will later be combined during scheduling,
96 * though this is not represented in this structure. Its format bridges
97 * the low-level binary representation with the higher level semantic meaning.
99 * Notably, it allows registers to be specified as block local SSA, for code
100 * emitted before the register allocation pass.
103 typedef struct midgard_instruction
{
104 /* Must be first for casting */
105 struct list_head link
;
107 unsigned type
; /* ALU, load/store, texture */
109 /* If the register allocator has not run yet... */
112 /* Special fields for an ALU instruction */
113 midgard_reg_info registers
;
115 /* I.e. (1 << alu_bit) */
120 uint16_t inline_constant
;
121 bool has_blend_constant
;
125 bool prepacked_branch
;
128 midgard_load_store_word load_store
;
129 midgard_vector_alu alu
;
130 midgard_texture_word texture
;
131 midgard_branch_extended branch_extended
;
134 /* General branch, rather than packed br_compact. Higher level
135 * than the other components */
136 midgard_branch branch
;
138 } midgard_instruction
;
140 typedef struct midgard_block
{
141 /* Link to next block. Must be first for mir_get_block */
142 struct list_head link
;
144 /* List of midgard_instructions emitted for the current block */
145 struct list_head instructions
;
149 /* List of midgard_bundles emitted (after the scheduler has run) */
150 struct util_dynarray bundles
;
152 /* Number of quadwords _actually_ emitted, as determined after scheduling */
153 unsigned quadword_count
;
155 struct midgard_block
*next_fallthrough
;
158 /* Helpers to generate midgard_instruction's using macro magic, since every
159 * driver seems to do it that way */
161 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
163 #define M_LOAD_STORE(name, rname, uname) \
164 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
165 midgard_instruction i = { \
166 .type = TAG_LOAD_STORE_4, \
173 .op = midgard_op_##name, \
175 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W), \
183 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
184 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
186 const midgard_vector_alu_src blank_alu_src
= {
187 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
190 const midgard_scalar_alu_src blank_scalar_alu_src
= {
194 /* Used for encoding the unused source of 1-op instructions */
195 const midgard_vector_alu_src zero_alu_src
= { 0 };
197 /* Coerce structs to integer */
200 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
203 memcpy(&u
, &src
, sizeof(src
));
207 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
208 * the corresponding Midgard source */
210 static midgard_vector_alu_src
211 vector_alu_modifiers(nir_alu_src
*src
)
213 if (!src
) return blank_alu_src
;
215 midgard_vector_alu_src alu_src
= {
217 .negate
= src
->negate
,
220 .half
= 0, /* TODO */
221 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
227 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
229 static midgard_instruction
230 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
232 midgard_instruction ins
= {
235 .src0
= SSA_UNUSED_1
,
240 .op
= midgard_alu_op_fmov
,
241 .reg_mode
= midgard_reg_mode_full
,
242 .dest_override
= midgard_dest_override_none
,
244 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
245 .src2
= vector_alu_srco_unsigned(mod
)
252 /* load/store instructions have both 32-bit and 16-bit variants, depending on
253 * whether we are using vectors composed of highp or mediump. At the moment, we
254 * don't support half-floats -- this requires changes in other parts of the
255 * compiler -- therefore the 16-bit versions are commented out. */
257 //M_LOAD(load_attr_16);
258 M_LOAD(load_attr_32
);
259 //M_LOAD(load_vary_16);
260 M_LOAD(load_vary_32
);
261 //M_LOAD(load_uniform_16);
262 M_LOAD(load_uniform_32
);
263 M_LOAD(load_color_buffer_8
);
264 //M_STORE(store_vary_16);
265 M_STORE(store_vary_32
);
267 static midgard_instruction
268 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
270 midgard_branch_cond branch
= {
278 memcpy(&compact
, &branch
, sizeof(branch
));
280 midgard_instruction ins
= {
282 .unit
= ALU_ENAB_BR_COMPACT
,
283 .prepacked_branch
= true,
284 .compact_branch
= true,
285 .br_compact
= compact
288 if (op
== midgard_jmp_writeout_op_writeout
)
294 static midgard_instruction
295 v_branch(bool conditional
, bool invert
)
297 midgard_instruction ins
= {
299 .unit
= ALU_ENAB_BRANCH
,
300 .compact_branch
= true,
302 .conditional
= conditional
,
303 .invert_conditional
= invert
310 static midgard_branch_extended
311 midgard_create_branch_extended( midgard_condition cond
,
312 midgard_jmp_writeout_op op
,
314 signed quadword_offset
)
316 /* For unclear reasons, the condition code is repeated 8 times */
317 uint16_t duplicated_cond
=
327 midgard_branch_extended branch
= {
329 .dest_tag
= dest_tag
,
330 .offset
= quadword_offset
,
331 .cond
= duplicated_cond
337 typedef struct midgard_bundle
{
338 /* Tag for the overall bundle */
341 /* Instructions contained by the bundle */
342 int instruction_count
;
343 midgard_instruction instructions
[5];
345 /* Bundle-wide ALU configuration */
348 bool has_embedded_constants
;
350 bool has_blend_constant
;
352 uint16_t register_words
[8];
353 int register_words_count
;
355 uint64_t body_words
[8];
357 int body_words_count
;
360 typedef struct compiler_context
{
362 gl_shader_stage stage
;
364 /* Is internally a blend shader? Depends on stage == FRAGMENT */
367 /* Tracking for blend constant patching */
368 int blend_constant_number
;
369 int blend_constant_offset
;
371 /* Current NIR function */
374 /* Unordered list of midgard_blocks */
376 struct list_head blocks
;
378 midgard_block
*initial_block
;
379 midgard_block
*previous_source_block
;
380 midgard_block
*final_block
;
382 /* List of midgard_instructions emitted for the current block */
383 midgard_block
*current_block
;
385 /* The index corresponding to the current loop, e.g. for breaks/contineus */
388 /* Constants which have been loaded, for later inlining */
389 struct hash_table_u64
*ssa_constants
;
391 /* SSA indices to be outputted to corresponding varying offset */
392 struct hash_table_u64
*ssa_varyings
;
394 /* SSA values / registers which have been aliased. Naively, these
395 * demand a fmov output; instead, we alias them in a later pass to
396 * avoid the wasted op.
398 * A note on encoding: to avoid dynamic memory management here, rather
399 * than ampping to a pointer, we map to the source index; the key
400 * itself is just the destination index. */
402 struct hash_table_u64
*ssa_to_alias
;
403 struct set
*leftover_ssa_to_alias
;
405 /* Actual SSA-to-register for RA */
406 struct hash_table_u64
*ssa_to_register
;
408 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
409 struct hash_table_u64
*hash_to_temp
;
413 /* Uniform IDs for mdg */
414 struct hash_table_u64
*uniform_nir_to_mdg
;
417 struct hash_table_u64
*varying_nir_to_mdg
;
420 /* Just the count of the max register used. Higher count => higher
421 * register pressure */
424 /* Used for cont/last hinting. Increase when a tex op is added.
425 * Decrease when a tex op is removed. */
426 int texture_op_count
;
428 /* Mapping of texture register -> SSA index for unaliasing */
429 int texture_index
[2];
431 /* Count of special uniforms (viewport, etc) in vec4 units */
432 int special_uniforms
;
434 /* If any path hits a discard instruction */
437 /* The number of uniforms allowable for the fast path */
440 /* Count of instructions emitted from NIR overall, across all blocks */
441 int instruction_count
;
443 /* Alpha ref value passed in */
446 /* The index corresponding to the fragment output */
447 unsigned fragment_output
;
450 /* Append instruction to end of current block */
452 static midgard_instruction
*
453 mir_upload_ins(struct midgard_instruction ins
)
455 midgard_instruction
*heap
= malloc(sizeof(ins
));
456 memcpy(heap
, &ins
, sizeof(ins
));
461 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
463 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
467 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
469 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
473 mir_remove_instruction(struct midgard_instruction
*ins
)
475 list_del(&ins
->link
);
478 static midgard_instruction
*
479 mir_prev_op(struct midgard_instruction
*ins
)
481 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
484 static midgard_instruction
*
485 mir_next_op(struct midgard_instruction
*ins
)
487 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
490 static midgard_block
*
491 mir_next_block(struct midgard_block
*blk
)
493 return list_first_entry(&(blk
->link
), midgard_block
, link
);
497 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
498 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
500 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
501 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
502 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
503 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
504 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
505 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
508 static midgard_instruction
*
509 mir_last_in_block(struct midgard_block
*block
)
511 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
514 static midgard_block
*
515 mir_get_block(compiler_context
*ctx
, int idx
)
517 struct list_head
*lst
= &ctx
->blocks
;
522 return (struct midgard_block
*) lst
;
525 /* Pretty printer for internal Midgard IR */
528 print_mir_source(int source
)
530 if (source
>= SSA_FIXED_MINIMUM
) {
531 /* Specific register */
532 int reg
= SSA_REG_FROM_FIXED(source
);
534 /* TODO: Moving threshold */
535 if (reg
> 16 && reg
< 24)
536 printf("u%d", 23 - reg
);
540 printf("%d", source
);
545 print_mir_instruction(midgard_instruction
*ins
)
551 midgard_alu_op op
= ins
->alu
.op
;
552 const char *name
= alu_opcode_names
[op
];
555 printf("%d.", ins
->unit
);
557 printf("%s", name
? name
: "??");
561 case TAG_LOAD_STORE_4
: {
562 midgard_load_store_op op
= ins
->load_store
.op
;
563 const char *name
= load_store_opcode_names
[op
];
570 case TAG_TEXTURE_4
: {
579 ssa_args
*args
= &ins
->ssa_args
;
581 printf(" %d, ", args
->dest
);
583 print_mir_source(args
->src0
);
586 if (args
->inline_constant
)
587 printf("#%d", ins
->inline_constant
);
589 print_mir_source(args
->src1
);
591 if (ins
->has_constants
)
592 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
598 print_mir_block(midgard_block
*block
)
602 mir_foreach_instr_in_block(block
, ins
) {
603 print_mir_instruction(ins
);
612 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
614 ins
->has_constants
= true;
615 memcpy(&ins
->constants
, constants
, 16);
617 /* If this is the special blend constant, mark this instruction */
619 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
620 ins
->has_blend_constant
= true;
624 glsl_type_size(const struct glsl_type
*type
)
626 return glsl_count_attribute_slots(type
, false);
629 /* Lower fdot2 to a vector multiplication followed by channel addition */
631 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
633 if (alu
->op
!= nir_op_fdot2
)
636 b
->cursor
= nir_before_instr(&alu
->instr
);
638 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
639 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
641 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
643 nir_ssa_def
*sum
= nir_fadd(b
,
644 nir_channel(b
, product
, 0),
645 nir_channel(b
, product
, 1));
647 /* Replace the fdot2 with this sum */
648 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
652 midgard_nir_lower_fdot2(nir_shader
*shader
)
654 bool progress
= false;
656 nir_foreach_function(function
, shader
) {
657 if (!function
->impl
) continue;
660 nir_builder
*b
= &_b
;
661 nir_builder_init(b
, function
->impl
);
663 nir_foreach_block(block
, function
->impl
) {
664 nir_foreach_instr_safe(instr
, block
) {
665 if (instr
->type
!= nir_instr_type_alu
) continue;
667 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
668 midgard_nir_lower_fdot2_body(b
, alu
);
674 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
682 optimise_nir(nir_shader
*nir
)
686 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
687 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
689 nir_lower_tex_options lower_tex_options
= {
693 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
698 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
699 NIR_PASS(progress
, nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
700 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
701 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
703 NIR_PASS(progress
, nir
, nir_copy_prop
);
704 NIR_PASS(progress
, nir
, nir_opt_dce
);
705 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
706 NIR_PASS(progress
, nir
, nir_opt_cse
);
707 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
708 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
709 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
710 NIR_PASS(progress
, nir
, nir_opt_undef
);
711 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
714 nir_var_function_temp
);
716 /* TODO: Enable vectorize when merged upstream */
717 // NIR_PASS(progress, nir, nir_opt_vectorize);
720 /* Must be run at the end to prevent creation of fsin/fcos ops */
721 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
726 NIR_PASS(progress
, nir
, nir_opt_dce
);
727 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
728 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
729 NIR_PASS(progress
, nir
, nir_copy_prop
);
732 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
735 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_all_source_mods
);
736 NIR_PASS(progress
, nir
, nir_copy_prop
);
737 NIR_PASS(progress
, nir
, nir_opt_dce
);
739 /* Take us out of SSA */
740 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
741 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
743 /* We are a vector architecture; write combine where possible */
744 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
745 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
747 NIR_PASS(progress
, nir
, nir_opt_dce
);
750 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
751 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
752 * r0. See the comments in compiler_context */
755 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
757 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
758 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
761 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
764 unalias_ssa(compiler_context
*ctx
, int dest
)
766 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
767 /* TODO: Remove from leftover or no? */
771 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
773 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
777 midgard_is_pinned(compiler_context
*ctx
, int index
)
779 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
782 /* Do not actually emit a load; instead, cache the constant for inlining */
785 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
787 nir_ssa_def def
= instr
->def
;
789 float *v
= ralloc_array(NULL
, float, 4);
790 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
791 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
794 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
798 expand_writemask(unsigned mask
)
802 for (int i
= 0; i
< 4; ++i
)
810 squeeze_writemask(unsigned mask
)
814 for (int i
= 0; i
< 4; ++i
)
815 if (mask
& (3 << (2 * i
)))
822 /* Determines effective writemask, taking quirks and expansion into account */
824 effective_writemask(midgard_vector_alu
*alu
)
826 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
829 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
831 /* If there is a fixed channel count, construct the appropriate mask */
834 return (1 << channel_count
) - 1;
836 /* Otherwise, just squeeze the existing mask */
837 return squeeze_writemask(alu
->mask
);
841 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
843 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
846 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
851 /* If no temp is find, allocate one */
852 temp
= ctx
->temp_count
++;
853 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
855 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
861 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
864 return src
->ssa
->index
;
866 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
870 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
873 return dst
->ssa
.index
;
875 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
879 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
881 return nir_src_index(ctx
, &src
->src
);
884 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
885 * a conditional test) into that register */
888 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
890 /* XXX: Force component correct */
891 int condition
= nir_src_index(ctx
, src
);
893 const midgard_vector_alu_src alu_src
= {
894 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
897 /* There is no boolean move instruction. Instead, we simulate a move by
898 * ANDing the condition with itself to get it into r31.w */
900 midgard_instruction ins
= {
902 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
906 .dest
= SSA_FIXED_REGISTER(31),
909 .op
= midgard_alu_op_iand
,
910 .reg_mode
= midgard_reg_mode_full
,
911 .dest_override
= midgard_dest_override_none
,
912 .mask
= (0x3 << 6), /* w */
913 .src1
= vector_alu_srco_unsigned(alu_src
),
914 .src2
= vector_alu_srco_unsigned(alu_src
)
918 emit_mir_instruction(ctx
, ins
);
921 #define ALU_CASE(nir, _op) \
923 op = midgard_alu_op_##_op; \
927 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
929 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
931 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
932 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
933 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
935 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
936 * supported. A few do not and are commented for now. Also, there are a
937 * number of NIR ops which Midgard does not support and need to be
938 * lowered, also TODO. This switch block emits the opcode and calling
939 * convention of the Midgard instruction; actual packing is done in
945 ALU_CASE(fadd
, fadd
);
946 ALU_CASE(fmul
, fmul
);
947 ALU_CASE(fmin
, fmin
);
948 ALU_CASE(fmax
, fmax
);
949 ALU_CASE(imin
, imin
);
950 ALU_CASE(imax
, imax
);
951 ALU_CASE(fmov
, fmov
);
952 ALU_CASE(ffloor
, ffloor
);
953 ALU_CASE(fceil
, fceil
);
954 ALU_CASE(fdot3
, fdot3
);
955 ALU_CASE(fdot4
, fdot4
);
956 ALU_CASE(iadd
, iadd
);
957 ALU_CASE(isub
, isub
);
958 ALU_CASE(imul
, imul
);
960 /* XXX: Use fmov, not imov, since imov was causing major
961 * issues with texture precision? XXX research */
962 ALU_CASE(imov
, fmov
);
971 ALU_CASE(frcp
, frcp
);
972 ALU_CASE(frsq
, frsqrt
);
973 ALU_CASE(fsqrt
, fsqrt
);
974 ALU_CASE(fexp2
, fexp2
);
975 ALU_CASE(flog2
, flog2
);
977 ALU_CASE(f2i32
, f2i
);
978 ALU_CASE(f2u32
, f2u
);
979 ALU_CASE(i2f32
, i2f
);
980 ALU_CASE(u2f32
, u2f
);
982 ALU_CASE(fsin
, fsin
);
983 ALU_CASE(fcos
, fcos
);
985 ALU_CASE(iand
, iand
);
987 ALU_CASE(ixor
, ixor
);
988 ALU_CASE(inot
, inot
);
989 ALU_CASE(ishl
, ishl
);
990 ALU_CASE(ishr
, iasr
);
991 ALU_CASE(ushr
, ilsr
);
993 ALU_CASE(ball_fequal4
, fball_eq
);
994 ALU_CASE(bany_fnequal4
, fbany_neq
);
995 ALU_CASE(ball_iequal4
, iball_eq
);
996 ALU_CASE(bany_inequal4
, ibany_neq
);
998 /* For greater-or-equal, we use less-or-equal and flip the
1002 op
= midgard_alu_op_ile
;
1004 /* Swap via temporary */
1005 nir_alu_src temp
= instr
->src
[1];
1006 instr
->src
[1] = instr
->src
[0];
1007 instr
->src
[0] = temp
;
1012 case nir_op_bcsel
: {
1013 op
= midgard_alu_op_fcsel
;
1015 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1018 emit_condition(ctx
, &instr
->src
[0].src
, false);
1020 /* The condition is the first argument; move the other
1021 * arguments up one to be a binary instruction for
1024 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1028 /* We don't have a native b2f32 instruction. Instead, like many GPUs,
1029 * we exploit booleans as 0/~0 for false/true, and correspondingly AND
1030 * by 1.0 to do the type conversion. For the moment, prime us to emit:
1032 * iand [whatever], #0
1034 * At the end of emit_alu (as MIR), we'll fix-up the constant */
1036 case nir_op_b2f32
: {
1037 op
= midgard_alu_op_iand
;
1042 printf("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1047 /* Fetch unit, quirks, etc information */
1048 unsigned opcode_props
= alu_opcode_props
[op
];
1049 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1051 /* Initialise fields common between scalar/vector instructions */
1052 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1054 /* src0 will always exist afaik, but src1 will not for 1-argument
1055 * instructions. The latter can only be fetched if the instruction
1056 * needs it, or else we may segfault. */
1058 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1059 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1061 /* Rather than use the instruction generation helpers, we do it
1062 * ourselves here to avoid the mess */
1064 midgard_instruction ins
= {
1067 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1068 .src1
= quirk_flipped_r24
? src0
: src1
,
1070 .inline_constant
= (nr_inputs
== 1) && !quirk_flipped_r24
1074 nir_alu_src
*nirmods
[2] = { NULL
};
1076 if (nr_inputs
== 2) {
1077 nirmods
[0] = &instr
->src
[0];
1078 nirmods
[1] = &instr
->src
[1];
1079 } else if (nr_inputs
== 1) {
1080 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1085 midgard_vector_alu alu
= {
1087 .reg_mode
= midgard_reg_mode_full
,
1088 .dest_override
= midgard_dest_override_none
,
1091 /* Writemask only valid for non-SSA NIR */
1092 .mask
= expand_writemask((1 << nr_components
) - 1),
1094 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1095 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1098 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1101 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1105 /* Late fixup for emulated instructions */
1107 if (instr
->op
== nir_op_b2f32
) {
1108 /* Presently, our second argument is an inline #0 constant.
1109 * Switch over to an embedded 1.0 constant (that can't fit
1110 * inline, since we're 32-bit, not 16-bit like the inline
1113 ins
.ssa_args
.inline_constant
= false;
1114 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1115 ins
.has_constants
= true;
1116 ins
.constants
[0] = 1.0;
1119 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1120 /* To avoid duplicating the lookup tables (probably), true LUT
1121 * instructions can only operate as if they were scalars. Lower
1122 * them here by changing the component. */
1124 uint8_t original_swizzle
[4];
1125 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1127 for (int i
= 0; i
< nr_components
; ++i
) {
1128 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1130 for (int j
= 0; j
< 4; ++j
)
1131 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1133 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1134 emit_mir_instruction(ctx
, ins
);
1137 emit_mir_instruction(ctx
, ins
);
1144 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1146 nir_const_value
*const_offset
;
1147 unsigned offset
, reg
;
1149 switch (instr
->intrinsic
) {
1150 case nir_intrinsic_discard_if
:
1151 emit_condition(ctx
, &instr
->src
[0], true);
1155 case nir_intrinsic_discard
: {
1156 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1157 struct midgard_instruction discard
= v_branch(conditional
, false);
1158 discard
.branch
.target_type
= TARGET_DISCARD
;
1159 emit_mir_instruction(ctx
, discard
);
1161 ctx
->can_discard
= true;
1165 case nir_intrinsic_load_uniform
:
1166 case nir_intrinsic_load_input
:
1167 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1168 assert (const_offset
&& "no indirect inputs");
1170 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1172 reg
= nir_dest_index(ctx
, &instr
->dest
);
1174 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1175 /* TODO: half-floats */
1177 int uniform_offset
= 0;
1179 if (offset
>= SPECIAL_UNIFORM_BASE
) {
1180 /* XXX: Resolve which uniform */
1183 /* Offset away from the special
1186 void *entry
= _mesa_hash_table_u64_search(ctx
->uniform_nir_to_mdg
, offset
+ 1);
1190 printf("WARNING: Unknown uniform %d\n", offset
);
1194 uniform_offset
= (uintptr_t) (entry
) - 1;
1195 uniform_offset
+= ctx
->special_uniforms
;
1198 if (uniform_offset
< ctx
->uniform_cutoff
) {
1199 /* Fast path: For the first 16 uniform,
1200 * accesses are 0-cycle, since they're
1201 * just a register fetch in the usual
1202 * case. So, we alias the registers
1203 * while we're still in SSA-space */
1205 int reg_slot
= 23 - uniform_offset
;
1206 alias_ssa(ctx
, reg
, SSA_FIXED_REGISTER(reg_slot
));
1208 /* Otherwise, read from the 'special'
1209 * UBO to access higher-indexed
1210 * uniforms, at a performance cost */
1212 midgard_instruction ins
= m_load_uniform_32(reg
, uniform_offset
);
1214 /* TODO: Don't split */
1215 ins
.load_store
.varying_parameters
= (uniform_offset
& 7) << 7;
1216 ins
.load_store
.address
= uniform_offset
>> 3;
1218 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1219 emit_mir_instruction(ctx
, ins
);
1221 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1222 /* XXX: Half-floats? */
1223 /* TODO: swizzle, mask */
1225 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1227 midgard_varying_parameter p
= {
1229 .interpolation
= midgard_interp_default
,
1230 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1234 memcpy(&u
, &p
, sizeof(p
));
1235 ins
.load_store
.varying_parameters
= u
;
1237 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1238 emit_mir_instruction(ctx
, ins
);
1239 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1240 /* Constant encoded as a pinned constant */
1242 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1243 ins
.has_constants
= true;
1244 ins
.has_blend_constant
= true;
1245 emit_mir_instruction(ctx
, ins
);
1246 } else if (ctx
->is_blend
) {
1247 /* For blend shaders, a load might be
1248 * translated various ways depending on what
1249 * we're loading. Figure out how this is used */
1251 nir_variable
*out
= NULL
;
1253 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1254 int drvloc
= var
->data
.driver_location
;
1256 if (nir_intrinsic_base(instr
) == drvloc
) {
1264 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1265 /* Source color preloaded to r0 */
1267 midgard_pin_output(ctx
, reg
, 0);
1268 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1269 /* Destination color must be read from framebuffer */
1271 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1272 ins
.load_store
.swizzle
= 0; /* xxxx */
1274 /* Read each component sequentially */
1276 for (int c
= 0; c
< 4; ++c
) {
1277 ins
.load_store
.mask
= (1 << c
);
1278 ins
.load_store
.unknown
= c
;
1279 emit_mir_instruction(ctx
, ins
);
1282 /* vadd.u2f hr2, abs(hr2), #0 */
1284 midgard_vector_alu_src alu_src
= blank_alu_src
;
1286 alu_src
.half
= true;
1288 midgard_instruction u2f
= {
1292 .src1
= SSA_UNUSED_0
,
1294 .inline_constant
= true
1297 .op
= midgard_alu_op_u2f
,
1298 .reg_mode
= midgard_reg_mode_half
,
1299 .dest_override
= midgard_dest_override_none
,
1301 .src1
= vector_alu_srco_unsigned(alu_src
),
1302 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1306 emit_mir_instruction(ctx
, u2f
);
1308 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1310 alu_src
.abs
= false;
1312 midgard_instruction fmul
= {
1314 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1318 .src1
= SSA_UNUSED_0
,
1319 .inline_constant
= true
1322 .op
= midgard_alu_op_fmul
,
1323 .reg_mode
= midgard_reg_mode_full
,
1324 .dest_override
= midgard_dest_override_none
,
1325 .outmod
= midgard_outmod_sat
,
1327 .src1
= vector_alu_srco_unsigned(alu_src
),
1328 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1332 emit_mir_instruction(ctx
, fmul
);
1334 printf("Unknown input in blend shader\n");
1337 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1338 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1339 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1340 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1341 emit_mir_instruction(ctx
, ins
);
1343 printf("Unknown load\n");
1349 case nir_intrinsic_store_output
:
1350 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1351 assert(const_offset
&& "no indirect outputs");
1353 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1355 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1357 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1358 /* gl_FragColor is not emitted with load/store
1359 * instructions. Instead, it gets plonked into
1360 * r0 at the end of the shader and we do the
1361 * framebuffer writeout dance. TODO: Defer
1364 midgard_pin_output(ctx
, reg
, 0);
1366 /* Save the index we're writing to for later reference
1367 * in the epilogue */
1369 ctx
->fragment_output
= reg
;
1370 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1371 /* Varyings are written into one of two special
1372 * varying register, r26 or r27. The register itself is selected as the register
1373 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1375 * Normally emitting fmov's is frowned upon,
1376 * but due to unique constraints of
1377 * REGISTER_VARYING, fmov emission + a
1378 * dedicated cleanup pass is the only way to
1379 * guarantee correctness when considering some
1380 * (common) edge cases XXX: FIXME */
1382 /* Look up how it was actually laid out */
1384 void *entry
= _mesa_hash_table_u64_search(ctx
->varying_nir_to_mdg
, offset
+ 1);
1387 printf("WARNING: skipping varying\n");
1391 offset
= (uintptr_t) (entry
) - 1;
1393 /* If this varying corresponds to a constant (why?!),
1394 * emit that now since it won't get picked up by
1395 * hoisting (since there is no corresponding move
1396 * emitted otherwise) */
1398 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1400 if (constant_value
) {
1401 /* Special case: emit the varying write
1402 * directly to r26 (looks funny in asm but it's
1403 * fine) and emit the store _now_. Possibly
1404 * slightly slower, but this is a really stupid
1405 * special case anyway (why on earth would you
1406 * have a constant varying? Your own fault for
1407 * slightly worse perf :P) */
1409 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1410 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1411 emit_mir_instruction(ctx
, ins
);
1413 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1414 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1415 emit_mir_instruction(ctx
, st
);
1417 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1419 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1422 printf("Unknown store\n");
1428 case nir_intrinsic_load_alpha_ref_float
:
1429 assert(instr
->dest
.is_ssa
);
1431 float ref_value
= ctx
->alpha_ref
;
1433 float *v
= ralloc_array(NULL
, float, 4);
1434 memcpy(v
, &ref_value
, sizeof(float));
1435 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1440 printf ("Unhandled intrinsic\n");
1447 midgard_tex_format(enum glsl_sampler_dim dim
)
1450 case GLSL_SAMPLER_DIM_2D
:
1451 case GLSL_SAMPLER_DIM_EXTERNAL
:
1454 case GLSL_SAMPLER_DIM_3D
:
1457 case GLSL_SAMPLER_DIM_CUBE
:
1458 return TEXTURE_CUBE
;
1461 printf("Unknown sampler dim type\n");
1468 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1471 //assert (!instr->sampler);
1472 //assert (!instr->texture_array_size);
1473 assert (instr
->op
== nir_texop_tex
);
1475 /* Allocate registers via a round robin scheme to alternate between the two registers */
1476 int reg
= ctx
->texture_op_count
& 1;
1477 int in_reg
= reg
, out_reg
= reg
;
1479 /* Make room for the reg */
1481 if (ctx
->texture_index
[reg
] > -1)
1482 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1484 int texture_index
= instr
->texture_index
;
1485 int sampler_index
= texture_index
;
1487 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1488 switch (instr
->src
[i
].src_type
) {
1489 case nir_tex_src_coord
: {
1490 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1492 midgard_vector_alu_src alu_src
= blank_alu_src
;
1493 alu_src
.swizzle
= (COMPONENT_Y
<< 2);
1495 midgard_instruction ins
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
));
1496 emit_mir_instruction(ctx
, ins
);
1498 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1504 printf("Unknown source type\n");
1511 /* No helper to build texture words -- we do it all here */
1512 midgard_instruction ins
= {
1513 .type
= TAG_TEXTURE_4
,
1515 .op
= TEXTURE_OP_NORMAL
,
1516 .format
= midgard_tex_format(instr
->sampler_dim
),
1517 .texture_handle
= texture_index
,
1518 .sampler_handle
= sampler_index
,
1520 /* TODO: Don't force xyzw */
1521 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1533 /* Assume we can continue; hint it out later */
1538 /* Set registers to read and write from the same place */
1539 ins
.texture
.in_reg_select
= in_reg
;
1540 ins
.texture
.out_reg_select
= out_reg
;
1542 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1543 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1544 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1545 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1546 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1548 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1549 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1550 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1553 emit_mir_instruction(ctx
, ins
);
1555 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1557 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1558 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1559 ctx
->texture_index
[reg
] = o_index
;
1561 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1562 emit_mir_instruction(ctx
, ins2
);
1564 /* Used for .cont and .last hinting */
1565 ctx
->texture_op_count
++;
1569 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1571 switch (instr
->type
) {
1572 case nir_jump_break
: {
1573 /* Emit a branch out of the loop */
1574 struct midgard_instruction br
= v_branch(false, false);
1575 br
.branch
.target_type
= TARGET_BREAK
;
1576 br
.branch
.target_break
= ctx
->current_loop
;
1577 emit_mir_instruction(ctx
, br
);
1579 printf("break..\n");
1584 printf("Unknown jump type %d\n", instr
->type
);
1590 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1592 switch (instr
->type
) {
1593 case nir_instr_type_load_const
:
1594 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1597 case nir_instr_type_intrinsic
:
1598 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1601 case nir_instr_type_alu
:
1602 emit_alu(ctx
, nir_instr_as_alu(instr
));
1605 case nir_instr_type_tex
:
1606 emit_tex(ctx
, nir_instr_as_tex(instr
));
1609 case nir_instr_type_jump
:
1610 emit_jump(ctx
, nir_instr_as_jump(instr
));
1613 case nir_instr_type_ssa_undef
:
1618 printf("Unhandled instruction type\n");
1623 /* Determine the actual hardware from the index based on the RA results or special values */
1626 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1628 if (reg
>= SSA_FIXED_MINIMUM
)
1629 return SSA_REG_FROM_FIXED(reg
);
1632 assert(reg
< maxreg
);
1633 int r
= ra_get_node_reg(g
, reg
);
1634 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1639 /* fmov style unused */
1641 return REGISTER_UNUSED
;
1643 /* lut style unused */
1645 return REGISTER_UNUSED
;
1648 printf("Unknown SSA register alias %d\n", reg
);
1655 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1657 /* Choose the first available register to minimise reported register pressure */
1659 for (int i
= 0; i
< 16; ++i
) {
1660 if (BITSET_TEST(regs
, i
)) {
1670 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1672 if (ins
->ssa_args
.src0
== src
) return true;
1673 if (ins
->ssa_args
.src1
== src
) return true;
1679 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1681 /* Check the rest of the block for liveness */
1682 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1683 if (midgard_is_live_in_instr(ins
, src
))
1687 /* Check the rest of the blocks for liveness */
1688 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1689 mir_foreach_instr_in_block(b
, ins
) {
1690 if (midgard_is_live_in_instr(ins
, src
))
1695 /* TODO: How does control flow interact in complex shaders? */
1701 allocate_registers(compiler_context
*ctx
)
1703 /* First, initialize the RA */
1704 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1706 /* Create a primary (general purpose) class, as well as special purpose
1707 * pipeline register classes */
1709 int primary_class
= ra_alloc_reg_class(regs
);
1710 int varying_class
= ra_alloc_reg_class(regs
);
1712 /* Add the full set of work registers */
1713 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1714 for (int i
= 0; i
< work_count
; ++i
)
1715 ra_class_add_reg(regs
, primary_class
, i
);
1717 /* Add special registers */
1718 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1719 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1721 /* We're done setting up */
1722 ra_set_finalize(regs
, NULL
);
1724 /* Transform the MIR into squeezed index form */
1725 mir_foreach_block(ctx
, block
) {
1726 mir_foreach_instr_in_block(block
, ins
) {
1727 if (ins
->compact_branch
) continue;
1729 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1730 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1731 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1734 print_mir_block(block
);
1737 /* Let's actually do register allocation */
1738 int nodes
= ctx
->temp_count
;
1739 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1741 /* Set everything to the work register class, unless it has somewhere
1744 mir_foreach_block(ctx
, block
) {
1745 mir_foreach_instr_in_block(block
, ins
) {
1746 if (ins
->compact_branch
) continue;
1748 if (ins
->ssa_args
.dest
< 0) continue;
1750 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1752 int class = primary_class
;
1754 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1758 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1759 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1762 unsigned reg
= temp
- 1;
1763 int t
= find_or_allocate_temp(ctx
, index
);
1764 ra_set_node_reg(g
, t
, reg
);
1768 /* Determine liveness */
1770 int *live_start
= malloc(nodes
* sizeof(int));
1771 int *live_end
= malloc(nodes
* sizeof(int));
1773 /* Initialize as non-existent */
1775 for (int i
= 0; i
< nodes
; ++i
) {
1776 live_start
[i
] = live_end
[i
] = -1;
1781 mir_foreach_block(ctx
, block
) {
1782 mir_foreach_instr_in_block(block
, ins
) {
1783 if (ins
->compact_branch
) continue;
1785 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1786 /* If this destination is not yet live, it is now since we just wrote it */
1788 int dest
= ins
->ssa_args
.dest
;
1790 if (live_start
[dest
] == -1)
1791 live_start
[dest
] = d
;
1794 /* Since we just used a source, the source might be
1795 * dead now. Scan the rest of the block for
1796 * invocations, and if there are none, the source dies
1799 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1801 for (int src
= 0; src
< 2; ++src
) {
1802 int s
= sources
[src
];
1804 if (s
< 0) continue;
1806 if (s
>= SSA_FIXED_MINIMUM
) continue;
1808 if (!is_live_after(ctx
, block
, ins
, s
)) {
1817 /* If a node still hasn't been killed, kill it now */
1819 for (int i
= 0; i
< nodes
; ++i
) {
1820 /* live_start == -1 most likely indicates a pinned output */
1822 if (live_end
[i
] == -1)
1826 /* Setup interference between nodes that are live at the same time */
1828 for (int i
= 0; i
< nodes
; ++i
) {
1829 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1830 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1831 ra_add_node_interference(g
, i
, j
);
1835 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1837 if (!ra_allocate(g
)) {
1838 printf("Error allocating registers\n");
1846 mir_foreach_block(ctx
, block
) {
1847 mir_foreach_instr_in_block(block
, ins
) {
1848 if (ins
->compact_branch
) continue;
1850 ssa_args args
= ins
->ssa_args
;
1852 switch (ins
->type
) {
1854 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1856 ins
->registers
.src2_imm
= args
.inline_constant
;
1858 if (args
.inline_constant
) {
1859 /* Encode inline 16-bit constant as a vector by default */
1861 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1863 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1865 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1866 ins
->alu
.src2
= imm
<< 2;
1868 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
1871 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
1875 case TAG_LOAD_STORE_4
: {
1876 if (OP_IS_STORE(ins
->load_store
.op
)) {
1877 /* TODO: use ssa_args for store_vary */
1878 ins
->load_store
.reg
= 0;
1880 bool has_dest
= args
.dest
>= 0;
1881 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
1883 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
1896 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1897 * use scalar ALU instructions, for functional or performance reasons. To do
1898 * this, we just demote vector ALU payloads to scalar. */
1901 component_from_mask(unsigned mask
)
1903 for (int c
= 0; c
< 4; ++c
) {
1904 if (mask
& (3 << (2 * c
)))
1913 is_single_component_mask(unsigned mask
)
1917 for (int c
= 0; c
< 4; ++c
)
1918 if (mask
& (3 << (2 * c
)))
1921 return components
== 1;
1924 /* Create a mask of accessed components from a swizzle to figure out vector
1928 swizzle_to_access_mask(unsigned swizzle
)
1930 unsigned component_mask
= 0;
1932 for (int i
= 0; i
< 4; ++i
) {
1933 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1934 component_mask
|= (1 << c
);
1937 return component_mask
;
1941 vector_to_scalar_source(unsigned u
)
1943 midgard_vector_alu_src v
;
1944 memcpy(&v
, &u
, sizeof(v
));
1946 midgard_scalar_alu_src s
= {
1950 .component
= (v
.swizzle
& 3) << 1
1954 memcpy(&o
, &s
, sizeof(s
));
1956 return o
& ((1 << 6) - 1);
1959 static midgard_scalar_alu
1960 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
1962 /* The output component is from the mask */
1963 midgard_scalar_alu s
= {
1965 .src1
= vector_to_scalar_source(v
.src1
),
1966 .src2
= vector_to_scalar_source(v
.src2
),
1969 .output_full
= 1, /* TODO: Half */
1970 .output_component
= component_from_mask(v
.mask
) << 1,
1973 /* Inline constant is passed along rather than trying to extract it
1976 if (ins
->ssa_args
.inline_constant
) {
1978 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1979 imm
|= (lower_11
>> 9) & 3;
1980 imm
|= (lower_11
>> 6) & 4;
1981 imm
|= (lower_11
>> 2) & 0x38;
1982 imm
|= (lower_11
& 63) << 6;
1990 /* Midgard prefetches instruction types, so during emission we need to
1991 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1992 * if this is the second to last and the last is an ALU, then it's also 1... */
1994 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
1995 tag == TAG_ALU_12 || tag == TAG_ALU_16)
1997 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
1998 bytes_emitted += sizeof(type)
2001 emit_binary_vector_instruction(midgard_instruction
*ains
,
2002 uint16_t *register_words
, int *register_words_count
,
2003 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2004 size_t *bytes_emitted
)
2006 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2007 *bytes_emitted
+= sizeof(midgard_reg_info
);
2009 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2010 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2011 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2014 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2015 * mind that we are a vector architecture and we can write to different
2016 * components simultaneously */
2019 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2021 /* Each instruction reads some registers and writes to a register. See
2022 * where the first writes */
2024 /* Figure out where exactly we wrote to */
2025 int source
= first
->ssa_args
.dest
;
2026 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2028 /* As long as the second doesn't read from the first, we're okay */
2029 if (second
->ssa_args
.src0
== source
) {
2030 if (first
->type
== TAG_ALU_4
) {
2031 /* Figure out which components we just read from */
2033 int q
= second
->alu
.src1
;
2034 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2036 /* Check if there are components in common, and fail if so */
2037 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2044 if (second
->ssa_args
.src1
== source
)
2047 /* Otherwise, it's safe in that regard. Another data hazard is both
2048 * writing to the same place, of course */
2050 if (second
->ssa_args
.dest
== source
) {
2051 /* ...but only if the components overlap */
2052 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2054 if (dest_mask
& source_mask
)
2062 /* Schedules, but does not emit, a single basic block. After scheduling, the
2063 * final tag and size of the block are known, which are necessary for branching
2066 static midgard_bundle
2067 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2069 int instructions_emitted
= 0, instructions_consumed
= -1;
2070 midgard_bundle bundle
= { 0 };
2072 uint8_t tag
= ins
->type
;
2074 /* Default to the instruction's tag */
2077 switch (ins
->type
) {
2079 uint32_t control
= 0;
2080 size_t bytes_emitted
= sizeof(control
);
2082 /* TODO: Constant combining */
2083 int index
= 0, last_unit
= 0;
2085 /* Previous instructions, for the purpose of parallelism */
2086 midgard_instruction
*segment
[4] = {0};
2087 int segment_size
= 0;
2089 instructions_emitted
= -1;
2090 midgard_instruction
*pins
= ins
;
2093 midgard_instruction
*ains
= pins
;
2095 /* Advance instruction pointer */
2097 ains
= mir_next_op(pins
);
2101 /* Out-of-work condition */
2102 if ((struct list_head
*) ains
== &block
->instructions
)
2105 /* Ensure that the chain can continue */
2106 if (ains
->type
!= TAG_ALU_4
) break;
2108 /* According to the presentation "The ARM
2109 * Mali-T880 Mobile GPU" from HotChips 27,
2110 * there are two pipeline stages. Branching
2111 * position determined experimentally. Lines
2112 * are executed in parallel:
2115 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2117 * Verify that there are no ordering dependencies here.
2119 * TODO: Allow for parallelism!!!
2122 /* Pick a unit for it if it doesn't force a particular unit */
2124 int unit
= ains
->unit
;
2127 int op
= ains
->alu
.op
;
2128 int units
= alu_opcode_props
[op
];
2130 /* TODO: Promotion of scalars to vectors */
2131 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2134 assert(units
& UNITS_SCALAR
);
2137 if (last_unit
>= UNIT_VADD
) {
2138 if (units
& UNIT_VLUT
)
2143 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2145 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2147 else if (units
& UNIT_VLUT
)
2153 if (last_unit
>= UNIT_VADD
) {
2154 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2156 else if (units
& UNIT_VLUT
)
2161 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
))
2163 else if (units
& UNIT_SMUL
)
2165 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2172 assert(unit
& units
);
2175 /* Late unit check, this time for encoding (not parallelism) */
2176 if (unit
<= last_unit
) break;
2178 /* Clear the segment */
2179 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2182 /* Check for data hazards */
2183 int has_hazard
= false;
2185 for (int s
= 0; s
< segment_size
; ++s
)
2186 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2192 /* We're good to go -- emit the instruction */
2195 segment
[segment_size
++] = ains
;
2197 /* Only one set of embedded constants per
2198 * bundle possible; if we have more, we must
2199 * break the chain early, unfortunately */
2201 if (ains
->has_constants
) {
2202 if (bundle
.has_embedded_constants
) {
2203 /* ...but if there are already
2204 * constants but these are the
2205 * *same* constants, we let it
2208 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2211 bundle
.has_embedded_constants
= true;
2212 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2214 /* If this is a blend shader special constant, track it for patching */
2215 if (ains
->has_blend_constant
)
2216 bundle
.has_blend_constant
= true;
2220 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2221 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2222 &bundle
.register_words_count
, bundle
.body_words
,
2223 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2224 } else if (ains
->compact_branch
) {
2225 /* All of r0 has to be written out
2226 * along with the branch writeout.
2229 if (ains
->writeout
) {
2231 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2232 ins
.unit
= UNIT_VMUL
;
2234 control
|= ins
.unit
;
2236 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2237 &bundle
.register_words_count
, bundle
.body_words
,
2238 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2240 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2241 bool written_late
= false;
2242 bool components
[4] = { 0 };
2243 uint16_t register_dep_mask
= 0;
2244 uint16_t written_mask
= 0;
2246 midgard_instruction
*qins
= ins
;
2247 for (int t
= 0; t
< index
; ++t
) {
2248 if (qins
->registers
.out_reg
!= 0) {
2249 /* Mark down writes */
2251 written_mask
|= (1 << qins
->registers
.out_reg
);
2253 /* Mark down the register dependencies for errata check */
2255 if (qins
->registers
.src1_reg
< 16)
2256 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2258 if (qins
->registers
.src2_reg
< 16)
2259 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2261 int mask
= qins
->alu
.mask
;
2263 for (int c
= 0; c
< 4; ++c
)
2264 if (mask
& (0x3 << (2 * c
)))
2265 components
[c
] = true;
2267 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2269 if (qins
->unit
== UNIT_VLUT
)
2270 written_late
= true;
2273 /* Advance instruction pointer */
2274 qins
= mir_next_op(qins
);
2278 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2279 if (register_dep_mask
& written_mask
) {
2280 printf("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2287 /* If even a single component is not written, break it up (conservative check). */
2288 bool breakup
= false;
2290 for (int c
= 0; c
< 4; ++c
)
2297 /* Otherwise, we're free to proceed */
2301 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2302 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2303 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2304 bytes_emitted
+= sizeof(midgard_branch_extended
);
2306 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2307 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2308 bytes_emitted
+= sizeof(ains
->br_compact
);
2311 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2312 bytes_emitted
+= sizeof(midgard_reg_info
);
2314 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2315 bundle
.body_words_count
++;
2316 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2319 /* Defer marking until after writing to allow for break */
2320 control
|= ains
->unit
;
2321 last_unit
= ains
->unit
;
2322 ++instructions_emitted
;
2326 /* Bubble up the number of instructions for skipping */
2327 instructions_consumed
= index
- 1;
2331 /* Pad ALU op to nearest word */
2333 if (bytes_emitted
& 15) {
2334 padding
= 16 - (bytes_emitted
& 15);
2335 bytes_emitted
+= padding
;
2338 /* Constants must always be quadwords */
2339 if (bundle
.has_embedded_constants
)
2340 bytes_emitted
+= 16;
2342 /* Size ALU instruction for tag */
2343 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2344 bundle
.padding
= padding
;
2345 bundle
.control
= bundle
.tag
| control
;
2350 case TAG_LOAD_STORE_4
: {
2351 /* Load store instructions have two words at once. If
2352 * we only have one queued up, we need to NOP pad.
2353 * Otherwise, we store both in succession to save space
2354 * and cycles -- letting them go in parallel -- skip
2355 * the next. The usefulness of this optimisation is
2356 * greatly dependent on the quality of the instruction
2360 midgard_instruction
*next_op
= mir_next_op(ins
);
2362 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2363 /* As the two operate concurrently, make sure
2364 * they are not dependent */
2366 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2367 /* Skip ahead, since it's redundant with the pair */
2368 instructions_consumed
= 1 + (instructions_emitted
++);
2376 /* Texture ops default to single-op-per-bundle scheduling */
2380 /* Copy the instructions into the bundle */
2381 bundle
.instruction_count
= instructions_emitted
+ 1;
2385 midgard_instruction
*uins
= ins
;
2386 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2387 bundle
.instructions
[used_idx
++] = *uins
;
2388 uins
= mir_next_op(uins
);
2391 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2397 quadword_size(int tag
)
2412 case TAG_LOAD_STORE_4
:
2424 /* Schedule a single block by iterating its instruction to create bundles.
2425 * While we go, tally about the bundle sizes to compute the block size. */
2428 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2430 util_dynarray_init(&block
->bundles
, NULL
);
2432 block
->quadword_count
= 0;
2434 mir_foreach_instr_in_block(block
, ins
) {
2436 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2437 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2439 if (bundle
.has_blend_constant
) {
2440 /* TODO: Multiblock? */
2441 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2442 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2446 ins
= mir_next_op(ins
);
2448 block
->quadword_count
+= quadword_size(bundle
.tag
);
2451 block
->is_scheduled
= true;
2455 schedule_program(compiler_context
*ctx
)
2457 allocate_registers(ctx
);
2459 mir_foreach_block(ctx
, block
) {
2460 schedule_block(ctx
, block
);
2464 /* After everything is scheduled, emit whole bundles at a time */
2467 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2469 int lookahead
= next_tag
<< 4;
2471 switch (bundle
->tag
) {
2476 /* Actually emit each component */
2477 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2479 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2480 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2482 /* Emit body words based on the instructions bundled */
2483 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2484 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2486 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2487 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2488 } else if (ins
->compact_branch
) {
2489 /* Dummy move, XXX DRY */
2490 if ((i
== 0) && ins
->writeout
) {
2491 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2492 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2495 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2496 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2498 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2502 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2503 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2507 /* Emit padding (all zero) */
2508 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2510 /* Tack on constants */
2512 if (bundle
->has_embedded_constants
) {
2513 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2514 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2515 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2516 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2522 case TAG_LOAD_STORE_4
: {
2523 /* One or two composing instructions */
2525 uint64_t current64
, next64
= LDST_NOP
;
2527 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2529 if (bundle
->instruction_count
== 2)
2530 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2532 midgard_load_store instruction
= {
2533 .type
= bundle
->tag
,
2534 .next_type
= next_tag
,
2539 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2544 case TAG_TEXTURE_4
: {
2545 /* Texture instructions are easy, since there is no
2546 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2548 midgard_instruction
*ins
= &bundle
->instructions
[0];
2550 ins
->texture
.type
= TAG_TEXTURE_4
;
2551 ins
->texture
.next_type
= next_tag
;
2553 ctx
->texture_op_count
--;
2555 if (!ctx
->texture_op_count
) {
2556 ins
->texture
.cont
= 0;
2557 ins
->texture
.last
= 1;
2560 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2565 printf("Unknown midgard instruction type\n");
2572 /* ALU instructions can inline or embed constants, which decreases register
2573 * pressure and saves space. */
2575 #define CONDITIONAL_ATTACH(src) { \
2576 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2579 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2580 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2585 inline_alu_constants(compiler_context
*ctx
)
2587 mir_foreach_instr(ctx
, alu
) {
2588 /* Other instructions cannot inline constants */
2589 if (alu
->type
!= TAG_ALU_4
) continue;
2591 /* If there is already a constant here, we can do nothing */
2592 if (alu
->has_constants
) continue;
2594 CONDITIONAL_ATTACH(src0
);
2596 if (!alu
->has_constants
) {
2597 CONDITIONAL_ATTACH(src1
)
2598 } else if (!alu
->inline_constant
) {
2599 /* Corner case: _two_ vec4 constants, for instance with a
2600 * csel. For this case, we can only use a constant
2601 * register for one, we'll have to emit a move for the
2602 * other. Note, if both arguments are constants, then
2603 * necessarily neither argument depends on the value of
2604 * any particular register. As the destination register
2605 * will be wiped, that means we can spill the constant
2606 * to the destination register.
2609 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2610 unsigned scratch
= alu
->ssa_args
.dest
;
2613 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2614 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2616 /* Force a break XXX Defer r31 writes */
2617 ins
.unit
= UNIT_VLUT
;
2619 /* Set the source */
2620 alu
->ssa_args
.src1
= scratch
;
2622 /* Inject us -before- the last instruction which set r31 */
2623 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2629 /* Midgard supports two types of constants, embedded constants (128-bit) and
2630 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2631 * constants can be demoted to inline constants, for space savings and
2632 * sometimes a performance boost */
2635 embedded_to_inline_constant(compiler_context
*ctx
)
2637 mir_foreach_instr(ctx
, ins
) {
2638 if (!ins
->has_constants
) continue;
2640 if (ins
->ssa_args
.inline_constant
) continue;
2642 /* Blend constants must not be inlined by definition */
2643 if (ins
->has_blend_constant
) continue;
2645 /* src1 cannot be an inline constant due to encoding
2646 * restrictions. So, if possible we try to flip the arguments
2649 int op
= ins
->alu
.op
;
2651 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2652 /* Flip based on op. Fallthrough intentional */
2655 /* These ops require an operational change to flip their arguments TODO */
2656 case midgard_alu_op_flt
:
2657 case midgard_alu_op_fle
:
2658 case midgard_alu_op_ilt
:
2659 case midgard_alu_op_ile
:
2660 case midgard_alu_op_fcsel
:
2661 case midgard_alu_op_icsel
:
2662 case midgard_alu_op_isub
:
2663 printf("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2666 /* These ops are commutative and Just Flip */
2667 case midgard_alu_op_fne
:
2668 case midgard_alu_op_fadd
:
2669 case midgard_alu_op_fmul
:
2670 case midgard_alu_op_fmin
:
2671 case midgard_alu_op_fmax
:
2672 case midgard_alu_op_iadd
:
2673 case midgard_alu_op_imul
:
2674 case midgard_alu_op_feq
:
2675 case midgard_alu_op_ieq
:
2676 case midgard_alu_op_ine
:
2677 case midgard_alu_op_iand
:
2678 case midgard_alu_op_ior
:
2679 case midgard_alu_op_ixor
:
2680 /* Flip the SSA numbers */
2681 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2682 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2684 /* And flip the modifiers */
2688 src_temp
= ins
->alu
.src2
;
2689 ins
->alu
.src2
= ins
->alu
.src1
;
2690 ins
->alu
.src1
= src_temp
;
2697 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2698 /* Extract the source information */
2700 midgard_vector_alu_src
*src
;
2701 int q
= ins
->alu
.src2
;
2702 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2705 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2706 int component
= src
->swizzle
& 3;
2708 /* Scale constant appropriately, if we can legally */
2709 uint16_t scaled_constant
= 0;
2711 /* XXX: Check legality */
2712 if (midgard_is_integer_op(op
)) {
2713 /* TODO: Inline integer */
2716 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2717 scaled_constant
= (uint16_t) iconstants
[component
];
2719 /* Constant overflow after resize */
2720 if (scaled_constant
!= iconstants
[component
])
2723 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2726 /* We don't know how to handle these with a constant */
2728 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2729 printf("Bailing inline constant...\n");
2733 /* Make sure that the constant is not itself a
2734 * vector by checking if all accessed values
2735 * (by the swizzle) are the same. */
2737 uint32_t *cons
= (uint32_t *) ins
->constants
;
2738 uint32_t value
= cons
[component
];
2740 bool is_vector
= false;
2741 unsigned mask
= effective_writemask(&ins
->alu
);
2743 for (int c
= 1; c
< 4; ++c
) {
2744 /* We only care if this component is actually used */
2745 if (!(mask
& (1 << c
)))
2748 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2750 if (test
!= value
) {
2759 /* Get rid of the embedded constant */
2760 ins
->has_constants
= false;
2761 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2762 ins
->ssa_args
.inline_constant
= true;
2763 ins
->inline_constant
= scaled_constant
;
2768 /* Map normal SSA sources to other SSA sources / fixed registers (like
2772 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2774 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2777 /* Remove entry in leftovers to avoid a redunant fmov */
2779 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2782 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2784 /* Assign the alias map */
2790 #define AS_SRC(to, u) \
2791 int q##to = ins->alu.src2; \
2792 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2794 /* Removing unused moves is necessary to clean up the texture pipeline results.
2796 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2799 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2801 mir_foreach_instr_in_block_safe(block
, ins
) {
2802 if (ins
->type
!= TAG_ALU_4
) continue;
2804 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2806 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2808 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2810 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2812 mir_remove_instruction(ins
);
2816 /* The following passes reorder MIR instructions to enable better scheduling */
2819 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2821 mir_foreach_instr_in_block_safe(block
, ins
) {
2822 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2824 /* We've found a load/store op. Check if next is also load/store. */
2825 midgard_instruction
*next_op
= mir_next_op(ins
);
2826 if (&next_op
->link
!= &block
->instructions
) {
2827 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2828 /* If so, we're done since we're a pair */
2829 ins
= mir_next_op(ins
);
2833 /* Maximum search distance to pair, to avoid register pressure disasters */
2834 int search_distance
= 8;
2836 /* Otherwise, we have an orphaned load/store -- search for another load */
2837 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2838 /* Terminate search if necessary */
2839 if (!(search_distance
--)) break;
2841 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2843 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2845 /* We found one! Move it up to pair and remove it from the old location */
2847 mir_insert_instruction_before(ins
, *c
);
2848 mir_remove_instruction(c
);
2856 /* Emit varying stores late */
2859 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2860 /* Iterate in reverse to get the final write, rather than the first */
2862 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2863 /* Check if what we just wrote needs a store */
2864 int idx
= ins
->ssa_args
.dest
;
2865 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2867 if (!varying
) continue;
2871 /* We need to store to the appropriate varying, so emit the
2874 /* TODO: Integrate with special purpose RA (and scheduler?) */
2875 bool high_varying_register
= false;
2877 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2879 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2880 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2882 mir_insert_instruction_before(mir_next_op(ins
), st
);
2883 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2885 /* We no longer need to store this varying */
2886 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2890 /* If there are leftovers after the below pass, emit actual fmov
2891 * instructions for the slow-but-correct path */
2894 emit_leftover_move(compiler_context
*ctx
)
2896 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2897 int base
= ((uintptr_t) leftover
->key
) - 1;
2900 map_ssa_to_alias(ctx
, &mapped
);
2901 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2906 actualise_ssa_to_alias(compiler_context
*ctx
)
2908 mir_foreach_instr(ctx
, ins
) {
2909 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2910 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2913 emit_leftover_move(ctx
);
2916 /* Vertex shaders do not write gl_Position as is; instead, they write a
2917 * transformed screen space position as a varying. See section 12.5 "Coordinate
2918 * Transformation" of the ES 3.2 full specification for details.
2920 * This transformation occurs early on, as NIR and prior to optimisation, in
2921 * order to take advantage of NIR optimisation passes of the transform itself.
2925 write_transformed_position(nir_builder
*b
, nir_src input_point_src
, int uniform_no
)
2927 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
2929 /* Get viewport from the uniforms */
2930 nir_intrinsic_instr
*load
;
2931 load
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
2932 load
->num_components
= 4;
2933 load
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, uniform_no
));
2934 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
2935 nir_builder_instr_insert(b
, &load
->instr
);
2937 /* Formatted as <width, height, centerx, centery> */
2938 nir_ssa_def
*viewport_vec4
= &load
->dest
.ssa
;
2939 nir_ssa_def
*viewport_width_2
= nir_channel(b
, viewport_vec4
, 0);
2940 nir_ssa_def
*viewport_height_2
= nir_channel(b
, viewport_vec4
, 1);
2941 nir_ssa_def
*viewport_offset
= nir_channels(b
, viewport_vec4
, 0x8 | 0x4);
2943 /* XXX: From uniforms? */
2944 nir_ssa_def
*depth_near
= nir_imm_float(b
, 0.0);
2945 nir_ssa_def
*depth_far
= nir_imm_float(b
, 1.0);
2947 /* World space to normalised device coordinates */
2949 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
2950 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
2952 /* Normalised device coordinates to screen space */
2954 nir_ssa_def
*viewport_multiplier
= nir_vec2(b
, viewport_width_2
, viewport_height_2
);
2955 nir_ssa_def
*viewport_xy
= nir_fadd(b
, nir_fmul(b
, nir_channels(b
, ndc_point
, 0x3), viewport_multiplier
), viewport_offset
);
2957 nir_ssa_def
*depth_multiplier
= nir_fmul(b
, nir_fsub(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2958 nir_ssa_def
*depth_offset
= nir_fmul(b
, nir_fadd(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2959 nir_ssa_def
*screen_depth
= nir_fadd(b
, nir_fmul(b
, nir_channel(b
, ndc_point
, 2), depth_multiplier
), depth_offset
);
2961 /* gl_Position will be written out in screenspace xyz, with w set to
2962 * the reciprocal we computed earlier. The transformed w component is
2963 * then used for perspective-correct varying interpolation. The
2964 * transformed w component must preserve its original sign; this is
2965 * used in depth clipping computations */
2967 nir_ssa_def
*screen_space
= nir_vec4(b
,
2968 nir_channel(b
, viewport_xy
, 0),
2969 nir_channel(b
, viewport_xy
, 1),
2973 /* Finally, write out the transformed values to the varying */
2975 nir_intrinsic_instr
*store
;
2976 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
2977 store
->num_components
= 4;
2978 nir_intrinsic_set_base(store
, 0);
2979 nir_intrinsic_set_write_mask(store
, 0xf);
2980 store
->src
[0].ssa
= screen_space
;
2981 store
->src
[0].is_ssa
= true;
2982 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
2983 nir_builder_instr_insert(b
, &store
->instr
);
2987 transform_position_writes(nir_shader
*shader
)
2989 nir_foreach_function(func
, shader
) {
2990 nir_foreach_block(block
, func
->impl
) {
2991 nir_foreach_instr_safe(instr
, block
) {
2992 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
2994 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
2995 nir_variable
*out
= NULL
;
2997 switch (intr
->intrinsic
) {
2998 case nir_intrinsic_store_output
:
2999 /* already had i/o lowered.. lookup the matching output var: */
3000 nir_foreach_variable(var
, &shader
->outputs
) {
3001 int drvloc
= var
->data
.driver_location
;
3003 if (nir_intrinsic_base(intr
) == drvloc
) {
3017 if (out
->data
.mode
!= nir_var_shader_out
)
3020 if (out
->data
.location
!= VARYING_SLOT_POS
)
3024 nir_builder_init(&b
, func
->impl
);
3025 b
.cursor
= nir_before_instr(instr
);
3027 write_transformed_position(&b
, intr
->src
[0], UNIFORM_VIEWPORT
);
3028 nir_instr_remove(instr
);
3035 emit_fragment_epilogue(compiler_context
*ctx
)
3037 /* Special case: writing out constants requires us to include the move
3038 * explicitly now, so shove it into r0 */
3040 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3042 if (constant_value
) {
3043 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3044 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3045 emit_mir_instruction(ctx
, ins
);
3048 /* Perform the actual fragment writeout. We have two writeout/branch
3049 * instructions, forming a loop until writeout is successful as per the
3050 * docs. TODO: gl_FragDepth */
3052 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3053 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3056 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3057 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3058 * with the int8 analogue to the fragment epilogue */
3061 emit_blend_epilogue(compiler_context
*ctx
)
3063 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3065 midgard_instruction scale
= {
3068 .inline_constant
= _mesa_float_to_half(255.0),
3070 .src0
= SSA_FIXED_REGISTER(0),
3071 .src1
= SSA_UNUSED_0
,
3072 .dest
= SSA_FIXED_REGISTER(24),
3073 .inline_constant
= true
3076 .op
= midgard_alu_op_fmul
,
3077 .reg_mode
= midgard_reg_mode_full
,
3078 .dest_override
= midgard_dest_override_lower
,
3080 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3081 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3085 emit_mir_instruction(ctx
, scale
);
3087 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3089 midgard_vector_alu_src alu_src
= blank_alu_src
;
3090 alu_src
.half
= true;
3092 midgard_instruction f2u8
= {
3095 .src0
= SSA_FIXED_REGISTER(24),
3096 .src1
= SSA_UNUSED_0
,
3097 .dest
= SSA_FIXED_REGISTER(0),
3098 .inline_constant
= true
3101 .op
= midgard_alu_op_f2u8
,
3102 .reg_mode
= midgard_reg_mode_half
,
3103 .dest_override
= midgard_dest_override_lower
,
3104 .outmod
= midgard_outmod_pos
,
3106 .src1
= vector_alu_srco_unsigned(alu_src
),
3107 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3111 emit_mir_instruction(ctx
, f2u8
);
3113 /* vmul.imov.quarter r0, r0, r0 */
3115 midgard_instruction imov_8
= {
3118 .src0
= SSA_UNUSED_1
,
3119 .src1
= SSA_FIXED_REGISTER(0),
3120 .dest
= SSA_FIXED_REGISTER(0),
3123 .op
= midgard_alu_op_imov
,
3124 .reg_mode
= midgard_reg_mode_quarter
,
3125 .dest_override
= midgard_dest_override_none
,
3127 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3128 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3132 /* Emit branch epilogue with the 8-bit move as the source */
3134 emit_mir_instruction(ctx
, imov_8
);
3135 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3137 emit_mir_instruction(ctx
, imov_8
);
3138 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3141 static midgard_block
*
3142 emit_block(compiler_context
*ctx
, nir_block
*block
)
3144 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3145 list_addtail(&this_block
->link
, &ctx
->blocks
);
3147 this_block
->is_scheduled
= false;
3150 ctx
->texture_index
[0] = -1;
3151 ctx
->texture_index
[1] = -1;
3153 /* Set up current block */
3154 list_inithead(&this_block
->instructions
);
3155 ctx
->current_block
= this_block
;
3157 nir_foreach_instr(instr
, block
) {
3158 emit_instr(ctx
, instr
);
3159 ++ctx
->instruction_count
;
3162 inline_alu_constants(ctx
);
3163 embedded_to_inline_constant(ctx
);
3165 /* Perform heavylifting for aliasing */
3166 actualise_ssa_to_alias(ctx
);
3168 midgard_emit_store(ctx
, this_block
);
3169 midgard_eliminate_orphan_moves(ctx
, this_block
);
3170 midgard_pair_load_store(ctx
, this_block
);
3172 /* Append fragment shader epilogue (value writeout) */
3173 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3174 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3176 emit_blend_epilogue(ctx
);
3178 emit_fragment_epilogue(ctx
);
3182 /* Fallthrough save */
3183 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3185 if (block
== nir_start_block(ctx
->func
->impl
))
3186 ctx
->initial_block
= this_block
;
3188 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3189 ctx
->final_block
= this_block
;
3191 /* Allow the next control flow to access us retroactively, for
3193 ctx
->current_block
= this_block
;
3195 /* Document the fallthrough chain */
3196 ctx
->previous_source_block
= this_block
;
3201 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3204 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3206 /* Conditional branches expect the condition in r31.w; emit a move for
3207 * that in the _previous_ block (which is the current block). */
3208 emit_condition(ctx
, &nif
->condition
, true);
3210 /* Speculatively emit the branch, but we can't fill it in until later */
3211 EMIT(branch
, true, true);
3212 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3214 /* Emit the two subblocks */
3215 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3217 /* Emit a jump from the end of the then block to the end of the else */
3218 EMIT(branch
, false, false);
3219 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3221 /* Emit second block, and check if it's empty */
3223 int else_idx
= ctx
->block_count
;
3224 int count_in
= ctx
->instruction_count
;
3225 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3226 int after_else_idx
= ctx
->block_count
;
3228 /* Now that we have the subblocks emitted, fix up the branches */
3233 if (ctx
->instruction_count
== count_in
) {
3234 /* The else block is empty, so don't emit an exit jump */
3235 mir_remove_instruction(then_exit
);
3236 then_branch
->branch
.target_block
= after_else_idx
;
3238 then_branch
->branch
.target_block
= else_idx
;
3239 then_exit
->branch
.target_block
= after_else_idx
;
3244 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3246 /* Remember where we are */
3247 midgard_block
*start_block
= ctx
->current_block
;
3249 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3250 * single current_loop variable, maybe we need a stack */
3252 int loop_idx
= ++ctx
->current_loop
;
3254 /* Get index from before the body so we can loop back later */
3255 int start_idx
= ctx
->block_count
;
3257 /* Emit the body itself */
3258 emit_cf_list(ctx
, &nloop
->body
);
3260 /* Branch back to loop back */
3261 struct midgard_instruction br_back
= v_branch(false, false);
3262 br_back
.branch
.target_block
= start_idx
;
3263 emit_mir_instruction(ctx
, br_back
);
3265 /* Find the index of the block about to follow us (note: we don't add
3266 * one; blocks are 0-indexed so we get a fencepost problem) */
3267 int break_block_idx
= ctx
->block_count
;
3269 /* Fix up the break statements we emitted to point to the right place,
3270 * now that we can allocate a block number for them */
3272 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3273 print_mir_block(block
);
3274 mir_foreach_instr_in_block(block
, ins
) {
3275 if (ins
->type
!= TAG_ALU_4
) continue;
3276 if (!ins
->compact_branch
) continue;
3277 if (ins
->prepacked_branch
) continue;
3279 /* We found a branch -- check the type to see if we need to do anything */
3280 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3282 /* It's a break! Check if it's our break */
3283 if (ins
->branch
.target_break
!= loop_idx
) continue;
3285 /* Okay, cool, we're breaking out of this loop.
3286 * Rewrite from a break to a goto */
3288 ins
->branch
.target_type
= TARGET_GOTO
;
3289 ins
->branch
.target_block
= break_block_idx
;
3294 static midgard_block
*
3295 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3297 midgard_block
*start_block
= NULL
;
3299 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3300 switch (node
->type
) {
3301 case nir_cf_node_block
: {
3302 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3305 start_block
= block
;
3310 case nir_cf_node_if
:
3311 emit_if(ctx
, nir_cf_node_as_if(node
));
3314 case nir_cf_node_loop
:
3315 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3318 case nir_cf_node_function
:
3327 /* Due to lookahead, we need to report the first tag executed in the command
3328 * stream and in branch targets. An initial block might be empty, so iterate
3329 * until we find one that 'works' */
3332 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3334 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3336 unsigned first_tag
= 0;
3339 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3341 if (initial_bundle
) {
3342 first_tag
= initial_bundle
->tag
;
3346 /* Initial block is empty, try the next block */
3347 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3348 } while(initial_block
!= NULL
);
3355 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3357 struct util_dynarray
*compiled
= &program
->compiled
;
3359 compiler_context ictx
= {
3361 .stage
= nir
->info
.stage
,
3363 .is_blend
= is_blend
,
3364 .blend_constant_offset
= -1,
3366 .alpha_ref
= program
->alpha_ref
3369 compiler_context
*ctx
= &ictx
;
3371 /* TODO: Decide this at runtime */
3372 ctx
->uniform_cutoff
= 8;
3374 switch (ctx
->stage
) {
3375 case MESA_SHADER_VERTEX
:
3376 ctx
->special_uniforms
= 1;
3380 ctx
->special_uniforms
= 0;
3384 /* Append epilogue uniforms if necessary. The cmdstream depends on
3385 * these being at the -end-; see assign_var_locations. */
3387 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3388 nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "viewport");
3391 /* Assign var locations early, so the epilogue can use them if necessary */
3393 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3394 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3395 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3397 /* Initialize at a global (not block) level hash tables */
3399 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3400 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3401 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3402 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3403 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3404 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3406 /* Assign actual uniform location, skipping over samplers */
3408 ctx
->uniform_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3410 nir_foreach_variable(var
, &nir
->uniforms
) {
3411 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_SAMPLER
) continue;
3413 unsigned length
= glsl_get_aoa_size(var
->type
);
3416 length
= glsl_get_length(var
->type
);
3420 length
= glsl_get_matrix_columns(var
->type
);
3423 for (int col
= 0; col
< length
; ++col
) {
3424 int id
= ctx
->uniform_count
++;
3425 _mesa_hash_table_u64_insert(ctx
->uniform_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3429 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3430 ctx
->varying_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3432 /* First, collect the special varyings */
3433 nir_foreach_variable(var
, &nir
->outputs
) {
3434 if (var
->data
.location
== VARYING_SLOT_POS
) {
3435 /* Set position first, always. It takes up two
3436 * spots, the latter one is de facto unused (at
3437 * least from the shader's perspective), we
3438 * just need to skip over the spot*/
3440 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (0 + 1)));
3441 ctx
->varying_count
= MAX2(ctx
->varying_count
, 2);
3442 } else if (var
->data
.location
== VARYING_SLOT_PSIZ
) {
3443 /* Set point size second (third, see above) */
3444 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (2 + 1)));
3445 ctx
->varying_count
= MAX2(ctx
->varying_count
, 3);
3447 program
->writes_point_size
= true;
3451 /* Now, collect normal varyings */
3453 nir_foreach_variable(var
, &nir
->outputs
) {
3454 if (var
->data
.location
== VARYING_SLOT_POS
|| var
->data
.location
== VARYING_SLOT_PSIZ
) continue;
3456 for (int col
= 0; col
< glsl_get_matrix_columns(var
->type
); ++col
) {
3457 int id
= ctx
->varying_count
++;
3458 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3465 /* Lower vars -- not I/O -- before epilogue */
3467 NIR_PASS_V(nir
, nir_lower_var_copies
);
3468 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3469 NIR_PASS_V(nir
, nir_split_var_copies
);
3470 NIR_PASS_V(nir
, nir_lower_var_copies
);
3471 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3472 NIR_PASS_V(nir
, nir_lower_var_copies
);
3473 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3474 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3476 /* Append vertex epilogue before optimisation, so the epilogue itself
3479 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3480 transform_position_writes(nir
);
3482 /* Optimisation passes */
3486 nir_print_shader(nir
, stdout
);
3488 /* Assign counts, now that we're sure (post-optimisation) */
3489 program
->uniform_count
= nir
->num_uniforms
;
3491 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3492 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3495 nir_foreach_function(func
, nir
) {
3499 list_inithead(&ctx
->blocks
);
3500 ctx
->block_count
= 0;
3503 emit_cf_list(ctx
, &func
->impl
->body
);
3504 emit_block(ctx
, func
->impl
->end_block
);
3506 break; /* TODO: Multi-function shaders */
3509 util_dynarray_init(compiled
, NULL
);
3512 schedule_program(ctx
);
3514 /* Now that all the bundles are scheduled and we can calculate block
3515 * sizes, emit actual branch instructions rather than placeholders */
3517 int br_block_idx
= 0;
3519 mir_foreach_block(ctx
, block
) {
3520 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3521 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3522 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3524 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3526 if (ins
->prepacked_branch
) continue;
3528 /* Parse some basic branch info */
3529 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3530 bool is_conditional
= ins
->branch
.conditional
;
3531 bool is_inverted
= ins
->branch
.invert_conditional
;
3532 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3534 /* Determine the block we're jumping to */
3535 int target_number
= ins
->branch
.target_block
;
3537 /* Report the destination tag. Discards don't need this */
3538 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3540 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3541 int quadword_offset
= 0;
3544 /* Jump to the end of the shader. We
3545 * need to include not only the
3546 * following blocks, but also the
3547 * contents of our current block (since
3548 * discard can come in the middle of
3551 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3553 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3554 quadword_offset
+= quadword_size(bun
->tag
);
3557 mir_foreach_block_from(ctx
, blk
, b
) {
3558 quadword_offset
+= b
->quadword_count
;
3561 } else if (target_number
> br_block_idx
) {
3564 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3565 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3568 quadword_offset
+= blk
->quadword_count
;
3571 /* Jump backwards */
3573 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3574 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3577 quadword_offset
-= blk
->quadword_count
;
3581 /* Unconditional extended branches (far jumps)
3582 * have issues, so we always use a conditional
3583 * branch, setting the condition to always for
3584 * unconditional. For compact unconditional
3585 * branches, cond isn't used so it doesn't
3586 * matter what we pick. */
3588 midgard_condition cond
=
3589 !is_conditional
? midgard_condition_always
:
3590 is_inverted
? midgard_condition_false
:
3591 midgard_condition_true
;
3593 midgard_jmp_writeout_op op
=
3594 is_discard
? midgard_jmp_writeout_op_discard
:
3595 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3596 midgard_jmp_writeout_op_branch_cond
;
3599 midgard_branch_extended branch
=
3600 midgard_create_branch_extended(
3605 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3606 } else if (is_conditional
|| is_discard
) {
3607 midgard_branch_cond branch
= {
3609 .dest_tag
= dest_tag
,
3610 .offset
= quadword_offset
,
3614 assert(branch
.offset
== quadword_offset
);
3616 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3618 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3620 midgard_branch_uncond branch
= {
3622 .dest_tag
= dest_tag
,
3623 .offset
= quadword_offset
,
3627 assert(branch
.offset
== quadword_offset
);
3629 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3637 /* Emit flat binary from the instruction arrays. Iterate each block in
3638 * sequence. Save instruction boundaries such that lookahead tags can
3639 * be assigned easily */
3641 /* Cache _all_ bundles in source order for lookahead across failed branches */
3643 int bundle_count
= 0;
3644 mir_foreach_block(ctx
, block
) {
3645 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3647 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3649 mir_foreach_block(ctx
, block
) {
3650 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3651 source_order_bundles
[bundle_idx
++] = bundle
;
3655 int current_bundle
= 0;
3657 mir_foreach_block(ctx
, block
) {
3658 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3661 if (current_bundle
+ 1 < bundle_count
) {
3662 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3664 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3671 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3675 /* TODO: Free deeper */
3676 //util_dynarray_fini(&block->instructions);
3679 free(source_order_bundles
);
3681 /* Report the very first tag executed */
3682 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3684 /* Deal with off-by-one related to the fencepost problem */
3685 program
->work_register_count
= ctx
->work_registers
+ 1;
3687 program
->can_discard
= ctx
->can_discard
;
3688 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3690 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3692 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);