2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 struct midgard_block
*next_fallthrough
;
175 /* Helpers to generate midgard_instruction's using macro magic, since every
176 * driver seems to do it that way */
178 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
179 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
181 #define M_LOAD_STORE(name, rname, uname) \
182 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
183 midgard_instruction i = { \
184 .type = TAG_LOAD_STORE_4, \
191 .op = midgard_op_##name, \
193 .swizzle = SWIZZLE_XYZW, \
201 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
202 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
204 const midgard_vector_alu_src blank_alu_src
= {
205 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
208 const midgard_vector_alu_src blank_alu_src_xxxx
= {
209 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
212 const midgard_scalar_alu_src blank_scalar_alu_src
= {
216 /* Used for encoding the unused source of 1-op instructions */
217 const midgard_vector_alu_src zero_alu_src
= { 0 };
219 /* Coerce structs to integer */
222 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
225 memcpy(&u
, &src
, sizeof(src
));
229 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
230 * the corresponding Midgard source */
232 static midgard_vector_alu_src
233 vector_alu_modifiers(nir_alu_src
*src
)
235 if (!src
) return blank_alu_src
;
237 midgard_vector_alu_src alu_src
= {
239 .negate
= src
->negate
,
242 .half
= 0, /* TODO */
243 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
249 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
251 static midgard_instruction
252 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
254 midgard_instruction ins
= {
257 .src0
= SSA_UNUSED_1
,
262 .op
= midgard_alu_op_fmov
,
263 .reg_mode
= midgard_reg_mode_full
,
264 .dest_override
= midgard_dest_override_none
,
266 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
267 .src2
= vector_alu_srco_unsigned(mod
)
274 /* load/store instructions have both 32-bit and 16-bit variants, depending on
275 * whether we are using vectors composed of highp or mediump. At the moment, we
276 * don't support half-floats -- this requires changes in other parts of the
277 * compiler -- therefore the 16-bit versions are commented out. */
279 //M_LOAD(load_attr_16);
280 M_LOAD(load_attr_32
);
281 //M_LOAD(load_vary_16);
282 M_LOAD(load_vary_32
);
283 //M_LOAD(load_uniform_16);
284 M_LOAD(load_uniform_32
);
285 M_LOAD(load_color_buffer_8
);
286 //M_STORE(store_vary_16);
287 M_STORE(store_vary_32
);
288 M_STORE(store_cubemap_coords
);
290 static midgard_instruction
291 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
293 midgard_branch_cond branch
= {
301 memcpy(&compact
, &branch
, sizeof(branch
));
303 midgard_instruction ins
= {
305 .unit
= ALU_ENAB_BR_COMPACT
,
306 .prepacked_branch
= true,
307 .compact_branch
= true,
308 .br_compact
= compact
311 if (op
== midgard_jmp_writeout_op_writeout
)
317 static midgard_instruction
318 v_branch(bool conditional
, bool invert
)
320 midgard_instruction ins
= {
322 .unit
= ALU_ENAB_BRANCH
,
323 .compact_branch
= true,
325 .conditional
= conditional
,
326 .invert_conditional
= invert
333 static midgard_branch_extended
334 midgard_create_branch_extended( midgard_condition cond
,
335 midgard_jmp_writeout_op op
,
337 signed quadword_offset
)
339 /* For unclear reasons, the condition code is repeated 8 times */
340 uint16_t duplicated_cond
=
350 midgard_branch_extended branch
= {
352 .dest_tag
= dest_tag
,
353 .offset
= quadword_offset
,
354 .cond
= duplicated_cond
360 typedef struct midgard_bundle
{
361 /* Tag for the overall bundle */
364 /* Instructions contained by the bundle */
365 int instruction_count
;
366 midgard_instruction instructions
[5];
368 /* Bundle-wide ALU configuration */
371 bool has_embedded_constants
;
373 bool has_blend_constant
;
375 uint16_t register_words
[8];
376 int register_words_count
;
378 uint64_t body_words
[8];
380 int body_words_count
;
383 typedef struct compiler_context
{
385 gl_shader_stage stage
;
387 /* Is internally a blend shader? Depends on stage == FRAGMENT */
390 /* Tracking for blend constant patching */
391 int blend_constant_number
;
392 int blend_constant_offset
;
394 /* Current NIR function */
397 /* Unordered list of midgard_blocks */
399 struct list_head blocks
;
401 midgard_block
*initial_block
;
402 midgard_block
*previous_source_block
;
403 midgard_block
*final_block
;
405 /* List of midgard_instructions emitted for the current block */
406 midgard_block
*current_block
;
408 /* The index corresponding to the current loop, e.g. for breaks/contineus */
411 /* Constants which have been loaded, for later inlining */
412 struct hash_table_u64
*ssa_constants
;
414 /* SSA indices to be outputted to corresponding varying offset */
415 struct hash_table_u64
*ssa_varyings
;
417 /* SSA values / registers which have been aliased. Naively, these
418 * demand a fmov output; instead, we alias them in a later pass to
419 * avoid the wasted op.
421 * A note on encoding: to avoid dynamic memory management here, rather
422 * than ampping to a pointer, we map to the source index; the key
423 * itself is just the destination index. */
425 struct hash_table_u64
*ssa_to_alias
;
426 struct set
*leftover_ssa_to_alias
;
428 /* Actual SSA-to-register for RA */
429 struct hash_table_u64
*ssa_to_register
;
431 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
432 struct hash_table_u64
*hash_to_temp
;
436 /* Just the count of the max register used. Higher count => higher
437 * register pressure */
440 /* Used for cont/last hinting. Increase when a tex op is added.
441 * Decrease when a tex op is removed. */
442 int texture_op_count
;
444 /* Mapping of texture register -> SSA index for unaliasing */
445 int texture_index
[2];
447 /* If any path hits a discard instruction */
450 /* The number of uniforms allowable for the fast path */
453 /* Count of instructions emitted from NIR overall, across all blocks */
454 int instruction_count
;
456 /* Alpha ref value passed in */
459 /* The index corresponding to the fragment output */
460 unsigned fragment_output
;
462 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
463 unsigned sysvals
[MAX_SYSVAL_COUNT
];
464 unsigned sysval_count
;
465 struct hash_table_u64
*sysval_to_id
;
468 /* Append instruction to end of current block */
470 static midgard_instruction
*
471 mir_upload_ins(struct midgard_instruction ins
)
473 midgard_instruction
*heap
= malloc(sizeof(ins
));
474 memcpy(heap
, &ins
, sizeof(ins
));
479 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
481 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
485 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
487 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
491 mir_remove_instruction(struct midgard_instruction
*ins
)
493 list_del(&ins
->link
);
496 static midgard_instruction
*
497 mir_prev_op(struct midgard_instruction
*ins
)
499 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
502 static midgard_instruction
*
503 mir_next_op(struct midgard_instruction
*ins
)
505 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
508 static midgard_block
*
509 mir_next_block(struct midgard_block
*blk
)
511 return list_first_entry(&(blk
->link
), midgard_block
, link
);
515 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
516 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
518 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
519 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
520 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
521 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
522 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
523 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
526 static midgard_instruction
*
527 mir_last_in_block(struct midgard_block
*block
)
529 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
532 static midgard_block
*
533 mir_get_block(compiler_context
*ctx
, int idx
)
535 struct list_head
*lst
= &ctx
->blocks
;
540 return (struct midgard_block
*) lst
;
543 /* Pretty printer for internal Midgard IR */
546 print_mir_source(int source
)
548 if (source
>= SSA_FIXED_MINIMUM
) {
549 /* Specific register */
550 int reg
= SSA_REG_FROM_FIXED(source
);
552 /* TODO: Moving threshold */
553 if (reg
> 16 && reg
< 24)
554 printf("u%d", 23 - reg
);
558 printf("%d", source
);
563 print_mir_instruction(midgard_instruction
*ins
)
569 midgard_alu_op op
= ins
->alu
.op
;
570 const char *name
= alu_opcode_names
[op
];
573 printf("%d.", ins
->unit
);
575 printf("%s", name
? name
: "??");
579 case TAG_LOAD_STORE_4
: {
580 midgard_load_store_op op
= ins
->load_store
.op
;
581 const char *name
= load_store_opcode_names
[op
];
588 case TAG_TEXTURE_4
: {
597 ssa_args
*args
= &ins
->ssa_args
;
599 printf(" %d, ", args
->dest
);
601 print_mir_source(args
->src0
);
604 if (args
->inline_constant
)
605 printf("#%d", ins
->inline_constant
);
607 print_mir_source(args
->src1
);
609 if (ins
->has_constants
)
610 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
616 print_mir_block(midgard_block
*block
)
620 mir_foreach_instr_in_block(block
, ins
) {
621 print_mir_instruction(ins
);
630 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
632 ins
->has_constants
= true;
633 memcpy(&ins
->constants
, constants
, 16);
635 /* If this is the special blend constant, mark this instruction */
637 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
638 ins
->has_blend_constant
= true;
642 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
644 return glsl_count_attribute_slots(type
, false);
647 /* Lower fdot2 to a vector multiplication followed by channel addition */
649 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
651 if (alu
->op
!= nir_op_fdot2
)
654 b
->cursor
= nir_before_instr(&alu
->instr
);
656 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
657 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
659 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
661 nir_ssa_def
*sum
= nir_fadd(b
,
662 nir_channel(b
, product
, 0),
663 nir_channel(b
, product
, 1));
665 /* Replace the fdot2 with this sum */
666 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
670 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
672 switch (instr
->intrinsic
) {
673 case nir_intrinsic_load_viewport_scale
:
674 return PAN_SYSVAL_VIEWPORT_SCALE
;
675 case nir_intrinsic_load_viewport_offset
:
676 return PAN_SYSVAL_VIEWPORT_OFFSET
;
683 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
687 if (instr
->type
== nir_instr_type_intrinsic
) {
688 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
689 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
695 /* We have a sysval load; check if it's already been assigned */
697 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
700 /* It hasn't -- so assign it now! */
702 unsigned id
= ctx
->sysval_count
++;
703 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
704 ctx
->sysvals
[id
] = sysval
;
708 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
710 ctx
->sysval_count
= 0;
712 nir_foreach_function(function
, shader
) {
713 if (!function
->impl
) continue;
715 nir_foreach_block(block
, function
->impl
) {
716 nir_foreach_instr_safe(instr
, block
) {
717 midgard_nir_assign_sysval_body(ctx
, instr
);
724 midgard_nir_lower_fdot2(nir_shader
*shader
)
726 bool progress
= false;
728 nir_foreach_function(function
, shader
) {
729 if (!function
->impl
) continue;
732 nir_builder
*b
= &_b
;
733 nir_builder_init(b
, function
->impl
);
735 nir_foreach_block(block
, function
->impl
) {
736 nir_foreach_instr_safe(instr
, block
) {
737 if (instr
->type
!= nir_instr_type_alu
) continue;
739 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
740 midgard_nir_lower_fdot2_body(b
, alu
);
746 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
754 optimise_nir(nir_shader
*nir
)
758 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
759 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
761 nir_lower_tex_options lower_tex_options
= {
765 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
770 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
771 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
773 NIR_PASS(progress
, nir
, nir_copy_prop
);
774 NIR_PASS(progress
, nir
, nir_opt_dce
);
775 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
776 NIR_PASS(progress
, nir
, nir_opt_cse
);
777 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
778 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
779 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
780 NIR_PASS(progress
, nir
, nir_opt_undef
);
781 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
784 nir_var_function_temp
);
786 /* TODO: Enable vectorize when merged upstream */
787 // NIR_PASS(progress, nir, nir_opt_vectorize);
790 /* Must be run at the end to prevent creation of fsin/fcos ops */
791 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
796 NIR_PASS(progress
, nir
, nir_opt_dce
);
797 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
798 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
799 NIR_PASS(progress
, nir
, nir_copy_prop
);
802 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
803 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
805 /* Lower mods for float ops only. Integer ops don't support modifiers
806 * (saturate doesn't make sense on integers, neg/abs require dedicated
809 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
810 NIR_PASS(progress
, nir
, nir_copy_prop
);
811 NIR_PASS(progress
, nir
, nir_opt_dce
);
813 /* We implement booleans as 32-bit 0/~0 */
814 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
816 /* Take us out of SSA */
817 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
818 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
820 /* We are a vector architecture; write combine where possible */
821 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
822 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
824 NIR_PASS(progress
, nir
, nir_opt_dce
);
827 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
828 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
829 * r0. See the comments in compiler_context */
832 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
834 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
835 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
838 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
841 unalias_ssa(compiler_context
*ctx
, int dest
)
843 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
844 /* TODO: Remove from leftover or no? */
848 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
850 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
854 midgard_is_pinned(compiler_context
*ctx
, int index
)
856 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
859 /* Do not actually emit a load; instead, cache the constant for inlining */
862 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
864 nir_ssa_def def
= instr
->def
;
866 float *v
= ralloc_array(NULL
, float, 4);
867 nir_const_load_to_arr(v
, instr
, f32
);
868 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
871 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
875 expand_writemask(unsigned mask
)
879 for (int i
= 0; i
< 4; ++i
)
887 squeeze_writemask(unsigned mask
)
891 for (int i
= 0; i
< 4; ++i
)
892 if (mask
& (3 << (2 * i
)))
899 /* Determines effective writemask, taking quirks and expansion into account */
901 effective_writemask(midgard_vector_alu
*alu
)
903 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
906 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
908 /* If there is a fixed channel count, construct the appropriate mask */
911 return (1 << channel_count
) - 1;
913 /* Otherwise, just squeeze the existing mask */
914 return squeeze_writemask(alu
->mask
);
918 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
920 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
923 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
928 /* If no temp is find, allocate one */
929 temp
= ctx
->temp_count
++;
930 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
932 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
938 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
941 return src
->ssa
->index
;
943 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
947 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
950 return dst
->ssa
.index
;
952 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
956 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
958 return nir_src_index(ctx
, &src
->src
);
961 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
962 * a conditional test) into that register */
965 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
967 int condition
= nir_src_index(ctx
, src
);
969 /* Source to swizzle the desired component into w */
971 const midgard_vector_alu_src alu_src
= {
972 .swizzle
= SWIZZLE(component
, component
, component
, component
),
975 /* There is no boolean move instruction. Instead, we simulate a move by
976 * ANDing the condition with itself to get it into r31.w */
978 midgard_instruction ins
= {
980 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
984 .dest
= SSA_FIXED_REGISTER(31),
987 .op
= midgard_alu_op_iand
,
988 .reg_mode
= midgard_reg_mode_full
,
989 .dest_override
= midgard_dest_override_none
,
990 .mask
= (0x3 << 6), /* w */
991 .src1
= vector_alu_srco_unsigned(alu_src
),
992 .src2
= vector_alu_srco_unsigned(alu_src
)
996 emit_mir_instruction(ctx
, ins
);
999 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1000 * pinning to eliminate this move in all known cases */
1003 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1005 int offset
= nir_src_index(ctx
, src
);
1007 midgard_instruction ins
= {
1010 .src0
= SSA_UNUSED_1
,
1012 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1015 .op
= midgard_alu_op_imov
,
1016 .reg_mode
= midgard_reg_mode_full
,
1017 .dest_override
= midgard_dest_override_none
,
1018 .mask
= (0x3 << 6), /* w */
1019 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1020 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1024 emit_mir_instruction(ctx
, ins
);
1027 #define ALU_CASE(nir, _op) \
1028 case nir_op_##nir: \
1029 op = midgard_alu_op_##_op; \
1033 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1035 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1037 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1038 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1039 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1041 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1042 * supported. A few do not and are commented for now. Also, there are a
1043 * number of NIR ops which Midgard does not support and need to be
1044 * lowered, also TODO. This switch block emits the opcode and calling
1045 * convention of the Midgard instruction; actual packing is done in
1050 switch (instr
->op
) {
1051 ALU_CASE(fadd
, fadd
);
1052 ALU_CASE(fmul
, fmul
);
1053 ALU_CASE(fmin
, fmin
);
1054 ALU_CASE(fmax
, fmax
);
1055 ALU_CASE(imin
, imin
);
1056 ALU_CASE(imax
, imax
);
1057 ALU_CASE(umin
, umin
);
1058 ALU_CASE(umax
, umax
);
1059 ALU_CASE(fmov
, fmov
);
1060 ALU_CASE(ffloor
, ffloor
);
1061 ALU_CASE(fround_even
, froundeven
);
1062 ALU_CASE(ftrunc
, ftrunc
);
1063 ALU_CASE(fceil
, fceil
);
1064 ALU_CASE(fdot3
, fdot3
);
1065 ALU_CASE(fdot4
, fdot4
);
1066 ALU_CASE(iadd
, iadd
);
1067 ALU_CASE(isub
, isub
);
1068 ALU_CASE(imul
, imul
);
1069 ALU_CASE(iabs
, iabs
);
1071 /* XXX: Use fmov, not imov, since imov was causing major
1072 * issues with texture precision? XXX research */
1073 ALU_CASE(imov
, fmov
);
1075 ALU_CASE(feq32
, feq
);
1076 ALU_CASE(fne32
, fne
);
1077 ALU_CASE(flt32
, flt
);
1078 ALU_CASE(ieq32
, ieq
);
1079 ALU_CASE(ine32
, ine
);
1080 ALU_CASE(ilt32
, ilt
);
1081 ALU_CASE(ult32
, ult
);
1083 /* We don't have a native b2f32 instruction. Instead, like many
1084 * GPUs, we exploit booleans as 0/~0 for false/true, and
1085 * correspondingly AND
1086 * by 1.0 to do the type conversion. For the moment, prime us
1089 * iand [whatever], #0
1091 * At the end of emit_alu (as MIR), we'll fix-up the constant
1094 ALU_CASE(b2f32
, iand
);
1095 ALU_CASE(b2i32
, iand
);
1097 /* Likewise, we don't have a dedicated f2b32 instruction, but
1098 * we can do a "not equal to 0.0" test. */
1100 ALU_CASE(f2b32
, fne
);
1101 ALU_CASE(i2b32
, ine
);
1103 ALU_CASE(frcp
, frcp
);
1104 ALU_CASE(frsq
, frsqrt
);
1105 ALU_CASE(fsqrt
, fsqrt
);
1106 ALU_CASE(fexp2
, fexp2
);
1107 ALU_CASE(flog2
, flog2
);
1109 ALU_CASE(f2i32
, f2i
);
1110 ALU_CASE(f2u32
, f2u
);
1111 ALU_CASE(i2f32
, i2f
);
1112 ALU_CASE(u2f32
, u2f
);
1114 ALU_CASE(fsin
, fsin
);
1115 ALU_CASE(fcos
, fcos
);
1117 ALU_CASE(iand
, iand
);
1119 ALU_CASE(ixor
, ixor
);
1120 ALU_CASE(inot
, inot
);
1121 ALU_CASE(ishl
, ishl
);
1122 ALU_CASE(ishr
, iasr
);
1123 ALU_CASE(ushr
, ilsr
);
1125 ALU_CASE(b32all_fequal2
, fball_eq
);
1126 ALU_CASE(b32all_fequal3
, fball_eq
);
1127 ALU_CASE(b32all_fequal4
, fball_eq
);
1129 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1130 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1131 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1133 ALU_CASE(b32all_iequal2
, iball_eq
);
1134 ALU_CASE(b32all_iequal3
, iball_eq
);
1135 ALU_CASE(b32all_iequal4
, iball_eq
);
1137 ALU_CASE(b32any_inequal2
, ibany_neq
);
1138 ALU_CASE(b32any_inequal3
, ibany_neq
);
1139 ALU_CASE(b32any_inequal4
, ibany_neq
);
1141 /* For greater-or-equal, we lower to less-or-equal and flip the
1147 case nir_op_uge32
: {
1149 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1150 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1151 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1152 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1155 /* Swap via temporary */
1156 nir_alu_src temp
= instr
->src
[1];
1157 instr
->src
[1] = instr
->src
[0];
1158 instr
->src
[0] = temp
;
1163 case nir_op_b32csel
: {
1164 op
= midgard_alu_op_fcsel
;
1166 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1169 /* Figure out which component the condition is in */
1171 unsigned comp
= instr
->src
[0].swizzle
[0];
1173 /* Make sure NIR isn't throwing a mixed condition at us */
1175 for (unsigned c
= 1; c
< nr_components
; ++c
)
1176 assert(instr
->src
[0].swizzle
[c
] == comp
);
1178 /* Emit the condition into r31.w */
1179 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1181 /* The condition is the first argument; move the other
1182 * arguments up one to be a binary instruction for
1185 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1190 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1195 /* Fetch unit, quirks, etc information */
1196 unsigned opcode_props
= alu_opcode_props
[op
];
1197 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1199 /* Initialise fields common between scalar/vector instructions */
1200 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1202 /* src0 will always exist afaik, but src1 will not for 1-argument
1203 * instructions. The latter can only be fetched if the instruction
1204 * needs it, or else we may segfault. */
1206 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1207 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1209 /* Rather than use the instruction generation helpers, we do it
1210 * ourselves here to avoid the mess */
1212 midgard_instruction ins
= {
1215 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1216 .src1
= quirk_flipped_r24
? src0
: src1
,
1221 nir_alu_src
*nirmods
[2] = { NULL
};
1223 if (nr_inputs
== 2) {
1224 nirmods
[0] = &instr
->src
[0];
1225 nirmods
[1] = &instr
->src
[1];
1226 } else if (nr_inputs
== 1) {
1227 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1232 midgard_vector_alu alu
= {
1234 .reg_mode
= midgard_reg_mode_full
,
1235 .dest_override
= midgard_dest_override_none
,
1238 /* Writemask only valid for non-SSA NIR */
1239 .mask
= expand_writemask((1 << nr_components
) - 1),
1241 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1242 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1245 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1248 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1252 /* Late fixup for emulated instructions */
1254 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1255 /* Presently, our second argument is an inline #0 constant.
1256 * Switch over to an embedded 1.0 constant (that can't fit
1257 * inline, since we're 32-bit, not 16-bit like the inline
1260 ins
.ssa_args
.inline_constant
= false;
1261 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1262 ins
.has_constants
= true;
1264 if (instr
->op
== nir_op_b2f32
) {
1265 ins
.constants
[0] = 1.0f
;
1267 /* Type pun it into place */
1269 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1272 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1273 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1274 ins
.ssa_args
.inline_constant
= false;
1275 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1276 ins
.has_constants
= true;
1277 ins
.constants
[0] = 0.0f
;
1278 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1281 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1282 /* To avoid duplicating the lookup tables (probably), true LUT
1283 * instructions can only operate as if they were scalars. Lower
1284 * them here by changing the component. */
1286 uint8_t original_swizzle
[4];
1287 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1289 for (int i
= 0; i
< nr_components
; ++i
) {
1290 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1292 for (int j
= 0; j
< 4; ++j
)
1293 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1295 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1296 emit_mir_instruction(ctx
, ins
);
1299 emit_mir_instruction(ctx
, ins
);
1306 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1308 /* TODO: half-floats */
1310 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1311 /* Fast path: For the first 16 uniforms, direct accesses are
1312 * 0-cycle, since they're just a register fetch in the usual
1313 * case. So, we alias the registers while we're still in
1316 int reg_slot
= 23 - offset
;
1317 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1319 /* Otherwise, read from the 'special' UBO to access
1320 * higher-indexed uniforms, at a performance cost. More
1321 * generally, we're emitting a UBO read instruction. */
1323 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1325 /* TODO: Don't split */
1326 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1327 ins
.load_store
.address
= offset
>> 3;
1329 if (indirect_offset
) {
1330 emit_indirect_offset(ctx
, indirect_offset
);
1331 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1333 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1336 emit_mir_instruction(ctx
, ins
);
1341 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1343 /* First, pull out the destination */
1344 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1346 /* Now, figure out which uniform this is */
1347 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1348 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1350 /* Sysvals are prefix uniforms */
1351 unsigned uniform
= ((uintptr_t) val
) - 1;
1353 /* Emit the read itself -- this is never indirect */
1354 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1358 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1360 unsigned offset
, reg
;
1362 switch (instr
->intrinsic
) {
1363 case nir_intrinsic_discard_if
:
1364 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1368 case nir_intrinsic_discard
: {
1369 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1370 struct midgard_instruction discard
= v_branch(conditional
, false);
1371 discard
.branch
.target_type
= TARGET_DISCARD
;
1372 emit_mir_instruction(ctx
, discard
);
1374 ctx
->can_discard
= true;
1378 case nir_intrinsic_load_uniform
:
1379 case nir_intrinsic_load_input
:
1380 offset
= nir_intrinsic_base(instr
);
1382 bool direct
= nir_src_is_const(instr
->src
[0]);
1385 offset
+= nir_src_as_uint(instr
->src
[0]);
1388 reg
= nir_dest_index(ctx
, &instr
->dest
);
1390 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1391 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1392 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1393 /* XXX: Half-floats? */
1394 /* TODO: swizzle, mask */
1396 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1398 midgard_varying_parameter p
= {
1400 .interpolation
= midgard_interp_default
,
1401 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1405 memcpy(&u
, &p
, sizeof(p
));
1406 ins
.load_store
.varying_parameters
= u
;
1409 /* We have the offset totally ready */
1410 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1412 /* We have it partially ready, but we need to
1413 * add in the dynamic index, moved to r27.w */
1414 emit_indirect_offset(ctx
, &instr
->src
[0]);
1415 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1418 emit_mir_instruction(ctx
, ins
);
1419 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1420 /* Constant encoded as a pinned constant */
1422 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1423 ins
.has_constants
= true;
1424 ins
.has_blend_constant
= true;
1425 emit_mir_instruction(ctx
, ins
);
1426 } else if (ctx
->is_blend
) {
1427 /* For blend shaders, a load might be
1428 * translated various ways depending on what
1429 * we're loading. Figure out how this is used */
1431 nir_variable
*out
= NULL
;
1433 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1434 int drvloc
= var
->data
.driver_location
;
1436 if (nir_intrinsic_base(instr
) == drvloc
) {
1444 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1445 /* Source color preloaded to r0 */
1447 midgard_pin_output(ctx
, reg
, 0);
1448 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1449 /* Destination color must be read from framebuffer */
1451 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1452 ins
.load_store
.swizzle
= 0; /* xxxx */
1454 /* Read each component sequentially */
1456 for (int c
= 0; c
< 4; ++c
) {
1457 ins
.load_store
.mask
= (1 << c
);
1458 ins
.load_store
.unknown
= c
;
1459 emit_mir_instruction(ctx
, ins
);
1462 /* vadd.u2f hr2, abs(hr2), #0 */
1464 midgard_vector_alu_src alu_src
= blank_alu_src
;
1466 alu_src
.half
= true;
1468 midgard_instruction u2f
= {
1472 .src1
= SSA_UNUSED_0
,
1474 .inline_constant
= true
1477 .op
= midgard_alu_op_u2f
,
1478 .reg_mode
= midgard_reg_mode_half
,
1479 .dest_override
= midgard_dest_override_none
,
1481 .src1
= vector_alu_srco_unsigned(alu_src
),
1482 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1486 emit_mir_instruction(ctx
, u2f
);
1488 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1490 alu_src
.abs
= false;
1492 midgard_instruction fmul
= {
1494 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1498 .src1
= SSA_UNUSED_0
,
1499 .inline_constant
= true
1502 .op
= midgard_alu_op_fmul
,
1503 .reg_mode
= midgard_reg_mode_full
,
1504 .dest_override
= midgard_dest_override_none
,
1505 .outmod
= midgard_outmod_sat
,
1507 .src1
= vector_alu_srco_unsigned(alu_src
),
1508 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1512 emit_mir_instruction(ctx
, fmul
);
1514 DBG("Unknown input in blend shader\n");
1517 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1518 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1519 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1520 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1521 emit_mir_instruction(ctx
, ins
);
1523 DBG("Unknown load\n");
1529 case nir_intrinsic_store_output
:
1530 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1532 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1534 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1536 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1537 /* gl_FragColor is not emitted with load/store
1538 * instructions. Instead, it gets plonked into
1539 * r0 at the end of the shader and we do the
1540 * framebuffer writeout dance. TODO: Defer
1543 midgard_pin_output(ctx
, reg
, 0);
1545 /* Save the index we're writing to for later reference
1546 * in the epilogue */
1548 ctx
->fragment_output
= reg
;
1549 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1550 /* Varyings are written into one of two special
1551 * varying register, r26 or r27. The register itself is selected as the register
1552 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1554 * Normally emitting fmov's is frowned upon,
1555 * but due to unique constraints of
1556 * REGISTER_VARYING, fmov emission + a
1557 * dedicated cleanup pass is the only way to
1558 * guarantee correctness when considering some
1559 * (common) edge cases XXX: FIXME */
1561 /* If this varying corresponds to a constant (why?!),
1562 * emit that now since it won't get picked up by
1563 * hoisting (since there is no corresponding move
1564 * emitted otherwise) */
1566 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1568 if (constant_value
) {
1569 /* Special case: emit the varying write
1570 * directly to r26 (looks funny in asm but it's
1571 * fine) and emit the store _now_. Possibly
1572 * slightly slower, but this is a really stupid
1573 * special case anyway (why on earth would you
1574 * have a constant varying? Your own fault for
1575 * slightly worse perf :P) */
1577 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1578 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1579 emit_mir_instruction(ctx
, ins
);
1581 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1582 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1583 emit_mir_instruction(ctx
, st
);
1585 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1587 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1590 DBG("Unknown store\n");
1596 case nir_intrinsic_load_alpha_ref_float
:
1597 assert(instr
->dest
.is_ssa
);
1599 float ref_value
= ctx
->alpha_ref
;
1601 float *v
= ralloc_array(NULL
, float, 4);
1602 memcpy(v
, &ref_value
, sizeof(float));
1603 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1606 case nir_intrinsic_load_viewport_scale
:
1607 case nir_intrinsic_load_viewport_offset
:
1608 emit_sysval_read(ctx
, instr
);
1612 printf ("Unhandled intrinsic\n");
1619 midgard_tex_format(enum glsl_sampler_dim dim
)
1622 case GLSL_SAMPLER_DIM_2D
:
1623 case GLSL_SAMPLER_DIM_EXTERNAL
:
1626 case GLSL_SAMPLER_DIM_3D
:
1629 case GLSL_SAMPLER_DIM_CUBE
:
1630 return TEXTURE_CUBE
;
1633 DBG("Unknown sampler dim type\n");
1640 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1643 //assert (!instr->sampler);
1644 //assert (!instr->texture_array_size);
1645 assert (instr
->op
== nir_texop_tex
);
1647 /* Allocate registers via a round robin scheme to alternate between the two registers */
1648 int reg
= ctx
->texture_op_count
& 1;
1649 int in_reg
= reg
, out_reg
= reg
;
1651 /* Make room for the reg */
1653 if (ctx
->texture_index
[reg
] > -1)
1654 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1656 int texture_index
= instr
->texture_index
;
1657 int sampler_index
= texture_index
;
1659 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1660 switch (instr
->src
[i
].src_type
) {
1661 case nir_tex_src_coord
: {
1662 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1664 midgard_vector_alu_src alu_src
= blank_alu_src
;
1666 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1668 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1669 /* For cubemaps, we need to load coords into
1670 * special r27, and then use a special ld/st op
1671 * to copy into the texture register */
1673 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1675 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1676 emit_mir_instruction(ctx
, move
);
1678 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1679 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1680 st
.load_store
.mask
= 0x3; /* xy? */
1681 st
.load_store
.swizzle
= alu_src
.swizzle
;
1682 emit_mir_instruction(ctx
, st
);
1685 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1687 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1688 emit_mir_instruction(ctx
, ins
);
1691 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1697 DBG("Unknown source type\n");
1704 /* No helper to build texture words -- we do it all here */
1705 midgard_instruction ins
= {
1706 .type
= TAG_TEXTURE_4
,
1708 .op
= TEXTURE_OP_NORMAL
,
1709 .format
= midgard_tex_format(instr
->sampler_dim
),
1710 .texture_handle
= texture_index
,
1711 .sampler_handle
= sampler_index
,
1713 /* TODO: Don't force xyzw */
1714 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1726 /* Assume we can continue; hint it out later */
1731 /* Set registers to read and write from the same place */
1732 ins
.texture
.in_reg_select
= in_reg
;
1733 ins
.texture
.out_reg_select
= out_reg
;
1735 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1736 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1737 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1738 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1739 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1741 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1742 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1743 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1746 emit_mir_instruction(ctx
, ins
);
1748 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1750 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1751 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1752 ctx
->texture_index
[reg
] = o_index
;
1754 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1755 emit_mir_instruction(ctx
, ins2
);
1757 /* Used for .cont and .last hinting */
1758 ctx
->texture_op_count
++;
1762 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1764 switch (instr
->type
) {
1765 case nir_jump_break
: {
1766 /* Emit a branch out of the loop */
1767 struct midgard_instruction br
= v_branch(false, false);
1768 br
.branch
.target_type
= TARGET_BREAK
;
1769 br
.branch
.target_break
= ctx
->current_loop
;
1770 emit_mir_instruction(ctx
, br
);
1777 DBG("Unknown jump type %d\n", instr
->type
);
1783 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1785 switch (instr
->type
) {
1786 case nir_instr_type_load_const
:
1787 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1790 case nir_instr_type_intrinsic
:
1791 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1794 case nir_instr_type_alu
:
1795 emit_alu(ctx
, nir_instr_as_alu(instr
));
1798 case nir_instr_type_tex
:
1799 emit_tex(ctx
, nir_instr_as_tex(instr
));
1802 case nir_instr_type_jump
:
1803 emit_jump(ctx
, nir_instr_as_jump(instr
));
1806 case nir_instr_type_ssa_undef
:
1811 DBG("Unhandled instruction type\n");
1816 /* Determine the actual hardware from the index based on the RA results or special values */
1819 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1821 if (reg
>= SSA_FIXED_MINIMUM
)
1822 return SSA_REG_FROM_FIXED(reg
);
1825 assert(reg
< maxreg
);
1826 int r
= ra_get_node_reg(g
, reg
);
1827 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1832 /* fmov style unused */
1834 return REGISTER_UNUSED
;
1836 /* lut style unused */
1838 return REGISTER_UNUSED
;
1841 DBG("Unknown SSA register alias %d\n", reg
);
1848 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1850 /* Choose the first available register to minimise reported register pressure */
1852 for (int i
= 0; i
< 16; ++i
) {
1853 if (BITSET_TEST(regs
, i
)) {
1863 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1865 if (ins
->ssa_args
.src0
== src
) return true;
1866 if (ins
->ssa_args
.src1
== src
) return true;
1872 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1874 /* Check the rest of the block for liveness */
1875 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1876 if (midgard_is_live_in_instr(ins
, src
))
1880 /* Check the rest of the blocks for liveness */
1881 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1882 mir_foreach_instr_in_block(b
, ins
) {
1883 if (midgard_is_live_in_instr(ins
, src
))
1888 /* TODO: How does control flow interact in complex shaders? */
1894 allocate_registers(compiler_context
*ctx
)
1896 /* First, initialize the RA */
1897 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1899 /* Create a primary (general purpose) class, as well as special purpose
1900 * pipeline register classes */
1902 int primary_class
= ra_alloc_reg_class(regs
);
1903 int varying_class
= ra_alloc_reg_class(regs
);
1905 /* Add the full set of work registers */
1906 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1907 for (int i
= 0; i
< work_count
; ++i
)
1908 ra_class_add_reg(regs
, primary_class
, i
);
1910 /* Add special registers */
1911 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1912 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1914 /* We're done setting up */
1915 ra_set_finalize(regs
, NULL
);
1917 /* Transform the MIR into squeezed index form */
1918 mir_foreach_block(ctx
, block
) {
1919 mir_foreach_instr_in_block(block
, ins
) {
1920 if (ins
->compact_branch
) continue;
1922 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1923 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1924 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1926 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1927 print_mir_block(block
);
1930 /* Let's actually do register allocation */
1931 int nodes
= ctx
->temp_count
;
1932 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1934 /* Set everything to the work register class, unless it has somewhere
1937 mir_foreach_block(ctx
, block
) {
1938 mir_foreach_instr_in_block(block
, ins
) {
1939 if (ins
->compact_branch
) continue;
1941 if (ins
->ssa_args
.dest
< 0) continue;
1943 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1945 int class = primary_class
;
1947 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1951 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1952 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1955 unsigned reg
= temp
- 1;
1956 int t
= find_or_allocate_temp(ctx
, index
);
1957 ra_set_node_reg(g
, t
, reg
);
1961 /* Determine liveness */
1963 int *live_start
= malloc(nodes
* sizeof(int));
1964 int *live_end
= malloc(nodes
* sizeof(int));
1966 /* Initialize as non-existent */
1968 for (int i
= 0; i
< nodes
; ++i
) {
1969 live_start
[i
] = live_end
[i
] = -1;
1974 mir_foreach_block(ctx
, block
) {
1975 mir_foreach_instr_in_block(block
, ins
) {
1976 if (ins
->compact_branch
) continue;
1978 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1979 /* If this destination is not yet live, it is now since we just wrote it */
1981 int dest
= ins
->ssa_args
.dest
;
1983 if (live_start
[dest
] == -1)
1984 live_start
[dest
] = d
;
1987 /* Since we just used a source, the source might be
1988 * dead now. Scan the rest of the block for
1989 * invocations, and if there are none, the source dies
1992 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1994 for (int src
= 0; src
< 2; ++src
) {
1995 int s
= sources
[src
];
1997 if (s
< 0) continue;
1999 if (s
>= SSA_FIXED_MINIMUM
) continue;
2001 if (!is_live_after(ctx
, block
, ins
, s
)) {
2010 /* If a node still hasn't been killed, kill it now */
2012 for (int i
= 0; i
< nodes
; ++i
) {
2013 /* live_start == -1 most likely indicates a pinned output */
2015 if (live_end
[i
] == -1)
2019 /* Setup interference between nodes that are live at the same time */
2021 for (int i
= 0; i
< nodes
; ++i
) {
2022 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2023 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2024 ra_add_node_interference(g
, i
, j
);
2028 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2030 if (!ra_allocate(g
)) {
2031 DBG("Error allocating registers\n");
2039 mir_foreach_block(ctx
, block
) {
2040 mir_foreach_instr_in_block(block
, ins
) {
2041 if (ins
->compact_branch
) continue;
2043 ssa_args args
= ins
->ssa_args
;
2045 switch (ins
->type
) {
2047 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
2049 ins
->registers
.src2_imm
= args
.inline_constant
;
2051 if (args
.inline_constant
) {
2052 /* Encode inline 16-bit constant as a vector by default */
2054 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2056 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2058 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2059 ins
->alu
.src2
= imm
<< 2;
2061 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2064 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2068 case TAG_LOAD_STORE_4
: {
2069 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2070 /* TODO: use ssa_args for store_vary */
2071 ins
->load_store
.reg
= 0;
2073 bool has_dest
= args
.dest
>= 0;
2074 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2076 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2089 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2090 * use scalar ALU instructions, for functional or performance reasons. To do
2091 * this, we just demote vector ALU payloads to scalar. */
2094 component_from_mask(unsigned mask
)
2096 for (int c
= 0; c
< 4; ++c
) {
2097 if (mask
& (3 << (2 * c
)))
2106 is_single_component_mask(unsigned mask
)
2110 for (int c
= 0; c
< 4; ++c
)
2111 if (mask
& (3 << (2 * c
)))
2114 return components
== 1;
2117 /* Create a mask of accessed components from a swizzle to figure out vector
2121 swizzle_to_access_mask(unsigned swizzle
)
2123 unsigned component_mask
= 0;
2125 for (int i
= 0; i
< 4; ++i
) {
2126 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2127 component_mask
|= (1 << c
);
2130 return component_mask
;
2134 vector_to_scalar_source(unsigned u
)
2136 midgard_vector_alu_src v
;
2137 memcpy(&v
, &u
, sizeof(v
));
2139 midgard_scalar_alu_src s
= {
2143 .component
= (v
.swizzle
& 3) << 1
2147 memcpy(&o
, &s
, sizeof(s
));
2149 return o
& ((1 << 6) - 1);
2152 static midgard_scalar_alu
2153 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2155 /* The output component is from the mask */
2156 midgard_scalar_alu s
= {
2158 .src1
= vector_to_scalar_source(v
.src1
),
2159 .src2
= vector_to_scalar_source(v
.src2
),
2162 .output_full
= 1, /* TODO: Half */
2163 .output_component
= component_from_mask(v
.mask
) << 1,
2166 /* Inline constant is passed along rather than trying to extract it
2169 if (ins
->ssa_args
.inline_constant
) {
2171 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2172 imm
|= (lower_11
>> 9) & 3;
2173 imm
|= (lower_11
>> 6) & 4;
2174 imm
|= (lower_11
>> 2) & 0x38;
2175 imm
|= (lower_11
& 63) << 6;
2183 /* Midgard prefetches instruction types, so during emission we need to
2184 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2185 * if this is the second to last and the last is an ALU, then it's also 1... */
2187 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2188 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2190 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2191 bytes_emitted += sizeof(type)
2194 emit_binary_vector_instruction(midgard_instruction
*ains
,
2195 uint16_t *register_words
, int *register_words_count
,
2196 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2197 size_t *bytes_emitted
)
2199 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2200 *bytes_emitted
+= sizeof(midgard_reg_info
);
2202 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2203 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2204 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2207 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2208 * mind that we are a vector architecture and we can write to different
2209 * components simultaneously */
2212 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2214 /* Each instruction reads some registers and writes to a register. See
2215 * where the first writes */
2217 /* Figure out where exactly we wrote to */
2218 int source
= first
->ssa_args
.dest
;
2219 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2221 /* As long as the second doesn't read from the first, we're okay */
2222 if (second
->ssa_args
.src0
== source
) {
2223 if (first
->type
== TAG_ALU_4
) {
2224 /* Figure out which components we just read from */
2226 int q
= second
->alu
.src1
;
2227 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2229 /* Check if there are components in common, and fail if so */
2230 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2237 if (second
->ssa_args
.src1
== source
)
2240 /* Otherwise, it's safe in that regard. Another data hazard is both
2241 * writing to the same place, of course */
2243 if (second
->ssa_args
.dest
== source
) {
2244 /* ...but only if the components overlap */
2245 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2247 if (dest_mask
& source_mask
)
2257 midgard_instruction
**segment
, unsigned segment_size
,
2258 midgard_instruction
*ains
)
2260 for (int s
= 0; s
< segment_size
; ++s
)
2261 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2269 /* Schedules, but does not emit, a single basic block. After scheduling, the
2270 * final tag and size of the block are known, which are necessary for branching
2273 static midgard_bundle
2274 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2276 int instructions_emitted
= 0, instructions_consumed
= -1;
2277 midgard_bundle bundle
= { 0 };
2279 uint8_t tag
= ins
->type
;
2281 /* Default to the instruction's tag */
2284 switch (ins
->type
) {
2286 uint32_t control
= 0;
2287 size_t bytes_emitted
= sizeof(control
);
2289 /* TODO: Constant combining */
2290 int index
= 0, last_unit
= 0;
2292 /* Previous instructions, for the purpose of parallelism */
2293 midgard_instruction
*segment
[4] = {0};
2294 int segment_size
= 0;
2296 instructions_emitted
= -1;
2297 midgard_instruction
*pins
= ins
;
2300 midgard_instruction
*ains
= pins
;
2302 /* Advance instruction pointer */
2304 ains
= mir_next_op(pins
);
2308 /* Out-of-work condition */
2309 if ((struct list_head
*) ains
== &block
->instructions
)
2312 /* Ensure that the chain can continue */
2313 if (ains
->type
!= TAG_ALU_4
) break;
2315 /* According to the presentation "The ARM
2316 * Mali-T880 Mobile GPU" from HotChips 27,
2317 * there are two pipeline stages. Branching
2318 * position determined experimentally. Lines
2319 * are executed in parallel:
2322 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2324 * Verify that there are no ordering dependencies here.
2326 * TODO: Allow for parallelism!!!
2329 /* Pick a unit for it if it doesn't force a particular unit */
2331 int unit
= ains
->unit
;
2334 int op
= ains
->alu
.op
;
2335 int units
= alu_opcode_props
[op
];
2337 /* TODO: Promotion of scalars to vectors */
2338 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2341 assert(units
& UNITS_SCALAR
);
2344 if (last_unit
>= UNIT_VADD
) {
2345 if (units
& UNIT_VLUT
)
2350 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2352 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2354 else if (units
& UNIT_VLUT
)
2360 if (last_unit
>= UNIT_VADD
) {
2361 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2363 else if (units
& UNIT_VLUT
)
2368 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2370 else if (units
& UNIT_SMUL
)
2371 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2372 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2379 assert(unit
& units
);
2382 /* Late unit check, this time for encoding (not parallelism) */
2383 if (unit
<= last_unit
) break;
2385 /* Clear the segment */
2386 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2389 if (midgard_has_hazard(segment
, segment_size
, ains
))
2392 /* We're good to go -- emit the instruction */
2395 segment
[segment_size
++] = ains
;
2397 /* Only one set of embedded constants per
2398 * bundle possible; if we have more, we must
2399 * break the chain early, unfortunately */
2401 if (ains
->has_constants
) {
2402 if (bundle
.has_embedded_constants
) {
2403 /* ...but if there are already
2404 * constants but these are the
2405 * *same* constants, we let it
2408 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2411 bundle
.has_embedded_constants
= true;
2412 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2414 /* If this is a blend shader special constant, track it for patching */
2415 if (ains
->has_blend_constant
)
2416 bundle
.has_blend_constant
= true;
2420 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2421 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2422 &bundle
.register_words_count
, bundle
.body_words
,
2423 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2424 } else if (ains
->compact_branch
) {
2425 /* All of r0 has to be written out
2426 * along with the branch writeout.
2429 if (ains
->writeout
) {
2431 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2432 ins
.unit
= UNIT_VMUL
;
2434 control
|= ins
.unit
;
2436 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2437 &bundle
.register_words_count
, bundle
.body_words
,
2438 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2440 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2441 bool written_late
= false;
2442 bool components
[4] = { 0 };
2443 uint16_t register_dep_mask
= 0;
2444 uint16_t written_mask
= 0;
2446 midgard_instruction
*qins
= ins
;
2447 for (int t
= 0; t
< index
; ++t
) {
2448 if (qins
->registers
.out_reg
!= 0) {
2449 /* Mark down writes */
2451 written_mask
|= (1 << qins
->registers
.out_reg
);
2453 /* Mark down the register dependencies for errata check */
2455 if (qins
->registers
.src1_reg
< 16)
2456 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2458 if (qins
->registers
.src2_reg
< 16)
2459 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2461 int mask
= qins
->alu
.mask
;
2463 for (int c
= 0; c
< 4; ++c
)
2464 if (mask
& (0x3 << (2 * c
)))
2465 components
[c
] = true;
2467 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2469 if (qins
->unit
== UNIT_VLUT
)
2470 written_late
= true;
2473 /* Advance instruction pointer */
2474 qins
= mir_next_op(qins
);
2478 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2479 if (register_dep_mask
& written_mask
) {
2480 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2487 /* If even a single component is not written, break it up (conservative check). */
2488 bool breakup
= false;
2490 for (int c
= 0; c
< 4; ++c
)
2497 /* Otherwise, we're free to proceed */
2501 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2502 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2503 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2504 bytes_emitted
+= sizeof(midgard_branch_extended
);
2506 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2507 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2508 bytes_emitted
+= sizeof(ains
->br_compact
);
2511 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2512 bytes_emitted
+= sizeof(midgard_reg_info
);
2514 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2515 bundle
.body_words_count
++;
2516 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2519 /* Defer marking until after writing to allow for break */
2520 control
|= ains
->unit
;
2521 last_unit
= ains
->unit
;
2522 ++instructions_emitted
;
2526 /* Bubble up the number of instructions for skipping */
2527 instructions_consumed
= index
- 1;
2531 /* Pad ALU op to nearest word */
2533 if (bytes_emitted
& 15) {
2534 padding
= 16 - (bytes_emitted
& 15);
2535 bytes_emitted
+= padding
;
2538 /* Constants must always be quadwords */
2539 if (bundle
.has_embedded_constants
)
2540 bytes_emitted
+= 16;
2542 /* Size ALU instruction for tag */
2543 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2544 bundle
.padding
= padding
;
2545 bundle
.control
= bundle
.tag
| control
;
2550 case TAG_LOAD_STORE_4
: {
2551 /* Load store instructions have two words at once. If
2552 * we only have one queued up, we need to NOP pad.
2553 * Otherwise, we store both in succession to save space
2554 * and cycles -- letting them go in parallel -- skip
2555 * the next. The usefulness of this optimisation is
2556 * greatly dependent on the quality of the instruction
2560 midgard_instruction
*next_op
= mir_next_op(ins
);
2562 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2563 /* As the two operate concurrently, make sure
2564 * they are not dependent */
2566 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2567 /* Skip ahead, since it's redundant with the pair */
2568 instructions_consumed
= 1 + (instructions_emitted
++);
2576 /* Texture ops default to single-op-per-bundle scheduling */
2580 /* Copy the instructions into the bundle */
2581 bundle
.instruction_count
= instructions_emitted
+ 1;
2585 midgard_instruction
*uins
= ins
;
2586 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2587 bundle
.instructions
[used_idx
++] = *uins
;
2588 uins
= mir_next_op(uins
);
2591 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2597 quadword_size(int tag
)
2612 case TAG_LOAD_STORE_4
:
2624 /* Schedule a single block by iterating its instruction to create bundles.
2625 * While we go, tally about the bundle sizes to compute the block size. */
2628 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2630 util_dynarray_init(&block
->bundles
, NULL
);
2632 block
->quadword_count
= 0;
2634 mir_foreach_instr_in_block(block
, ins
) {
2636 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2637 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2639 if (bundle
.has_blend_constant
) {
2640 /* TODO: Multiblock? */
2641 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2642 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2646 ins
= mir_next_op(ins
);
2648 block
->quadword_count
+= quadword_size(bundle
.tag
);
2651 block
->is_scheduled
= true;
2655 schedule_program(compiler_context
*ctx
)
2657 allocate_registers(ctx
);
2659 mir_foreach_block(ctx
, block
) {
2660 schedule_block(ctx
, block
);
2664 /* After everything is scheduled, emit whole bundles at a time */
2667 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2669 int lookahead
= next_tag
<< 4;
2671 switch (bundle
->tag
) {
2676 /* Actually emit each component */
2677 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2679 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2680 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2682 /* Emit body words based on the instructions bundled */
2683 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2684 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2686 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2687 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2688 } else if (ins
->compact_branch
) {
2689 /* Dummy move, XXX DRY */
2690 if ((i
== 0) && ins
->writeout
) {
2691 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2692 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2695 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2696 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2698 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2702 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2703 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2707 /* Emit padding (all zero) */
2708 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2710 /* Tack on constants */
2712 if (bundle
->has_embedded_constants
) {
2713 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2714 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2715 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2716 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2722 case TAG_LOAD_STORE_4
: {
2723 /* One or two composing instructions */
2725 uint64_t current64
, next64
= LDST_NOP
;
2727 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2729 if (bundle
->instruction_count
== 2)
2730 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2732 midgard_load_store instruction
= {
2733 .type
= bundle
->tag
,
2734 .next_type
= next_tag
,
2739 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2744 case TAG_TEXTURE_4
: {
2745 /* Texture instructions are easy, since there is no
2746 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2748 midgard_instruction
*ins
= &bundle
->instructions
[0];
2750 ins
->texture
.type
= TAG_TEXTURE_4
;
2751 ins
->texture
.next_type
= next_tag
;
2753 ctx
->texture_op_count
--;
2755 if (!ctx
->texture_op_count
) {
2756 ins
->texture
.cont
= 0;
2757 ins
->texture
.last
= 1;
2760 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2765 DBG("Unknown midgard instruction type\n");
2772 /* ALU instructions can inline or embed constants, which decreases register
2773 * pressure and saves space. */
2775 #define CONDITIONAL_ATTACH(src) { \
2776 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2779 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2780 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2785 inline_alu_constants(compiler_context
*ctx
)
2787 mir_foreach_instr(ctx
, alu
) {
2788 /* Other instructions cannot inline constants */
2789 if (alu
->type
!= TAG_ALU_4
) continue;
2791 /* If there is already a constant here, we can do nothing */
2792 if (alu
->has_constants
) continue;
2794 CONDITIONAL_ATTACH(src0
);
2796 if (!alu
->has_constants
) {
2797 CONDITIONAL_ATTACH(src1
)
2798 } else if (!alu
->inline_constant
) {
2799 /* Corner case: _two_ vec4 constants, for instance with a
2800 * csel. For this case, we can only use a constant
2801 * register for one, we'll have to emit a move for the
2802 * other. Note, if both arguments are constants, then
2803 * necessarily neither argument depends on the value of
2804 * any particular register. As the destination register
2805 * will be wiped, that means we can spill the constant
2806 * to the destination register.
2809 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2810 unsigned scratch
= alu
->ssa_args
.dest
;
2813 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2814 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2816 /* Force a break XXX Defer r31 writes */
2817 ins
.unit
= UNIT_VLUT
;
2819 /* Set the source */
2820 alu
->ssa_args
.src1
= scratch
;
2822 /* Inject us -before- the last instruction which set r31 */
2823 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2829 /* Midgard supports two types of constants, embedded constants (128-bit) and
2830 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2831 * constants can be demoted to inline constants, for space savings and
2832 * sometimes a performance boost */
2835 embedded_to_inline_constant(compiler_context
*ctx
)
2837 mir_foreach_instr(ctx
, ins
) {
2838 if (!ins
->has_constants
) continue;
2840 if (ins
->ssa_args
.inline_constant
) continue;
2842 /* Blend constants must not be inlined by definition */
2843 if (ins
->has_blend_constant
) continue;
2845 /* src1 cannot be an inline constant due to encoding
2846 * restrictions. So, if possible we try to flip the arguments
2849 int op
= ins
->alu
.op
;
2851 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2852 /* Flip based on op. Fallthrough intentional */
2855 /* These ops require an operational change to flip their arguments TODO */
2856 case midgard_alu_op_flt
:
2857 case midgard_alu_op_fle
:
2858 case midgard_alu_op_ilt
:
2859 case midgard_alu_op_ile
:
2860 case midgard_alu_op_fcsel
:
2861 case midgard_alu_op_icsel
:
2862 case midgard_alu_op_isub
:
2863 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2866 /* These ops are commutative and Just Flip */
2867 case midgard_alu_op_fne
:
2868 case midgard_alu_op_fadd
:
2869 case midgard_alu_op_fmul
:
2870 case midgard_alu_op_fmin
:
2871 case midgard_alu_op_fmax
:
2872 case midgard_alu_op_iadd
:
2873 case midgard_alu_op_imul
:
2874 case midgard_alu_op_feq
:
2875 case midgard_alu_op_ieq
:
2876 case midgard_alu_op_ine
:
2877 case midgard_alu_op_iand
:
2878 case midgard_alu_op_ior
:
2879 case midgard_alu_op_ixor
:
2880 /* Flip the SSA numbers */
2881 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2882 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2884 /* And flip the modifiers */
2888 src_temp
= ins
->alu
.src2
;
2889 ins
->alu
.src2
= ins
->alu
.src1
;
2890 ins
->alu
.src1
= src_temp
;
2897 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2898 /* Extract the source information */
2900 midgard_vector_alu_src
*src
;
2901 int q
= ins
->alu
.src2
;
2902 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2905 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2906 int component
= src
->swizzle
& 3;
2908 /* Scale constant appropriately, if we can legally */
2909 uint16_t scaled_constant
= 0;
2911 /* XXX: Check legality */
2912 if (midgard_is_integer_op(op
)) {
2913 /* TODO: Inline integer */
2916 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2917 scaled_constant
= (uint16_t) iconstants
[component
];
2919 /* Constant overflow after resize */
2920 if (scaled_constant
!= iconstants
[component
])
2923 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2926 /* We don't know how to handle these with a constant */
2928 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2929 DBG("Bailing inline constant...\n");
2933 /* Make sure that the constant is not itself a
2934 * vector by checking if all accessed values
2935 * (by the swizzle) are the same. */
2937 uint32_t *cons
= (uint32_t *) ins
->constants
;
2938 uint32_t value
= cons
[component
];
2940 bool is_vector
= false;
2941 unsigned mask
= effective_writemask(&ins
->alu
);
2943 for (int c
= 1; c
< 4; ++c
) {
2944 /* We only care if this component is actually used */
2945 if (!(mask
& (1 << c
)))
2948 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2950 if (test
!= value
) {
2959 /* Get rid of the embedded constant */
2960 ins
->has_constants
= false;
2961 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2962 ins
->ssa_args
.inline_constant
= true;
2963 ins
->inline_constant
= scaled_constant
;
2968 /* Map normal SSA sources to other SSA sources / fixed registers (like
2972 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2974 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2977 /* Remove entry in leftovers to avoid a redunant fmov */
2979 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2982 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2984 /* Assign the alias map */
2990 #define AS_SRC(to, u) \
2991 int q##to = ins->alu.src2; \
2992 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2994 /* Removing unused moves is necessary to clean up the texture pipeline results.
2996 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2999 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
3001 mir_foreach_instr_in_block_safe(block
, ins
) {
3002 if (ins
->type
!= TAG_ALU_4
) continue;
3004 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
3006 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3008 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3010 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3012 mir_remove_instruction(ins
);
3016 /* The following passes reorder MIR instructions to enable better scheduling */
3019 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3021 mir_foreach_instr_in_block_safe(block
, ins
) {
3022 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3024 /* We've found a load/store op. Check if next is also load/store. */
3025 midgard_instruction
*next_op
= mir_next_op(ins
);
3026 if (&next_op
->link
!= &block
->instructions
) {
3027 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3028 /* If so, we're done since we're a pair */
3029 ins
= mir_next_op(ins
);
3033 /* Maximum search distance to pair, to avoid register pressure disasters */
3034 int search_distance
= 8;
3036 /* Otherwise, we have an orphaned load/store -- search for another load */
3037 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3038 /* Terminate search if necessary */
3039 if (!(search_distance
--)) break;
3041 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3043 /* Stores cannot be reordered, since they have
3044 * dependencies. For the same reason, indirect
3045 * loads cannot be reordered as their index is
3046 * loaded in r27.w */
3048 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3050 /* It appears the 0x800 bit is set whenever a
3051 * load is direct, unset when it is indirect.
3052 * Skip indirect loads. */
3054 if (!(c
->load_store
.unknown
& 0x800)) continue;
3056 /* We found one! Move it up to pair and remove it from the old location */
3058 mir_insert_instruction_before(ins
, *c
);
3059 mir_remove_instruction(c
);
3067 /* Emit varying stores late */
3070 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3071 /* Iterate in reverse to get the final write, rather than the first */
3073 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3074 /* Check if what we just wrote needs a store */
3075 int idx
= ins
->ssa_args
.dest
;
3076 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3078 if (!varying
) continue;
3082 /* We need to store to the appropriate varying, so emit the
3085 /* TODO: Integrate with special purpose RA (and scheduler?) */
3086 bool high_varying_register
= false;
3088 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3090 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3091 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3093 mir_insert_instruction_before(mir_next_op(ins
), st
);
3094 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3096 /* We no longer need to store this varying */
3097 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3101 /* If there are leftovers after the below pass, emit actual fmov
3102 * instructions for the slow-but-correct path */
3105 emit_leftover_move(compiler_context
*ctx
)
3107 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3108 int base
= ((uintptr_t) leftover
->key
) - 1;
3111 map_ssa_to_alias(ctx
, &mapped
);
3112 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3117 actualise_ssa_to_alias(compiler_context
*ctx
)
3119 mir_foreach_instr(ctx
, ins
) {
3120 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3121 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3124 emit_leftover_move(ctx
);
3128 emit_fragment_epilogue(compiler_context
*ctx
)
3130 /* Special case: writing out constants requires us to include the move
3131 * explicitly now, so shove it into r0 */
3133 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3135 if (constant_value
) {
3136 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3137 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3138 emit_mir_instruction(ctx
, ins
);
3141 /* Perform the actual fragment writeout. We have two writeout/branch
3142 * instructions, forming a loop until writeout is successful as per the
3143 * docs. TODO: gl_FragDepth */
3145 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3146 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3149 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3150 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3151 * with the int8 analogue to the fragment epilogue */
3154 emit_blend_epilogue(compiler_context
*ctx
)
3156 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3158 midgard_instruction scale
= {
3161 .inline_constant
= _mesa_float_to_half(255.0),
3163 .src0
= SSA_FIXED_REGISTER(0),
3164 .src1
= SSA_UNUSED_0
,
3165 .dest
= SSA_FIXED_REGISTER(24),
3166 .inline_constant
= true
3169 .op
= midgard_alu_op_fmul
,
3170 .reg_mode
= midgard_reg_mode_full
,
3171 .dest_override
= midgard_dest_override_lower
,
3173 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3174 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3178 emit_mir_instruction(ctx
, scale
);
3180 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3182 midgard_vector_alu_src alu_src
= blank_alu_src
;
3183 alu_src
.half
= true;
3185 midgard_instruction f2u8
= {
3188 .src0
= SSA_FIXED_REGISTER(24),
3189 .src1
= SSA_UNUSED_0
,
3190 .dest
= SSA_FIXED_REGISTER(0),
3191 .inline_constant
= true
3194 .op
= midgard_alu_op_f2u8
,
3195 .reg_mode
= midgard_reg_mode_half
,
3196 .dest_override
= midgard_dest_override_lower
,
3197 .outmod
= midgard_outmod_pos
,
3199 .src1
= vector_alu_srco_unsigned(alu_src
),
3200 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3204 emit_mir_instruction(ctx
, f2u8
);
3206 /* vmul.imov.quarter r0, r0, r0 */
3208 midgard_instruction imov_8
= {
3211 .src0
= SSA_UNUSED_1
,
3212 .src1
= SSA_FIXED_REGISTER(0),
3213 .dest
= SSA_FIXED_REGISTER(0),
3216 .op
= midgard_alu_op_imov
,
3217 .reg_mode
= midgard_reg_mode_quarter
,
3218 .dest_override
= midgard_dest_override_none
,
3220 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3221 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3225 /* Emit branch epilogue with the 8-bit move as the source */
3227 emit_mir_instruction(ctx
, imov_8
);
3228 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3230 emit_mir_instruction(ctx
, imov_8
);
3231 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3234 static midgard_block
*
3235 emit_block(compiler_context
*ctx
, nir_block
*block
)
3237 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3238 list_addtail(&this_block
->link
, &ctx
->blocks
);
3240 this_block
->is_scheduled
= false;
3243 ctx
->texture_index
[0] = -1;
3244 ctx
->texture_index
[1] = -1;
3246 /* Set up current block */
3247 list_inithead(&this_block
->instructions
);
3248 ctx
->current_block
= this_block
;
3250 nir_foreach_instr(instr
, block
) {
3251 emit_instr(ctx
, instr
);
3252 ++ctx
->instruction_count
;
3255 inline_alu_constants(ctx
);
3256 embedded_to_inline_constant(ctx
);
3258 /* Perform heavylifting for aliasing */
3259 actualise_ssa_to_alias(ctx
);
3261 midgard_emit_store(ctx
, this_block
);
3262 midgard_eliminate_orphan_moves(ctx
, this_block
);
3263 midgard_pair_load_store(ctx
, this_block
);
3265 /* Append fragment shader epilogue (value writeout) */
3266 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3267 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3269 emit_blend_epilogue(ctx
);
3271 emit_fragment_epilogue(ctx
);
3275 /* Fallthrough save */
3276 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3278 if (block
== nir_start_block(ctx
->func
->impl
))
3279 ctx
->initial_block
= this_block
;
3281 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3282 ctx
->final_block
= this_block
;
3284 /* Allow the next control flow to access us retroactively, for
3286 ctx
->current_block
= this_block
;
3288 /* Document the fallthrough chain */
3289 ctx
->previous_source_block
= this_block
;
3294 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3297 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3299 /* Conditional branches expect the condition in r31.w; emit a move for
3300 * that in the _previous_ block (which is the current block). */
3301 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3303 /* Speculatively emit the branch, but we can't fill it in until later */
3304 EMIT(branch
, true, true);
3305 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3307 /* Emit the two subblocks */
3308 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3310 /* Emit a jump from the end of the then block to the end of the else */
3311 EMIT(branch
, false, false);
3312 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3314 /* Emit second block, and check if it's empty */
3316 int else_idx
= ctx
->block_count
;
3317 int count_in
= ctx
->instruction_count
;
3318 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3319 int after_else_idx
= ctx
->block_count
;
3321 /* Now that we have the subblocks emitted, fix up the branches */
3326 if (ctx
->instruction_count
== count_in
) {
3327 /* The else block is empty, so don't emit an exit jump */
3328 mir_remove_instruction(then_exit
);
3329 then_branch
->branch
.target_block
= after_else_idx
;
3331 then_branch
->branch
.target_block
= else_idx
;
3332 then_exit
->branch
.target_block
= after_else_idx
;
3337 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3339 /* Remember where we are */
3340 midgard_block
*start_block
= ctx
->current_block
;
3342 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3343 * single current_loop variable, maybe we need a stack */
3345 int loop_idx
= ++ctx
->current_loop
;
3347 /* Get index from before the body so we can loop back later */
3348 int start_idx
= ctx
->block_count
;
3350 /* Emit the body itself */
3351 emit_cf_list(ctx
, &nloop
->body
);
3353 /* Branch back to loop back */
3354 struct midgard_instruction br_back
= v_branch(false, false);
3355 br_back
.branch
.target_block
= start_idx
;
3356 emit_mir_instruction(ctx
, br_back
);
3358 /* Find the index of the block about to follow us (note: we don't add
3359 * one; blocks are 0-indexed so we get a fencepost problem) */
3360 int break_block_idx
= ctx
->block_count
;
3362 /* Fix up the break statements we emitted to point to the right place,
3363 * now that we can allocate a block number for them */
3365 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3366 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3367 print_mir_block(block
);
3368 mir_foreach_instr_in_block(block
, ins
) {
3369 if (ins
->type
!= TAG_ALU_4
) continue;
3370 if (!ins
->compact_branch
) continue;
3371 if (ins
->prepacked_branch
) continue;
3373 /* We found a branch -- check the type to see if we need to do anything */
3374 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3376 /* It's a break! Check if it's our break */
3377 if (ins
->branch
.target_break
!= loop_idx
) continue;
3379 /* Okay, cool, we're breaking out of this loop.
3380 * Rewrite from a break to a goto */
3382 ins
->branch
.target_type
= TARGET_GOTO
;
3383 ins
->branch
.target_block
= break_block_idx
;
3388 static midgard_block
*
3389 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3391 midgard_block
*start_block
= NULL
;
3393 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3394 switch (node
->type
) {
3395 case nir_cf_node_block
: {
3396 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3399 start_block
= block
;
3404 case nir_cf_node_if
:
3405 emit_if(ctx
, nir_cf_node_as_if(node
));
3408 case nir_cf_node_loop
:
3409 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3412 case nir_cf_node_function
:
3421 /* Due to lookahead, we need to report the first tag executed in the command
3422 * stream and in branch targets. An initial block might be empty, so iterate
3423 * until we find one that 'works' */
3426 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3428 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3430 unsigned first_tag
= 0;
3433 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3435 if (initial_bundle
) {
3436 first_tag
= initial_bundle
->tag
;
3440 /* Initial block is empty, try the next block */
3441 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3442 } while(initial_block
!= NULL
);
3449 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3451 struct util_dynarray
*compiled
= &program
->compiled
;
3453 midgard_debug
= debug_get_option_midgard_debug();
3455 compiler_context ictx
= {
3457 .stage
= nir
->info
.stage
,
3459 .is_blend
= is_blend
,
3460 .blend_constant_offset
= -1,
3462 .alpha_ref
= program
->alpha_ref
3465 compiler_context
*ctx
= &ictx
;
3467 /* TODO: Decide this at runtime */
3468 ctx
->uniform_cutoff
= 8;
3470 /* Assign var locations early, so the epilogue can use them if necessary */
3472 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3473 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3474 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3476 /* Initialize at a global (not block) level hash tables */
3478 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3479 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3480 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3481 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3482 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3483 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3484 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3486 /* Record the varying mapping for the command stream's bookkeeping */
3488 struct exec_list
*varyings
=
3489 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3491 nir_foreach_variable(var
, varyings
) {
3492 unsigned loc
= var
->data
.driver_location
;
3493 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3495 for (int c
= 0; c
< sz
; ++c
) {
3496 program
->varyings
[loc
+ c
] = var
->data
.location
;
3500 /* Lower gl_Position pre-optimisation */
3502 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3503 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3505 NIR_PASS_V(nir
, nir_lower_var_copies
);
3506 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3507 NIR_PASS_V(nir
, nir_split_var_copies
);
3508 NIR_PASS_V(nir
, nir_lower_var_copies
);
3509 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3510 NIR_PASS_V(nir
, nir_lower_var_copies
);
3511 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3513 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3515 /* Optimisation passes */
3519 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3520 nir_print_shader(nir
, stdout
);
3523 /* Assign sysvals and counts, now that we're sure
3524 * (post-optimisation) */
3526 midgard_nir_assign_sysvals(ctx
, nir
);
3528 program
->uniform_count
= nir
->num_uniforms
;
3529 program
->sysval_count
= ctx
->sysval_count
;
3530 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3532 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3533 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3535 nir_foreach_function(func
, nir
) {
3539 list_inithead(&ctx
->blocks
);
3540 ctx
->block_count
= 0;
3543 emit_cf_list(ctx
, &func
->impl
->body
);
3544 emit_block(ctx
, func
->impl
->end_block
);
3546 break; /* TODO: Multi-function shaders */
3549 util_dynarray_init(compiled
, NULL
);
3552 schedule_program(ctx
);
3554 /* Now that all the bundles are scheduled and we can calculate block
3555 * sizes, emit actual branch instructions rather than placeholders */
3557 int br_block_idx
= 0;
3559 mir_foreach_block(ctx
, block
) {
3560 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3561 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3562 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3564 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3566 if (ins
->prepacked_branch
) continue;
3568 /* Parse some basic branch info */
3569 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3570 bool is_conditional
= ins
->branch
.conditional
;
3571 bool is_inverted
= ins
->branch
.invert_conditional
;
3572 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3574 /* Determine the block we're jumping to */
3575 int target_number
= ins
->branch
.target_block
;
3577 /* Report the destination tag. Discards don't need this */
3578 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3580 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3581 int quadword_offset
= 0;
3584 /* Jump to the end of the shader. We
3585 * need to include not only the
3586 * following blocks, but also the
3587 * contents of our current block (since
3588 * discard can come in the middle of
3591 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3593 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3594 quadword_offset
+= quadword_size(bun
->tag
);
3597 mir_foreach_block_from(ctx
, blk
, b
) {
3598 quadword_offset
+= b
->quadword_count
;
3601 } else if (target_number
> br_block_idx
) {
3604 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3605 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3608 quadword_offset
+= blk
->quadword_count
;
3611 /* Jump backwards */
3613 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3614 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3617 quadword_offset
-= blk
->quadword_count
;
3621 /* Unconditional extended branches (far jumps)
3622 * have issues, so we always use a conditional
3623 * branch, setting the condition to always for
3624 * unconditional. For compact unconditional
3625 * branches, cond isn't used so it doesn't
3626 * matter what we pick. */
3628 midgard_condition cond
=
3629 !is_conditional
? midgard_condition_always
:
3630 is_inverted
? midgard_condition_false
:
3631 midgard_condition_true
;
3633 midgard_jmp_writeout_op op
=
3634 is_discard
? midgard_jmp_writeout_op_discard
:
3635 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3636 midgard_jmp_writeout_op_branch_cond
;
3639 midgard_branch_extended branch
=
3640 midgard_create_branch_extended(
3645 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3646 } else if (is_conditional
|| is_discard
) {
3647 midgard_branch_cond branch
= {
3649 .dest_tag
= dest_tag
,
3650 .offset
= quadword_offset
,
3654 assert(branch
.offset
== quadword_offset
);
3656 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3658 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3660 midgard_branch_uncond branch
= {
3662 .dest_tag
= dest_tag
,
3663 .offset
= quadword_offset
,
3667 assert(branch
.offset
== quadword_offset
);
3669 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3677 /* Emit flat binary from the instruction arrays. Iterate each block in
3678 * sequence. Save instruction boundaries such that lookahead tags can
3679 * be assigned easily */
3681 /* Cache _all_ bundles in source order for lookahead across failed branches */
3683 int bundle_count
= 0;
3684 mir_foreach_block(ctx
, block
) {
3685 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3687 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3689 mir_foreach_block(ctx
, block
) {
3690 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3691 source_order_bundles
[bundle_idx
++] = bundle
;
3695 int current_bundle
= 0;
3697 mir_foreach_block(ctx
, block
) {
3698 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3701 if (current_bundle
+ 1 < bundle_count
) {
3702 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3704 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3711 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3715 /* TODO: Free deeper */
3716 //util_dynarray_fini(&block->instructions);
3719 free(source_order_bundles
);
3721 /* Report the very first tag executed */
3722 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3724 /* Deal with off-by-one related to the fencepost problem */
3725 program
->work_register_count
= ctx
->work_registers
+ 1;
3727 program
->can_discard
= ctx
->can_discard
;
3728 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3730 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3732 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3733 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);