src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  * Copyright (C) 2019 Collabora, Ltd.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "compiler.h"
  26
  27 /* Creates pipeline registers. This is a prepass run before the main register
  28  * allocator but after scheduling, once bundles are created. It works by
  29  * iterating the scheduled IR, checking if a value is ever used after the end
  30  * of the current bundle. If it is not, it is promoted to a bundle-specific
  31  * pipeline register.
  32  *
  33  * Pipeline registers are only written from the first two stages of the
  34  * pipeline (vmul/sadd) lasting the duration of the bundle only. There are two
  35  * 128-bit pipeline registers available (r24/r25). The upshot is that no actual
  36  * register allocation is needed; we can _always_ promote a value to a pipeline
  37  * register, liveness permitting. This greatly simplifies the logic of this
  38  * passing, negating the need for a proper RA like work registers.
  39  */
  40
  41 static bool
  42 mir_pipeline_ins(
  43         compiler_context *ctx,
  44         midgard_block *block,
  45         midgard_bundle *bundle, unsigned i,
  46         unsigned pipeline_count)
  47 {
  48         midgard_instruction *ins = bundle->instructions[i];
  49         unsigned dest = ins->ssa_args.dest;
  50
  51         /* Check to make sure we're legal */
  52
  53         if (ins->compact_branch)
  54                 return false;
  55
  56         /* Don't allow non-SSA. Pipelining registers is theoretically possible,
  57          * but the analysis is much hairier, so don't bother quite yet */
  58         if ((dest < 0) || (dest >= ctx->func->impl->ssa_alloc))
  59                 return false;
  60
  61         /* Make sure they're not lying to us. Blend shaders lie. TODO: Fix your
  62          * bad code Alyssa */
  63
  64         if (mir_has_multiple_writes(ctx, dest))
  65                 return false;
  66
  67         /* We want to know if we live after this bundle, so check if
  68          * we're live after the last instruction of the bundle */
  69
  70         midgard_instruction *end = bundle->instructions[
  71                                     bundle->instruction_count - 1];
  72
  73         if (mir_is_live_after(ctx, block, end, ins->ssa_args.dest))
  74                 return false;
  75
  76         /* We're only live in this bundle -- pipeline! */
  77
  78         mir_rewrite_index(ctx, dest, SSA_FIXED_REGISTER(24 + pipeline_count));
  79
  80         return true;
  81 }
  82
  83 void
  84 mir_create_pipeline_registers(compiler_context *ctx)
  85 {
  86         mir_foreach_block(ctx, block) {
  87                 mir_foreach_bundle_in_block(block, bundle) {
  88                         if (!mir_is_alu_bundle(bundle)) continue;
  89                         if (bundle->instruction_count < 2) continue;
  90
  91                         /* Only first 2 instructions could pipeline */
  92                         bool succ = mir_pipeline_ins(ctx, block, bundle, 0, 0);
  93                         mir_pipeline_ins(ctx, block, bundle, 1, succ);
  94                 }
  95         }
  96 }