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panfrost: Isolate panfrost_bo_access_for_stage to pan_cmdstream.c
[mesa.git] / src / gallium / drivers / panfrost / pan_cmdstream.c
1 /*
2 * Copyright (C) 2018 Alyssa Rosenzweig
3 * Copyright (C) 2020 Collabora Ltd.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include "util/macros.h"
26 #include "util/u_prim.h"
27 #include "util/u_vbuf.h"
28
29 #include "panfrost-quirks.h"
30
31 #include "pan_allocate.h"
32 #include "pan_bo.h"
33 #include "pan_cmdstream.h"
34 #include "pan_context.h"
35 #include "pan_job.h"
36
37 /* If a BO is accessed for a particular shader stage, will it be in the primary
38 * batch (vertex/tiler) or the secondary batch (fragment)? Anything but
39 * fragment will be primary, e.g. compute jobs will be considered
40 * "vertex/tiler" by analogy */
41
42 static inline uint32_t
43 panfrost_bo_access_for_stage(enum pipe_shader_type stage)
44 {
45 assert(stage == PIPE_SHADER_FRAGMENT ||
46 stage == PIPE_SHADER_VERTEX ||
47 stage == PIPE_SHADER_COMPUTE);
48
49 return stage == PIPE_SHADER_FRAGMENT ?
50 PAN_BO_ACCESS_FRAGMENT :
51 PAN_BO_ACCESS_VERTEX_TILER;
52 }
53
54 /* TODO: Bifrost requires just a mali_shared_memory, without the rest of the
55 * framebuffer */
56
57 void
58 panfrost_vt_attach_framebuffer(struct panfrost_context *ctx,
59 struct midgard_payload_vertex_tiler *vt)
60 {
61 struct panfrost_device *dev = pan_device(ctx->base.screen);
62 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
63
64 /* If we haven't, reserve space for the framebuffer */
65
66 if (!batch->framebuffer.gpu) {
67 unsigned size = (dev->quirks & MIDGARD_SFBD) ?
68 sizeof(struct mali_single_framebuffer) :
69 sizeof(struct mali_framebuffer);
70
71 batch->framebuffer = panfrost_allocate_transient(batch, size);
72
73 /* Tag the pointer */
74 if (!(dev->quirks & MIDGARD_SFBD))
75 batch->framebuffer.gpu |= MALI_MFBD;
76 }
77
78 vt->postfix.shared_memory = batch->framebuffer.gpu;
79 }
80
81 void
82 panfrost_vt_update_rasterizer(struct panfrost_context *ctx,
83 struct midgard_payload_vertex_tiler *tp)
84 {
85 struct panfrost_rasterizer *rasterizer = ctx->rasterizer;
86
87 tp->gl_enables |= 0x7;
88 SET_BIT(tp->gl_enables, MALI_FRONT_CCW_TOP,
89 rasterizer && rasterizer->base.front_ccw);
90 SET_BIT(tp->gl_enables, MALI_CULL_FACE_FRONT,
91 rasterizer && (rasterizer->base.cull_face & PIPE_FACE_FRONT));
92 SET_BIT(tp->gl_enables, MALI_CULL_FACE_BACK,
93 rasterizer && (rasterizer->base.cull_face & PIPE_FACE_BACK));
94 SET_BIT(tp->prefix.unknown_draw, MALI_DRAW_FLATSHADE_FIRST,
95 rasterizer && rasterizer->base.flatshade_first);
96
97 if (!panfrost_writes_point_size(ctx)) {
98 bool points = tp->prefix.draw_mode == MALI_POINTS;
99 float val = 0.0f;
100
101 if (rasterizer)
102 val = points ?
103 rasterizer->base.point_size :
104 rasterizer->base.line_width;
105
106 tp->primitive_size.constant = val;
107 }
108 }
109
110 void
111 panfrost_vt_update_occlusion_query(struct panfrost_context *ctx,
112 struct midgard_payload_vertex_tiler *tp)
113 {
114 SET_BIT(tp->gl_enables, MALI_OCCLUSION_QUERY, ctx->occlusion_query);
115 if (ctx->occlusion_query)
116 tp->postfix.occlusion_counter = ctx->occlusion_query->bo->gpu;
117 else
118 tp->postfix.occlusion_counter = 0;
119 }
120
121 void
122 panfrost_vt_init(struct panfrost_context *ctx,
123 enum pipe_shader_type stage,
124 struct midgard_payload_vertex_tiler *vtp)
125 {
126 if (!ctx->shader[stage])
127 return;
128
129 memset(vtp, 0, sizeof(*vtp));
130 vtp->gl_enables = 0x6;
131 panfrost_vt_attach_framebuffer(ctx, vtp);
132
133 if (stage == PIPE_SHADER_FRAGMENT) {
134 panfrost_vt_update_occlusion_query(ctx, vtp);
135 panfrost_vt_update_rasterizer(ctx, vtp);
136 }
137 }
138
139
140 static unsigned
141 panfrost_translate_index_size(unsigned size)
142 {
143 switch (size) {
144 case 1:
145 return MALI_DRAW_INDEXED_UINT8;
146
147 case 2:
148 return MALI_DRAW_INDEXED_UINT16;
149
150 case 4:
151 return MALI_DRAW_INDEXED_UINT32;
152
153 default:
154 unreachable("Invalid index size");
155 }
156 }
157
158 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
159 * good for the duration of the draw (transient), could last longer. Also get
160 * the bounds on the index buffer for the range accessed by the draw. We do
161 * these operations together because there are natural optimizations which
162 * require them to be together. */
163
164 static mali_ptr
165 panfrost_get_index_buffer_bounded(struct panfrost_context *ctx,
166 const struct pipe_draw_info *info,
167 unsigned *min_index, unsigned *max_index)
168 {
169 struct panfrost_resource *rsrc = pan_resource(info->index.resource);
170 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
171 off_t offset = info->start * info->index_size;
172 bool needs_indices = true;
173 mali_ptr out = 0;
174
175 if (info->max_index != ~0u) {
176 *min_index = info->min_index;
177 *max_index = info->max_index;
178 needs_indices = false;
179 }
180
181 if (!info->has_user_indices) {
182 /* Only resources can be directly mapped */
183 panfrost_batch_add_bo(batch, rsrc->bo,
184 PAN_BO_ACCESS_SHARED |
185 PAN_BO_ACCESS_READ |
186 PAN_BO_ACCESS_VERTEX_TILER);
187 out = rsrc->bo->gpu + offset;
188
189 /* Check the cache */
190 needs_indices = !panfrost_minmax_cache_get(rsrc->index_cache,
191 info->start,
192 info->count,
193 min_index,
194 max_index);
195 } else {
196 /* Otherwise, we need to upload to transient memory */
197 const uint8_t *ibuf8 = (const uint8_t *) info->index.user;
198 out = panfrost_upload_transient(batch, ibuf8 + offset,
199 info->count *
200 info->index_size);
201 }
202
203 if (needs_indices) {
204 /* Fallback */
205 u_vbuf_get_minmax_index(&ctx->base, info, min_index, max_index);
206
207 if (!info->has_user_indices)
208 panfrost_minmax_cache_add(rsrc->index_cache,
209 info->start, info->count,
210 *min_index, *max_index);
211 }
212
213 return out;
214 }
215
216 void
217 panfrost_vt_set_draw_info(struct panfrost_context *ctx,
218 const struct pipe_draw_info *info,
219 enum mali_draw_mode draw_mode,
220 struct midgard_payload_vertex_tiler *vp,
221 struct midgard_payload_vertex_tiler *tp,
222 unsigned *vertex_count,
223 unsigned *padded_count)
224 {
225 tp->prefix.draw_mode = draw_mode;
226
227 unsigned draw_flags = 0;
228
229 if (panfrost_writes_point_size(ctx))
230 draw_flags |= MALI_DRAW_VARYING_SIZE;
231
232 if (info->primitive_restart)
233 draw_flags |= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX;
234
235 /* These doesn't make much sense */
236
237 draw_flags |= 0x3000;
238
239 if (info->index_size) {
240 unsigned min_index = 0, max_index = 0;
241
242 tp->prefix.indices = panfrost_get_index_buffer_bounded(ctx,
243 info,
244 &min_index,
245 &max_index);
246
247 /* Use the corresponding values */
248 *vertex_count = max_index - min_index + 1;
249 tp->offset_start = vp->offset_start = min_index + info->index_bias;
250 tp->prefix.offset_bias_correction = -min_index;
251 tp->prefix.index_count = MALI_POSITIVE(info->count);
252 draw_flags |= panfrost_translate_index_size(info->index_size);
253 } else {
254 tp->prefix.indices = 0;
255 *vertex_count = ctx->vertex_count;
256 tp->offset_start = vp->offset_start = info->start;
257 tp->prefix.offset_bias_correction = 0;
258 tp->prefix.index_count = MALI_POSITIVE(ctx->vertex_count);
259 }
260
261 tp->prefix.unknown_draw = draw_flags;
262
263 /* Encode the padded vertex count */
264
265 if (info->instance_count > 1) {
266 *padded_count = panfrost_padded_vertex_count(*vertex_count);
267
268 unsigned shift = __builtin_ctz(ctx->padded_count);
269 unsigned k = ctx->padded_count >> (shift + 1);
270
271 tp->instance_shift = vp->instance_shift = shift;
272 tp->instance_odd = vp->instance_odd = k;
273 } else {
274 *padded_count = *vertex_count;
275
276 /* Reset instancing state */
277 tp->instance_shift = vp->instance_shift = 0;
278 tp->instance_odd = vp->instance_odd = 0;
279 }
280 }
281
282 static void
283 panfrost_shader_meta_init(struct panfrost_context *ctx,
284 enum pipe_shader_type st,
285 struct mali_shader_meta *meta)
286 {
287 struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st);
288
289 memset(meta, 0, sizeof(*meta));
290 meta->shader = (ss->bo ? ss->bo->gpu : 0) | ss->first_tag;
291 meta->midgard1.uniform_count = MIN2(ss->uniform_count,
292 ss->uniform_cutoff);
293 meta->midgard1.work_count = ss->work_reg_count;
294 meta->attribute_count = ss->attribute_count;
295 meta->varying_count = ss->varying_count;
296 meta->midgard1.flags_hi = 0x8; /* XXX */
297 meta->midgard1.flags_lo = 0x220;
298 meta->texture_count = ctx->sampler_view_count[st];
299 meta->sampler_count = ctx->sampler_count[st];
300 meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st);
301 }
302
303 static unsigned
304 panfrost_translate_compare_func(enum pipe_compare_func in)
305 {
306 switch (in) {
307 case PIPE_FUNC_NEVER:
308 return MALI_FUNC_NEVER;
309
310 case PIPE_FUNC_LESS:
311 return MALI_FUNC_LESS;
312
313 case PIPE_FUNC_EQUAL:
314 return MALI_FUNC_EQUAL;
315
316 case PIPE_FUNC_LEQUAL:
317 return MALI_FUNC_LEQUAL;
318
319 case PIPE_FUNC_GREATER:
320 return MALI_FUNC_GREATER;
321
322 case PIPE_FUNC_NOTEQUAL:
323 return MALI_FUNC_NOTEQUAL;
324
325 case PIPE_FUNC_GEQUAL:
326 return MALI_FUNC_GEQUAL;
327
328 case PIPE_FUNC_ALWAYS:
329 return MALI_FUNC_ALWAYS;
330
331 default:
332 unreachable("Invalid func");
333 }
334 }
335
336 static unsigned
337 panfrost_translate_stencil_op(enum pipe_stencil_op in)
338 {
339 switch (in) {
340 case PIPE_STENCIL_OP_KEEP:
341 return MALI_STENCIL_KEEP;
342
343 case PIPE_STENCIL_OP_ZERO:
344 return MALI_STENCIL_ZERO;
345
346 case PIPE_STENCIL_OP_REPLACE:
347 return MALI_STENCIL_REPLACE;
348
349 case PIPE_STENCIL_OP_INCR:
350 return MALI_STENCIL_INCR;
351
352 case PIPE_STENCIL_OP_DECR:
353 return MALI_STENCIL_DECR;
354
355 case PIPE_STENCIL_OP_INCR_WRAP:
356 return MALI_STENCIL_INCR_WRAP;
357
358 case PIPE_STENCIL_OP_DECR_WRAP:
359 return MALI_STENCIL_DECR_WRAP;
360
361 case PIPE_STENCIL_OP_INVERT:
362 return MALI_STENCIL_INVERT;
363
364 default:
365 unreachable("Invalid stencil op");
366 }
367 }
368
369 static unsigned
370 translate_tex_wrap(enum pipe_tex_wrap w)
371 {
372 switch (w) {
373 case PIPE_TEX_WRAP_REPEAT:
374 return MALI_WRAP_REPEAT;
375
376 case PIPE_TEX_WRAP_CLAMP:
377 return MALI_WRAP_CLAMP;
378
379 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
380 return MALI_WRAP_CLAMP_TO_EDGE;
381
382 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
383 return MALI_WRAP_CLAMP_TO_BORDER;
384
385 case PIPE_TEX_WRAP_MIRROR_REPEAT:
386 return MALI_WRAP_MIRRORED_REPEAT;
387
388 case PIPE_TEX_WRAP_MIRROR_CLAMP:
389 return MALI_WRAP_MIRRORED_CLAMP;
390
391 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
392 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE;
393
394 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
395 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER;
396
397 default:
398 unreachable("Invalid wrap");
399 }
400 }
401
402 void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso,
403 struct mali_sampler_descriptor *hw)
404 {
405 unsigned func = panfrost_translate_compare_func(cso->compare_func);
406 bool min_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
407 bool mag_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
408 bool mip_linear = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR;
409 unsigned min_filter = min_nearest ? MALI_SAMP_MIN_NEAREST : 0;
410 unsigned mag_filter = mag_nearest ? MALI_SAMP_MAG_NEAREST : 0;
411 unsigned mip_filter = mip_linear ?
412 (MALI_SAMP_MIP_LINEAR_1 | MALI_SAMP_MIP_LINEAR_2) : 0;
413 unsigned normalized = cso->normalized_coords ? MALI_SAMP_NORM_COORDS : 0;
414
415 *hw = (struct mali_sampler_descriptor) {
416 .filter_mode = min_filter | mag_filter | mip_filter |
417 normalized,
418 .wrap_s = translate_tex_wrap(cso->wrap_s),
419 .wrap_t = translate_tex_wrap(cso->wrap_t),
420 .wrap_r = translate_tex_wrap(cso->wrap_r),
421 .compare_func = panfrost_flip_compare_func(func),
422 .border_color = {
423 cso->border_color.f[0],
424 cso->border_color.f[1],
425 cso->border_color.f[2],
426 cso->border_color.f[3]
427 },
428 .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */
429 .max_lod = FIXED_16(cso->max_lod, false),
430 .lod_bias = FIXED_16(cso->lod_bias, true), /* can be negative */
431 .seamless_cube_map = cso->seamless_cube_map,
432 };
433
434 /* If necessary, we disable mipmapping in the sampler descriptor by
435 * clamping the LOD as tight as possible (from 0 to epsilon,
436 * essentially -- remember these are fixed point numbers, so
437 * epsilon=1/256) */
438
439 if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
440 hw->max_lod = hw->min_lod + 1;
441 }
442
443 static void
444 panfrost_make_stencil_state(const struct pipe_stencil_state *in,
445 struct mali_stencil_test *out)
446 {
447 out->ref = 0; /* Gallium gets it from elsewhere */
448
449 out->mask = in->valuemask;
450 out->func = panfrost_translate_compare_func(in->func);
451 out->sfail = panfrost_translate_stencil_op(in->fail_op);
452 out->dpfail = panfrost_translate_stencil_op(in->zfail_op);
453 out->dppass = panfrost_translate_stencil_op(in->zpass_op);
454 }
455
456 static void
457 panfrost_frag_meta_rasterizer_update(struct panfrost_context *ctx,
458 struct mali_shader_meta *fragmeta)
459 {
460 if (!ctx->rasterizer) {
461 SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, true);
462 SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, false);
463 fragmeta->depth_units = 0.0f;
464 fragmeta->depth_factor = 0.0f;
465 SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, false);
466 SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, false);
467 return;
468 }
469
470 bool msaa = ctx->rasterizer->base.multisample;
471
472 /* TODO: Sample size */
473 SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa);
474 SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa);
475 fragmeta->depth_units = ctx->rasterizer->base.offset_units * 2.0f;
476 fragmeta->depth_factor = ctx->rasterizer->base.offset_scale;
477
478 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
479
480 SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A,
481 ctx->rasterizer->base.offset_tri);
482 SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B,
483 ctx->rasterizer->base.offset_tri);
484 }
485
486 static void
487 panfrost_frag_meta_zsa_update(struct panfrost_context *ctx,
488 struct mali_shader_meta *fragmeta)
489 {
490 const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil;
491 int zfunc = PIPE_FUNC_ALWAYS;
492
493 if (!zsa) {
494 struct pipe_stencil_state default_stencil = {
495 .enabled = 0,
496 .func = PIPE_FUNC_ALWAYS,
497 .fail_op = MALI_STENCIL_KEEP,
498 .zfail_op = MALI_STENCIL_KEEP,
499 .zpass_op = MALI_STENCIL_KEEP,
500 .writemask = 0xFF,
501 .valuemask = 0xFF
502 };
503
504 panfrost_make_stencil_state(&default_stencil,
505 &fragmeta->stencil_front);
506 fragmeta->stencil_mask_front = default_stencil.writemask;
507 fragmeta->stencil_back = fragmeta->stencil_front;
508 fragmeta->stencil_mask_back = default_stencil.writemask;
509 SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, false);
510 SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, false);
511 } else {
512 SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST,
513 zsa->stencil[0].enabled);
514 panfrost_make_stencil_state(&zsa->stencil[0],
515 &fragmeta->stencil_front);
516 fragmeta->stencil_mask_front = zsa->stencil[0].writemask;
517 fragmeta->stencil_front.ref = ctx->stencil_ref.ref_value[0];
518
519 /* If back-stencil is not enabled, use the front values */
520
521 if (zsa->stencil[1].enabled) {
522 panfrost_make_stencil_state(&zsa->stencil[1],
523 &fragmeta->stencil_back);
524 fragmeta->stencil_mask_back = zsa->stencil[1].writemask;
525 fragmeta->stencil_back.ref = ctx->stencil_ref.ref_value[1];
526 } else {
527 fragmeta->stencil_back = fragmeta->stencil_front;
528 fragmeta->stencil_mask_back = fragmeta->stencil_mask_front;
529 fragmeta->stencil_back.ref = fragmeta->stencil_front.ref;
530 }
531
532 if (zsa->depth.enabled)
533 zfunc = zsa->depth.func;
534
535 /* Depth state (TODO: Refactor) */
536
537 SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK,
538 zsa->depth.writemask);
539 }
540
541 fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
542 fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(zfunc));
543 }
544
545 static void
546 panfrost_frag_meta_blend_update(struct panfrost_context *ctx,
547 struct mali_shader_meta *fragmeta,
548 struct midgard_blend_rt *rts)
549 {
550 const struct panfrost_device *dev = pan_device(ctx->base.screen);
551
552 SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER,
553 (dev->quirks & MIDGARD_SFBD) && ctx->blend &&
554 !ctx->blend->base.dither);
555
556 /* Get blending setup */
557 unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1);
558
559 struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS];
560 unsigned shader_offset = 0;
561 struct panfrost_bo *shader_bo = NULL;
562
563 for (unsigned c = 0; c < rt_count; ++c)
564 blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo,
565 &shader_offset);
566
567 /* If there is a blend shader, work registers are shared. XXX: opt */
568
569 for (unsigned c = 0; c < rt_count; ++c) {
570 if (blend[c].is_shader)
571 fragmeta->midgard1.work_count = 16;
572 }
573
574 /* Even on MFBD, the shader descriptor gets blend shaders. It's *also*
575 * copied to the blend_meta appended (by convention), but this is the
576 * field actually read by the hardware. (Or maybe both are read...?).
577 * Specify the last RTi with a blend shader. */
578
579 fragmeta->blend.shader = 0;
580
581 for (signed rt = (rt_count - 1); rt >= 0; --rt) {
582 if (!blend[rt].is_shader)
583 continue;
584
585 fragmeta->blend.shader = blend[rt].shader.gpu |
586 blend[rt].shader.first_tag;
587 break;
588 }
589
590 if (dev->quirks & MIDGARD_SFBD) {
591 /* When only a single render target platform is used, the blend
592 * information is inside the shader meta itself. We additionally
593 * need to signal CAN_DISCARD for nontrivial blend modes (so
594 * we're able to read back the destination buffer) */
595
596 SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER,
597 blend[0].is_shader);
598
599 if (!blend[0].is_shader) {
600 fragmeta->blend.equation = *blend[0].equation.equation;
601 fragmeta->blend.constant = blend[0].equation.constant;
602 }
603
604 SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD,
605 !blend[0].no_blending);
606 return;
607 }
608
609 /* Additional blend descriptor tacked on for jobs using MFBD */
610
611 for (unsigned i = 0; i < rt_count; ++i) {
612 rts[i].flags = 0x200;
613
614 bool is_srgb = (ctx->pipe_framebuffer.nr_cbufs > i) &&
615 (ctx->pipe_framebuffer.cbufs[i]) &&
616 util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format);
617
618 SET_BIT(rts[i].flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader);
619 SET_BIT(rts[i].flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending);
620 SET_BIT(rts[i].flags, MALI_BLEND_SRGB, is_srgb);
621 SET_BIT(rts[i].flags, MALI_BLEND_NO_DITHER, !ctx->blend->base.dither);
622
623 if (blend[i].is_shader) {
624 rts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag;
625 } else {
626 rts[i].blend.equation = *blend[i].equation.equation;
627 rts[i].blend.constant = blend[i].equation.constant;
628 }
629 }
630 }
631
632 static void
633 panfrost_frag_shader_meta_init(struct panfrost_context *ctx,
634 struct mali_shader_meta *fragmeta,
635 struct midgard_blend_rt *rts)
636 {
637 const struct panfrost_device *dev = pan_device(ctx->base.screen);
638 struct panfrost_shader_state *fs;
639
640 fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
641
642 fragmeta->alpha_coverage = ~MALI_ALPHA_COVERAGE(0.000000);
643 fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x3010;
644 fragmeta->unknown2_4 = 0x4e0;
645
646 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this
647 * is required (independent of 32-bit/64-bit descriptors), or why it's
648 * not used on later GPU revisions. Otherwise, all shader jobs fault on
649 * these earlier chips (perhaps this is a chicken bit of some kind).
650 * More investigation is needed. */
651
652 SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD);
653
654 /* Depending on whether it's legal to in the given shader, we try to
655 * enable early-z testing (or forward-pixel kill?) */
656
657 SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z,
658 !fs->can_discard && !fs->writes_depth);
659
660 /* Add the writes Z/S flags if needed. */
661 SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth);
662 SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil);
663
664 /* Any time texturing is used, derivatives are implicitly calculated,
665 * so we need to enable helper invocations */
666
667 SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS,
668 fs->helper_invocations);
669
670 /* CAN_DISCARD should be set if the fragment shader possibly contains a
671 * 'discard' instruction. It is likely this is related to optimizations
672 * related to forward-pixel kill, as per "Mali Performance 3: Is
673 * EGL_BUFFER_PRESERVED a good thing?" by Peter Harris */
674
675 SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, fs->can_discard);
676 SET_BIT(fragmeta->midgard1.flags_lo, 0x400, fs->can_discard);
677
678 panfrost_frag_meta_rasterizer_update(ctx, fragmeta);
679 panfrost_frag_meta_zsa_update(ctx, fragmeta);
680 panfrost_frag_meta_blend_update(ctx, fragmeta, rts);
681 }
682
683 void
684 panfrost_emit_shader_meta(struct panfrost_batch *batch,
685 enum pipe_shader_type st,
686 struct midgard_payload_vertex_tiler *vtp)
687 {
688 struct panfrost_context *ctx = batch->ctx;
689 struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st);
690
691 if (!ss) {
692 vtp->postfix.shader = 0;
693 return;
694 }
695
696 struct mali_shader_meta meta;
697
698 panfrost_shader_meta_init(ctx, st, &meta);
699
700 /* Add the shader BO to the batch. */
701 panfrost_batch_add_bo(batch, ss->bo,
702 PAN_BO_ACCESS_PRIVATE |
703 PAN_BO_ACCESS_READ |
704 panfrost_bo_access_for_stage(st));
705
706 mali_ptr shader_ptr;
707
708 if (st == PIPE_SHADER_FRAGMENT) {
709 struct panfrost_device *dev = pan_device(ctx->base.screen);
710 unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1);
711 size_t desc_size = sizeof(meta);
712 struct midgard_blend_rt rts[4];
713 struct panfrost_transfer xfer;
714
715 assert(rt_count <= ARRAY_SIZE(rts));
716
717 panfrost_frag_shader_meta_init(ctx, &meta, rts);
718
719 if (!(dev->quirks & MIDGARD_SFBD))
720 desc_size += sizeof(*rts) * rt_count;
721
722 xfer = panfrost_allocate_transient(batch, desc_size);
723
724 memcpy(xfer.cpu, &meta, sizeof(meta));
725 memcpy(xfer.cpu + sizeof(meta), rts, sizeof(*rts) * rt_count);
726
727 shader_ptr = xfer.gpu;
728 } else {
729 shader_ptr = panfrost_upload_transient(batch, &meta,
730 sizeof(meta));
731 }
732
733 vtp->postfix.shader = shader_ptr;
734 }
735
736 static void
737 panfrost_mali_viewport_init(struct panfrost_context *ctx,
738 struct mali_viewport *mvp)
739 {
740 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
741
742 /* Clip bounds are encoded as floats. The viewport itself is encoded as
743 * (somewhat) asymmetric ints. */
744
745 const struct pipe_scissor_state *ss = &ctx->scissor;
746
747 memset(mvp, 0, sizeof(*mvp));
748
749 /* By default, do no viewport clipping, i.e. clip to (-inf, inf) in
750 * each direction. Clipping to the viewport in theory should work, but
751 * in practice causes issues when we're not explicitly trying to
752 * scissor */
753
754 *mvp = (struct mali_viewport) {
755 .clip_minx = -INFINITY,
756 .clip_miny = -INFINITY,
757 .clip_maxx = INFINITY,
758 .clip_maxy = INFINITY,
759 };
760
761 /* Always scissor to the viewport by default. */
762 float vp_minx = (int) (vp->translate[0] - fabsf(vp->scale[0]));
763 float vp_maxx = (int) (vp->translate[0] + fabsf(vp->scale[0]));
764
765 float vp_miny = (int) (vp->translate[1] - fabsf(vp->scale[1]));
766 float vp_maxy = (int) (vp->translate[1] + fabsf(vp->scale[1]));
767
768 float minz = (vp->translate[2] - fabsf(vp->scale[2]));
769 float maxz = (vp->translate[2] + fabsf(vp->scale[2]));
770
771 /* Apply the scissor test */
772
773 unsigned minx, miny, maxx, maxy;
774
775 if (ss && ctx->rasterizer && ctx->rasterizer->base.scissor) {
776 minx = MAX2(ss->minx, vp_minx);
777 miny = MAX2(ss->miny, vp_miny);
778 maxx = MIN2(ss->maxx, vp_maxx);
779 maxy = MIN2(ss->maxy, vp_maxy);
780 } else {
781 minx = vp_minx;
782 miny = vp_miny;
783 maxx = vp_maxx;
784 maxy = vp_maxy;
785 }
786
787 /* Hardware needs the min/max to be strictly ordered, so flip if we
788 * need to. The viewport transformation in the vertex shader will
789 * handle the negatives if we don't */
790
791 if (miny > maxy) {
792 unsigned temp = miny;
793 miny = maxy;
794 maxy = temp;
795 }
796
797 if (minx > maxx) {
798 unsigned temp = minx;
799 minx = maxx;
800 maxx = temp;
801 }
802
803 if (minz > maxz) {
804 float temp = minz;
805 minz = maxz;
806 maxz = temp;
807 }
808
809 /* Clamp to the framebuffer size as a last check */
810
811 minx = MIN2(ctx->pipe_framebuffer.width, minx);
812 maxx = MIN2(ctx->pipe_framebuffer.width, maxx);
813
814 miny = MIN2(ctx->pipe_framebuffer.height, miny);
815 maxy = MIN2(ctx->pipe_framebuffer.height, maxy);
816
817 /* Upload */
818
819 mvp->viewport0[0] = minx;
820 mvp->viewport1[0] = MALI_POSITIVE(maxx);
821
822 mvp->viewport0[1] = miny;
823 mvp->viewport1[1] = MALI_POSITIVE(maxy);
824
825 mvp->clip_minz = minz;
826 mvp->clip_maxz = maxz;
827 }
828
829 void
830 panfrost_emit_viewport(struct panfrost_batch *batch,
831 struct midgard_payload_vertex_tiler *tp)
832 {
833 struct panfrost_context *ctx = batch->ctx;
834 struct mali_viewport mvp;
835
836 panfrost_mali_viewport_init(batch->ctx, &mvp);
837
838 /* Update the job, unless we're doing wallpapering (whose lack of
839 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
840 * just... be faster :) */
841
842 if (!ctx->wallpaper_batch)
843 panfrost_batch_union_scissor(batch, mvp.viewport0[0],
844 mvp.viewport0[1],
845 mvp.viewport1[0] + 1,
846 mvp.viewport1[1] + 1);
847
848 tp->postfix.viewport = panfrost_upload_transient(batch, &mvp,
849 sizeof(mvp));
850 }
851
852 static mali_ptr
853 panfrost_map_constant_buffer_gpu(struct panfrost_batch *batch,
854 enum pipe_shader_type st,
855 struct panfrost_constant_buffer *buf,
856 unsigned index)
857 {
858 struct pipe_constant_buffer *cb = &buf->cb[index];
859 struct panfrost_resource *rsrc = pan_resource(cb->buffer);
860
861 if (rsrc) {
862 panfrost_batch_add_bo(batch, rsrc->bo,
863 PAN_BO_ACCESS_SHARED |
864 PAN_BO_ACCESS_READ |
865 panfrost_bo_access_for_stage(st));
866
867 /* Alignment gauranteed by
868 * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
869 return rsrc->bo->gpu + cb->buffer_offset;
870 } else if (cb->user_buffer) {
871 return panfrost_upload_transient(batch,
872 cb->user_buffer +
873 cb->buffer_offset,
874 cb->buffer_size);
875 } else {
876 unreachable("No constant buffer");
877 }
878 }
879
880 struct sysval_uniform {
881 union {
882 float f[4];
883 int32_t i[4];
884 uint32_t u[4];
885 uint64_t du[2];
886 };
887 };
888
889 static void
890 panfrost_upload_viewport_scale_sysval(struct panfrost_batch *batch,
891 struct sysval_uniform *uniform)
892 {
893 struct panfrost_context *ctx = batch->ctx;
894 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
895
896 uniform->f[0] = vp->scale[0];
897 uniform->f[1] = vp->scale[1];
898 uniform->f[2] = vp->scale[2];
899 }
900
901 static void
902 panfrost_upload_viewport_offset_sysval(struct panfrost_batch *batch,
903 struct sysval_uniform *uniform)
904 {
905 struct panfrost_context *ctx = batch->ctx;
906 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
907
908 uniform->f[0] = vp->translate[0];
909 uniform->f[1] = vp->translate[1];
910 uniform->f[2] = vp->translate[2];
911 }
912
913 static void panfrost_upload_txs_sysval(struct panfrost_batch *batch,
914 enum pipe_shader_type st,
915 unsigned int sysvalid,
916 struct sysval_uniform *uniform)
917 {
918 struct panfrost_context *ctx = batch->ctx;
919 unsigned texidx = PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid);
920 unsigned dim = PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid);
921 bool is_array = PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid);
922 struct pipe_sampler_view *tex = &ctx->sampler_views[st][texidx]->base;
923
924 assert(dim);
925 uniform->i[0] = u_minify(tex->texture->width0, tex->u.tex.first_level);
926
927 if (dim > 1)
928 uniform->i[1] = u_minify(tex->texture->height0,
929 tex->u.tex.first_level);
930
931 if (dim > 2)
932 uniform->i[2] = u_minify(tex->texture->depth0,
933 tex->u.tex.first_level);
934
935 if (is_array)
936 uniform->i[dim] = tex->texture->array_size;
937 }
938
939 static void
940 panfrost_upload_ssbo_sysval(struct panfrost_batch *batch,
941 enum pipe_shader_type st,
942 unsigned ssbo_id,
943 struct sysval_uniform *uniform)
944 {
945 struct panfrost_context *ctx = batch->ctx;
946
947 assert(ctx->ssbo_mask[st] & (1 << ssbo_id));
948 struct pipe_shader_buffer sb = ctx->ssbo[st][ssbo_id];
949
950 /* Compute address */
951 struct panfrost_bo *bo = pan_resource(sb.buffer)->bo;
952
953 panfrost_batch_add_bo(batch, bo,
954 PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_RW |
955 panfrost_bo_access_for_stage(st));
956
957 /* Upload address and size as sysval */
958 uniform->du[0] = bo->gpu + sb.buffer_offset;
959 uniform->u[2] = sb.buffer_size;
960 }
961
962 static void
963 panfrost_upload_sampler_sysval(struct panfrost_batch *batch,
964 enum pipe_shader_type st,
965 unsigned samp_idx,
966 struct sysval_uniform *uniform)
967 {
968 struct panfrost_context *ctx = batch->ctx;
969 struct pipe_sampler_state *sampl = &ctx->samplers[st][samp_idx]->base;
970
971 uniform->f[0] = sampl->min_lod;
972 uniform->f[1] = sampl->max_lod;
973 uniform->f[2] = sampl->lod_bias;
974
975 /* Even without any errata, Midgard represents "no mipmapping" as
976 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
977 * panfrost_create_sampler_state which also explains our choice of
978 * epsilon value (again to keep behaviour consistent) */
979
980 if (sampl->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
981 uniform->f[1] = uniform->f[0] + (1.0/256.0);
982 }
983
984 static void
985 panfrost_upload_num_work_groups_sysval(struct panfrost_batch *batch,
986 struct sysval_uniform *uniform)
987 {
988 struct panfrost_context *ctx = batch->ctx;
989
990 uniform->u[0] = ctx->compute_grid->grid[0];
991 uniform->u[1] = ctx->compute_grid->grid[1];
992 uniform->u[2] = ctx->compute_grid->grid[2];
993 }
994
995 static void
996 panfrost_upload_sysvals(struct panfrost_batch *batch, void *buf,
997 struct panfrost_shader_state *ss,
998 enum pipe_shader_type st)
999 {
1000 struct sysval_uniform *uniforms = (void *)buf;
1001
1002 for (unsigned i = 0; i < ss->sysval_count; ++i) {
1003 int sysval = ss->sysval[i];
1004
1005 switch (PAN_SYSVAL_TYPE(sysval)) {
1006 case PAN_SYSVAL_VIEWPORT_SCALE:
1007 panfrost_upload_viewport_scale_sysval(batch,
1008 &uniforms[i]);
1009 break;
1010 case PAN_SYSVAL_VIEWPORT_OFFSET:
1011 panfrost_upload_viewport_offset_sysval(batch,
1012 &uniforms[i]);
1013 break;
1014 case PAN_SYSVAL_TEXTURE_SIZE:
1015 panfrost_upload_txs_sysval(batch, st,
1016 PAN_SYSVAL_ID(sysval),
1017 &uniforms[i]);
1018 break;
1019 case PAN_SYSVAL_SSBO:
1020 panfrost_upload_ssbo_sysval(batch, st,
1021 PAN_SYSVAL_ID(sysval),
1022 &uniforms[i]);
1023 break;
1024 case PAN_SYSVAL_NUM_WORK_GROUPS:
1025 panfrost_upload_num_work_groups_sysval(batch,
1026 &uniforms[i]);
1027 break;
1028 case PAN_SYSVAL_SAMPLER:
1029 panfrost_upload_sampler_sysval(batch, st,
1030 PAN_SYSVAL_ID(sysval),
1031 &uniforms[i]);
1032 break;
1033 default:
1034 assert(0);
1035 }
1036 }
1037 }
1038
1039 static const void *
1040 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer *buf,
1041 unsigned index)
1042 {
1043 struct pipe_constant_buffer *cb = &buf->cb[index];
1044 struct panfrost_resource *rsrc = pan_resource(cb->buffer);
1045
1046 if (rsrc)
1047 return rsrc->bo->cpu;
1048 else if (cb->user_buffer)
1049 return cb->user_buffer;
1050 else
1051 unreachable("No constant buffer");
1052 }
1053
1054 void
1055 panfrost_emit_const_buf(struct panfrost_batch *batch,
1056 enum pipe_shader_type stage,
1057 struct midgard_payload_vertex_tiler *vtp)
1058 {
1059 struct panfrost_context *ctx = batch->ctx;
1060 struct panfrost_shader_variants *all = ctx->shader[stage];
1061
1062 if (!all)
1063 return;
1064
1065 struct panfrost_constant_buffer *buf = &ctx->constant_buffer[stage];
1066
1067 struct panfrost_shader_state *ss = &all->variants[all->active_variant];
1068
1069 /* Uniforms are implicitly UBO #0 */
1070 bool has_uniforms = buf->enabled_mask & (1 << 0);
1071
1072 /* Allocate room for the sysval and the uniforms */
1073 size_t sys_size = sizeof(float) * 4 * ss->sysval_count;
1074 size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0;
1075 size_t size = sys_size + uniform_size;
1076 struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
1077 size);
1078
1079 /* Upload sysvals requested by the shader */
1080 panfrost_upload_sysvals(batch, transfer.cpu, ss, stage);
1081
1082 /* Upload uniforms */
1083 if (has_uniforms && uniform_size) {
1084 const void *cpu = panfrost_map_constant_buffer_cpu(buf, 0);
1085 memcpy(transfer.cpu + sys_size, cpu, uniform_size);
1086 }
1087
1088 struct mali_vertex_tiler_postfix *postfix = &vtp->postfix;
1089
1090 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1091 * uploaded */
1092
1093 unsigned ubo_count = panfrost_ubo_count(ctx, stage);
1094 assert(ubo_count >= 1);
1095
1096 size_t sz = sizeof(uint64_t) * ubo_count;
1097 uint64_t ubos[PAN_MAX_CONST_BUFFERS];
1098 int uniform_count = ss->uniform_count;
1099
1100 /* Upload uniforms as a UBO */
1101 ubos[0] = MALI_MAKE_UBO(2 + uniform_count, transfer.gpu);
1102
1103 /* The rest are honest-to-goodness UBOs */
1104
1105 for (unsigned ubo = 1; ubo < ubo_count; ++ubo) {
1106 size_t usz = buf->cb[ubo].buffer_size;
1107 bool enabled = buf->enabled_mask & (1 << ubo);
1108 bool empty = usz == 0;
1109
1110 if (!enabled || empty) {
1111 /* Stub out disabled UBOs to catch accesses */
1112 ubos[ubo] = MALI_MAKE_UBO(0, 0xDEAD0000);
1113 continue;
1114 }
1115
1116 mali_ptr gpu = panfrost_map_constant_buffer_gpu(batch, stage,
1117 buf, ubo);
1118
1119 unsigned bytes_per_field = 16;
1120 unsigned aligned = ALIGN_POT(usz, bytes_per_field);
1121 ubos[ubo] = MALI_MAKE_UBO(aligned / bytes_per_field, gpu);
1122 }
1123
1124 mali_ptr ubufs = panfrost_upload_transient(batch, ubos, sz);
1125 postfix->uniforms = transfer.gpu;
1126 postfix->uniform_buffers = ubufs;
1127
1128 buf->dirty_mask = 0;
1129 }
1130
1131 void
1132 panfrost_emit_shared_memory(struct panfrost_batch *batch,
1133 const struct pipe_grid_info *info,
1134 struct midgard_payload_vertex_tiler *vtp)
1135 {
1136 struct panfrost_context *ctx = batch->ctx;
1137 struct panfrost_shader_variants *all = ctx->shader[PIPE_SHADER_COMPUTE];
1138 struct panfrost_shader_state *ss = &all->variants[all->active_variant];
1139 unsigned single_size = util_next_power_of_two(MAX2(ss->shared_size,
1140 128));
1141 unsigned shared_size = single_size * info->grid[0] * info->grid[1] *
1142 info->grid[2] * 4;
1143 struct panfrost_bo *bo = panfrost_batch_get_shared_memory(batch,
1144 shared_size,
1145 1);
1146
1147 struct mali_shared_memory shared = {
1148 .shared_memory = bo->gpu,
1149 .shared_workgroup_count =
1150 util_logbase2_ceil(info->grid[0]) +
1151 util_logbase2_ceil(info->grid[1]) +
1152 util_logbase2_ceil(info->grid[2]),
1153 .shared_unk1 = 0x2,
1154 .shared_shift = util_logbase2(single_size) - 1
1155 };
1156
1157 vtp->postfix.shared_memory = panfrost_upload_transient(batch, &shared,
1158 sizeof(shared));
1159 }
1160
1161 static mali_ptr
1162 panfrost_get_tex_desc(struct panfrost_batch *batch,
1163 enum pipe_shader_type st,
1164 struct panfrost_sampler_view *view)
1165 {
1166 if (!view)
1167 return (mali_ptr) 0;
1168
1169 struct pipe_sampler_view *pview = &view->base;
1170 struct panfrost_resource *rsrc = pan_resource(pview->texture);
1171
1172 /* Add the BO to the job so it's retained until the job is done. */
1173
1174 panfrost_batch_add_bo(batch, rsrc->bo,
1175 PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
1176 panfrost_bo_access_for_stage(st));
1177
1178 panfrost_batch_add_bo(batch, view->bo,
1179 PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ |
1180 panfrost_bo_access_for_stage(st));
1181
1182 return view->bo->gpu;
1183 }
1184
1185 void
1186 panfrost_emit_texture_descriptors(struct panfrost_batch *batch,
1187 enum pipe_shader_type stage,
1188 struct midgard_payload_vertex_tiler *vtp)
1189 {
1190 struct panfrost_context *ctx = batch->ctx;
1191
1192 if (!ctx->sampler_view_count[stage])
1193 return;
1194
1195 uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
1196
1197 for (int i = 0; i < ctx->sampler_view_count[stage]; ++i)
1198 trampolines[i] = panfrost_get_tex_desc(batch, stage,
1199 ctx->sampler_views[stage][i]);
1200
1201 vtp->postfix.texture_trampoline = panfrost_upload_transient(batch,
1202 trampolines,
1203 sizeof(uint64_t) *
1204 ctx->sampler_view_count[stage]);
1205 }
1206
1207 void
1208 panfrost_emit_sampler_descriptors(struct panfrost_batch *batch,
1209 enum pipe_shader_type stage,
1210 struct midgard_payload_vertex_tiler *vtp)
1211 {
1212 struct panfrost_context *ctx = batch->ctx;
1213
1214 if (!ctx->sampler_count[stage])
1215 return;
1216
1217 size_t desc_size = sizeof(struct mali_sampler_descriptor);
1218 size_t transfer_size = desc_size * ctx->sampler_count[stage];
1219 struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
1220 transfer_size);
1221 struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *)transfer.cpu;
1222
1223 for (int i = 0; i < ctx->sampler_count[stage]; ++i)
1224 desc[i] = ctx->samplers[stage][i]->hw;
1225
1226 vtp->postfix.sampler_descriptor = transfer.gpu;
1227 }
1228
1229 void
1230 panfrost_emit_vertex_attr_meta(struct panfrost_batch *batch,
1231 struct midgard_payload_vertex_tiler *vp)
1232 {
1233 struct panfrost_context *ctx = batch->ctx;
1234
1235 if (!ctx->vertex)
1236 return;
1237
1238 struct panfrost_vertex_state *so = ctx->vertex;
1239
1240 panfrost_vertex_state_upd_attr_offs(ctx, vp);
1241 vp->postfix.attribute_meta = panfrost_upload_transient(batch, so->hw,
1242 sizeof(*so->hw) *
1243 PAN_MAX_ATTRIBUTE);
1244 }
1245
1246 void
1247 panfrost_emit_vertex_data(struct panfrost_batch *batch,
1248 struct midgard_payload_vertex_tiler *vp)
1249 {
1250 struct panfrost_context *ctx = batch->ctx;
1251 struct panfrost_vertex_state *so = ctx->vertex;
1252
1253 /* Staged mali_attr, and index into them. i =/= k, depending on the
1254 * vertex buffer mask and instancing. Twice as much room is allocated,
1255 * for a worst case of NPOT_DIVIDEs which take up extra slot */
1256 union mali_attr attrs[PIPE_MAX_ATTRIBS * 2];
1257 unsigned k = 0;
1258
1259 for (unsigned i = 0; i < so->num_elements; ++i) {
1260 /* We map a mali_attr to be 1:1 with the mali_attr_meta, which
1261 * means duplicating some vertex buffers (who cares? aside from
1262 * maybe some caching implications but I somehow doubt that
1263 * matters) */
1264
1265 struct pipe_vertex_element *elem = &so->pipe[i];
1266 unsigned vbi = elem->vertex_buffer_index;
1267
1268 /* The exception to 1:1 mapping is that we can have multiple
1269 * entries (NPOT divisors), so we fixup anyways */
1270
1271 so->hw[i].index = k;
1272
1273 if (!(ctx->vb_mask & (1 << vbi)))
1274 continue;
1275
1276 struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
1277 struct panfrost_resource *rsrc;
1278
1279 rsrc = pan_resource(buf->buffer.resource);
1280 if (!rsrc)
1281 continue;
1282
1283 /* Align to 64 bytes by masking off the lower bits. This
1284 * will be adjusted back when we fixup the src_offset in
1285 * mali_attr_meta */
1286
1287 mali_ptr raw_addr = rsrc->bo->gpu + buf->buffer_offset;
1288 mali_ptr addr = raw_addr & ~63;
1289 unsigned chopped_addr = raw_addr - addr;
1290
1291 /* Add a dependency of the batch on the vertex buffer */
1292 panfrost_batch_add_bo(batch, rsrc->bo,
1293 PAN_BO_ACCESS_SHARED |
1294 PAN_BO_ACCESS_READ |
1295 PAN_BO_ACCESS_VERTEX_TILER);
1296
1297 /* Set common fields */
1298 attrs[k].elements = addr;
1299 attrs[k].stride = buf->stride;
1300
1301 /* Since we advanced the base pointer, we shrink the buffer
1302 * size */
1303 attrs[k].size = rsrc->base.width0 - buf->buffer_offset;
1304
1305 /* We need to add the extra size we masked off (for
1306 * correctness) so the data doesn't get clamped away */
1307 attrs[k].size += chopped_addr;
1308
1309 /* For non-instancing make sure we initialize */
1310 attrs[k].shift = attrs[k].extra_flags = 0;
1311
1312 /* Instancing uses a dramatically different code path than
1313 * linear, so dispatch for the actual emission now that the
1314 * common code is finished */
1315
1316 unsigned divisor = elem->instance_divisor;
1317
1318 if (divisor && ctx->instance_count == 1) {
1319 /* Silly corner case where there's a divisor(=1) but
1320 * there's no legitimate instancing. So we want *every*
1321 * attribute to be the same. So set stride to zero so
1322 * we don't go anywhere. */
1323
1324 attrs[k].size = attrs[k].stride + chopped_addr;
1325 attrs[k].stride = 0;
1326 attrs[k++].elements |= MALI_ATTR_LINEAR;
1327 } else if (ctx->instance_count <= 1) {
1328 /* Normal, non-instanced attributes */
1329 attrs[k++].elements |= MALI_ATTR_LINEAR;
1330 } else {
1331 unsigned instance_shift = vp->instance_shift;
1332 unsigned instance_odd = vp->instance_odd;
1333
1334 k += panfrost_vertex_instanced(ctx->padded_count,
1335 instance_shift,
1336 instance_odd,
1337 divisor, &attrs[k]);
1338 }
1339 }
1340
1341 /* Add special gl_VertexID/gl_InstanceID buffers */
1342
1343 panfrost_vertex_id(ctx->padded_count, &attrs[k]);
1344 so->hw[PAN_VERTEX_ID].index = k++;
1345 panfrost_instance_id(ctx->padded_count, &attrs[k]);
1346 so->hw[PAN_INSTANCE_ID].index = k++;
1347
1348 /* Upload whatever we emitted and go */
1349
1350 vp->postfix.attributes = panfrost_upload_transient(batch, attrs,
1351 k * sizeof(*attrs));
1352 }
1353
1354 static mali_ptr
1355 panfrost_emit_varyings(struct panfrost_batch *batch, union mali_attr *slot,
1356 unsigned stride, unsigned count)
1357 {
1358 /* Fill out the descriptor */
1359 slot->stride = stride;
1360 slot->size = stride * count;
1361 slot->shift = slot->extra_flags = 0;
1362
1363 struct panfrost_transfer transfer = panfrost_allocate_transient(batch,
1364 slot->size);
1365
1366 slot->elements = transfer.gpu | MALI_ATTR_LINEAR;
1367
1368 return transfer.gpu;
1369 }
1370
1371 static void
1372 panfrost_emit_streamout(struct panfrost_batch *batch, union mali_attr *slot,
1373 unsigned stride, unsigned offset, unsigned count,
1374 struct pipe_stream_output_target *target)
1375 {
1376 /* Fill out the descriptor */
1377 slot->stride = stride * 4;
1378 slot->shift = slot->extra_flags = 0;
1379
1380 unsigned max_size = target->buffer_size;
1381 unsigned expected_size = slot->stride * count;
1382
1383 slot->size = MIN2(max_size, expected_size);
1384
1385 /* Grab the BO and bind it to the batch */
1386 struct panfrost_bo *bo = pan_resource(target->buffer)->bo;
1387
1388 /* Varyings are WRITE from the perspective of the VERTEX but READ from
1389 * the perspective of the TILER and FRAGMENT.
1390 */
1391 panfrost_batch_add_bo(batch, bo,
1392 PAN_BO_ACCESS_SHARED |
1393 PAN_BO_ACCESS_RW |
1394 PAN_BO_ACCESS_VERTEX_TILER |
1395 PAN_BO_ACCESS_FRAGMENT);
1396
1397 mali_ptr addr = bo->gpu + target->buffer_offset + (offset * slot->stride);
1398 slot->elements = addr;
1399 }
1400
1401 /* Given a shader and buffer indices, link varying metadata together */
1402
1403 static bool
1404 is_special_varying(gl_varying_slot loc)
1405 {
1406 switch (loc) {
1407 case VARYING_SLOT_POS:
1408 case VARYING_SLOT_PSIZ:
1409 case VARYING_SLOT_PNTC:
1410 case VARYING_SLOT_FACE:
1411 return true;
1412 default:
1413 return false;
1414 }
1415 }
1416
1417 static void
1418 panfrost_emit_varying_meta(void *outptr, struct panfrost_shader_state *ss,
1419 signed general, signed gl_Position,
1420 signed gl_PointSize, signed gl_PointCoord,
1421 signed gl_FrontFacing)
1422 {
1423 struct mali_attr_meta *out = (struct mali_attr_meta *) outptr;
1424
1425 for (unsigned i = 0; i < ss->varying_count; ++i) {
1426 gl_varying_slot location = ss->varyings_loc[i];
1427 int index = -1;
1428
1429 switch (location) {
1430 case VARYING_SLOT_POS:
1431 index = gl_Position;
1432 break;
1433 case VARYING_SLOT_PSIZ:
1434 index = gl_PointSize;
1435 break;
1436 case VARYING_SLOT_PNTC:
1437 index = gl_PointCoord;
1438 break;
1439 case VARYING_SLOT_FACE:
1440 index = gl_FrontFacing;
1441 break;
1442 default:
1443 index = general;
1444 break;
1445 }
1446
1447 assert(index >= 0);
1448 out[i].index = index;
1449 }
1450 }
1451
1452 static bool
1453 has_point_coord(unsigned mask, gl_varying_slot loc)
1454 {
1455 if ((loc >= VARYING_SLOT_TEX0) && (loc <= VARYING_SLOT_TEX7))
1456 return (mask & (1 << (loc - VARYING_SLOT_TEX0)));
1457 else if (loc == VARYING_SLOT_PNTC)
1458 return (mask & (1 << 8));
1459 else
1460 return false;
1461 }
1462
1463 /* Helpers for manipulating stream out information so we can pack varyings
1464 * accordingly. Compute the src_offset for a given captured varying */
1465
1466 static struct pipe_stream_output *
1467 pan_get_so(struct pipe_stream_output_info *info, gl_varying_slot loc)
1468 {
1469 for (unsigned i = 0; i < info->num_outputs; ++i) {
1470 if (info->output[i].register_index == loc)
1471 return &info->output[i];
1472 }
1473
1474 unreachable("Varying not captured");
1475 }
1476
1477 /* TODO: Integers */
1478 static enum mali_format
1479 pan_xfb_format(unsigned nr_components)
1480 {
1481 switch (nr_components) {
1482 case 1: return MALI_R32F;
1483 case 2: return MALI_RG32F;
1484 case 3: return MALI_RGB32F;
1485 case 4: return MALI_RGBA32F;
1486 default: unreachable("Invalid format");
1487 }
1488 }
1489
1490 void
1491 panfrost_emit_varying_descriptor(struct panfrost_batch *batch,
1492 unsigned vertex_count,
1493 struct midgard_payload_vertex_tiler *vp,
1494 struct midgard_payload_vertex_tiler *tp)
1495 {
1496 /* Load the shaders */
1497 struct panfrost_context *ctx = batch->ctx;
1498 struct panfrost_shader_state *vs, *fs;
1499 unsigned int num_gen_varyings = 0;
1500 size_t vs_size, fs_size;
1501
1502 /* Allocate the varying descriptor */
1503
1504 vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
1505 fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
1506 vs_size = sizeof(struct mali_attr_meta) * vs->varying_count;
1507 fs_size = sizeof(struct mali_attr_meta) * fs->varying_count;
1508
1509 struct panfrost_transfer trans = panfrost_allocate_transient(batch,
1510 vs_size +
1511 fs_size);
1512
1513 struct pipe_stream_output_info *so = &vs->stream_output;
1514
1515 /* Check if this varying is linked by us. This is the case for
1516 * general-purpose, non-captured varyings. If it is, link it. If it's
1517 * not, use the provided stream out information to determine the
1518 * offset, since it was already linked for us. */
1519
1520 for (unsigned i = 0; i < vs->varying_count; i++) {
1521 gl_varying_slot loc = vs->varyings_loc[i];
1522
1523 bool special = is_special_varying(loc);
1524 bool captured = ((vs->so_mask & (1ll << loc)) ? true : false);
1525
1526 if (captured) {
1527 struct pipe_stream_output *o = pan_get_so(so, loc);
1528
1529 unsigned dst_offset = o->dst_offset * 4; /* dwords */
1530 vs->varyings[i].src_offset = dst_offset;
1531 } else if (!special) {
1532 vs->varyings[i].src_offset = 16 * (num_gen_varyings++);
1533 }
1534 }
1535
1536 /* Conversely, we need to set src_offset for the captured varyings.
1537 * Here, the layout is defined by the stream out info, not us */
1538
1539 /* Link up with fragment varyings */
1540 bool reads_point_coord = fs->reads_point_coord;
1541
1542 for (unsigned i = 0; i < fs->varying_count; i++) {
1543 gl_varying_slot loc = fs->varyings_loc[i];
1544 unsigned src_offset;
1545 signed vs_idx = -1;
1546
1547 /* Link up */
1548 for (unsigned j = 0; j < vs->varying_count; ++j) {
1549 if (vs->varyings_loc[j] == loc) {
1550 vs_idx = j;
1551 break;
1552 }
1553 }
1554
1555 /* Either assign or reuse */
1556 if (vs_idx >= 0)
1557 src_offset = vs->varyings[vs_idx].src_offset;
1558 else
1559 src_offset = 16 * (num_gen_varyings++);
1560
1561 fs->varyings[i].src_offset = src_offset;
1562
1563 if (has_point_coord(fs->point_sprite_mask, loc))
1564 reads_point_coord = true;
1565 }
1566
1567 memcpy(trans.cpu, vs->varyings, vs_size);
1568 memcpy(trans.cpu + vs_size, fs->varyings, fs_size);
1569
1570 union mali_attr varyings[PIPE_MAX_ATTRIBS] = {0};
1571
1572 /* Figure out how many streamout buffers could be bound */
1573 unsigned so_count = ctx->streamout.num_targets;
1574 for (unsigned i = 0; i < vs->varying_count; i++) {
1575 gl_varying_slot loc = vs->varyings_loc[i];
1576
1577 bool captured = ((vs->so_mask & (1ll << loc)) ? true : false);
1578 if (!captured) continue;
1579
1580 struct pipe_stream_output *o = pan_get_so(so, loc);
1581 so_count = MAX2(so_count, o->output_buffer + 1);
1582 }
1583
1584 signed idx = so_count;
1585 signed general = idx++;
1586 signed gl_Position = idx++;
1587 signed gl_PointSize = vs->writes_point_size ? (idx++) : -1;
1588 signed gl_PointCoord = reads_point_coord ? (idx++) : -1;
1589 signed gl_FrontFacing = fs->reads_face ? (idx++) : -1;
1590 signed gl_FragCoord = fs->reads_frag_coord ? (idx++) : -1;
1591
1592 /* Emit the stream out buffers */
1593
1594 unsigned out_count = u_stream_outputs_for_vertices(ctx->active_prim,
1595 ctx->vertex_count);
1596
1597 for (unsigned i = 0; i < so_count; ++i) {
1598 if (i < ctx->streamout.num_targets) {
1599 panfrost_emit_streamout(batch, &varyings[i],
1600 so->stride[i],
1601 ctx->streamout.offsets[i],
1602 out_count,
1603 ctx->streamout.targets[i]);
1604 } else {
1605 /* Emit a dummy buffer */
1606 panfrost_emit_varyings(batch, &varyings[i],
1607 so->stride[i] * 4,
1608 out_count);
1609
1610 /* Clear the attribute type */
1611 varyings[i].elements &= ~0xF;
1612 }
1613 }
1614
1615 panfrost_emit_varyings(batch, &varyings[general],
1616 num_gen_varyings * 16,
1617 vertex_count);
1618
1619 mali_ptr varyings_p;
1620
1621 /* fp32 vec4 gl_Position */
1622 varyings_p = panfrost_emit_varyings(batch, &varyings[gl_Position],
1623 sizeof(float) * 4, vertex_count);
1624 tp->postfix.position_varying = varyings_p;
1625
1626
1627 if (panfrost_writes_point_size(ctx)) {
1628 varyings_p = panfrost_emit_varyings(batch,
1629 &varyings[gl_PointSize],
1630 2, vertex_count);
1631 tp->primitive_size.pointer = varyings_p;
1632 }
1633
1634 if (reads_point_coord)
1635 varyings[gl_PointCoord].elements = MALI_VARYING_POINT_COORD;
1636
1637 if (fs->reads_face)
1638 varyings[gl_FrontFacing].elements = MALI_VARYING_FRONT_FACING;
1639
1640 if (fs->reads_frag_coord)
1641 varyings[gl_FragCoord].elements = MALI_VARYING_FRAG_COORD;
1642
1643 /* Let's go ahead and link varying meta to the buffer in question, now
1644 * that that information is available. VARYING_SLOT_POS is mapped to
1645 * gl_FragCoord for fragment shaders but gl_Positionf or vertex shaders
1646 * */
1647
1648 panfrost_emit_varying_meta(trans.cpu, vs, general, gl_Position,
1649 gl_PointSize, gl_PointCoord,
1650 gl_FrontFacing);
1651
1652 panfrost_emit_varying_meta(trans.cpu + vs_size, fs, general,
1653 gl_FragCoord, gl_PointSize,
1654 gl_PointCoord, gl_FrontFacing);
1655
1656 /* Replace streamout */
1657
1658 struct mali_attr_meta *ovs = (struct mali_attr_meta *)trans.cpu;
1659 struct mali_attr_meta *ofs = ovs + vs->varying_count;
1660
1661 for (unsigned i = 0; i < vs->varying_count; i++) {
1662 gl_varying_slot loc = vs->varyings_loc[i];
1663
1664 bool captured = ((vs->so_mask & (1ll << loc)) ? true : false);
1665 if (!captured)
1666 continue;
1667
1668 struct pipe_stream_output *o = pan_get_so(so, loc);
1669 ovs[i].index = o->output_buffer;
1670
1671 /* Set the type appropriately. TODO: Integer varyings XXX */
1672 assert(o->stream == 0);
1673 ovs[i].format = pan_xfb_format(o->num_components);
1674 ovs[i].swizzle = panfrost_get_default_swizzle(o->num_components);
1675
1676 /* Link to the fragment */
1677 signed fs_idx = -1;
1678
1679 /* Link up */
1680 for (unsigned j = 0; j < fs->varying_count; ++j) {
1681 if (fs->varyings_loc[j] == loc) {
1682 fs_idx = j;
1683 break;
1684 }
1685 }
1686
1687 if (fs_idx >= 0) {
1688 ofs[fs_idx].index = ovs[i].index;
1689 ofs[fs_idx].format = ovs[i].format;
1690 ofs[fs_idx].swizzle = ovs[i].swizzle;
1691 }
1692 }
1693
1694 /* Replace point sprite */
1695 for (unsigned i = 0; i < fs->varying_count; i++) {
1696 /* If we have a point sprite replacement, handle that here. We
1697 * have to translate location first. TODO: Flip y in shader.
1698 * We're already keying ... just time crunch .. */
1699
1700 if (has_point_coord(fs->point_sprite_mask,
1701 fs->varyings_loc[i])) {
1702 ofs[i].index = gl_PointCoord;
1703
1704 /* Swizzle out the z/w to 0/1 */
1705 ofs[i].format = MALI_RG16F;
1706 ofs[i].swizzle = panfrost_get_default_swizzle(2);
1707 }
1708 }
1709
1710 /* Fix up unaligned addresses */
1711 for (unsigned i = 0; i < so_count; ++i) {
1712 if (varyings[i].elements < MALI_RECORD_SPECIAL)
1713 continue;
1714
1715 unsigned align = (varyings[i].elements & 63);
1716
1717 /* While we're at it, the SO buffers are linear */
1718
1719 if (!align) {
1720 varyings[i].elements |= MALI_ATTR_LINEAR;
1721 continue;
1722 }
1723
1724 /* We need to adjust alignment */
1725 varyings[i].elements &= ~63;
1726 varyings[i].elements |= MALI_ATTR_LINEAR;
1727 varyings[i].size += align;
1728
1729 for (unsigned v = 0; v < vs->varying_count; ++v) {
1730 if (ovs[v].index != i)
1731 continue;
1732
1733 ovs[v].src_offset = vs->varyings[v].src_offset + align;
1734 }
1735
1736 for (unsigned f = 0; f < fs->varying_count; ++f) {
1737 if (ofs[f].index != i)
1738 continue;
1739
1740 ofs[f].src_offset = fs->varyings[f].src_offset + align;
1741 }
1742 }
1743
1744 varyings_p = panfrost_upload_transient(batch, varyings,
1745 idx * sizeof(*varyings));
1746 vp->postfix.varyings = varyings_p;
1747 tp->postfix.varyings = varyings_p;
1748
1749 vp->postfix.varying_meta = trans.gpu;
1750 tp->postfix.varying_meta = trans.gpu + vs_size;
1751 }
1752
1753 void
1754 panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch,
1755 struct midgard_payload_vertex_tiler *vp,
1756 struct midgard_payload_vertex_tiler *tp)
1757 {
1758 struct panfrost_context *ctx = batch->ctx;
1759 bool wallpapering = ctx->wallpaper_batch && batch->tiler_dep;
1760
1761 if (wallpapering) {
1762 /* Inject in reverse order, with "predicted" job indices.
1763 * THIS IS A HACK XXX */
1764 panfrost_new_job(batch, JOB_TYPE_TILER, false,
1765 batch->job_index + 2, tp, sizeof(*tp), true);
1766 panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0,
1767 vp, sizeof(*vp), true);
1768 return;
1769 }
1770
1771 /* If rasterizer discard is enable, only submit the vertex */
1772
1773 bool rasterizer_discard = ctx->rasterizer &&
1774 ctx->rasterizer->base.rasterizer_discard;
1775
1776 unsigned vertex = panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0,
1777 vp, sizeof(*vp), false);
1778
1779 if (rasterizer_discard)
1780 return;
1781
1782 panfrost_new_job(batch, JOB_TYPE_TILER, false, vertex, tp, sizeof(*tp),
1783 false);
1784 }