2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
55 #include "pandecode/decode.h"
57 struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
61 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
62 struct midgard_tiler_descriptor t
= {0};
63 unsigned height
= batch
->key
.height
;
64 unsigned width
= batch
->key
.width
;
67 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
69 /* Compute the polygon header size and use that to offset the body */
71 unsigned header_size
= panfrost_tiler_header_size(
72 width
, height
, t
.hierarchy_mask
, hierarchy
);
74 t
.polygon_list_size
= panfrost_tiler_full_size(
75 width
, height
, t
.hierarchy_mask
, hierarchy
);
80 struct panfrost_bo
*tiler_heap
;
82 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
83 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
88 /* Allow the entire tiler heap */
89 t
.heap_start
= tiler_heap
->gpu
;
90 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
92 struct panfrost_bo
*tiler_dummy
;
94 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
95 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
97 /* The tiler is disabled, so don't allow the tiler heap */
98 t
.heap_start
= tiler_dummy
->gpu
;
99 t
.heap_end
= t
.heap_start
;
101 /* Use a dummy polygon list */
102 t
.polygon_list
= tiler_dummy
->gpu
;
104 /* Disable the tiler */
106 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
108 t
.hierarchy_mask
= MALI_TILER_USER
;
109 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
111 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
112 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
113 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
117 t
.polygon_list_body
=
118 t
.polygon_list
+ header_size
;
125 struct pipe_context
*pipe
,
127 const union pipe_color_union
*color
,
128 double depth
, unsigned stencil
)
130 struct panfrost_context
*ctx
= pan_context(pipe
);
132 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
133 * the existing batch targeting this FBO has draws. We could probably
134 * avoid that by replacing plain clears by quad-draws with a specific
135 * color/depth/stencil value, thus avoiding the generation of extra
138 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
140 panfrost_batch_add_fbo_bos(batch
);
141 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
144 /* TODO: Bifrost requires just a mali_shared_memory, without the rest of the
148 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
150 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
151 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
153 /* If we haven't, reserve space for the framebuffer */
155 if (!batch
->framebuffer
.gpu
) {
156 unsigned size
= (screen
->quirks
& MIDGARD_SFBD
) ?
157 sizeof(struct mali_single_framebuffer
) :
158 sizeof(struct mali_framebuffer
);
160 batch
->framebuffer
= panfrost_allocate_transient(batch
, size
);
162 /* Tag the pointer */
163 if (!(screen
->quirks
& MIDGARD_SFBD
))
164 batch
->framebuffer
.gpu
|= MALI_MFBD
;
167 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
168 ctx
->payloads
[i
].postfix
.shared_memory
= batch
->framebuffer
.gpu
;
171 /* Reset per-frame context, called on context initialisation as well as after
172 * flushing a frame */
175 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
177 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
178 ctx
->payloads
[i
].postfix
.shared_memory
= 0;
181 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
184 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
186 /* TODO: When does this need to be handled? */
187 ctx
->active_queries
= true;
190 /* In practice, every field of these payloads should be configurable
191 * arbitrarily, which means these functions are basically catch-all's for
192 * as-of-yet unwavering unknowns */
195 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
197 /* 0x2 bit clear on 32-bit T6XX */
199 struct midgard_payload_vertex_tiler payload
= {
200 .gl_enables
= 0x4 | 0x2,
203 /* Vertex and compute are closely coupled, so share a payload */
205 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
206 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
210 translate_tex_wrap(enum pipe_tex_wrap w
)
213 case PIPE_TEX_WRAP_REPEAT
:
214 return MALI_WRAP_REPEAT
;
216 case PIPE_TEX_WRAP_CLAMP
:
217 return MALI_WRAP_CLAMP
;
219 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
220 return MALI_WRAP_CLAMP_TO_EDGE
;
222 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
223 return MALI_WRAP_CLAMP_TO_BORDER
;
225 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
226 return MALI_WRAP_MIRRORED_REPEAT
;
228 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
229 return MALI_WRAP_MIRRORED_CLAMP
;
231 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
232 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
234 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
235 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
238 unreachable("Invalid wrap");
243 panfrost_translate_compare_func(enum pipe_compare_func in
)
246 case PIPE_FUNC_NEVER
:
247 return MALI_FUNC_NEVER
;
250 return MALI_FUNC_LESS
;
252 case PIPE_FUNC_EQUAL
:
253 return MALI_FUNC_EQUAL
;
255 case PIPE_FUNC_LEQUAL
:
256 return MALI_FUNC_LEQUAL
;
258 case PIPE_FUNC_GREATER
:
259 return MALI_FUNC_GREATER
;
261 case PIPE_FUNC_NOTEQUAL
:
262 return MALI_FUNC_NOTEQUAL
;
264 case PIPE_FUNC_GEQUAL
:
265 return MALI_FUNC_GEQUAL
;
267 case PIPE_FUNC_ALWAYS
:
268 return MALI_FUNC_ALWAYS
;
271 unreachable("Invalid func");
276 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
279 case PIPE_STENCIL_OP_KEEP
:
280 return MALI_STENCIL_KEEP
;
282 case PIPE_STENCIL_OP_ZERO
:
283 return MALI_STENCIL_ZERO
;
285 case PIPE_STENCIL_OP_REPLACE
:
286 return MALI_STENCIL_REPLACE
;
288 case PIPE_STENCIL_OP_INCR
:
289 return MALI_STENCIL_INCR
;
291 case PIPE_STENCIL_OP_DECR
:
292 return MALI_STENCIL_DECR
;
294 case PIPE_STENCIL_OP_INCR_WRAP
:
295 return MALI_STENCIL_INCR_WRAP
;
297 case PIPE_STENCIL_OP_DECR_WRAP
:
298 return MALI_STENCIL_DECR_WRAP
;
300 case PIPE_STENCIL_OP_INVERT
:
301 return MALI_STENCIL_INVERT
;
304 unreachable("Invalid stencil op");
309 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
311 out
->ref
= 0; /* Gallium gets it from elsewhere */
313 out
->mask
= in
->valuemask
;
314 out
->func
= panfrost_translate_compare_func(in
->func
);
315 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
316 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
317 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
321 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
323 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
324 struct mali_shader_meta shader
= {
325 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
327 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
328 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
331 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
332 * required (independent of 32-bit/64-bit descriptors), or why it's not
333 * used on later GPU revisions. Otherwise, all shader jobs fault on
334 * these earlier chips (perhaps this is a chicken bit of some kind).
335 * More investigation is needed. */
337 if (screen
->quirks
& MIDGARD_SFBD
)
338 shader
.unknown2_4
|= 0x10;
340 struct pipe_stencil_state default_stencil
= {
342 .func
= PIPE_FUNC_ALWAYS
,
343 .fail_op
= MALI_STENCIL_KEEP
,
344 .zfail_op
= MALI_STENCIL_KEEP
,
345 .zpass_op
= MALI_STENCIL_KEEP
,
350 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
351 shader
.stencil_mask_front
= default_stencil
.writemask
;
353 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
354 shader
.stencil_mask_back
= default_stencil
.writemask
;
356 if (default_stencil
.enabled
)
357 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
359 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
363 panfrost_writes_point_size(struct panfrost_context
*ctx
)
365 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
366 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
368 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
371 /* Stage the attribute descriptors so we can adjust src_offset
372 * to let BOs align nicely */
375 panfrost_stage_attributes(struct panfrost_context
*ctx
)
377 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
378 struct panfrost_vertex_state
*so
= ctx
->vertex
;
380 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
381 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
382 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
384 /* Copy as-is for the first pass */
385 memcpy(target
, so
->hw
, sz
);
387 /* Fixup offsets for the second pass. Recall that the hardware
388 * calculates attribute addresses as:
390 * addr = base + (stride * vtx) + src_offset;
392 * However, on Mali, base must be aligned to 64-bytes, so we
395 * base' = base & ~63 = base - (base & 63)
397 * To compensate when using base' (see emit_vertex_data), we have
398 * to adjust src_offset by the masked off piece:
400 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
401 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
402 * = base + (stride * vtx) + src_offset
408 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
410 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
411 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
412 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
413 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
414 mali_ptr addr
= rsrc
->bo
->gpu
+ buf
->buffer_offset
;
416 /* Adjust by the masked off bits of the offset. Make sure we
417 * read src_offset from so->hw (which is not GPU visible)
418 * rather than target (which is) due to caching effects */
420 unsigned src_offset
= so
->hw
[i
].src_offset
;
421 src_offset
+= (addr
& 63);
423 /* Also, somewhat obscurely per-instance data needs to be
424 * offset in response to a delayed start in an indexed draw */
426 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
427 src_offset
-= buf
->stride
* start
;
429 target
[i
].src_offset
= src_offset
;
432 /* Let's also include vertex builtins */
434 struct mali_attr_meta builtin
= {
435 .format
= MALI_R32UI
,
436 .swizzle
= panfrost_get_default_swizzle(1)
439 /* See mali_attr_meta specification for the magic number */
440 memcpy(&target
[PAN_VERTEX_ID
], &builtin
, 4);
441 memcpy(&target
[PAN_INSTANCE_ID
], &builtin
, 4);
443 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
447 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
449 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
450 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
452 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
455 if (ctx
->sampler_count
[t
]) {
456 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
458 struct panfrost_transfer transfer
=
459 panfrost_allocate_transient(batch
, transfer_size
);
461 struct mali_sampler_descriptor
*desc
=
462 (struct mali_sampler_descriptor
*) transfer
.cpu
;
464 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
465 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
467 upload
= transfer
.gpu
;
470 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
474 static enum mali_texture_layout
475 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
477 switch (rsrc
->layout
) {
479 return MALI_TEXTURE_AFBC
;
481 return MALI_TEXTURE_TILED
;
483 return MALI_TEXTURE_LINEAR
;
485 unreachable("Invalid texture layout");
491 struct panfrost_context
*ctx
,
492 enum pipe_shader_type st
,
493 struct panfrost_sampler_view
*view
)
498 struct pipe_sampler_view
*pview
= &view
->base
;
499 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
500 mali_ptr descriptor_gpu
;
503 /* Do we interleave an explicit stride with every element? */
505 bool has_manual_stride
= view
->manual_stride
;
507 /* For easy access */
509 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
510 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
511 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
512 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
513 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
514 unsigned first_face
= 0;
515 unsigned last_face
= 0;
516 unsigned face_mult
= 1;
518 /* Cubemaps have 6 faces as layers in between each actual layer.
519 * There's a bit of an impedence mismatch between Gallium and the
520 * hardware, let's fixup for it */
522 if (pview
->target
== PIPE_TEXTURE_CUBE
|| pview
->target
== PIPE_TEXTURE_CUBE_ARRAY
) {
523 /* TODO: logic wrong in the asserted out cases ... can they happen? */
525 first_face
= first_layer
% 6;
526 last_face
= last_layer
% 6;
530 assert((first_layer
== last_layer
) || (first_face
== 0 && last_face
== 5));
534 /* Lower-bit is set when sampling from colour AFBC */
535 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
536 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
537 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
539 /* Add the BO to the job so it's retained until the job is done. */
540 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
541 panfrost_batch_add_bo(batch
, rsrc
->bo
,
542 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
543 panfrost_bo_access_for_stage(st
));
545 /* Add the usage flags in, since they can change across the CSO
546 * lifetime due to layout switches */
548 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
549 view
->hw
.format
.manual_stride
= has_manual_stride
;
551 /* Inject the addresses in, interleaving array indices, mip levels,
552 * cube faces, and strides in that order */
555 unsigned levels
= 1 + last_level
- first_level
;
556 unsigned layers
= 1 + last_layer
- first_layer
;
557 unsigned faces
= 1 + last_face
- first_face
;
558 unsigned num_elements
= levels
* layers
* faces
;
559 if (has_manual_stride
)
562 descriptor
= malloc(sizeof(struct mali_texture_descriptor
) +
563 sizeof(mali_ptr
) * num_elements
);
564 memcpy(descriptor
, &view
->hw
, sizeof(struct mali_texture_descriptor
));
566 mali_ptr
*pointers_and_strides
= descriptor
+
567 sizeof(struct mali_texture_descriptor
);
569 for (unsigned w
= first_layer
; w
<= last_layer
; ++w
) {
570 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
571 for (unsigned f
= first_face
; f
<= last_face
; ++f
) {
572 pointers_and_strides
[idx
++] =
573 panfrost_get_texture_address(rsrc
, l
, w
* face_mult
+ f
)
574 + afbc_bit
+ view
->astc_stretch
;
575 if (has_manual_stride
) {
576 pointers_and_strides
[idx
++] =
577 rsrc
->slices
[l
].stride
;
583 descriptor_gpu
= panfrost_upload_transient(batch
, descriptor
,
584 sizeof(struct mali_texture_descriptor
) +
585 num_elements
* sizeof(*pointers_and_strides
));
588 return descriptor_gpu
;
592 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
594 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
596 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
597 mali_ptr trampoline
= 0;
599 if (ctx
->sampler_view_count
[t
]) {
600 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
602 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
604 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
606 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
609 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
613 struct sysval_uniform
{
622 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
623 struct sysval_uniform
*uniform
)
625 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
627 uniform
->f
[0] = vp
->scale
[0];
628 uniform
->f
[1] = vp
->scale
[1];
629 uniform
->f
[2] = vp
->scale
[2];
632 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
633 struct sysval_uniform
*uniform
)
635 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
637 uniform
->f
[0] = vp
->translate
[0];
638 uniform
->f
[1] = vp
->translate
[1];
639 uniform
->f
[2] = vp
->translate
[2];
642 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
643 enum pipe_shader_type st
,
644 unsigned int sysvalid
,
645 struct sysval_uniform
*uniform
)
647 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
648 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
649 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
650 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
653 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
656 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
657 tex
->u
.tex
.first_level
);
660 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
661 tex
->u
.tex
.first_level
);
664 uniform
->i
[dim
] = tex
->texture
->array_size
;
667 static void panfrost_upload_ssbo_sysval(
668 struct panfrost_context
*ctx
,
669 enum pipe_shader_type st
,
671 struct sysval_uniform
*uniform
)
673 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
674 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
676 /* Compute address */
677 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
678 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
680 panfrost_batch_add_bo(batch
, bo
,
681 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
682 panfrost_bo_access_for_stage(st
));
684 /* Upload address and size as sysval */
685 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
686 uniform
->u
[2] = sb
.buffer_size
;
690 panfrost_upload_sampler_sysval(
691 struct panfrost_context
*ctx
,
692 enum pipe_shader_type st
,
693 unsigned sampler_index
,
694 struct sysval_uniform
*uniform
)
696 struct pipe_sampler_state
*sampl
=
697 &ctx
->samplers
[st
][sampler_index
]->base
;
699 uniform
->f
[0] = sampl
->min_lod
;
700 uniform
->f
[1] = sampl
->max_lod
;
701 uniform
->f
[2] = sampl
->lod_bias
;
703 /* Even without any errata, Midgard represents "no mipmapping" as
704 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
705 * panfrost_create_sampler_state which also explains our choice of
706 * epsilon value (again to keep behaviour consistent) */
708 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
709 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
712 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
713 struct sysval_uniform
*uniform
)
715 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
716 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
717 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
720 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
721 struct panfrost_shader_state
*ss
,
722 enum pipe_shader_type st
)
724 struct sysval_uniform
*uniforms
= (void *)buf
;
726 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
727 int sysval
= ss
->sysval
[i
];
729 switch (PAN_SYSVAL_TYPE(sysval
)) {
730 case PAN_SYSVAL_VIEWPORT_SCALE
:
731 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
733 case PAN_SYSVAL_VIEWPORT_OFFSET
:
734 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
736 case PAN_SYSVAL_TEXTURE_SIZE
:
737 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
740 case PAN_SYSVAL_SSBO
:
741 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
744 case PAN_SYSVAL_NUM_WORK_GROUPS
:
745 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
747 case PAN_SYSVAL_SAMPLER
:
748 panfrost_upload_sampler_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
758 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
760 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
761 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
764 return rsrc
->bo
->cpu
;
765 else if (cb
->user_buffer
)
766 return cb
->user_buffer
;
768 unreachable("No constant buffer");
772 panfrost_map_constant_buffer_gpu(
773 struct panfrost_context
*ctx
,
774 enum pipe_shader_type st
,
775 struct panfrost_constant_buffer
*buf
,
778 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
779 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
780 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
783 panfrost_batch_add_bo(batch
, rsrc
->bo
,
784 PAN_BO_ACCESS_SHARED
|
786 panfrost_bo_access_for_stage(st
));
788 /* Alignment gauranteed by PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */
789 return rsrc
->bo
->gpu
+ cb
->buffer_offset
;
790 } else if (cb
->user_buffer
) {
791 return panfrost_upload_transient(batch
, cb
->user_buffer
+ cb
->buffer_offset
, cb
->buffer_size
);
793 unreachable("No constant buffer");
797 /* Compute number of UBOs active (more specifically, compute the highest UBO
798 * number addressable -- if there are gaps, include them in the count anyway).
799 * We always include UBO #0 in the count, since we *need* uniforms enabled for
803 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
805 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
806 return 32 - __builtin_clz(mask
);
809 /* Fixes up a shader state with current state */
812 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
813 enum pipe_shader_type stage
)
815 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
818 ctx
->payloads
[stage
].postfix
.shader
= 0;
822 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
824 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
825 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
827 ss
->tripipe
->midgard1
.flags_lo
= 0x220;
829 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
830 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
832 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
834 /* Add the shader BO to the batch. */
835 panfrost_batch_add_bo(batch
, ss
->bo
,
836 PAN_BO_ACCESS_PRIVATE
|
838 panfrost_bo_access_for_stage(stage
));
840 ctx
->payloads
[stage
].postfix
.shader
= panfrost_upload_transient(batch
,
842 sizeof(struct mali_shader_meta
));
845 /* Go through dirty flags and actualise them in the cmdstream. */
848 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
850 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
851 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
853 panfrost_batch_add_fbo_bos(batch
);
854 panfrost_attach_vt_framebuffer(ctx
);
856 if (with_vertex_data
) {
857 panfrost_emit_vertex_data(batch
);
859 /* Varyings emitted for -all- geometry */
860 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
861 panfrost_emit_varying_descriptor(ctx
, total_count
);
864 bool msaa
= ctx
->rasterizer
->base
.multisample
;
866 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
867 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
869 /* TODO: Sample size */
870 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
871 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
874 panfrost_batch_set_requirements(batch
);
876 if (ctx
->occlusion_query
) {
877 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
878 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
881 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
882 panfrost_patch_shader_state(ctx
, PIPE_SHADER_COMPUTE
);
884 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
885 /* Check if we need to link the gl_PointSize varying */
886 if (!panfrost_writes_point_size(ctx
)) {
887 /* If the size is constant, write it out. Otherwise,
888 * don't touch primitive_size (since we would clobber
889 * the pointer there) */
891 bool points
= ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
893 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= points
?
894 ctx
->rasterizer
->base
.point_size
:
895 ctx
->rasterizer
->base
.line_width
;
899 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
900 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
901 ctx
->dirty
|= PAN_DIRTY_FS
;
903 if (ctx
->dirty
& PAN_DIRTY_FS
) {
904 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
905 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
907 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
909 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
912 COPY(attribute_count
);
916 COPY(midgard1
.uniform_count
);
917 COPY(midgard1
.uniform_buffer_count
);
918 COPY(midgard1
.work_count
);
919 COPY(midgard1
.flags_lo
);
920 COPY(midgard1
.flags_hi
);
924 /* Get blending setup */
925 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
927 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
928 unsigned shader_offset
= 0;
929 struct panfrost_bo
*shader_bo
= NULL
;
931 for (unsigned c
= 0; c
< rt_count
; ++c
) {
932 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
, &shader_bo
, &shader_offset
);
935 /* If there is a blend shader, work registers are shared. XXX: opt */
937 for (unsigned c
= 0; c
< rt_count
; ++c
) {
938 if (blend
[c
].is_shader
)
939 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
942 /* Depending on whether it's legal to in the given shader, we
943 * try to enable early-z testing (or forward-pixel kill?) */
945 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_EARLY_Z
,
946 !variant
->can_discard
&& !variant
->writes_depth
);
948 /* Add the writes Z/S flags if needed. */
949 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
,
950 MALI_WRITES_Z
, variant
->writes_depth
);
951 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_hi
,
952 MALI_WRITES_S
, variant
->writes_stencil
);
954 /* Any time texturing is used, derivatives are implicitly
955 * calculated, so we need to enable helper invocations */
957 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
959 /* Assign the stencil refs late */
961 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
962 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
963 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
965 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
966 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
968 /* CAN_DISCARD should be set if the fragment shader possibly
969 * contains a 'discard' instruction. It is likely this is
970 * related to optimizations related to forward-pixel kill, as
971 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
972 * thing?" by Peter Harris
975 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
976 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags_lo
, 0x400, variant
->can_discard
);
978 /* Even on MFBD, the shader descriptor gets blend shaders. It's
979 * *also* copied to the blend_meta appended (by convention),
980 * but this is the field actually read by the hardware. (Or
981 * maybe both are read...?). Specify the last RTi with a blend
984 ctx
->fragment_shader_core
.blend
.shader
= 0;
986 for (signed rt
= (rt_count
- 1); rt
>= 0; --rt
) {
987 if (blend
[rt
].is_shader
) {
988 ctx
->fragment_shader_core
.blend
.shader
=
989 blend
[rt
].shader
.gpu
| blend
[rt
].shader
.first_tag
;
994 if (screen
->quirks
& MIDGARD_SFBD
) {
995 /* When only a single render target platform is used, the blend
996 * information is inside the shader meta itself. We
997 * additionally need to signal CAN_DISCARD for nontrivial blend
998 * modes (so we're able to read back the destination buffer) */
1000 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
1002 if (!blend
[0].is_shader
) {
1003 ctx
->fragment_shader_core
.blend
.equation
=
1004 *blend
[0].equation
.equation
;
1005 ctx
->fragment_shader_core
.blend
.constant
=
1006 blend
[0].equation
.constant
;
1009 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
1012 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1013 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1014 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1016 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
1018 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
1019 /* Additional blend descriptor tacked on for jobs using MFBD */
1021 struct midgard_blend_rt rts
[4];
1023 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1024 rts
[i
].flags
= 0x200;
1027 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1028 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1029 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1031 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
1032 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
1033 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
1034 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
1036 if (blend
[i
].is_shader
) {
1037 rts
[i
].blend
.shader
= blend
[i
].shader
.gpu
| blend
[i
].shader
.first_tag
;
1039 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1040 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1044 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1048 /* We stage to transient, so always dirty.. */
1050 panfrost_stage_attributes(ctx
);
1052 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1053 panfrost_upload_sampler_descriptors(ctx
);
1055 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1056 panfrost_upload_texture_descriptors(ctx
);
1058 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1060 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1061 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1066 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1068 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1070 /* Uniforms are implicitly UBO #0 */
1071 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1073 /* Allocate room for the sysval and the uniforms */
1074 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1075 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1076 size_t size
= sys_size
+ uniform_size
;
1077 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1079 /* Upload sysvals requested by the shader */
1080 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1082 /* Upload uniforms */
1083 if (has_uniforms
&& uniform_size
) {
1084 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1085 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1089 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1091 struct mali_vertex_tiler_postfix
*postfix
=
1092 &ctx
->payloads
[i
].postfix
;
1094 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1097 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1098 assert(ubo_count
>= 1);
1100 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1101 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1103 /* Upload uniforms as a UBO */
1104 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1105 ubos
[0].ptr
= transfer
.gpu
>> 2;
1107 /* The rest are honest-to-goodness UBOs */
1109 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1110 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1112 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1113 bool empty
= usz
== 0;
1115 if (!enabled
|| empty
) {
1116 /* Stub out disabled UBOs to catch accesses */
1119 ubos
[ubo
].ptr
= 0xDEAD0000;
1123 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1125 unsigned bytes_per_field
= 16;
1126 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1127 unsigned fields
= aligned
/ bytes_per_field
;
1129 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1130 ubos
[ubo
].ptr
= gpu
>> 2;
1133 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1134 postfix
->uniforms
= transfer
.gpu
;
1135 postfix
->uniform_buffers
= ubufs
;
1137 buf
->dirty_mask
= 0;
1140 /* TODO: Upload the viewport somewhere more appropriate */
1142 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1143 * (somewhat) asymmetric ints. */
1144 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1146 struct mali_viewport view
= {
1147 /* By default, do no viewport clipping, i.e. clip to (-inf,
1148 * inf) in each direction. Clipping to the viewport in theory
1149 * should work, but in practice causes issues when we're not
1150 * explicitly trying to scissor */
1152 .clip_minx
= -INFINITY
,
1153 .clip_miny
= -INFINITY
,
1154 .clip_maxx
= INFINITY
,
1155 .clip_maxy
= INFINITY
,
1158 /* Always scissor to the viewport by default. */
1159 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1160 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1162 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1163 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1165 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1166 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1168 /* Apply the scissor test */
1170 unsigned minx
, miny
, maxx
, maxy
;
1172 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1173 minx
= MAX2(ss
->minx
, vp_minx
);
1174 miny
= MAX2(ss
->miny
, vp_miny
);
1175 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1176 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1184 /* Hardware needs the min/max to be strictly ordered, so flip if we
1185 * need to. The viewport transformation in the vertex shader will
1186 * handle the negatives if we don't */
1189 unsigned temp
= miny
;
1195 unsigned temp
= minx
;
1206 /* Clamp to the framebuffer size as a last check */
1208 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1209 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1211 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1212 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1214 /* Update the job, unless we're doing wallpapering (whose lack of
1215 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1216 * just... be faster :) */
1218 if (!ctx
->wallpaper_batch
)
1219 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1223 view
.viewport0
[0] = minx
;
1224 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1226 view
.viewport0
[1] = miny
;
1227 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1229 view
.clip_minz
= minz
;
1230 view
.clip_maxz
= maxz
;
1232 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1233 panfrost_upload_transient(batch
,
1235 sizeof(struct mali_viewport
));
1240 /* Corresponds to exactly one draw, but does not submit anything */
1243 panfrost_queue_draw(struct panfrost_context
*ctx
)
1245 /* Handle dirty flags now */
1246 panfrost_emit_for_draw(ctx
, true);
1248 /* If rasterizer discard is enable, only submit the vertex */
1250 bool rasterizer_discard
= ctx
->rasterizer
1251 && ctx
->rasterizer
->base
.rasterizer_discard
;
1254 struct midgard_payload_vertex_tiler
*vertex_payload
= &ctx
->payloads
[PIPE_SHADER_VERTEX
];
1255 struct midgard_payload_vertex_tiler
*tiler_payload
= &ctx
->payloads
[PIPE_SHADER_FRAGMENT
];
1257 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1258 bool wallpapering
= ctx
->wallpaper_batch
&& batch
->tiler_dep
;
1261 /* Inject in reverse order, with "predicted" job indices. THIS IS A HACK XXX */
1262 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, batch
->job_index
+ 2, tiler_payload
, sizeof(*tiler_payload
), true);
1263 panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), true);
1265 unsigned vertex
= panfrost_new_job(batch
, JOB_TYPE_VERTEX
, false, 0, vertex_payload
, sizeof(*vertex_payload
), false);
1267 if (!rasterizer_discard
)
1268 panfrost_new_job(batch
, JOB_TYPE_TILER
, false, vertex
, tiler_payload
, sizeof(*tiler_payload
), false);
1271 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1272 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1277 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1278 batch
->stack_size
= MAX2(batch
->stack_size
, ss
->stack_size
);
1282 /* The entire frame is in memory -- send it off to the kernel! */
1286 struct pipe_context
*pipe
,
1287 struct pipe_fence_handle
**fence
,
1290 struct panfrost_context
*ctx
= pan_context(pipe
);
1291 struct util_dynarray fences
;
1293 /* We must collect the fences before the flush is done, otherwise we'll
1294 * lose track of them.
1297 util_dynarray_init(&fences
, NULL
);
1298 hash_table_foreach(ctx
->batches
, hentry
) {
1299 struct panfrost_batch
*batch
= hentry
->data
;
1301 panfrost_batch_fence_reference(batch
->out_sync
);
1302 util_dynarray_append(&fences
,
1303 struct panfrost_batch_fence
*,
1308 /* Submit all pending jobs */
1309 panfrost_flush_all_batches(ctx
, false);
1312 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1313 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1314 *fence
= (struct pipe_fence_handle
*)f
;
1316 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1317 panfrost_batch_fence_unreference(*fence
);
1319 util_dynarray_fini(&fences
);
1322 if (pan_debug
& PAN_DBG_TRACE
)
1323 pandecode_next_frame();
1326 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1329 g2m_draw_mode(enum pipe_prim_type mode
)
1332 DEFINE_CASE(POINTS
);
1334 DEFINE_CASE(LINE_LOOP
);
1335 DEFINE_CASE(LINE_STRIP
);
1336 DEFINE_CASE(TRIANGLES
);
1337 DEFINE_CASE(TRIANGLE_STRIP
);
1338 DEFINE_CASE(TRIANGLE_FAN
);
1340 DEFINE_CASE(QUAD_STRIP
);
1341 DEFINE_CASE(POLYGON
);
1344 unreachable("Invalid draw mode");
1351 panfrost_translate_index_size(unsigned size
)
1355 return MALI_DRAW_INDEXED_UINT8
;
1358 return MALI_DRAW_INDEXED_UINT16
;
1361 return MALI_DRAW_INDEXED_UINT32
;
1364 unreachable("Invalid index size");
1368 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1369 * good for the duration of the draw (transient), could last longer */
1372 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1374 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1376 off_t offset
= info
->start
* info
->index_size
;
1377 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1379 if (!info
->has_user_indices
) {
1380 /* Only resources can be directly mapped */
1381 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1382 PAN_BO_ACCESS_SHARED
|
1383 PAN_BO_ACCESS_READ
|
1384 PAN_BO_ACCESS_VERTEX_TILER
);
1385 return rsrc
->bo
->gpu
+ offset
;
1387 /* Otherwise, we need to upload to transient memory */
1388 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1389 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1394 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1396 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1398 /* Check if we're scissoring at all */
1400 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1403 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1406 /* Count generated primitives (when there is no geom/tess shaders) for
1407 * transform feedback */
1410 panfrost_statistics_record(
1411 struct panfrost_context
*ctx
,
1412 const struct pipe_draw_info
*info
)
1414 if (!ctx
->active_queries
)
1417 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1418 ctx
->prims_generated
+= prims
;
1420 if (!ctx
->streamout
.num_targets
)
1423 ctx
->tf_prims_generated
+= prims
;
1428 struct pipe_context
*pipe
,
1429 const struct pipe_draw_info
*info
)
1431 struct panfrost_context
*ctx
= pan_context(pipe
);
1433 /* First of all, check the scissor to see if anything is drawn at all.
1434 * If it's not, we drop the draw (mostly a conformance issue;
1435 * well-behaved apps shouldn't hit this) */
1437 if (panfrost_scissor_culls_everything(ctx
))
1440 int mode
= info
->mode
;
1442 /* Fallback unsupported restart index */
1443 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1445 if (info
->primitive_restart
&& info
->index_size
1446 && info
->restart_index
!= primitive_index
) {
1447 util_draw_vbo_without_prim_restart(pipe
, info
);
1451 /* Fallback for unsupported modes */
1453 assert(ctx
->rasterizer
!= NULL
);
1455 if (!(ctx
->draw_modes
& (1 << mode
))) {
1456 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1457 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1459 if (info
->count
< 4) {
1460 /* Degenerate case? */
1464 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1465 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1470 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1471 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1473 /* Now that we have a guaranteed terminating path, find the job.
1474 * Assignment commented out to prevent unused warning */
1476 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1478 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1480 /* Take into account a negative bias */
1481 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1482 ctx
->instance_count
= info
->instance_count
;
1483 ctx
->active_prim
= info
->mode
;
1485 /* For non-indexed draws, they're the same */
1486 unsigned vertex_count
= ctx
->vertex_count
;
1488 unsigned draw_flags
= 0;
1490 /* The draw flags interpret how primitive size is interpreted */
1492 if (panfrost_writes_point_size(ctx
))
1493 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1495 if (info
->primitive_restart
)
1496 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1498 /* These doesn't make much sense */
1500 draw_flags
|= 0x3000;
1502 if (ctx
->rasterizer
&& ctx
->rasterizer
->base
.flatshade_first
)
1503 draw_flags
|= MALI_DRAW_FLATSHADE_FIRST
;
1505 panfrost_statistics_record(ctx
, info
);
1507 if (info
->index_size
) {
1508 /* Calculate the min/max index used so we can figure out how
1509 * many times to invoke the vertex shader */
1511 /* Fetch / calculate index bounds */
1512 unsigned min_index
= 0, max_index
= 0;
1514 if (info
->max_index
== ~0u) {
1515 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1517 min_index
= info
->min_index
;
1518 max_index
= info
->max_index
;
1521 /* Use the corresponding values */
1522 vertex_count
= max_index
- min_index
+ 1;
1523 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1524 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1526 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1527 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1529 //assert(!info->restart_index); /* TODO: Research */
1531 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1532 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1534 /* Index count == vertex count, if no indexing is applied, as
1535 * if it is internally indexed in the expected order */
1537 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1538 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1540 /* Reverse index state */
1541 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (mali_ptr
) 0;
1544 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1545 * vertex_count, 1) */
1547 panfrost_pack_work_groups_fused(
1548 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1549 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1550 1, vertex_count
, info
->instance_count
,
1553 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1555 /* Encode the padded vertex count */
1557 if (info
->instance_count
> 1) {
1558 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1560 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1561 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1563 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1564 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1566 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1567 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1569 ctx
->padded_count
= vertex_count
;
1571 /* Reset instancing state */
1572 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1573 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1574 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1575 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1578 /* Fire off the draw itself */
1579 panfrost_queue_draw(ctx
);
1581 /* Increment transform feedback offsets */
1583 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1584 unsigned output_count
= u_stream_outputs_for_vertices(
1585 ctx
->active_prim
, ctx
->vertex_count
);
1587 ctx
->streamout
.offsets
[i
] += output_count
;
1594 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1600 panfrost_create_rasterizer_state(
1601 struct pipe_context
*pctx
,
1602 const struct pipe_rasterizer_state
*cso
)
1604 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1608 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1609 so
->tiler_gl_enables
= 0x7;
1612 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1614 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1615 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1617 if (cso
->cull_face
& PIPE_FACE_BACK
)
1618 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1624 panfrost_bind_rasterizer_state(
1625 struct pipe_context
*pctx
,
1628 struct panfrost_context
*ctx
= pan_context(pctx
);
1630 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1634 ctx
->rasterizer
= hwcso
;
1635 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1637 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1638 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1640 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1641 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1643 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1645 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1646 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1648 /* Point sprites are emulated */
1650 struct panfrost_shader_state
*variant
=
1651 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1653 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1654 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1658 panfrost_create_vertex_elements_state(
1659 struct pipe_context
*pctx
,
1660 unsigned num_elements
,
1661 const struct pipe_vertex_element
*elements
)
1663 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1665 so
->num_elements
= num_elements
;
1666 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1668 for (int i
= 0; i
< num_elements
; ++i
) {
1669 so
->hw
[i
].index
= i
;
1671 enum pipe_format fmt
= elements
[i
].src_format
;
1672 const struct util_format_description
*desc
= util_format_description(fmt
);
1673 so
->hw
[i
].unknown1
= 0x2;
1674 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1676 so
->hw
[i
].format
= panfrost_find_format(desc
);
1678 /* The field itself should probably be shifted over */
1679 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1686 panfrost_bind_vertex_elements_state(
1687 struct pipe_context
*pctx
,
1690 struct panfrost_context
*ctx
= pan_context(pctx
);
1692 ctx
->vertex
= hwcso
;
1693 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1697 panfrost_create_shader_state(
1698 struct pipe_context
*pctx
,
1699 const struct pipe_shader_state
*cso
,
1700 enum pipe_shader_type stage
)
1702 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1705 /* Token deep copy to prevent memory corruption */
1707 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1708 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1710 /* Precompile for shader-db if we need to */
1711 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1712 struct panfrost_context
*ctx
= pan_context(pctx
);
1714 struct mali_shader_meta meta
;
1715 struct panfrost_shader_state state
;
1716 uint64_t outputs_written
;
1718 panfrost_shader_compile(ctx
, &meta
,
1721 tgsi_processor_to_shader_stage(stage
), &state
,
1729 panfrost_delete_shader_state(
1730 struct pipe_context
*pctx
,
1733 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1735 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1736 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1739 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1740 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1741 panfrost_bo_unreference(shader_state
->bo
);
1742 shader_state
->bo
= NULL
;
1744 free(cso
->variants
);
1750 panfrost_create_sampler_state(
1751 struct pipe_context
*pctx
,
1752 const struct pipe_sampler_state
*cso
)
1754 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1757 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1759 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1760 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1761 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1763 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1764 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1765 unsigned mip_filter
= mip_linear
?
1766 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1767 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1769 struct mali_sampler_descriptor sampler_descriptor
= {
1770 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1771 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1772 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1773 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1774 .compare_func
= panfrost_flip_compare_func(
1775 panfrost_translate_compare_func(
1776 cso
->compare_func
)),
1778 cso
->border_color
.f
[0],
1779 cso
->border_color
.f
[1],
1780 cso
->border_color
.f
[2],
1781 cso
->border_color
.f
[3]
1783 .min_lod
= FIXED_16(cso
->min_lod
, false), /* clamp at 0 */
1784 .max_lod
= FIXED_16(cso
->max_lod
, false),
1785 .lod_bias
= FIXED_16(cso
->lod_bias
, true), /* can be negative */
1786 .seamless_cube_map
= cso
->seamless_cube_map
,
1789 /* If necessary, we disable mipmapping in the sampler descriptor by
1790 * clamping the LOD as tight as possible (from 0 to epsilon,
1791 * essentially -- remember these are fixed point numbers, so
1794 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
1795 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1797 /* Enforce that there is something in the middle by adding epsilon*/
1799 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1800 sampler_descriptor
.max_lod
++;
1803 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1806 so
->hw
= sampler_descriptor
;
1812 panfrost_bind_sampler_states(
1813 struct pipe_context
*pctx
,
1814 enum pipe_shader_type shader
,
1815 unsigned start_slot
, unsigned num_sampler
,
1818 assert(start_slot
== 0);
1820 struct panfrost_context
*ctx
= pan_context(pctx
);
1822 /* XXX: Should upload, not just copy? */
1823 ctx
->sampler_count
[shader
] = num_sampler
;
1824 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1826 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1830 panfrost_variant_matches(
1831 struct panfrost_context
*ctx
,
1832 struct panfrost_shader_state
*variant
,
1833 enum pipe_shader_type type
)
1835 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1836 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1838 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1840 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1841 /* Make sure enable state is at least the same */
1842 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1846 /* Check that the contents of the test are the same */
1847 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1848 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1850 if (!(same_func
&& same_ref
)) {
1855 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1856 variant
->point_sprite_mask
)) {
1857 /* Ensure the same varyings are turned to point sprites */
1858 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1861 /* Ensure the orientation is correct */
1863 rasterizer
->sprite_coord_mode
==
1864 PIPE_SPRITE_COORD_UPPER_LEFT
;
1866 if (variant
->point_sprite_upper_left
!= upper_left
)
1870 /* Otherwise, we're good to go */
1875 * Fix an uncompiled shader's stream output info, and produce a bitmask
1876 * of which VARYING_SLOT_* are captured for stream output.
1878 * Core Gallium stores output->register_index as a "slot" number, where
1879 * slots are assigned consecutively to all outputs in info->outputs_written.
1880 * This naive packing of outputs doesn't work for us - we too have slots,
1881 * but the layout is defined by the VUE map, which we won't have until we
1882 * compile a specific shader variant. So, we remap these and simply store
1883 * VARYING_SLOT_* in our copy's output->register_index fields.
1885 * We then produce a bitmask of outputs which are used for SO.
1887 * Implementation from iris.
1891 update_so_info(struct pipe_stream_output_info
*so_info
,
1892 uint64_t outputs_written
)
1894 uint64_t so_outputs
= 0;
1895 uint8_t reverse_map
[64] = {0};
1898 while (outputs_written
)
1899 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1901 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1902 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1904 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1905 output
->register_index
= reverse_map
[output
->register_index
];
1907 so_outputs
|= 1ull << output
->register_index
;
1914 panfrost_bind_shader_state(
1915 struct pipe_context
*pctx
,
1917 enum pipe_shader_type type
)
1919 struct panfrost_context
*ctx
= pan_context(pctx
);
1921 ctx
->shader
[type
] = hwcso
;
1923 if (type
== PIPE_SHADER_FRAGMENT
)
1924 ctx
->dirty
|= PAN_DIRTY_FS
;
1926 ctx
->dirty
|= PAN_DIRTY_VS
;
1930 /* Match the appropriate variant */
1932 signed variant
= -1;
1933 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1935 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1936 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1942 if (variant
== -1) {
1943 /* No variant matched, so create a new one */
1944 variant
= variants
->variant_count
++;
1946 if (variants
->variant_count
> variants
->variant_space
) {
1947 unsigned old_space
= variants
->variant_space
;
1949 variants
->variant_space
*= 2;
1950 if (variants
->variant_space
== 0)
1951 variants
->variant_space
= 1;
1953 /* Arbitrary limit to stop runaway programs from
1954 * creating an unbounded number of shader variants. */
1955 assert(variants
->variant_space
< 1024);
1957 unsigned msize
= sizeof(struct panfrost_shader_state
);
1958 variants
->variants
= realloc(variants
->variants
,
1959 variants
->variant_space
* msize
);
1961 memset(&variants
->variants
[old_space
], 0,
1962 (variants
->variant_space
- old_space
) * msize
);
1965 struct panfrost_shader_state
*v
=
1966 &variants
->variants
[variant
];
1968 if (type
== PIPE_SHADER_FRAGMENT
) {
1969 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1971 if (ctx
->rasterizer
) {
1972 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1973 v
->point_sprite_upper_left
=
1974 ctx
->rasterizer
->base
.sprite_coord_mode
==
1975 PIPE_SPRITE_COORD_UPPER_LEFT
;
1979 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1983 /* Select this variant */
1984 variants
->active_variant
= variant
;
1986 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1987 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1989 /* We finally have a variant, so compile it */
1991 if (!shader_state
->compiled
) {
1992 uint64_t outputs_written
= 0;
1994 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1995 variants
->base
.type
,
1996 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1997 variants
->base
.ir
.nir
:
1998 variants
->base
.tokens
,
1999 tgsi_processor_to_shader_stage(type
), shader_state
,
2002 shader_state
->compiled
= true;
2004 /* Fixup the stream out information, since what Gallium returns
2005 * normally is mildly insane */
2007 shader_state
->stream_output
= variants
->base
.stream_output
;
2008 shader_state
->so_mask
=
2009 update_so_info(&shader_state
->stream_output
, outputs_written
);
2014 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
2016 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2020 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
2022 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2026 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2028 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2032 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2034 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2038 panfrost_set_vertex_buffers(
2039 struct pipe_context
*pctx
,
2040 unsigned start_slot
,
2041 unsigned num_buffers
,
2042 const struct pipe_vertex_buffer
*buffers
)
2044 struct panfrost_context
*ctx
= pan_context(pctx
);
2046 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2050 panfrost_set_constant_buffer(
2051 struct pipe_context
*pctx
,
2052 enum pipe_shader_type shader
, uint index
,
2053 const struct pipe_constant_buffer
*buf
)
2055 struct panfrost_context
*ctx
= pan_context(pctx
);
2056 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2058 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2060 unsigned mask
= (1 << index
);
2062 if (unlikely(!buf
)) {
2063 pbuf
->enabled_mask
&= ~mask
;
2064 pbuf
->dirty_mask
&= ~mask
;
2068 pbuf
->enabled_mask
|= mask
;
2069 pbuf
->dirty_mask
|= mask
;
2073 panfrost_set_stencil_ref(
2074 struct pipe_context
*pctx
,
2075 const struct pipe_stencil_ref
*ref
)
2077 struct panfrost_context
*ctx
= pan_context(pctx
);
2078 ctx
->stencil_ref
= *ref
;
2080 /* Shader core dirty */
2081 ctx
->dirty
|= PAN_DIRTY_FS
;
2084 static enum mali_texture_type
2085 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2089 case PIPE_TEXTURE_1D
:
2090 case PIPE_TEXTURE_1D_ARRAY
:
2093 case PIPE_TEXTURE_2D
:
2094 case PIPE_TEXTURE_2D_ARRAY
:
2095 case PIPE_TEXTURE_RECT
:
2098 case PIPE_TEXTURE_3D
:
2101 case PIPE_TEXTURE_CUBE
:
2102 case PIPE_TEXTURE_CUBE_ARRAY
:
2103 return MALI_TEX_CUBE
;
2106 unreachable("Unknown target");
2111 panfrost_compute_astc_stretch(
2112 const struct util_format_description
*desc
)
2114 unsigned width
= desc
->block
.width
;
2115 unsigned height
= desc
->block
.height
;
2116 assert(width
>= 4 && width
<= 12);
2117 assert(height
>= 4 && height
<= 12);
2122 return ((height
- 4) * 8) + (width
- 4);
2125 static struct pipe_sampler_view
*
2126 panfrost_create_sampler_view(
2127 struct pipe_context
*pctx
,
2128 struct pipe_resource
*texture
,
2129 const struct pipe_sampler_view
*template)
2131 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2132 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2134 pipe_reference(NULL
, &texture
->reference
);
2136 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2139 so
->base
= *template;
2140 so
->base
.texture
= texture
;
2141 so
->base
.reference
.count
= 1;
2142 so
->base
.context
= pctx
;
2144 /* sampler_views correspond to texture descriptors, minus the texture
2145 * (data) itself. So, we serialise the descriptor here and cache it for
2148 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2150 unsigned char user_swizzle
[4] = {
2151 template->swizzle_r
,
2152 template->swizzle_g
,
2153 template->swizzle_b
,
2157 enum mali_format format
= panfrost_find_format(desc
);
2159 if (format
== MALI_ASTC_HDR_SUPP
|| format
== MALI_ASTC_SRGB_SUPP
)
2160 so
->astc_stretch
= panfrost_compute_astc_stretch(desc
);
2162 /* Check if we need to set a custom stride by computing the "expected"
2163 * stride and comparing it to what the BO actually wants. Only applies
2164 * to linear textures, since tiled/compressed textures have strict
2165 * alignment requirements for their strides as it is */
2167 unsigned first_level
= template->u
.tex
.first_level
;
2168 unsigned last_level
= template->u
.tex
.last_level
;
2170 if (prsrc
->layout
== PAN_LINEAR
) {
2171 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2172 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2173 unsigned width
= u_minify(texture
->width0
, l
);
2174 unsigned comp_stride
= width
* bytes_per_pixel
;
2176 if (comp_stride
!= actual_stride
) {
2177 so
->manual_stride
= true;
2183 /* In the hardware, array_size refers specifically to array textures,
2184 * whereas in Gallium, it also covers cubemaps */
2186 unsigned array_size
= texture
->array_size
;
2188 if (template->target
== PIPE_TEXTURE_CUBE
) {
2189 /* TODO: Cubemap arrays */
2190 assert(array_size
== 6);
2194 struct mali_texture_descriptor texture_descriptor
= {
2195 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2196 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2197 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2198 .array_size
= MALI_POSITIVE(array_size
),
2201 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2203 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2204 .type
= panfrost_translate_texture_type(template->target
),
2208 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2211 texture_descriptor
.levels
= last_level
- first_level
;
2213 so
->hw
= texture_descriptor
;
2215 return (struct pipe_sampler_view
*) so
;
2219 panfrost_set_sampler_views(
2220 struct pipe_context
*pctx
,
2221 enum pipe_shader_type shader
,
2222 unsigned start_slot
, unsigned num_views
,
2223 struct pipe_sampler_view
**views
)
2225 struct panfrost_context
*ctx
= pan_context(pctx
);
2226 unsigned new_nr
= 0;
2229 assert(start_slot
== 0);
2231 for (i
= 0; i
< num_views
; ++i
) {
2234 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2238 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
2239 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2242 ctx
->sampler_view_count
[shader
] = new_nr
;
2244 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2248 panfrost_sampler_view_destroy(
2249 struct pipe_context
*pctx
,
2250 struct pipe_sampler_view
*view
)
2252 pipe_resource_reference(&view
->texture
, NULL
);
2257 panfrost_set_shader_buffers(
2258 struct pipe_context
*pctx
,
2259 enum pipe_shader_type shader
,
2260 unsigned start
, unsigned count
,
2261 const struct pipe_shader_buffer
*buffers
,
2262 unsigned writable_bitmask
)
2264 struct panfrost_context
*ctx
= pan_context(pctx
);
2266 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2267 buffers
, start
, count
);
2270 /* Hints that a framebuffer should use AFBC where possible */
2274 struct panfrost_screen
*screen
,
2275 const struct pipe_framebuffer_state
*fb
)
2277 /* AFBC implemenation incomplete; hide it */
2278 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2280 /* Hint AFBC to the resources bound to each color buffer */
2282 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2283 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2284 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2285 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2288 /* Also hint it to the depth buffer */
2291 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2292 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2297 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2298 const struct pipe_framebuffer_state
*fb
)
2300 struct panfrost_context
*ctx
= pan_context(pctx
);
2302 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2303 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2305 panfrost_invalidate_frame(ctx
);
2309 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2310 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2312 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2316 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2319 struct panfrost_context
*ctx
= pan_context(pipe
);
2320 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2321 ctx
->depth_stencil
= depth_stencil
;
2326 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2327 * emulated in the fragment shader */
2329 if (depth_stencil
->alpha
.enabled
) {
2330 /* We need to trigger a new shader (maybe) */
2331 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2335 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2337 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2338 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2340 /* If back-stencil is not enabled, use the front values */
2341 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2342 unsigned back_index
= back_enab
? 1 : 0;
2344 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2345 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2347 /* Depth state (TODO: Refactor) */
2348 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2349 depth_stencil
->depth
.writemask
);
2351 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2353 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2354 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2356 /* Bounds test not implemented */
2357 assert(!depth_stencil
->depth
.bounds_test
);
2359 ctx
->dirty
|= PAN_DIRTY_FS
;
2363 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2369 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2370 unsigned sample_mask
)
2375 panfrost_set_clip_state(struct pipe_context
*pipe
,
2376 const struct pipe_clip_state
*clip
)
2378 //struct panfrost_context *panfrost = pan_context(pipe);
2382 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2383 unsigned start_slot
,
2384 unsigned num_viewports
,
2385 const struct pipe_viewport_state
*viewports
)
2387 struct panfrost_context
*ctx
= pan_context(pipe
);
2389 assert(start_slot
== 0);
2390 assert(num_viewports
== 1);
2392 ctx
->pipe_viewport
= *viewports
;
2396 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2397 unsigned start_slot
,
2398 unsigned num_scissors
,
2399 const struct pipe_scissor_state
*scissors
)
2401 struct panfrost_context
*ctx
= pan_context(pipe
);
2403 assert(start_slot
== 0);
2404 assert(num_scissors
== 1);
2406 ctx
->scissor
= *scissors
;
2410 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2411 const struct pipe_poly_stipple
*stipple
)
2413 //struct panfrost_context *panfrost = pan_context(pipe);
2417 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2420 struct panfrost_context
*ctx
= pan_context(pipe
);
2421 ctx
->active_queries
= enable
;
2425 panfrost_destroy(struct pipe_context
*pipe
)
2427 struct panfrost_context
*panfrost
= pan_context(pipe
);
2429 if (panfrost
->blitter
)
2430 util_blitter_destroy(panfrost
->blitter
);
2432 if (panfrost
->blitter_wallpaper
)
2433 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2435 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
2436 u_upload_destroy(pipe
->stream_uploader
);
2441 static struct pipe_query
*
2442 panfrost_create_query(struct pipe_context
*pipe
,
2446 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2451 return (struct pipe_query
*) q
;
2455 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2457 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2460 panfrost_bo_unreference(query
->bo
);
2468 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2470 struct panfrost_context
*ctx
= pan_context(pipe
);
2471 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2473 switch (query
->type
) {
2474 case PIPE_QUERY_OCCLUSION_COUNTER
:
2475 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2476 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2477 /* Allocate a bo for the query results to be stored */
2479 query
->bo
= panfrost_bo_create(
2480 pan_screen(ctx
->base
.screen
),
2481 sizeof(unsigned), 0);
2484 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2485 *result
= 0; /* Default to 0 if nothing at all drawn. */
2486 ctx
->occlusion_query
= query
;
2489 /* Geometry statistics are computed in the driver. XXX: geom/tess
2492 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2493 query
->start
= ctx
->prims_generated
;
2495 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2496 query
->start
= ctx
->tf_prims_generated
;
2500 DBG("Skipping query %u\n", query
->type
);
2508 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2510 struct panfrost_context
*ctx
= pan_context(pipe
);
2511 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2513 switch (query
->type
) {
2514 case PIPE_QUERY_OCCLUSION_COUNTER
:
2515 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2516 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2517 ctx
->occlusion_query
= NULL
;
2519 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2520 query
->end
= ctx
->prims_generated
;
2522 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2523 query
->end
= ctx
->tf_prims_generated
;
2531 panfrost_get_query_result(struct pipe_context
*pipe
,
2532 struct pipe_query
*q
,
2534 union pipe_query_result
*vresult
)
2536 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2537 struct panfrost_context
*ctx
= pan_context(pipe
);
2540 switch (query
->type
) {
2541 case PIPE_QUERY_OCCLUSION_COUNTER
:
2542 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2543 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2545 panfrost_flush_all_batches(ctx
, true);
2547 /* Read back the query results */
2548 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2549 unsigned passed
= *result
;
2551 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2552 vresult
->u64
= passed
;
2554 vresult
->b
= !!passed
;
2559 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2560 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2561 panfrost_flush_all_batches(ctx
, true);
2562 vresult
->u64
= query
->end
- query
->start
;
2566 DBG("Skipped query get %u\n", query
->type
);
2573 static struct pipe_stream_output_target
*
2574 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2575 struct pipe_resource
*prsc
,
2576 unsigned buffer_offset
,
2577 unsigned buffer_size
)
2579 struct pipe_stream_output_target
*target
;
2581 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2586 pipe_reference_init(&target
->reference
, 1);
2587 pipe_resource_reference(&target
->buffer
, prsc
);
2589 target
->context
= pctx
;
2590 target
->buffer_offset
= buffer_offset
;
2591 target
->buffer_size
= buffer_size
;
2597 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2598 struct pipe_stream_output_target
*target
)
2600 pipe_resource_reference(&target
->buffer
, NULL
);
2601 ralloc_free(target
);
2605 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2606 unsigned num_targets
,
2607 struct pipe_stream_output_target
**targets
,
2608 const unsigned *offsets
)
2610 struct panfrost_context
*ctx
= pan_context(pctx
);
2611 struct panfrost_streamout
*so
= &ctx
->streamout
;
2613 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2615 for (unsigned i
= 0; i
< num_targets
; i
++) {
2616 if (offsets
[i
] != -1)
2617 so
->offsets
[i
] = offsets
[i
];
2619 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2622 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2623 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2625 so
->num_targets
= num_targets
;
2628 struct pipe_context
*
2629 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2631 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2632 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2634 gallium
->screen
= screen
;
2636 gallium
->destroy
= panfrost_destroy
;
2638 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2640 gallium
->flush
= panfrost_flush
;
2641 gallium
->clear
= panfrost_clear
;
2642 gallium
->draw_vbo
= panfrost_draw_vbo
;
2644 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2645 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2646 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2648 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2650 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2651 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2652 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2654 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2655 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2656 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2658 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2659 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2660 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2662 gallium
->create_fs_state
= panfrost_create_fs_state
;
2663 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2664 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2666 gallium
->create_vs_state
= panfrost_create_vs_state
;
2667 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2668 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2670 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2671 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2672 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2674 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2675 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2676 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2678 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2680 gallium
->set_clip_state
= panfrost_set_clip_state
;
2681 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2682 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2683 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2684 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2686 gallium
->create_query
= panfrost_create_query
;
2687 gallium
->destroy_query
= panfrost_destroy_query
;
2688 gallium
->begin_query
= panfrost_begin_query
;
2689 gallium
->end_query
= panfrost_end_query
;
2690 gallium
->get_query_result
= panfrost_get_query_result
;
2692 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2693 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2694 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2696 panfrost_resource_context_init(gallium
);
2697 panfrost_blend_context_init(gallium
);
2698 panfrost_compute_context_init(gallium
);
2701 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2702 gallium
->const_uploader
= gallium
->stream_uploader
;
2703 assert(gallium
->stream_uploader
);
2705 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2706 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2708 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2710 ctx
->blitter
= util_blitter_create(gallium
);
2711 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2713 assert(ctx
->blitter
);
2714 assert(ctx
->blitter_wallpaper
);
2716 /* Prepare for render! */
2718 panfrost_batch_init(ctx
);
2719 panfrost_emit_vertex_payload(ctx
);
2720 panfrost_invalidate_frame(ctx
);
2721 panfrost_default_shader_backend(ctx
);