2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/half_float.h"
38 #include "indices/u_primconvert.h"
39 #include "tgsi/tgsi_parse.h"
41 #include "pan_screen.h"
42 #include "pan_blending.h"
43 #include "pan_blend_shaders.h"
45 #include "pan_wallpaper.h"
47 static int performance_counter_number
= 0;
48 extern const char *pan_counters_base
;
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
53 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
54 * indepdent between color buffers and depth/stencil). To enable, we allocate
55 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
56 * edit the fragment job here. This routine should be called ONCE per
57 * AFBC-compressed buffer, rather than on every frame. */
60 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
62 if (ctx
->require_sfbd
) {
63 DBG("AFBC not supported yet on SFBD\n");
67 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
68 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
69 /* AFBC metadata is 16 bytes per tile */
70 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
71 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
72 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
73 int stride
= bytes_per_pixel
* ALIGN(rsrc
->base
.width0
, 16);
75 stride
*= 2; /* TODO: Should this be carried over? */
76 int main_size
= stride
* rsrc
->base
.height0
;
77 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
79 /* Allocate the AFBC slab itself, large enough to hold the above */
80 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
81 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
84 rsrc
->bo
->layout
= PAN_AFBC
;
86 /* Compressed textured reads use a tagged pointer to the metadata */
88 rsrc
->bo
->gpu
[0] = rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
89 rsrc
->bo
->cpu
[0] = rsrc
->bo
->afbc_slab
.cpu
;
93 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
95 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
96 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
97 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
98 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
100 /* 8 byte checksum per tile */
101 rsrc
->bo
->checksum_stride
= tile_w
* 8;
102 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
103 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
105 rsrc
->bo
->has_checksum
= true;
108 /* Framebuffer descriptor */
111 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
113 fb
->width
= MALI_POSITIVE(w
);
114 fb
->height
= MALI_POSITIVE(h
);
116 /* No idea why this is needed, but it's how resolution_check is
117 * calculated. It's not clear to us yet why the hardware wants this.
118 * The formula itself was discovered mostly by manual bruteforce and
119 * aggressive algebraic simplification. */
121 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
124 struct mali_single_framebuffer
125 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
127 struct mali_single_framebuffer framebuffer
= {
129 .format
= 0x30000000,
130 .clear_flags
= 0x1000,
131 .unknown_address_0
= ctx
->scratchpad
.gpu
,
132 .unknown_address_1
= ctx
->misc_0
.gpu
,
133 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
135 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
136 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
139 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
144 struct bifrost_framebuffer
145 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
147 struct bifrost_framebuffer framebuffer
= {
148 /* It is not yet clear what tiler_meta means or how it's
149 * calculated, but we can tell the lower 32-bits are a
150 * (monotonically increasing?) function of tile count and
151 * geometry complexity; I suspect it defines a memory size of
152 * some kind? for the tiler. It's really unclear at the
153 * moment... but to add to the confusion, the hardware is happy
154 * enough to accept a zero in this field, so we don't even have
155 * to worry about it right now.
157 * The byte (just after the 32-bit mark) is much more
158 * interesting. The higher nibble I've only ever seen as 0xF,
159 * but the lower one I've seen as 0x0 or 0xF, and it's not
160 * obvious what the difference is. But what -is- obvious is
161 * that when the lower nibble is zero, performance is severely
162 * degraded compared to when the lower nibble is set.
163 * Evidently, that nibble enables some sort of fast path,
164 * perhaps relating to caching or tile flush? Regardless, at
165 * this point there's no clear reason not to set it, aside from
166 * substantially increased memory requirements (of the misc_0
169 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
171 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
172 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
173 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
174 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
179 .rt_count_1
= MALI_POSITIVE(1),
184 /* Corresponds to unknown_address_X of SFBD */
185 .scratchpad
= ctx
->scratchpad
.gpu
,
186 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
188 /* The constant added here is, like the lower word of
189 * tiler_meta, (loosely) another product of framebuffer size
190 * and geometry complexity. It must be sufficiently large for
191 * the tiler_meta fast path to work; if it's too small, there
192 * will be DATA_INVALID_FAULTs. Conversely, it must be less
193 * than the total size of misc_0, or else there's no room. It's
194 * possible this constant configures a partition between two
195 * parts of misc_0? We haven't investigated the functionality,
196 * as these buffers are internally used by the hardware
197 * (presumably by the tiler) but not seemingly touched by the driver
200 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
202 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
203 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
209 /* Are we currently rendering to the screen (rather than an FBO)? */
212 panfrost_is_scanout(struct panfrost_context
*ctx
)
214 /* If there is no color buffer, it's an FBO */
215 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
218 /* If we're too early that no framebuffer was sent, it's scanout */
219 if (!ctx
->pipe_framebuffer
.cbufs
[0])
222 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
223 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
224 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
227 /* Maps float 0.0-1.0 to int 0x00-0xFF */
229 normalised_float_to_u8(float f
)
231 return (uint8_t) (int) (f
* 255.0f
);
236 struct pipe_context
*pipe
,
238 const union pipe_color_union
*color
,
239 double depth
, unsigned stencil
)
241 struct panfrost_context
*ctx
= pan_context(pipe
);
242 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
244 if (buffers
& PIPE_CLEAR_COLOR
) {
245 /* Alpha clear only meaningful without alpha channel, TODO less ad hoc */
246 bool has_alpha
= util_format_has_alpha(ctx
->pipe_framebuffer
.cbufs
[0]->format
);
247 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
249 uint32_t packed_color
=
250 (normalised_float_to_u8(clear_alpha
) << 24) |
251 (normalised_float_to_u8(color
->f
[2]) << 16) |
252 (normalised_float_to_u8(color
->f
[1]) << 8) |
253 (normalised_float_to_u8(color
->f
[0]) << 0);
255 job
->clear_color
= packed_color
;
259 if (buffers
& PIPE_CLEAR_DEPTH
) {
260 job
->clear_depth
= depth
;
263 if (buffers
& PIPE_CLEAR_STENCIL
) {
264 job
->clear_stencil
= stencil
;
267 job
->clear
|= buffers
;
271 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
273 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
274 struct bifrost_render_target rts_list
[] = {
279 .framebuffer
= ctx
->misc_0
.gpu
,
284 /* Allocate memory for the three components */
285 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
286 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
288 /* Opaque 1024-block */
289 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
291 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
292 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
294 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
298 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
300 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
304 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
306 mali_ptr framebuffer
= ctx
->require_sfbd
?
307 panfrost_attach_vt_sfbd(ctx
) :
308 panfrost_attach_vt_mfbd(ctx
);
310 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
311 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
314 /* Reset per-frame context, called on context initialisation as well as after
315 * flushing a frame */
318 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
320 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
321 DBG("Uploaded transient %d bytes\n", transient_count
);
323 /* Rotate cmdstream */
324 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
325 ctx
->cmdstream_i
= 0;
327 if (ctx
->require_sfbd
)
328 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
330 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
332 /* Reset varyings allocated */
333 ctx
->varying_height
= 0;
335 /* The transient cmdstream is dirty every frame; the only bits worth preserving
336 * (textures, shaders, etc) are in other buffers anyways */
338 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
339 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
341 /* Regenerate payloads */
342 panfrost_attach_vt_framebuffer(ctx
);
345 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
348 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
351 /* In practice, every field of these payloads should be configurable
352 * arbitrarily, which means these functions are basically catch-all's for
353 * as-of-yet unwavering unknowns */
356 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
358 struct midgard_payload_vertex_tiler payload
= {
360 .workgroups_z_shift
= 32,
361 .workgroups_x_shift_2
= 0x2,
362 .workgroups_x_shift_3
= 0x5,
364 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
367 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
371 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
373 struct midgard_payload_vertex_tiler payload
= {
375 .workgroups_z_shift
= 32,
376 .workgroups_x_shift_2
= 0x2,
377 .workgroups_x_shift_3
= 0x6,
379 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
383 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
387 translate_tex_wrap(enum pipe_tex_wrap w
)
390 case PIPE_TEX_WRAP_REPEAT
:
391 return MALI_WRAP_REPEAT
;
393 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
394 return MALI_WRAP_CLAMP_TO_EDGE
;
396 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
397 return MALI_WRAP_CLAMP_TO_BORDER
;
399 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
400 return MALI_WRAP_MIRRORED_REPEAT
;
409 translate_tex_filter(enum pipe_tex_filter f
)
412 case PIPE_TEX_FILTER_NEAREST
:
415 case PIPE_TEX_FILTER_LINEAR
:
425 translate_mip_filter(enum pipe_tex_mipfilter f
)
427 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
431 panfrost_translate_compare_func(enum pipe_compare_func in
)
434 case PIPE_FUNC_NEVER
:
435 return MALI_FUNC_NEVER
;
438 return MALI_FUNC_LESS
;
440 case PIPE_FUNC_EQUAL
:
441 return MALI_FUNC_EQUAL
;
443 case PIPE_FUNC_LEQUAL
:
444 return MALI_FUNC_LEQUAL
;
446 case PIPE_FUNC_GREATER
:
447 return MALI_FUNC_GREATER
;
449 case PIPE_FUNC_NOTEQUAL
:
450 return MALI_FUNC_NOTEQUAL
;
452 case PIPE_FUNC_GEQUAL
:
453 return MALI_FUNC_GEQUAL
;
455 case PIPE_FUNC_ALWAYS
:
456 return MALI_FUNC_ALWAYS
;
460 return 0; /* Unreachable */
464 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
467 case PIPE_FUNC_NEVER
:
468 return MALI_ALT_FUNC_NEVER
;
471 return MALI_ALT_FUNC_LESS
;
473 case PIPE_FUNC_EQUAL
:
474 return MALI_ALT_FUNC_EQUAL
;
476 case PIPE_FUNC_LEQUAL
:
477 return MALI_ALT_FUNC_LEQUAL
;
479 case PIPE_FUNC_GREATER
:
480 return MALI_ALT_FUNC_GREATER
;
482 case PIPE_FUNC_NOTEQUAL
:
483 return MALI_ALT_FUNC_NOTEQUAL
;
485 case PIPE_FUNC_GEQUAL
:
486 return MALI_ALT_FUNC_GEQUAL
;
488 case PIPE_FUNC_ALWAYS
:
489 return MALI_ALT_FUNC_ALWAYS
;
493 return 0; /* Unreachable */
497 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
500 case PIPE_STENCIL_OP_KEEP
:
501 return MALI_STENCIL_KEEP
;
503 case PIPE_STENCIL_OP_ZERO
:
504 return MALI_STENCIL_ZERO
;
506 case PIPE_STENCIL_OP_REPLACE
:
507 return MALI_STENCIL_REPLACE
;
509 case PIPE_STENCIL_OP_INCR
:
510 return MALI_STENCIL_INCR
;
512 case PIPE_STENCIL_OP_DECR
:
513 return MALI_STENCIL_DECR
;
515 case PIPE_STENCIL_OP_INCR_WRAP
:
516 return MALI_STENCIL_INCR_WRAP
;
518 case PIPE_STENCIL_OP_DECR_WRAP
:
519 return MALI_STENCIL_DECR_WRAP
;
521 case PIPE_STENCIL_OP_INVERT
:
522 return MALI_STENCIL_INVERT
;
526 return 0; /* Unreachable */
530 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
532 out
->ref
= 0; /* Gallium gets it from elsewhere */
534 out
->mask
= in
->valuemask
;
535 out
->func
= panfrost_translate_compare_func(in
->func
);
536 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
537 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
538 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
542 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
544 struct mali_shader_meta shader
= {
545 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
547 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
548 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
552 shader
.unknown2_4
|= 0x10;
555 struct pipe_stencil_state default_stencil
= {
557 .func
= PIPE_FUNC_ALWAYS
,
558 .fail_op
= MALI_STENCIL_KEEP
,
559 .zfail_op
= MALI_STENCIL_KEEP
,
560 .zpass_op
= MALI_STENCIL_KEEP
,
565 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
566 shader
.stencil_mask_front
= default_stencil
.writemask
;
568 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
569 shader
.stencil_mask_back
= default_stencil
.writemask
;
571 if (default_stencil
.enabled
)
572 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
574 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
577 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
578 * graphics command stream. It should be called once per draw, accordding to
579 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
580 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
583 struct panfrost_transfer
584 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
, bool is_elided_tiler
)
586 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
587 int draw_job_index
= 1 + (2 * ctx
->draw_count
);
589 struct mali_job_descriptor_header job
= {
590 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
591 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
593 .job_descriptor_size
= 1,
597 /* Only non-elided tiler jobs have dependencies which are known at this point */
599 if (is_tiler
&& !is_elided_tiler
) {
600 /* Tiler jobs depend on vertex jobs */
602 job
.job_dependency_index_1
= draw_job_index
;
604 /* Tiler jobs also depend on the previous tiler job */
607 job
.job_dependency_index_2
= draw_job_index
- 1;
610 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
612 /* There's some padding hacks on 32-bit */
619 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
620 memcpy(transfer
.cpu
, &job
, sizeof(job
));
621 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
625 /* Generates a set value job. It's unclear what exactly this does, why it's
626 * necessary, and when to call it. */
629 panfrost_set_value_job(struct panfrost_context
*ctx
)
631 struct mali_job_descriptor_header job
= {
632 .job_type
= JOB_TYPE_SET_VALUE
,
633 .job_descriptor_size
= 1,
634 .job_index
= 1 + (2 * ctx
->draw_count
),
637 struct mali_payload_set_value payload
= {
638 .out
= ctx
->misc_0
.gpu
,
642 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
643 memcpy(transfer
.cpu
, &job
, sizeof(job
));
644 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
646 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
647 ctx
->set_value_job
= transfer
.gpu
;
651 panfrost_emit_varyings(
652 struct panfrost_context
*ctx
,
653 union mali_attr
*slot
,
657 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
659 /* Fill out the descriptor */
660 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
661 slot
->stride
= stride
;
662 slot
->size
= stride
* count
;
664 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
665 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
667 return varying_address
;
671 panfrost_emit_point_coord(union mali_attr
*slot
)
673 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
674 slot
->stride
= slot
->size
= 0;
678 panfrost_emit_varying_descriptor(
679 struct panfrost_context
*ctx
,
680 unsigned invocation_count
)
682 /* Load the shaders */
684 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
685 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
687 /* Allocate the varying descriptor */
689 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
690 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
692 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
695 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
696 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
698 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
699 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
701 /* Buffer indices must be in this order per our convention */
702 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
705 /* General varyings -- use the VS's, since those are more likely to be
706 * accurate on desktop */
708 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
709 vs
->general_varying_stride
, invocation_count
);
711 /* fp32 vec4 gl_Position */
712 ctx
->payload_tiler
.postfix
.position_varying
=
713 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
714 sizeof(float) * 4, invocation_count
);
717 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
718 /* fp16 vec1 gl_PointSize */
719 ctx
->payload_tiler
.primitive_size
.pointer
=
720 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
721 2, invocation_count
);
724 if (fs
->reads_point_coord
) {
725 /* Special descriptor */
726 panfrost_emit_point_coord(&varyings
[idx
++]);
729 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
730 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
731 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
734 /* Emits attributes and varying descriptors, which should be called every draw,
735 * excepting some obscure circumstances */
738 panfrost_emit_vertex_data(struct panfrost_context
*ctx
)
740 /* TODO: Only update the dirtied buffers */
741 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
743 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
745 for (int i
= 0; i
< ctx
->vertex_buffer_count
; ++i
) {
746 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
747 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
749 /* Let's figure out the layout of the attributes in memory so
750 * we can be smart about size computation. The idea is to
751 * figure out the maximum src_offset, which tells us the latest
752 * spot a vertex could start. Meanwhile, we figure out the size
753 * of the attribute memory (assuming interleaved
754 * representation) and tack on the max src_offset for a
755 * reasonably good upper bound on the size.
757 * Proving correctness is left as an exercise to the reader.
760 unsigned max_src_offset
= 0;
762 for (unsigned j
= 0; j
< ctx
->vertex
->num_elements
; ++j
) {
763 if (ctx
->vertex
->pipe
[j
].vertex_buffer_index
!= i
) continue;
764 max_src_offset
= MAX2(max_src_offset
, ctx
->vertex
->pipe
[j
].src_offset
);
767 /* Offset vertex count by draw_start to make sure we upload enough */
768 attrs
[i
].stride
= buf
->stride
;
769 attrs
[i
].size
= buf
->stride
* (ctx
->payload_vertex
.draw_start
+ invocation_count
) + max_src_offset
;
771 /* Vertex elements are -already- GPU-visible, at
772 * rsrc->gpu. However, attribute buffers must be 64 aligned. If
773 * it is not, for now we have to duplicate the buffer. */
775 mali_ptr effective_address
= (rsrc
->bo
->gpu
[0] + buf
->buffer_offset
);
777 if (effective_address
& 0x3F) {
778 attrs
[i
].elements
= panfrost_upload_transient(ctx
, rsrc
->bo
->cpu
[0] + buf
->buffer_offset
, attrs
[i
].size
) | 1;
780 attrs
[i
].elements
= effective_address
| 1;
784 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, ctx
->vertex_buffer_count
* sizeof(union mali_attr
));
786 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
789 /* Go through dirty flags and actualise them in the cmdstream. */
792 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
794 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
796 if (with_vertex_data
) {
797 panfrost_emit_vertex_data(ctx
);
800 bool msaa
= ctx
->rasterizer
->base
.multisample
;
802 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
803 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
805 /* TODO: Sample size */
806 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
807 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
810 /* Enable job requirements at draw-time */
813 job
->requirements
|= PAN_REQ_MSAA
;
815 if (ctx
->depth_stencil
->depth
.writemask
)
816 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
818 if (ctx
->occlusion_query
) {
819 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
820 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
823 if (ctx
->dirty
& PAN_DIRTY_VS
) {
826 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
828 /* Late shader descriptor assignments */
830 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
831 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
834 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
836 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
839 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
840 /* Check if we need to link the gl_PointSize varying */
842 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
844 bool needs_gl_point_size
= vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
846 if (!needs_gl_point_size
) {
847 /* If the size is constant, write it out. Otherwise,
848 * don't touch primitive_size (since we would clobber
849 * the pointer there) */
851 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
854 /* Set the flag for varying (pointer) point size if the shader needs that */
855 SET_BIT(ctx
->payload_tiler
.prefix
.unknown_draw
, MALI_DRAW_VARYING_SIZE
, needs_gl_point_size
);
858 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
860 ctx
->dirty
|= PAN_DIRTY_FS
;
862 if (ctx
->dirty
& PAN_DIRTY_FS
) {
864 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
866 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
869 COPY(attribute_count
);
871 COPY(midgard1
.uniform_count
);
872 COPY(midgard1
.work_count
);
873 COPY(midgard1
.unknown2
);
876 /* If there is a blend shader, work registers are shared */
878 if (ctx
->blend
->has_blend_shader
)
879 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
881 /* Set late due to depending on render state */
882 /* The one at the end seems to mean "1 UBO" */
883 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
885 /* Assign texture/sample count right before upload */
886 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
887 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
889 /* Assign the stencil refs late */
890 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
891 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
893 /* CAN_DISCARD should be set if the fragment shader possibly
894 * contains a 'discard' instruction. It is likely this is
895 * related to optimizations related to forward-pixel kill, as
896 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
897 * thing?" by Peter Harris
900 if (variant
->can_discard
) {
901 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
902 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
903 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
904 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
907 /* Check if we're using the default blend descriptor (fast path) */
910 !ctx
->blend
->has_blend_shader
&&
911 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
912 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
913 (ctx
->blend
->equation
.color_mask
== 0xf);
915 if (ctx
->require_sfbd
) {
916 /* When only a single render target platform is used, the blend
917 * information is inside the shader meta itself. We
918 * additionally need to signal CAN_DISCARD for nontrivial blend
919 * modes (so we're able to read back the destination buffer) */
921 if (ctx
->blend
->has_blend_shader
) {
922 ctx
->fragment_shader_core
.blend_shader
= ctx
->blend
->blend_shader
;
924 memcpy(&ctx
->fragment_shader_core
.blend_equation
, &ctx
->blend
->equation
, sizeof(ctx
->blend
->equation
));
928 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
932 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct mali_blend_meta
);
933 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
934 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
936 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
938 if (!ctx
->require_sfbd
) {
939 /* Additional blend descriptor tacked on for jobs using MFBD */
941 unsigned blend_count
= 0;
943 if (ctx
->blend
->has_blend_shader
) {
944 /* For a blend shader, the bottom nibble corresponds to
945 * the number of work registers used, which signals the
946 * -existence- of a blend shader */
948 assert(ctx
->blend
->blend_work_count
>= 2);
949 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
951 /* Otherwise, the bottom bit simply specifies if
952 * blending (anything other than REPLACE) is enabled */
959 /* Second blend equation is always a simple replace */
961 uint64_t replace_magic
= 0xf0122122;
962 struct mali_blend_equation replace_mode
;
963 memcpy(&replace_mode
, &replace_magic
, sizeof(replace_mode
));
965 struct mali_blend_meta blend_meta
[] = {
967 .unk1
= 0x200 | blend_count
,
968 .blend_equation_1
= ctx
->blend
->equation
,
969 .blend_equation_2
= replace_mode
973 if (ctx
->blend
->has_blend_shader
)
974 memcpy(&blend_meta
[0].blend_equation_1
, &ctx
->blend
->blend_shader
, sizeof(ctx
->blend
->blend_shader
));
976 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), blend_meta
, sizeof(blend_meta
));
980 if (ctx
->dirty
& PAN_DIRTY_VERTEX
) {
981 ctx
->payload_vertex
.postfix
.attribute_meta
= ctx
->vertex
->descriptor_ptr
;
984 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
985 /* Upload samplers back to back, no padding */
987 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
988 if (!ctx
->sampler_count
[t
]) continue;
990 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
991 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
993 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
994 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
997 if (t
== PIPE_SHADER_FRAGMENT
)
998 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
999 else if (t
== PIPE_SHADER_VERTEX
)
1000 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
1006 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
1007 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1009 if (!ctx
->sampler_view_count
[t
]) continue;
1011 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1013 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1014 if (!ctx
->sampler_views
[t
][i
])
1017 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1018 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1020 /* Inject the address in. */
1021 for (int l
= 0; l
< (tex_rsrc
->last_level
+ 1); ++l
)
1022 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[l
] = rsrc
->bo
->gpu
[l
];
1024 /* Workaround maybe-errata (?) with non-mipmaps */
1025 int s
= ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
;
1027 if (!rsrc
->bo
->is_mipmap
) {
1029 /* HW ERRATA, not needed after t6XX */
1030 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[1] = rsrc
->bo
->gpu
[0];
1032 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 1;
1035 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= 0;
1038 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1041 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= s
;
1044 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 0;
1048 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1050 if (t
== PIPE_SHADER_FRAGMENT
)
1051 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1052 else if (t
== PIPE_SHADER_VERTEX
)
1053 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1059 /* Generate the viewport vector of the form: <width/2, height/2, centerx, centery> */
1060 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1062 /* For flipped-Y buffers (signaled by negative scale), the translate is
1063 * flipped as well */
1066 vp
->scale
[1] >= 0.0 ? vp
->translate
[1] :
1067 (ctx
->pipe_framebuffer
.height
- vp
->translate
[1]);
1069 float viewport_vec4
[] = {
1071 fabsf(vp
->scale
[1]),
1077 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1078 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1080 if (i
== PIPE_SHADER_VERTEX
|| i
== PIPE_SHADER_FRAGMENT
) {
1081 /* It doesn't matter if we don't use all the memory;
1082 * we'd need a dummy UBO anyway. Compute the max */
1084 size_t size
= sizeof(viewport_vec4
) + buf
->size
;
1085 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1087 /* Keep track how much we've uploaded */
1090 if (i
== PIPE_SHADER_VERTEX
) {
1091 /* Upload viewport */
1092 memcpy(transfer
.cpu
+ offset
, viewport_vec4
, sizeof(viewport_vec4
));
1093 offset
+= sizeof(viewport_vec4
);
1096 /* Upload uniforms */
1097 memcpy(transfer
.cpu
+ offset
, buf
->buffer
, buf
->size
);
1099 int uniform_count
= 0;
1101 struct mali_vertex_tiler_postfix
*postfix
;
1104 case PIPE_SHADER_VERTEX
:
1105 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1106 postfix
= &ctx
->payload_vertex
.postfix
;
1109 case PIPE_SHADER_FRAGMENT
:
1110 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1111 postfix
= &ctx
->payload_tiler
.postfix
;
1115 DBG("Unknown shader stage %d in uniform upload\n", i
);
1119 /* Also attach the same buffer as a UBO for extended access */
1121 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1123 .size
= MALI_POSITIVE((2 + uniform_count
)),
1124 .ptr
= transfer
.gpu
>> 2,
1128 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1129 postfix
->uniforms
= transfer
.gpu
;
1130 postfix
->uniform_buffers
= ubufs
;
1136 /* TODO: Upload the viewport somewhere more appropriate */
1138 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1139 * (somewhat) asymmetric ints. */
1140 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1142 struct mali_viewport view
= {
1143 /* By default, do no viewport clipping, i.e. clip to (-inf,
1144 * inf) in each direction. Clipping to the viewport in theory
1145 * should work, but in practice causes issues when we're not
1146 * explicitly trying to scissor */
1157 /* Always scissor to the viewport by default. */
1158 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1159 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1161 view
.viewport0
[1] = (int) (translate_y
- fabs(vp
->scale
[1]));
1162 view
.viewport1
[1] = MALI_POSITIVE((int) (translate_y
+ fabs(vp
->scale
[1])));
1164 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
&& 0) {
1165 view
.viewport0
[0] = ss
->minx
;
1166 view
.viewport0
[1] = ss
->miny
;
1167 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1168 view
.viewport1
[1] = MALI_POSITIVE(ss
->maxy
);
1171 ctx
->payload_tiler
.postfix
.viewport
=
1172 panfrost_upload_transient(ctx
,
1174 sizeof(struct mali_viewport
));
1179 /* Corresponds to exactly one draw, but does not submit anything */
1182 panfrost_queue_draw(struct panfrost_context
*ctx
)
1184 /* TODO: Expand the array? */
1185 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1186 DBG("Job buffer overflow, ignoring draw\n");
1190 /* Handle dirty flags now */
1191 panfrost_emit_for_draw(ctx
, true);
1193 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false, false);
1194 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true, false);
1196 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1197 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1199 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1200 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1205 /* At the end of the frame, the vertex and tiler jobs are linked together and
1206 * then the fragment job is plonked at the end. Set value job is first for
1207 * unknown reasons. */
1210 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
1212 if (first
->job_descriptor_size
)
1213 first
->next_job_64
= (u64
) (uintptr_t) next
;
1215 first
->next_job_32
= (u32
) (uintptr_t) next
;
1219 panfrost_link_jobs(struct panfrost_context
*ctx
)
1221 if (ctx
->draw_count
) {
1222 /* Generate the set_value_job */
1223 panfrost_set_value_job(ctx
);
1225 /* Have the first vertex job depend on the set value job */
1226 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1229 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[0]);
1232 /* V -> V/T ; T -> T/null */
1233 for (int i
= 0; i
< ctx
->vertex_job_count
; ++i
) {
1234 bool isLast
= (i
+ 1) == ctx
->vertex_job_count
;
1236 panfrost_link_job_pair(ctx
->u_vertex_jobs
[i
], isLast
? ctx
->tiler_jobs
[0] : ctx
->vertex_jobs
[i
+ 1]);
1240 for (int i
= 0; i
< ctx
->tiler_job_count
; ++i
) {
1241 bool isLast
= (i
+ 1) == ctx
->tiler_job_count
;
1242 panfrost_link_job_pair(ctx
->u_tiler_jobs
[i
], isLast
? 0 : ctx
->tiler_jobs
[i
+ 1]);
1246 /* The entire frame is in memory -- send it off to the kernel! */
1249 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1250 struct pipe_fence_handle
**fence
)
1252 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1253 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1255 /* Edge case if screen is cleared and nothing else */
1256 bool has_draws
= ctx
->draw_count
> 0;
1258 /* Workaround a bizarre lockup (a hardware errata?) */
1260 flush_immediate
= true;
1262 /* A number of jobs are batched -- this must be linked and cleared */
1263 panfrost_link_jobs(ctx
);
1265 ctx
->draw_count
= 0;
1266 ctx
->vertex_job_count
= 0;
1267 ctx
->tiler_job_count
= 0;
1271 bool is_scanout
= panfrost_is_scanout(ctx
);
1272 int fragment_id
= screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1274 /* If visual, we can stall a frame */
1276 if (!flush_immediate
)
1277 screen
->driver
->force_flush_fragment(ctx
, fence
);
1279 screen
->last_fragment_id
= fragment_id
;
1280 screen
->last_fragment_flushed
= false;
1282 /* If readback, flush now (hurts the pipelined performance) */
1283 if (flush_immediate
)
1284 screen
->driver
->force_flush_fragment(ctx
, fence
);
1286 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1287 screen
->driver
->dump_counters(screen
);
1290 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1291 FILE *fp
= fopen(filename
, "wb");
1292 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1301 struct pipe_context
*pipe
,
1302 struct pipe_fence_handle
**fence
,
1305 struct panfrost_context
*ctx
= pan_context(pipe
);
1306 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1308 /* Nothing to do! */
1309 if (!ctx
->draw_count
&& !job
->clear
) return;
1311 /* Whether to stall the pipeline for immediately correct results */
1312 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1314 /* Submit the frame itself */
1315 panfrost_submit_frame(ctx
, flush_immediate
, fence
);
1317 /* Prepare for the next frame */
1318 panfrost_invalidate_frame(ctx
);
1321 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1324 g2m_draw_mode(enum pipe_prim_type mode
)
1327 DEFINE_CASE(POINTS
);
1329 DEFINE_CASE(LINE_LOOP
);
1330 DEFINE_CASE(LINE_STRIP
);
1331 DEFINE_CASE(TRIANGLES
);
1332 DEFINE_CASE(TRIANGLE_STRIP
);
1333 DEFINE_CASE(TRIANGLE_FAN
);
1335 DEFINE_CASE(QUAD_STRIP
);
1336 DEFINE_CASE(POLYGON
);
1339 DBG("Illegal draw mode %d\n", mode
);
1341 return MALI_LINE_LOOP
;
1348 panfrost_translate_index_size(unsigned size
)
1352 return MALI_DRAW_INDEXED_UINT8
;
1355 return MALI_DRAW_INDEXED_UINT16
;
1358 return MALI_DRAW_INDEXED_UINT32
;
1361 DBG("Unknown index size %d\n", size
);
1367 static const uint8_t *
1368 panfrost_get_index_buffer_raw(const struct pipe_draw_info
*info
)
1370 if (info
->has_user_indices
) {
1371 return (const uint8_t *) info
->index
.user
;
1373 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1374 return (const uint8_t *) rsrc
->bo
->cpu
[0];
1378 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1379 * good for the duration of the draw (transient), could last longer */
1382 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1384 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1386 off_t offset
= info
->start
* info
->index_size
;
1388 if (!info
->has_user_indices
) {
1389 /* Only resources can be directly mapped */
1390 return rsrc
->bo
->gpu
[0] + offset
;
1392 /* Otherwise, we need to upload to transient memory */
1393 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1394 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1398 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1399 for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1400 T idx = buffer[_idx]; \
1401 if (idx > max_index) max_index = idx; \
1402 if (idx < min_index) min_index = idx; \
1407 struct pipe_context
*pipe
,
1408 const struct pipe_draw_info
*info
)
1410 struct panfrost_context
*ctx
= pan_context(pipe
);
1412 ctx
->payload_vertex
.draw_start
= info
->start
;
1413 ctx
->payload_tiler
.draw_start
= info
->start
;
1415 int mode
= info
->mode
;
1417 /* Fallback for unsupported modes */
1419 if (!(ctx
->draw_modes
& (1 << mode
))) {
1420 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1421 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1423 if (info
->count
< 4) {
1424 /* Degenerate case? */
1428 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1429 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1434 /* Now that we have a guaranteed terminating path, find the job.
1435 * Assignment commented out to prevent unused warning */
1437 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1439 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1441 ctx
->vertex_count
= info
->count
;
1443 /* For non-indexed draws, they're the same */
1444 unsigned invocation_count
= ctx
->vertex_count
;
1446 /* For higher amounts of vertices (greater than what fits in a 16-bit
1447 * short), the other value is needed, otherwise there will be bizarre
1448 * rendering artefacts. It's not clear what these values mean yet. */
1450 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~(0x3000 | 0x18000);
1451 ctx
->payload_tiler
.prefix
.unknown_draw
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1453 if (info
->index_size
) {
1454 /* Calculate the min/max index used so we can figure out how
1455 * many times to invoke the vertex shader */
1457 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1459 int min_index
= INT_MAX
;
1462 if (info
->index_size
== 1) {
1463 CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8
, info
->start
, info
->count
);
1464 } else if (info
->index_size
== 2) {
1465 const uint16_t *ibuf16
= (const uint16_t *) ibuf8
;
1466 CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16
, info
->start
, info
->count
);
1467 } else if (info
->index_size
== 4) {
1468 const uint32_t *ibuf32
= (const uint32_t *) ibuf8
;
1469 CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32
, info
->start
, info
->count
);
1474 /* Make sure we didn't go crazy */
1475 assert(min_index
< INT_MAX
);
1476 assert(max_index
> 0);
1477 assert(max_index
> min_index
);
1479 /* Use the corresponding values */
1480 invocation_count
= max_index
- min_index
+ 1;
1481 ctx
->payload_vertex
.draw_start
= min_index
;
1482 ctx
->payload_tiler
.draw_start
= min_index
;
1484 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1485 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1487 //assert(!info->restart_index); /* TODO: Research */
1488 assert(!info
->index_bias
);
1489 //assert(!info->min_index); /* TODO: Use value */
1491 ctx
->payload_tiler
.prefix
.unknown_draw
|= panfrost_translate_index_size(info
->index_size
);
1492 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1494 /* Index count == vertex count, if no indexing is applied, as
1495 * if it is internally indexed in the expected order */
1497 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1498 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1500 /* Reverse index state */
1501 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~MALI_DRAW_INDEXED_UINT32
;
1502 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1505 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1506 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1508 /* Fire off the draw itself */
1509 panfrost_queue_draw(ctx
);
1515 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1521 panfrost_create_rasterizer_state(
1522 struct pipe_context
*pctx
,
1523 const struct pipe_rasterizer_state
*cso
)
1525 struct panfrost_context
*ctx
= pan_context(pctx
);
1526 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1530 /* Bitmask, unknown meaning of the start value */
1531 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1533 so
->tiler_gl_enables
|= MALI_FRONT_FACE(
1534 cso
->front_ccw
? MALI_CCW
: MALI_CW
);
1536 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1537 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1539 if (cso
->cull_face
& PIPE_FACE_BACK
)
1540 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1546 panfrost_bind_rasterizer_state(
1547 struct pipe_context
*pctx
,
1550 struct panfrost_context
*ctx
= pan_context(pctx
);
1552 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1556 ctx
->rasterizer
= hwcso
;
1557 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1561 panfrost_create_vertex_elements_state(
1562 struct pipe_context
*pctx
,
1563 unsigned num_elements
,
1564 const struct pipe_vertex_element
*elements
)
1566 struct panfrost_context
*ctx
= pan_context(pctx
);
1567 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1569 so
->num_elements
= num_elements
;
1570 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1572 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_attr_meta
) * num_elements
, HEAP_DESCRIPTOR
);
1573 so
->hw
= (struct mali_attr_meta
*) transfer
.cpu
;
1574 so
->descriptor_ptr
= transfer
.gpu
;
1576 /* Allocate memory for the descriptor state */
1578 for (int i
= 0; i
< num_elements
; ++i
) {
1579 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1581 enum pipe_format fmt
= elements
[i
].src_format
;
1582 const struct util_format_description
*desc
= util_format_description(fmt
);
1583 so
->hw
[i
].unknown1
= 0x2;
1584 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1586 so
->hw
[i
].format
= panfrost_find_format(desc
);
1588 /* The field itself should probably be shifted over */
1589 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1596 panfrost_bind_vertex_elements_state(
1597 struct pipe_context
*pctx
,
1600 struct panfrost_context
*ctx
= pan_context(pctx
);
1602 ctx
->vertex
= hwcso
;
1603 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1607 panfrost_delete_vertex_elements_state(struct pipe_context
*pctx
, void *hwcso
)
1609 struct panfrost_vertex_state
*so
= (struct panfrost_vertex_state
*) hwcso
;
1610 unsigned bytes
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
1611 DBG("Vertex elements delete leaks descriptor (%d bytes)\n", bytes
);
1616 panfrost_create_shader_state(
1617 struct pipe_context
*pctx
,
1618 const struct pipe_shader_state
*cso
)
1620 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1623 /* Token deep copy to prevent memory corruption */
1625 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1626 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1632 panfrost_delete_shader_state(
1633 struct pipe_context
*pctx
,
1636 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1638 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1639 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1642 unsigned leak
= cso
->variant_count
* sizeof(struct mali_shader_meta
);
1643 DBG("Deleting shader state leaks descriptors (%d bytes), and shader bytecode\n", leak
);
1649 panfrost_create_sampler_state(
1650 struct pipe_context
*pctx
,
1651 const struct pipe_sampler_state
*cso
)
1653 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1656 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1658 struct mali_sampler_descriptor sampler_descriptor
= {
1659 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1660 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1661 | translate_mip_filter(cso
->min_mip_filter
)
1664 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1665 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1666 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1667 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1669 cso
->border_color
.f
[0],
1670 cso
->border_color
.f
[1],
1671 cso
->border_color
.f
[2],
1672 cso
->border_color
.f
[3]
1674 .min_lod
= FIXED_16(0.0),
1675 .max_lod
= FIXED_16(31.0),
1679 so
->hw
= sampler_descriptor
;
1685 panfrost_bind_sampler_states(
1686 struct pipe_context
*pctx
,
1687 enum pipe_shader_type shader
,
1688 unsigned start_slot
, unsigned num_sampler
,
1691 assert(start_slot
== 0);
1693 struct panfrost_context
*ctx
= pan_context(pctx
);
1695 /* XXX: Should upload, not just copy? */
1696 ctx
->sampler_count
[shader
] = num_sampler
;
1697 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1699 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1703 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
1705 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1707 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
1708 /* Make sure enable state is at least the same */
1709 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1713 /* Check that the contents of the test are the same */
1714 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1715 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1717 if (!(same_func
&& same_ref
)) {
1721 /* Otherwise, we're good to go */
1726 panfrost_bind_fs_state(
1727 struct pipe_context
*pctx
,
1730 struct panfrost_context
*ctx
= pan_context(pctx
);
1735 /* Match the appropriate variant */
1737 signed variant
= -1;
1739 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1741 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1742 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
1748 if (variant
== -1) {
1749 /* No variant matched, so create a new one */
1750 variant
= variants
->variant_count
++;
1751 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1753 variants
->variants
[variant
].base
= hwcso
;
1754 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1756 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
1757 struct panfrost_context
*ctx
= pan_context(pctx
);
1758 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1760 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1761 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1765 /* Select this variant */
1766 variants
->active_variant
= variant
;
1768 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1769 assert(panfrost_variant_matches(ctx
, shader_state
));
1771 /* Now we have a variant selected, so compile and go */
1773 if (!shader_state
->compiled
) {
1774 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
1775 shader_state
->compiled
= true;
1779 ctx
->dirty
|= PAN_DIRTY_FS
;
1783 panfrost_bind_vs_state(
1784 struct pipe_context
*pctx
,
1787 struct panfrost_context
*ctx
= pan_context(pctx
);
1792 if (!ctx
->vs
->variants
[0].compiled
) {
1793 ctx
->vs
->variants
[0].base
= hwcso
;
1795 /* TODO DRY from above */
1796 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1797 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1798 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
1800 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
1801 ctx
->vs
->variants
[0].compiled
= true;
1805 ctx
->dirty
|= PAN_DIRTY_VS
;
1809 panfrost_set_vertex_buffers(
1810 struct pipe_context
*pctx
,
1811 unsigned start_slot
,
1812 unsigned num_buffers
,
1813 const struct pipe_vertex_buffer
*buffers
)
1815 struct panfrost_context
*ctx
= pan_context(pctx
);
1816 assert(num_buffers
<= PIPE_MAX_ATTRIBS
);
1818 /* XXX: Dirty tracking? etc */
1820 size_t sz
= sizeof(buffers
[0]) * num_buffers
;
1821 ctx
->vertex_buffers
= malloc(sz
);
1822 ctx
->vertex_buffer_count
= num_buffers
;
1823 memcpy(ctx
->vertex_buffers
, buffers
, sz
);
1825 if (ctx
->vertex_buffers
) {
1826 free(ctx
->vertex_buffers
);
1827 ctx
->vertex_buffers
= NULL
;
1830 ctx
->vertex_buffer_count
= 0;
1835 panfrost_set_constant_buffer(
1836 struct pipe_context
*pctx
,
1837 enum pipe_shader_type shader
, uint index
,
1838 const struct pipe_constant_buffer
*buf
)
1840 struct panfrost_context
*ctx
= pan_context(pctx
);
1841 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1843 size_t sz
= buf
? buf
->buffer_size
: 0;
1845 /* Free previous buffer */
1852 pbuf
->buffer
= NULL
;
1855 /* If unbinding, we're done */
1860 /* Multiple constant buffers not yet supported */
1865 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1868 cpu
= rsrc
->bo
->cpu
[0];
1869 } else if (buf
->user_buffer
) {
1870 cpu
= buf
->user_buffer
;
1872 DBG("No constant buffer?\n");
1876 /* Copy the constant buffer into the driver context for later upload */
1878 pbuf
->buffer
= malloc(sz
);
1879 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1883 panfrost_set_stencil_ref(
1884 struct pipe_context
*pctx
,
1885 const struct pipe_stencil_ref
*ref
)
1887 struct panfrost_context
*ctx
= pan_context(pctx
);
1888 ctx
->stencil_ref
= *ref
;
1890 /* Shader core dirty */
1891 ctx
->dirty
|= PAN_DIRTY_FS
;
1894 static struct pipe_sampler_view
*
1895 panfrost_create_sampler_view(
1896 struct pipe_context
*pctx
,
1897 struct pipe_resource
*texture
,
1898 const struct pipe_sampler_view
*template)
1900 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1901 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1903 pipe_reference(NULL
, &texture
->reference
);
1905 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1907 so
->base
= *template;
1908 so
->base
.texture
= texture
;
1909 so
->base
.reference
.count
= 1;
1910 so
->base
.context
= pctx
;
1912 /* sampler_views correspond to texture descriptors, minus the texture
1913 * (data) itself. So, we serialise the descriptor here and cache it for
1916 /* TODO: Other types of textures */
1917 assert(template->target
== PIPE_TEXTURE_2D
);
1919 /* Make sure it's something with which we're familiar */
1920 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1922 /* TODO: Detect from format better */
1923 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1925 unsigned char user_swizzle
[4] = {
1926 template->swizzle_r
,
1927 template->swizzle_g
,
1928 template->swizzle_b
,
1932 enum mali_format format
= panfrost_find_format(desc
);
1934 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
1936 unsigned usage2_layout
= 0x10;
1938 switch (prsrc
->bo
->layout
) {
1940 usage2_layout
|= 0x8 | 0x4;
1943 usage2_layout
|= 0x1;
1946 usage2_layout
|= is_depth
? 0x1 : 0x2;
1953 struct mali_texture_descriptor texture_descriptor
= {
1954 .width
= MALI_POSITIVE(texture
->width0
),
1955 .height
= MALI_POSITIVE(texture
->height0
),
1956 .depth
= MALI_POSITIVE(texture
->depth0
),
1960 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
1964 .is_not_cubemap
= 1,
1966 .usage2
= usage2_layout
1969 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
1972 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
1973 assert (template->u
.tex
.first_level
== 0);
1975 texture_descriptor
.nr_mipmap_levels
= template->u
.tex
.last_level
- template->u
.tex
.first_level
;
1977 so
->hw
= texture_descriptor
;
1979 return (struct pipe_sampler_view
*) so
;
1983 panfrost_set_sampler_views(
1984 struct pipe_context
*pctx
,
1985 enum pipe_shader_type shader
,
1986 unsigned start_slot
, unsigned num_views
,
1987 struct pipe_sampler_view
**views
)
1989 struct panfrost_context
*ctx
= pan_context(pctx
);
1991 assert(start_slot
== 0);
1993 ctx
->sampler_view_count
[shader
] = num_views
;
1994 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
1996 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2000 panfrost_sampler_view_destroy(
2001 struct pipe_context
*pctx
,
2002 struct pipe_sampler_view
*views
)
2004 //struct panfrost_context *ctx = pan_context(pctx);
2012 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2013 const struct pipe_framebuffer_state
*fb
)
2015 struct panfrost_context
*ctx
= pan_context(pctx
);
2017 /* Flush when switching away from an FBO */
2019 if (!panfrost_is_scanout(ctx
)) {
2020 panfrost_flush(pctx
, NULL
, 0);
2023 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2024 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2025 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2026 ctx
->pipe_framebuffer
.width
= fb
->width
;
2027 ctx
->pipe_framebuffer
.height
= fb
->height
;
2029 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2030 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2032 /* check if changing cbuf */
2033 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2035 if (cb
&& (i
!= 0)) {
2036 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2041 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2046 if (ctx
->require_sfbd
)
2047 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2049 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2051 panfrost_attach_vt_framebuffer(ctx
);
2053 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2054 bool is_scanout
= panfrost_is_scanout(ctx
);
2056 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
) {
2057 /* The blob is aggressive about enabling AFBC. As such,
2058 * it's pretty much necessary to use it here, since we
2059 * have no traces of non-compressed FBO. */
2061 panfrost_enable_afbc(ctx
, tex
, false);
2064 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2065 /* Enable transaction elimination if we can */
2066 panfrost_enable_checksum(ctx
, tex
);
2071 struct pipe_surface
*zb
= fb
->zsbuf
;
2073 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2074 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2079 if (ctx
->require_sfbd
)
2080 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2082 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2084 panfrost_attach_vt_framebuffer(ctx
);
2086 /* Keep the depth FBO linear */
2093 panfrost_create_blend_state(struct pipe_context
*pipe
,
2094 const struct pipe_blend_state
*blend
)
2096 struct panfrost_context
*ctx
= pan_context(pipe
);
2097 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2100 /* TODO: The following features are not yet implemented */
2101 assert(!blend
->logicop_enable
);
2102 assert(!blend
->alpha_to_coverage
);
2103 assert(!blend
->alpha_to_one
);
2105 /* Compile the blend state, first as fixed-function if we can */
2107 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], &so
->equation
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2110 /* If we can't, compile a blend shader instead */
2112 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2118 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2121 struct panfrost_context
*ctx
= pan_context(pipe
);
2122 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2123 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2124 ctx
->blend
= pblend
;
2129 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2131 /* TODO: Attach color */
2133 /* Shader itself is not dirty, but the shader core is */
2134 ctx
->dirty
|= PAN_DIRTY_FS
;
2138 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2141 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2143 if (so
->has_blend_shader
) {
2144 DBG("Deleting blend state leak blend shaders bytecode\n");
2151 panfrost_set_blend_color(struct pipe_context
*pipe
,
2152 const struct pipe_blend_color
*blend_color
)
2154 struct panfrost_context
*ctx
= pan_context(pipe
);
2156 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2159 ctx
->blend_color
= *blend_color
;
2161 /* The blend mode depends on the blend constant color, due to the
2162 * fixed/programmable split. So, we're forced to regenerate the blend
2165 /* TODO: Attach color */
2170 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2171 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2173 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2177 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2180 struct panfrost_context
*ctx
= pan_context(pipe
);
2181 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2182 ctx
->depth_stencil
= depth_stencil
;
2187 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2188 * emulated in the fragment shader */
2190 if (depth_stencil
->alpha
.enabled
) {
2191 /* We need to trigger a new shader (maybe) */
2192 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2196 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2198 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2199 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2201 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2202 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2204 /* Depth state (TODO: Refactor) */
2205 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2207 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2209 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2210 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2212 /* Bounds test not implemented */
2213 assert(!depth_stencil
->depth
.bounds_test
);
2215 ctx
->dirty
|= PAN_DIRTY_FS
;
2219 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2225 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2226 unsigned sample_mask
)
2231 panfrost_set_clip_state(struct pipe_context
*pipe
,
2232 const struct pipe_clip_state
*clip
)
2234 //struct panfrost_context *panfrost = pan_context(pipe);
2238 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2239 unsigned start_slot
,
2240 unsigned num_viewports
,
2241 const struct pipe_viewport_state
*viewports
)
2243 struct panfrost_context
*ctx
= pan_context(pipe
);
2245 assert(start_slot
== 0);
2246 assert(num_viewports
== 1);
2248 ctx
->pipe_viewport
= *viewports
;
2251 /* TODO: What if not centered? */
2252 float w
= abs(viewports
->scale
[0]) * 2.0;
2253 float h
= abs(viewports
->scale
[1]) * 2.0;
2255 ctx
->viewport
.viewport1
[0] = MALI_POSITIVE((int) w
);
2256 ctx
->viewport
.viewport1
[1] = MALI_POSITIVE((int) h
);
2261 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2262 unsigned start_slot
,
2263 unsigned num_scissors
,
2264 const struct pipe_scissor_state
*scissors
)
2266 struct panfrost_context
*ctx
= pan_context(pipe
);
2268 assert(start_slot
== 0);
2269 assert(num_scissors
== 1);
2271 ctx
->scissor
= *scissors
;
2275 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2276 const struct pipe_poly_stipple
*stipple
)
2278 //struct panfrost_context *panfrost = pan_context(pipe);
2282 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2285 //struct panfrost_context *panfrost = pan_context(pipe);
2289 panfrost_destroy(struct pipe_context
*pipe
)
2291 struct panfrost_context
*panfrost
= pan_context(pipe
);
2292 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2294 if (panfrost
->blitter
)
2295 util_blitter_destroy(panfrost
->blitter
);
2297 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2298 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2299 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2300 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2301 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2304 static struct pipe_query
*
2305 panfrost_create_query(struct pipe_context
*pipe
,
2309 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2314 return (struct pipe_query
*) q
;
2318 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2324 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2326 struct panfrost_context
*ctx
= pan_context(pipe
);
2327 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2329 switch (query
->type
) {
2330 case PIPE_QUERY_OCCLUSION_COUNTER
:
2331 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2332 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2334 /* Allocate a word for the query results to be stored */
2335 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2337 ctx
->occlusion_query
= query
;
2343 DBG("Skipping query %d\n", query
->type
);
2351 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2353 struct panfrost_context
*ctx
= pan_context(pipe
);
2354 ctx
->occlusion_query
= NULL
;
2359 panfrost_get_query_result(struct pipe_context
*pipe
,
2360 struct pipe_query
*q
,
2362 union pipe_query_result
*vresult
)
2365 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2367 /* We need to flush out the jobs to actually run the counter, TODO
2368 * check wait, TODO wallpaper after if needed */
2370 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2372 switch (query
->type
) {
2373 case PIPE_QUERY_OCCLUSION_COUNTER
:
2374 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2375 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2376 /* Read back the query results */
2377 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2378 unsigned passed
= *result
;
2380 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2381 vresult
->u64
= passed
;
2383 vresult
->b
= !!passed
;
2389 DBG("Skipped query get %d\n", query
->type
);
2397 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2399 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2400 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2402 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2403 /* Allocate the beginning of the transient pool */
2404 int entry_size
= (1 << 22); /* 4MB */
2406 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2407 ctx
->transient_pools
[i
].entry_count
= 1;
2409 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2412 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2413 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2414 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2415 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2416 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2420 /* New context creation, which also does hardware initialisation since I don't
2421 * know the better way to structure this :smirk: */
2423 struct pipe_context
*
2424 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2426 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2427 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2428 memset(ctx
, 0, sizeof(*ctx
));
2429 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2432 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2434 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2435 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2437 gallium
->screen
= screen
;
2439 gallium
->destroy
= panfrost_destroy
;
2441 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2443 gallium
->flush
= panfrost_flush
;
2444 gallium
->clear
= panfrost_clear
;
2445 gallium
->draw_vbo
= panfrost_draw_vbo
;
2447 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2448 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2450 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2452 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2453 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2454 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2456 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2457 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2458 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2460 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2461 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2462 gallium
->delete_vertex_elements_state
= panfrost_delete_vertex_elements_state
;
2464 gallium
->create_fs_state
= panfrost_create_shader_state
;
2465 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2466 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2468 gallium
->create_vs_state
= panfrost_create_shader_state
;
2469 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2470 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2472 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2473 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2474 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2476 gallium
->create_blend_state
= panfrost_create_blend_state
;
2477 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2478 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2480 gallium
->set_blend_color
= panfrost_set_blend_color
;
2482 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2483 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2484 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2486 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2488 gallium
->set_clip_state
= panfrost_set_clip_state
;
2489 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2490 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2491 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2492 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2494 gallium
->create_query
= panfrost_create_query
;
2495 gallium
->destroy_query
= panfrost_destroy_query
;
2496 gallium
->begin_query
= panfrost_begin_query
;
2497 gallium
->end_query
= panfrost_end_query
;
2498 gallium
->get_query_result
= panfrost_get_query_result
;
2500 panfrost_resource_context_init(gallium
);
2502 pscreen
->driver
->init_context(ctx
);
2504 panfrost_setup_hardware(ctx
);
2507 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2508 gallium
->const_uploader
= gallium
->stream_uploader
;
2509 assert(gallium
->stream_uploader
);
2511 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2512 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2514 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2516 ctx
->blitter
= util_blitter_create(gallium
);
2517 assert(ctx
->blitter
);
2519 /* Prepare for render! */
2521 panfrost_job_init(ctx
);
2522 panfrost_emit_vertex_payload(ctx
);
2523 panfrost_emit_tiler_payload(ctx
);
2524 panfrost_invalidate_frame(ctx
);
2525 panfrost_default_shader_backend(ctx
);
2526 panfrost_generate_space_filler_indices();