2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_format.h"
31 #include "util/macros.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_memory.h"
36 #include "util/u_vbuf.h"
37 #include "util/half_float.h"
38 #include "util/u_helpers.h"
39 #include "util/u_format.h"
40 #include "indices/u_primconvert.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "util/u_math.h"
44 #include "pan_screen.h"
45 #include "pan_blending.h"
46 #include "pan_blend_shaders.h"
48 #include "pan_tiler.h"
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
53 static enum mali_job_type
54 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
57 case PIPE_SHADER_VERTEX
:
58 return JOB_TYPE_VERTEX
;
60 case PIPE_SHADER_FRAGMENT
:
61 /* Note: JOB_TYPE_FRAGMENT is different.
62 * JOB_TYPE_FRAGMENT actually executes the
63 * fragment shader, but JOB_TYPE_TILER is how you
65 return JOB_TYPE_TILER
;
67 case PIPE_SHADER_GEOMETRY
:
68 return JOB_TYPE_GEOMETRY
;
70 case PIPE_SHADER_COMPUTE
:
71 return JOB_TYPE_COMPUTE
;
74 unreachable("Unsupported shader stage");
79 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
81 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
82 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
83 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
84 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
86 /* 8 byte checksum per tile */
87 rsrc
->bo
->checksum_stride
= tile_w
* 8;
88 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
89 panfrost_drm_allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
91 rsrc
->bo
->has_checksum
= true;
94 /* Framebuffer descriptor */
97 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
99 fb
->width
= MALI_POSITIVE(w
);
100 fb
->height
= MALI_POSITIVE(h
);
102 /* No idea why this is needed, but it's how resolution_check is
103 * calculated. It's not clear to us yet why the hardware wants this.
104 * The formula itself was discovered mostly by manual bruteforce and
105 * aggressive algebraic simplification. */
107 fb
->tiler_resolution_check
= ((w
+ h
) / 3) << 4;
110 struct mali_single_framebuffer
111 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
113 struct mali_single_framebuffer framebuffer
= {
115 .format
= 0x30000000,
116 .clear_flags
= 0x1000,
117 .unknown_address_0
= ctx
->scratchpad
.gpu
,
118 .tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
,
119 .tiler_polygon_list_body
= ctx
->tiler_polygon_list
.gpu
+ 40960,
120 .tiler_hierarchy_mask
= 0xF0,
122 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
123 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
126 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
131 struct bifrost_framebuffer
132 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
134 unsigned width
= ctx
->pipe_framebuffer
.width
;
135 unsigned height
= ctx
->pipe_framebuffer
.height
;
137 struct bifrost_framebuffer framebuffer
= {
138 .width1
= MALI_POSITIVE(width
),
139 .height1
= MALI_POSITIVE(height
),
140 .width2
= MALI_POSITIVE(width
),
141 .height2
= MALI_POSITIVE(height
),
146 .rt_count_1
= MALI_POSITIVE(1),
151 .scratchpad
= ctx
->scratchpad
.gpu
,
154 framebuffer
.tiler_hierarchy_mask
=
155 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
157 /* Compute the polygon header size and use that to offset the body */
159 unsigned header_size
= panfrost_tiler_header_size(
160 width
, height
, framebuffer
.tiler_hierarchy_mask
);
162 unsigned body_size
= panfrost_tiler_body_size(
163 width
, height
, framebuffer
.tiler_hierarchy_mask
);
167 unsigned total_size
= header_size
+ body_size
;
169 if (framebuffer
.tiler_hierarchy_mask
) {
170 assert(ctx
->tiler_polygon_list
.size
>= total_size
);
172 /* Specify allocated tiler structures */
173 framebuffer
.tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
;
175 /* Allow the entire tiler heap */
176 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
177 framebuffer
.tiler_heap_end
=
178 ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
;
180 /* The tiler is disabled, so don't allow the tiler heap */
181 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
182 framebuffer
.tiler_heap_end
= framebuffer
.tiler_heap_start
;
184 /* Use a dummy polygon list */
185 framebuffer
.tiler_polygon_list
= ctx
->tiler_dummy
.gpu
;
187 /* Also, set a "tiler disabled?" flag? */
188 framebuffer
.tiler_hierarchy_mask
|= 0x1000;
191 framebuffer
.tiler_polygon_list_body
=
192 framebuffer
.tiler_polygon_list
+ header_size
;
194 framebuffer
.tiler_polygon_list_size
=
195 header_size
+ body_size
;
202 /* Are we currently rendering to the screen (rather than an FBO)? */
205 panfrost_is_scanout(struct panfrost_context
*ctx
)
207 /* If there is no color buffer, it's an FBO */
208 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
211 /* If we're too early that no framebuffer was sent, it's scanout */
212 if (!ctx
->pipe_framebuffer
.cbufs
[0])
215 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
216 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
217 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
222 struct pipe_context
*pipe
,
224 const union pipe_color_union
*color
,
225 double depth
, unsigned stencil
)
227 struct panfrost_context
*ctx
= pan_context(pipe
);
228 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
230 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
234 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
236 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
240 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
242 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
246 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
248 mali_ptr framebuffer
= ctx
->require_sfbd
?
249 panfrost_attach_vt_sfbd(ctx
) :
250 panfrost_attach_vt_mfbd(ctx
);
252 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
253 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
256 /* Reset per-frame context, called on context initialisation as well as after
257 * flushing a frame */
260 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
262 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
263 DBG("Uploaded transient %d bytes\n", transient_count
);
265 /* Rotate cmdstream */
266 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
267 ctx
->cmdstream_i
= 0;
269 if (ctx
->require_sfbd
)
270 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
272 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
274 /* Reset varyings allocated */
275 ctx
->varying_height
= 0;
277 /* The transient cmdstream is dirty every frame; the only bits worth preserving
278 * (textures, shaders, etc) are in other buffers anyways */
280 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
281 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
283 /* Regenerate payloads */
284 panfrost_attach_vt_framebuffer(ctx
);
287 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
290 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
293 /* In practice, every field of these payloads should be configurable
294 * arbitrarily, which means these functions are basically catch-all's for
295 * as-of-yet unwavering unknowns */
298 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
300 struct midgard_payload_vertex_tiler payload
= {
302 .workgroups_z_shift
= 32,
303 .workgroups_x_shift_2
= 0x2,
304 .workgroups_x_shift_3
= 0x5,
306 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
309 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
313 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
315 struct midgard_payload_vertex_tiler payload
= {
317 .workgroups_z_shift
= 32,
318 .workgroups_x_shift_2
= 0x2,
319 .workgroups_x_shift_3
= 0x6,
321 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
325 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
329 translate_tex_wrap(enum pipe_tex_wrap w
)
332 case PIPE_TEX_WRAP_REPEAT
:
333 return MALI_WRAP_REPEAT
;
335 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
336 return MALI_WRAP_CLAMP_TO_EDGE
;
338 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
339 return MALI_WRAP_CLAMP_TO_BORDER
;
341 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
342 return MALI_WRAP_MIRRORED_REPEAT
;
345 unreachable("Invalid wrap");
350 translate_tex_filter(enum pipe_tex_filter f
)
353 case PIPE_TEX_FILTER_NEAREST
:
356 case PIPE_TEX_FILTER_LINEAR
:
360 unreachable("Invalid filter");
365 translate_mip_filter(enum pipe_tex_mipfilter f
)
367 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
371 panfrost_translate_compare_func(enum pipe_compare_func in
)
374 case PIPE_FUNC_NEVER
:
375 return MALI_FUNC_NEVER
;
378 return MALI_FUNC_LESS
;
380 case PIPE_FUNC_EQUAL
:
381 return MALI_FUNC_EQUAL
;
383 case PIPE_FUNC_LEQUAL
:
384 return MALI_FUNC_LEQUAL
;
386 case PIPE_FUNC_GREATER
:
387 return MALI_FUNC_GREATER
;
389 case PIPE_FUNC_NOTEQUAL
:
390 return MALI_FUNC_NOTEQUAL
;
392 case PIPE_FUNC_GEQUAL
:
393 return MALI_FUNC_GEQUAL
;
395 case PIPE_FUNC_ALWAYS
:
396 return MALI_FUNC_ALWAYS
;
399 unreachable("Invalid func");
404 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
407 case PIPE_FUNC_NEVER
:
408 return MALI_ALT_FUNC_NEVER
;
411 return MALI_ALT_FUNC_LESS
;
413 case PIPE_FUNC_EQUAL
:
414 return MALI_ALT_FUNC_EQUAL
;
416 case PIPE_FUNC_LEQUAL
:
417 return MALI_ALT_FUNC_LEQUAL
;
419 case PIPE_FUNC_GREATER
:
420 return MALI_ALT_FUNC_GREATER
;
422 case PIPE_FUNC_NOTEQUAL
:
423 return MALI_ALT_FUNC_NOTEQUAL
;
425 case PIPE_FUNC_GEQUAL
:
426 return MALI_ALT_FUNC_GEQUAL
;
428 case PIPE_FUNC_ALWAYS
:
429 return MALI_ALT_FUNC_ALWAYS
;
432 unreachable("Invalid alt func");
437 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
440 case PIPE_STENCIL_OP_KEEP
:
441 return MALI_STENCIL_KEEP
;
443 case PIPE_STENCIL_OP_ZERO
:
444 return MALI_STENCIL_ZERO
;
446 case PIPE_STENCIL_OP_REPLACE
:
447 return MALI_STENCIL_REPLACE
;
449 case PIPE_STENCIL_OP_INCR
:
450 return MALI_STENCIL_INCR
;
452 case PIPE_STENCIL_OP_DECR
:
453 return MALI_STENCIL_DECR
;
455 case PIPE_STENCIL_OP_INCR_WRAP
:
456 return MALI_STENCIL_INCR_WRAP
;
458 case PIPE_STENCIL_OP_DECR_WRAP
:
459 return MALI_STENCIL_DECR_WRAP
;
461 case PIPE_STENCIL_OP_INVERT
:
462 return MALI_STENCIL_INVERT
;
465 unreachable("Invalid stencil op");
470 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
472 out
->ref
= 0; /* Gallium gets it from elsewhere */
474 out
->mask
= in
->valuemask
;
475 out
->func
= panfrost_translate_compare_func(in
->func
);
476 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
477 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
478 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
482 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
484 struct mali_shader_meta shader
= {
485 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
487 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
488 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
492 shader
.unknown2_4
|= 0x10;
495 struct pipe_stencil_state default_stencil
= {
497 .func
= PIPE_FUNC_ALWAYS
,
498 .fail_op
= MALI_STENCIL_KEEP
,
499 .zfail_op
= MALI_STENCIL_KEEP
,
500 .zpass_op
= MALI_STENCIL_KEEP
,
505 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
506 shader
.stencil_mask_front
= default_stencil
.writemask
;
508 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
509 shader
.stencil_mask_back
= default_stencil
.writemask
;
511 if (default_stencil
.enabled
)
512 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
514 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
517 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
518 * graphics command stream. It should be called once per draw, accordding to
519 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
520 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
523 struct panfrost_transfer
524 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
526 struct mali_job_descriptor_header job
= {
527 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
529 .job_descriptor_size
= 1,
533 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
535 /* There's some padding hacks on 32-bit */
542 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
544 memcpy(transfer
.cpu
, &job
, sizeof(job
));
545 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
550 panfrost_emit_varyings(
551 struct panfrost_context
*ctx
,
552 union mali_attr
*slot
,
556 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
558 /* Fill out the descriptor */
559 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
560 slot
->stride
= stride
;
561 slot
->size
= stride
* count
;
563 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
564 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
566 return varying_address
;
570 panfrost_emit_point_coord(union mali_attr
*slot
)
572 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
573 slot
->stride
= slot
->size
= 0;
577 panfrost_emit_varying_descriptor(
578 struct panfrost_context
*ctx
,
579 unsigned invocation_count
)
581 /* Load the shaders */
583 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
584 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
585 unsigned int num_gen_varyings
= 0;
587 /* Allocate the varying descriptor */
589 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
590 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
592 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
596 * Assign ->src_offset now that we know about all the general purpose
597 * varyings that will be used by the fragment and vertex shaders.
599 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
601 * General purpose varyings have ->index set to 0, skip other
604 if (vs
->varyings
[i
].index
)
607 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
610 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
613 /* If we have a point sprite replacement, handle that here. We
614 * have to translate location first. TODO: Flip y in shader.
615 * We're already keying ... just time crunch .. */
617 unsigned loc
= fs
->varyings_loc
[i
];
619 (loc
>= VARYING_SLOT_VAR0
) ? (loc
- VARYING_SLOT_VAR0
) :
620 (loc
== VARYING_SLOT_PNTC
) ? 8 :
623 if (~pnt_loc
&& fs
->point_sprite_mask
& (1 << pnt_loc
)) {
624 /* gl_PointCoord index by convention */
625 fs
->varyings
[i
].index
= 3;
626 fs
->reads_point_coord
= true;
628 /* Swizzle out the z/w to 0/1 */
629 fs
->varyings
[i
].format
= MALI_RG16F
;
630 fs
->varyings
[i
].swizzle
=
631 panfrost_get_default_swizzle(2);
636 if (fs
->varyings
[i
].index
)
640 * Re-use the VS general purpose varying pos if it exists,
641 * create a new one otherwise.
643 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
644 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
648 if (j
< vs
->tripipe
->varying_count
)
649 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
651 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
654 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
655 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
657 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
658 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
660 /* Buffer indices must be in this order per our convention */
661 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
664 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
667 /* fp32 vec4 gl_Position */
668 ctx
->payload_tiler
.postfix
.position_varying
=
669 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
670 sizeof(float) * 4, invocation_count
);
673 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
674 /* fp16 vec1 gl_PointSize */
675 ctx
->payload_tiler
.primitive_size
.pointer
=
676 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
677 2, invocation_count
);
680 if (fs
->reads_point_coord
) {
681 /* Special descriptor */
682 panfrost_emit_point_coord(&varyings
[idx
++]);
685 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
686 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
687 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
691 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
693 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
694 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
696 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
699 /* Emits attributes and varying descriptors, which should be called every draw,
700 * excepting some obscure circumstances */
703 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
705 /* Staged mali_attr, and index into them. i =/= k, depending on the
706 * vertex buffer mask */
707 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
710 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
712 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
713 if (!(ctx
->vb_mask
& (1 << i
))) continue;
715 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
716 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
720 /* Align to 64 bytes by masking off the lower bits. This
721 * will be adjusted back when we fixup the src_offset in
724 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
726 /* Offset vertex count by draw_start to make sure we upload enough */
727 attrs
[k
].stride
= buf
->stride
;
728 attrs
[k
].size
= rsrc
->base
.width0
;
730 panfrost_job_add_bo(job
, rsrc
->bo
);
731 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
736 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
738 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
742 panfrost_writes_point_size(struct panfrost_context
*ctx
)
745 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
747 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
750 /* Stage the attribute descriptors so we can adjust src_offset
751 * to let BOs align nicely */
754 panfrost_stage_attributes(struct panfrost_context
*ctx
)
756 struct panfrost_vertex_state
*so
= ctx
->vertex
;
758 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
759 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
760 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
762 /* Copy as-is for the first pass */
763 memcpy(target
, so
->hw
, sz
);
765 /* Fixup offsets for the second pass. Recall that the hardware
766 * calculates attribute addresses as:
768 * addr = base + (stride * vtx) + src_offset;
770 * However, on Mali, base must be aligned to 64-bytes, so we
773 * base' = base & ~63 = base - (base & 63)
775 * To compensate when using base' (see emit_vertex_data), we have
776 * to adjust src_offset by the masked off piece:
778 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
779 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
780 * = base + (stride * vtx) + src_offset
786 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
787 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
788 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
790 /* Adjust by the masked off bits of the offset */
791 target
[i
].src_offset
+= (addr
& 63);
794 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
798 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
800 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
802 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
805 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
806 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
808 struct panfrost_transfer transfer
=
809 panfrost_allocate_transient(ctx
, transfer_size
);
811 struct mali_sampler_descriptor
*desc
=
812 (struct mali_sampler_descriptor
*) transfer
.cpu
;
814 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
815 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
817 upload
= transfer
.gpu
;
820 if (t
== PIPE_SHADER_FRAGMENT
)
821 ctx
->payload_tiler
.postfix
.sampler_descriptor
= upload
;
822 else if (t
== PIPE_SHADER_VERTEX
)
823 ctx
->payload_vertex
.postfix
.sampler_descriptor
= upload
;
829 /* Computes the address to a texture at a particular slice */
832 panfrost_get_texture_address(
833 struct panfrost_resource
*rsrc
,
834 unsigned level
, unsigned face
)
836 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
837 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
839 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
845 struct panfrost_context
*ctx
,
846 struct panfrost_sampler_view
*view
)
849 return (mali_ptr
) NULL
;
851 struct pipe_sampler_view
*pview
= &view
->base
;
852 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
854 /* Do we interleave an explicit stride with every element? */
856 bool has_manual_stride
=
857 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
859 /* For easy access */
861 assert(pview
->target
!= PIPE_BUFFER
);
862 unsigned first_level
= pview
->u
.tex
.first_level
;
863 unsigned last_level
= pview
->u
.tex
.last_level
;
865 /* Inject the addresses in, interleaving mip levels, cube faces, and
866 * strides in that order */
870 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
871 for (unsigned f
= 0; f
< pview
->texture
->array_size
; ++f
) {
872 view
->hw
.payload
[idx
++] =
873 panfrost_get_texture_address(rsrc
, l
, f
);
875 if (has_manual_stride
) {
876 view
->hw
.payload
[idx
++] =
877 rsrc
->bo
->slices
[l
].stride
;
882 return panfrost_upload_transient(ctx
, &view
->hw
,
883 sizeof(struct mali_texture_descriptor
));
887 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
889 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
890 mali_ptr trampoline
= 0;
892 if (ctx
->sampler_view_count
[t
]) {
893 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
895 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
897 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
899 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
902 if (t
== PIPE_SHADER_FRAGMENT
)
903 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
904 else if (t
== PIPE_SHADER_VERTEX
)
905 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
911 struct sysval_uniform
{
919 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
920 struct sysval_uniform
*uniform
)
922 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
924 uniform
->f
[0] = vp
->scale
[0];
925 uniform
->f
[1] = vp
->scale
[1];
926 uniform
->f
[2] = vp
->scale
[2];
929 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
930 struct sysval_uniform
*uniform
)
932 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
934 uniform
->f
[0] = vp
->translate
[0];
935 uniform
->f
[1] = vp
->translate
[1];
936 uniform
->f
[2] = vp
->translate
[2];
939 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
940 enum pipe_shader_type st
,
941 unsigned int sysvalid
,
942 struct sysval_uniform
*uniform
)
944 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
945 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
946 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
947 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
950 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
953 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
954 tex
->u
.tex
.first_level
);
957 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
958 tex
->u
.tex
.first_level
);
961 uniform
->i
[dim
] = tex
->texture
->array_size
;
964 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
965 struct panfrost_shader_state
*ss
,
966 enum pipe_shader_type st
)
968 struct sysval_uniform
*uniforms
= (void *)buf
;
970 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
971 int sysval
= ss
->sysval
[i
];
973 switch (PAN_SYSVAL_TYPE(sysval
)) {
974 case PAN_SYSVAL_VIEWPORT_SCALE
:
975 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
977 case PAN_SYSVAL_VIEWPORT_OFFSET
:
978 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
980 case PAN_SYSVAL_TEXTURE_SIZE
:
981 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
991 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
993 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
994 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
997 return rsrc
->bo
->cpu
;
998 else if (cb
->user_buffer
)
999 return cb
->user_buffer
;
1001 unreachable("No constant buffer");
1005 panfrost_map_constant_buffer_gpu(
1006 struct panfrost_context
*ctx
,
1007 struct panfrost_constant_buffer
*buf
,
1010 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
1011 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
1014 return rsrc
->bo
->gpu
;
1015 else if (cb
->user_buffer
)
1016 return panfrost_upload_transient(ctx
, cb
->user_buffer
, cb
->buffer_size
);
1018 unreachable("No constant buffer");
1021 /* Compute number of UBOs active (more specifically, compute the highest UBO
1022 * number addressable -- if there are gaps, include them in the count anyway).
1023 * We always include UBO #0 in the count, since we *need* uniforms enabled for
1027 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
1029 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
1030 return 32 - __builtin_clz(mask
);
1033 /* Fixes up a shader state with current state, returning a GPU address to the
1037 panfrost_patch_shader_state(
1038 struct panfrost_context
*ctx
,
1039 struct panfrost_shader_state
*ss
,
1040 enum pipe_shader_type stage
)
1042 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
1043 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
1045 ss
->tripipe
->midgard1
.flags
= 0x220;
1047 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
1048 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
1050 return ss
->tripipe_gpu
;
1053 /* Go through dirty flags and actualise them in the cmdstream. */
1056 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1058 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1060 if (with_vertex_data
) {
1061 panfrost_emit_vertex_data(ctx
, job
);
1064 bool msaa
= ctx
->rasterizer
->base
.multisample
;
1066 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1067 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1069 /* TODO: Sample size */
1070 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1071 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1074 panfrost_job_set_requirements(ctx
, job
);
1076 if (ctx
->occlusion_query
) {
1077 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1078 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1081 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1084 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1086 ctx
->payload_vertex
.postfix
._shader_upper
=
1087 panfrost_patch_shader_state(ctx
, vs
, PIPE_SHADER_VERTEX
) >> 4;
1090 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1091 /* Check if we need to link the gl_PointSize varying */
1092 if (!panfrost_writes_point_size(ctx
)) {
1093 /* If the size is constant, write it out. Otherwise,
1094 * don't touch primitive_size (since we would clobber
1095 * the pointer there) */
1097 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1101 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1103 ctx
->dirty
|= PAN_DIRTY_FS
;
1105 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1107 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1109 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
);
1111 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1114 COPY(attribute_count
);
1115 COPY(varying_count
);
1116 COPY(texture_count
);
1117 COPY(sampler_count
);
1118 COPY(sampler_count
);
1119 COPY(midgard1
.uniform_count
);
1120 COPY(midgard1
.uniform_buffer_count
);
1121 COPY(midgard1
.work_count
);
1122 COPY(midgard1
.flags
);
1123 COPY(midgard1
.unknown2
);
1126 /* If there is a blend shader, work registers are shared */
1128 if (ctx
->blend
->has_blend_shader
)
1129 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1131 /* Set late due to depending on render state */
1132 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
1134 /* Depending on whether it's legal to in the given shader, we
1135 * try to enable early-z testing (or forward-pixel kill?) */
1137 if (!variant
->can_discard
)
1138 flags
|= MALI_EARLY_Z
;
1140 /* Any time texturing is used, derivatives are implicitly
1141 * calculated, so we need to enable helper invocations */
1143 if (ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
])
1144 flags
|= MALI_HELPER_INVOCATIONS
;
1146 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
1148 /* Assign the stencil refs late */
1149 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1150 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1152 /* CAN_DISCARD should be set if the fragment shader possibly
1153 * contains a 'discard' instruction. It is likely this is
1154 * related to optimizations related to forward-pixel kill, as
1155 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1156 * thing?" by Peter Harris
1159 if (variant
->can_discard
) {
1160 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1161 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1164 /* Check if we're using the default blend descriptor (fast path) */
1167 !ctx
->blend
->has_blend_shader
&&
1168 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1169 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1170 (ctx
->blend
->equation
.color_mask
== 0xf);
1172 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1173 * *also* copied to the blend_meta appended (by convention),
1174 * but this is the field actually read by the hardware. (Or
1175 * maybe both are read...?) */
1177 if (ctx
->blend
->has_blend_shader
) {
1178 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1180 ctx
->fragment_shader_core
.blend
.shader
= 0;
1183 if (ctx
->require_sfbd
) {
1184 /* When only a single render target platform is used, the blend
1185 * information is inside the shader meta itself. We
1186 * additionally need to signal CAN_DISCARD for nontrivial blend
1187 * modes (so we're able to read back the destination buffer) */
1189 if (!ctx
->blend
->has_blend_shader
) {
1190 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1191 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1195 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1199 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1200 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1201 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1203 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1205 if (!ctx
->require_sfbd
) {
1206 /* Additional blend descriptor tacked on for jobs using MFBD */
1208 unsigned blend_count
= 0x200;
1210 if (ctx
->blend
->has_blend_shader
) {
1211 /* For a blend shader, the bottom nibble corresponds to
1212 * the number of work registers used, which signals the
1213 * -existence- of a blend shader */
1215 assert(ctx
->blend
->blend_work_count
>= 2);
1216 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1218 /* Otherwise, the bottom bit simply specifies if
1219 * blending (anything other than REPLACE) is enabled */
1226 struct midgard_blend_rt rts
[4];
1230 for (unsigned i
= 0; i
< 1; ++i
) {
1232 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1233 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1235 rts
[i
].flags
= blend_count
;
1238 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1240 /* TODO: sRGB in blend shaders is currently
1241 * unimplemented. Contact me (Alyssa) if you're
1242 * interested in working on this. We have
1243 * native Midgard ops for helping here, but
1244 * they're not well-understood yet. */
1246 assert(!(is_srgb
&& ctx
->blend
->has_blend_shader
));
1248 if (ctx
->blend
->has_blend_shader
) {
1249 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1251 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1252 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1256 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1260 /* We stage to transient, so always dirty.. */
1261 panfrost_stage_attributes(ctx
);
1263 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1264 panfrost_upload_sampler_descriptors(ctx
);
1266 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1267 panfrost_upload_texture_descriptors(ctx
);
1269 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1271 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1272 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1274 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1275 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1276 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1278 /* Uniforms are implicitly UBO #0 */
1279 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1281 /* Allocate room for the sysval and the uniforms */
1282 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1283 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1284 size_t size
= sys_size
+ uniform_size
;
1285 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1287 /* Upload sysvals requested by the shader */
1288 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1290 /* Upload uniforms */
1292 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1293 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1296 int uniform_count
= 0;
1298 struct mali_vertex_tiler_postfix
*postfix
;
1301 case PIPE_SHADER_VERTEX
:
1302 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1303 postfix
= &ctx
->payload_vertex
.postfix
;
1306 case PIPE_SHADER_FRAGMENT
:
1307 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1308 postfix
= &ctx
->payload_tiler
.postfix
;
1312 unreachable("Invalid shader stage\n");
1315 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1318 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1319 assert(ubo_count
>= 1);
1321 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1322 struct mali_uniform_buffer_meta
*ubos
= calloc(sz
, 1);
1324 /* Upload uniforms as a UBO */
1325 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1326 ubos
[0].ptr
= transfer
.gpu
>> 2;
1328 /* The rest are honest-to-goodness UBOs */
1330 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1331 size_t sz
= buf
->cb
[ubo
].buffer_size
;
1333 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1334 bool empty
= sz
== 0;
1336 if (!enabled
|| empty
) {
1337 /* Stub out disabled UBOs to catch accesses */
1340 ubos
[ubo
].ptr
= 0xDEAD0000;
1344 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1346 unsigned bytes_per_field
= 16;
1347 unsigned aligned
= ALIGN(sz
, bytes_per_field
);
1348 unsigned fields
= aligned
/ bytes_per_field
;
1350 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1351 ubos
[ubo
].ptr
= gpu
>> 2;
1354 mali_ptr ubufs
= panfrost_upload_transient(ctx
, ubos
, sz
);
1355 postfix
->uniforms
= transfer
.gpu
;
1356 postfix
->uniform_buffers
= ubufs
;
1358 buf
->dirty_mask
= 0;
1361 /* TODO: Upload the viewport somewhere more appropriate */
1363 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1364 * (somewhat) asymmetric ints. */
1365 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1367 struct mali_viewport view
= {
1368 /* By default, do no viewport clipping, i.e. clip to (-inf,
1369 * inf) in each direction. Clipping to the viewport in theory
1370 * should work, but in practice causes issues when we're not
1371 * explicitly trying to scissor */
1382 /* Always scissor to the viewport by default. */
1383 int minx
= (int) (vp
->translate
[0] - vp
->scale
[0]);
1384 int maxx
= (int) (vp
->translate
[0] + vp
->scale
[0]);
1386 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1387 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1389 /* Apply the scissor test */
1391 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1398 /* Hardware needs the min/max to be strictly ordered, so flip if we
1399 * need to. The viewport transformation in the vertex shader will
1400 * handle the negatives if we don't */
1414 /* Clamp everything positive, just in case */
1416 maxx
= MAX2(0, maxx
);
1417 maxy
= MAX2(0, maxy
);
1418 minx
= MAX2(0, minx
);
1419 miny
= MAX2(0, miny
);
1421 /* Clamp to the framebuffer size as a last check */
1423 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1424 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1426 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1427 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1429 /* Update the job, unless we're doing wallpapering (whose lack of
1430 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1431 * just... be faster :) */
1433 if (!ctx
->wallpaper_batch
)
1434 panfrost_job_union_scissor(job
, minx
, miny
, maxx
, maxy
);
1438 view
.viewport0
[0] = minx
;
1439 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1441 view
.viewport0
[1] = miny
;
1442 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1444 ctx
->payload_tiler
.postfix
.viewport
=
1445 panfrost_upload_transient(ctx
,
1447 sizeof(struct mali_viewport
));
1452 /* Corresponds to exactly one draw, but does not submit anything */
1455 panfrost_queue_draw(struct panfrost_context
*ctx
)
1457 /* Handle dirty flags now */
1458 panfrost_emit_for_draw(ctx
, true);
1460 /* If rasterizer discard is enable, only submit the vertex */
1462 bool rasterizer_discard
= ctx
->rasterizer
1463 && ctx
->rasterizer
->base
.rasterizer_discard
;
1465 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1466 struct panfrost_transfer tiler
;
1468 if (!rasterizer_discard
)
1469 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1471 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1473 if (rasterizer_discard
)
1474 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1475 else if (ctx
->wallpaper_batch
)
1476 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1478 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1481 /* The entire frame is in memory -- send it off to the kernel! */
1484 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1485 struct pipe_fence_handle
**fence
,
1486 struct panfrost_job
*job
)
1488 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1489 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1493 panfrost_job_submit(ctx
, job
);
1495 /* If visual, we can stall a frame */
1497 if (!flush_immediate
)
1498 panfrost_drm_force_flush_fragment(ctx
, fence
);
1500 screen
->last_fragment_flushed
= false;
1501 screen
->last_job
= job
;
1503 /* If readback, flush now (hurts the pipelined performance) */
1504 if (flush_immediate
)
1505 panfrost_drm_force_flush_fragment(ctx
, fence
);
1510 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1512 struct panfrost_context
*ctx
= pan_context(pipe
);
1514 /* Nothing to reload? */
1515 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1518 /* Check if the buffer has any content on it worth preserving */
1520 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1521 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1522 unsigned level
= surf
->u
.tex
.level
;
1524 if (!rsrc
->bo
->slices
[level
].initialized
)
1527 /* Save the batch */
1528 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1530 ctx
->wallpaper_batch
= batch
;
1531 panfrost_blit_wallpaper(ctx
);
1532 ctx
->wallpaper_batch
= NULL
;
1537 struct pipe_context
*pipe
,
1538 struct pipe_fence_handle
**fence
,
1541 struct panfrost_context
*ctx
= pan_context(pipe
);
1542 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1544 /* Nothing to do! */
1545 if (!job
->last_job
.gpu
&& !job
->clear
) return;
1548 panfrost_draw_wallpaper(&ctx
->base
);
1550 /* Whether to stall the pipeline for immediately correct results. Since
1551 * pipelined rendering is quite broken right now (to be fixed by the
1552 * panfrost_job refactor, just take the perf hit for correctness) */
1553 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1555 /* Submit the frame itself */
1556 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1558 /* Prepare for the next frame */
1559 panfrost_invalidate_frame(ctx
);
1562 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1565 g2m_draw_mode(enum pipe_prim_type mode
)
1568 DEFINE_CASE(POINTS
);
1570 DEFINE_CASE(LINE_LOOP
);
1571 DEFINE_CASE(LINE_STRIP
);
1572 DEFINE_CASE(TRIANGLES
);
1573 DEFINE_CASE(TRIANGLE_STRIP
);
1574 DEFINE_CASE(TRIANGLE_FAN
);
1576 DEFINE_CASE(QUAD_STRIP
);
1577 DEFINE_CASE(POLYGON
);
1580 unreachable("Invalid draw mode");
1587 panfrost_translate_index_size(unsigned size
)
1591 return MALI_DRAW_INDEXED_UINT8
;
1594 return MALI_DRAW_INDEXED_UINT16
;
1597 return MALI_DRAW_INDEXED_UINT32
;
1600 unreachable("Invalid index size");
1604 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1605 * good for the duration of the draw (transient), could last longer */
1608 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1610 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1612 off_t offset
= info
->start
* info
->index_size
;
1614 if (!info
->has_user_indices
) {
1615 /* Only resources can be directly mapped */
1616 return rsrc
->bo
->gpu
+ offset
;
1618 /* Otherwise, we need to upload to transient memory */
1619 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1620 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1625 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1627 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1629 /* Check if we're scissoring at all */
1631 if (!(ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1634 return (ss
->minx
== ss
->maxx
) && (ss
->miny
== ss
->maxy
);
1639 struct pipe_context
*pipe
,
1640 const struct pipe_draw_info
*info
)
1642 struct panfrost_context
*ctx
= pan_context(pipe
);
1644 /* First of all, check the scissor to see if anything is drawn at all.
1645 * If it's not, we drop the draw (mostly a conformance issue;
1646 * well-behaved apps shouldn't hit this) */
1648 if (panfrost_scissor_culls_everything(ctx
))
1651 ctx
->payload_vertex
.draw_start
= info
->start
;
1652 ctx
->payload_tiler
.draw_start
= info
->start
;
1654 int mode
= info
->mode
;
1656 /* Fallback for unsupported modes */
1658 if (!(ctx
->draw_modes
& (1 << mode
))) {
1659 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1660 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1662 if (info
->count
< 4) {
1663 /* Degenerate case? */
1667 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1668 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1673 /* Now that we have a guaranteed terminating path, find the job.
1674 * Assignment commented out to prevent unused warning */
1676 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1678 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1680 ctx
->vertex_count
= info
->count
;
1682 /* For non-indexed draws, they're the same */
1683 unsigned invocation_count
= ctx
->vertex_count
;
1685 unsigned draw_flags
= 0;
1687 /* The draw flags interpret how primitive size is interpreted */
1689 if (panfrost_writes_point_size(ctx
))
1690 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1692 /* For higher amounts of vertices (greater than what fits in a 16-bit
1693 * short), the other value is needed, otherwise there will be bizarre
1694 * rendering artefacts. It's not clear what these values mean yet. */
1696 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1698 if (info
->index_size
) {
1699 /* Calculate the min/max index used so we can figure out how
1700 * many times to invoke the vertex shader */
1702 /* Fetch / calculate index bounds */
1703 unsigned min_index
= 0, max_index
= 0;
1705 if (info
->max_index
== ~0u) {
1706 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1708 min_index
= info
->min_index
;
1709 max_index
= info
->max_index
;
1712 /* Use the corresponding values */
1713 invocation_count
= max_index
- min_index
+ 1;
1714 ctx
->payload_vertex
.draw_start
= min_index
;
1715 ctx
->payload_tiler
.draw_start
= min_index
;
1717 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1718 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1720 //assert(!info->restart_index); /* TODO: Research */
1721 assert(!info
->index_bias
);
1723 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1724 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1726 /* Index count == vertex count, if no indexing is applied, as
1727 * if it is internally indexed in the expected order */
1729 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1730 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1732 /* Reverse index state */
1733 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1736 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1737 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1738 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1740 /* Fire off the draw itself */
1741 panfrost_queue_draw(ctx
);
1747 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1753 panfrost_create_rasterizer_state(
1754 struct pipe_context
*pctx
,
1755 const struct pipe_rasterizer_state
*cso
)
1757 struct panfrost_context
*ctx
= pan_context(pctx
);
1758 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1762 /* Bitmask, unknown meaning of the start value */
1763 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1766 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1768 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1769 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1771 if (cso
->cull_face
& PIPE_FACE_BACK
)
1772 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1778 panfrost_bind_rasterizer_state(
1779 struct pipe_context
*pctx
,
1782 struct panfrost_context
*ctx
= pan_context(pctx
);
1784 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1788 ctx
->rasterizer
= hwcso
;
1789 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1791 /* Point sprites are emulated */
1793 struct panfrost_shader_state
*variant
=
1794 ctx
->fs
? &ctx
->fs
->variants
[ctx
->fs
->active_variant
] : NULL
;
1796 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1797 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
1801 panfrost_create_vertex_elements_state(
1802 struct pipe_context
*pctx
,
1803 unsigned num_elements
,
1804 const struct pipe_vertex_element
*elements
)
1806 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1808 so
->num_elements
= num_elements
;
1809 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1811 /* XXX: What the cornball? This is totally, 100%, unapologetically
1812 * nonsense. And yet it somehow fixes a regression in -bshadow
1813 * (previously, we allocated the descriptor here... a newer commit
1814 * removed that allocation, and then memory corruption led to
1815 * shader_meta getting overwritten in bad ways and then the whole test
1816 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1818 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1820 for (int i
= 0; i
< num_elements
; ++i
) {
1821 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1823 enum pipe_format fmt
= elements
[i
].src_format
;
1824 const struct util_format_description
*desc
= util_format_description(fmt
);
1825 so
->hw
[i
].unknown1
= 0x2;
1826 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1828 so
->hw
[i
].format
= panfrost_find_format(desc
);
1830 /* The field itself should probably be shifted over */
1831 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1838 panfrost_bind_vertex_elements_state(
1839 struct pipe_context
*pctx
,
1842 struct panfrost_context
*ctx
= pan_context(pctx
);
1844 ctx
->vertex
= hwcso
;
1845 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1849 panfrost_create_shader_state(
1850 struct pipe_context
*pctx
,
1851 const struct pipe_shader_state
*cso
)
1853 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1856 /* Token deep copy to prevent memory corruption */
1858 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1859 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1865 panfrost_delete_shader_state(
1866 struct pipe_context
*pctx
,
1869 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1871 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1872 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1879 panfrost_create_sampler_state(
1880 struct pipe_context
*pctx
,
1881 const struct pipe_sampler_state
*cso
)
1883 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1886 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1888 struct mali_sampler_descriptor sampler_descriptor
= {
1889 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1890 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1891 | translate_mip_filter(cso
->min_mip_filter
)
1894 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1895 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1896 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1897 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1899 cso
->border_color
.f
[0],
1900 cso
->border_color
.f
[1],
1901 cso
->border_color
.f
[2],
1902 cso
->border_color
.f
[3]
1904 .min_lod
= FIXED_16(cso
->min_lod
),
1905 .max_lod
= FIXED_16(cso
->max_lod
),
1909 so
->hw
= sampler_descriptor
;
1915 panfrost_bind_sampler_states(
1916 struct pipe_context
*pctx
,
1917 enum pipe_shader_type shader
,
1918 unsigned start_slot
, unsigned num_sampler
,
1921 assert(start_slot
== 0);
1923 struct panfrost_context
*ctx
= pan_context(pctx
);
1925 /* XXX: Should upload, not just copy? */
1926 ctx
->sampler_count
[shader
] = num_sampler
;
1927 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1929 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1933 panfrost_variant_matches(
1934 struct panfrost_context
*ctx
,
1935 struct panfrost_shader_state
*variant
,
1936 enum pipe_shader_type type
)
1938 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1939 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1941 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1943 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1944 /* Make sure enable state is at least the same */
1945 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1949 /* Check that the contents of the test are the same */
1950 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1951 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1953 if (!(same_func
&& same_ref
)) {
1958 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1959 variant
->point_sprite_mask
)) {
1960 /* Ensure the same varyings are turned to point sprites */
1961 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1964 /* Ensure the orientation is correct */
1966 rasterizer
->sprite_coord_mode
==
1967 PIPE_SPRITE_COORD_UPPER_LEFT
;
1969 if (variant
->point_sprite_upper_left
!= upper_left
)
1973 /* Otherwise, we're good to go */
1978 panfrost_bind_shader_state(
1979 struct pipe_context
*pctx
,
1981 enum pipe_shader_type type
)
1983 struct panfrost_context
*ctx
= pan_context(pctx
);
1985 if (type
== PIPE_SHADER_FRAGMENT
) {
1987 ctx
->dirty
|= PAN_DIRTY_FS
;
1989 assert(type
== PIPE_SHADER_VERTEX
);
1991 ctx
->dirty
|= PAN_DIRTY_VS
;
1996 /* Match the appropriate variant */
1998 signed variant
= -1;
1999 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2001 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2002 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2008 if (variant
== -1) {
2009 /* No variant matched, so create a new one */
2010 variant
= variants
->variant_count
++;
2011 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2013 struct panfrost_shader_state
*v
=
2014 &variants
->variants
[variant
];
2018 if (type
== PIPE_SHADER_FRAGMENT
) {
2019 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2021 if (ctx
->rasterizer
) {
2022 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2023 v
->point_sprite_upper_left
=
2024 ctx
->rasterizer
->base
.sprite_coord_mode
==
2025 PIPE_SPRITE_COORD_UPPER_LEFT
;
2029 /* Allocate the mapped descriptor ahead-of-time. */
2030 struct panfrost_context
*ctx
= pan_context(pctx
);
2031 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2033 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2034 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
2038 /* Select this variant */
2039 variants
->active_variant
= variant
;
2041 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2042 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2044 /* We finally have a variant, so compile it */
2046 if (!shader_state
->compiled
) {
2047 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
2048 panfrost_job_type_for_pipe(type
), shader_state
);
2050 shader_state
->compiled
= true;
2055 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2057 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2061 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2063 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2067 panfrost_set_vertex_buffers(
2068 struct pipe_context
*pctx
,
2069 unsigned start_slot
,
2070 unsigned num_buffers
,
2071 const struct pipe_vertex_buffer
*buffers
)
2073 struct panfrost_context
*ctx
= pan_context(pctx
);
2075 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2079 panfrost_set_constant_buffer(
2080 struct pipe_context
*pctx
,
2081 enum pipe_shader_type shader
, uint index
,
2082 const struct pipe_constant_buffer
*buf
)
2084 struct panfrost_context
*ctx
= pan_context(pctx
);
2085 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2087 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2089 unsigned mask
= (1 << index
);
2091 if (unlikely(!buf
)) {
2092 pbuf
->enabled_mask
&= ~mask
;
2093 pbuf
->dirty_mask
&= ~mask
;
2097 pbuf
->enabled_mask
|= mask
;
2098 pbuf
->dirty_mask
|= mask
;
2102 panfrost_set_stencil_ref(
2103 struct pipe_context
*pctx
,
2104 const struct pipe_stencil_ref
*ref
)
2106 struct panfrost_context
*ctx
= pan_context(pctx
);
2107 ctx
->stencil_ref
= *ref
;
2109 /* Shader core dirty */
2110 ctx
->dirty
|= PAN_DIRTY_FS
;
2113 static enum mali_texture_type
2114 panfrost_translate_texture_type(enum pipe_texture_target t
)
2118 case PIPE_TEXTURE_1D
:
2119 case PIPE_TEXTURE_1D_ARRAY
:
2122 case PIPE_TEXTURE_2D
:
2123 case PIPE_TEXTURE_2D_ARRAY
:
2124 case PIPE_TEXTURE_RECT
:
2127 case PIPE_TEXTURE_3D
:
2130 case PIPE_TEXTURE_CUBE
:
2131 case PIPE_TEXTURE_CUBE_ARRAY
:
2132 return MALI_TEX_CUBE
;
2135 unreachable("Unknown target");
2139 static struct pipe_sampler_view
*
2140 panfrost_create_sampler_view(
2141 struct pipe_context
*pctx
,
2142 struct pipe_resource
*texture
,
2143 const struct pipe_sampler_view
*template)
2145 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2146 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2148 pipe_reference(NULL
, &texture
->reference
);
2150 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2153 so
->base
= *template;
2154 so
->base
.texture
= texture
;
2155 so
->base
.reference
.count
= 1;
2156 so
->base
.context
= pctx
;
2158 /* sampler_views correspond to texture descriptors, minus the texture
2159 * (data) itself. So, we serialise the descriptor here and cache it for
2162 /* Make sure it's something with which we're familiar */
2163 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2165 /* TODO: Detect from format better */
2166 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2168 unsigned char user_swizzle
[4] = {
2169 template->swizzle_r
,
2170 template->swizzle_g
,
2171 template->swizzle_b
,
2175 enum mali_format format
= panfrost_find_format(desc
);
2177 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2179 unsigned usage2_layout
= 0x10;
2181 switch (prsrc
->bo
->layout
) {
2183 usage2_layout
|= 0x8 | 0x4;
2186 usage2_layout
|= 0x1;
2189 usage2_layout
|= is_depth
? 0x1 : 0x2;
2196 /* Check if we need to set a custom stride by computing the "expected"
2197 * stride and comparing it to what the BO actually wants. Only applies
2198 * to linear textures, since tiled/compressed textures have strict
2199 * alignment requirements for their strides as it is */
2201 unsigned first_level
= template->u
.tex
.first_level
;
2202 unsigned last_level
= template->u
.tex
.last_level
;
2204 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
2205 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2206 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
2207 unsigned width
= u_minify(texture
->width0
, l
);
2208 unsigned comp_stride
= width
* bytes_per_pixel
;
2210 if (comp_stride
!= actual_stride
) {
2211 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2217 /* In the hardware, array_size refers specifically to array textures,
2218 * whereas in Gallium, it also covers cubemaps */
2220 unsigned array_size
= texture
->array_size
;
2222 if (texture
->target
== PIPE_TEXTURE_CUBE
) {
2223 /* TODO: Cubemap arrays */
2224 assert(array_size
== 6);
2227 struct mali_texture_descriptor texture_descriptor
= {
2228 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2229 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2230 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2231 .array_size
= MALI_POSITIVE(array_size
),
2235 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2238 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2239 .type
= panfrost_translate_texture_type(texture
->target
),
2241 .usage2
= usage2_layout
2244 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2247 //texture_descriptor.nr_mipmap_levels = last_level - first_level;
2249 so
->hw
= texture_descriptor
;
2251 return (struct pipe_sampler_view
*) so
;
2255 panfrost_set_sampler_views(
2256 struct pipe_context
*pctx
,
2257 enum pipe_shader_type shader
,
2258 unsigned start_slot
, unsigned num_views
,
2259 struct pipe_sampler_view
**views
)
2261 struct panfrost_context
*ctx
= pan_context(pctx
);
2263 assert(start_slot
== 0);
2265 unsigned new_nr
= 0;
2266 for (unsigned i
= 0; i
< num_views
; ++i
) {
2271 ctx
->sampler_view_count
[shader
] = new_nr
;
2272 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2274 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2278 panfrost_sampler_view_destroy(
2279 struct pipe_context
*pctx
,
2280 struct pipe_sampler_view
*view
)
2282 pipe_resource_reference(&view
->texture
, NULL
);
2287 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2288 const struct pipe_framebuffer_state
*fb
)
2290 struct panfrost_context
*ctx
= pan_context(pctx
);
2292 /* Flush when switching framebuffers, but not if the framebuffer
2293 * state is being restored by u_blitter
2296 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
2297 bool is_scanout
= panfrost_is_scanout(ctx
);
2298 bool has_draws
= job
->last_job
.gpu
;
2300 if (!ctx
->blitter
->running
&& (!is_scanout
|| has_draws
)) {
2301 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2304 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2305 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2306 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2307 ctx
->pipe_framebuffer
.width
= fb
->width
;
2308 ctx
->pipe_framebuffer
.height
= fb
->height
;
2310 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2311 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2313 /* check if changing cbuf */
2314 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2316 if (cb
&& (i
!= 0)) {
2317 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2322 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2327 if (ctx
->require_sfbd
)
2328 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2330 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2332 panfrost_attach_vt_framebuffer(ctx
);
2334 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2335 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2337 bool can_afbc
= panfrost_format_supports_afbc(format
);
2338 bool is_scanout
= panfrost_is_scanout(ctx
);
2340 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2341 panfrost_enable_afbc(ctx
, tex
, false);
2343 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2344 panfrost_enable_checksum(ctx
, tex
);
2348 struct pipe_surface
*zb
= fb
->zsbuf
;
2350 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2351 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2354 if (ctx
->require_sfbd
)
2355 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2357 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2359 panfrost_attach_vt_framebuffer(ctx
);
2361 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2362 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2363 bool is_scanout
= panfrost_is_scanout(ctx
);
2365 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2366 panfrost_enable_afbc(ctx
, tex
, true);
2373 panfrost_create_blend_state(struct pipe_context
*pipe
,
2374 const struct pipe_blend_state
*blend
)
2376 struct panfrost_context
*ctx
= pan_context(pipe
);
2377 struct panfrost_blend_state
*so
= rzalloc(ctx
, struct panfrost_blend_state
);
2380 /* TODO: The following features are not yet implemented */
2381 assert(!blend
->logicop_enable
);
2382 assert(!blend
->alpha_to_coverage
);
2383 assert(!blend
->alpha_to_one
);
2385 /* Compile the blend state, first as fixed-function if we can */
2387 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2390 /* If we can't, compile a blend shader instead */
2392 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2398 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2401 struct panfrost_context
*ctx
= pan_context(pipe
);
2402 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2403 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2404 ctx
->blend
= pblend
;
2409 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2411 /* TODO: Attach color */
2413 /* Shader itself is not dirty, but the shader core is */
2414 ctx
->dirty
|= PAN_DIRTY_FS
;
2418 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2421 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2423 if (so
->has_blend_shader
) {
2424 DBG("Deleting blend state leak blend shaders bytecode\n");
2431 panfrost_set_blend_color(struct pipe_context
*pipe
,
2432 const struct pipe_blend_color
*blend_color
)
2434 struct panfrost_context
*ctx
= pan_context(pipe
);
2436 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2439 ctx
->blend_color
= *blend_color
;
2441 /* The blend mode depends on the blend constant color, due to the
2442 * fixed/programmable split. So, we're forced to regenerate the blend
2445 /* TODO: Attach color */
2450 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2451 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2453 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2457 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2460 struct panfrost_context
*ctx
= pan_context(pipe
);
2461 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2462 ctx
->depth_stencil
= depth_stencil
;
2467 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2468 * emulated in the fragment shader */
2470 if (depth_stencil
->alpha
.enabled
) {
2471 /* We need to trigger a new shader (maybe) */
2472 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2476 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2478 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2479 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2481 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2482 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2484 /* Depth state (TODO: Refactor) */
2485 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2487 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2489 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2490 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2492 /* Bounds test not implemented */
2493 assert(!depth_stencil
->depth
.bounds_test
);
2495 ctx
->dirty
|= PAN_DIRTY_FS
;
2499 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2505 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2506 unsigned sample_mask
)
2511 panfrost_set_clip_state(struct pipe_context
*pipe
,
2512 const struct pipe_clip_state
*clip
)
2514 //struct panfrost_context *panfrost = pan_context(pipe);
2518 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2519 unsigned start_slot
,
2520 unsigned num_viewports
,
2521 const struct pipe_viewport_state
*viewports
)
2523 struct panfrost_context
*ctx
= pan_context(pipe
);
2525 assert(start_slot
== 0);
2526 assert(num_viewports
== 1);
2528 ctx
->pipe_viewport
= *viewports
;
2532 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2533 unsigned start_slot
,
2534 unsigned num_scissors
,
2535 const struct pipe_scissor_state
*scissors
)
2537 struct panfrost_context
*ctx
= pan_context(pipe
);
2539 assert(start_slot
== 0);
2540 assert(num_scissors
== 1);
2542 ctx
->scissor
= *scissors
;
2546 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2547 const struct pipe_poly_stipple
*stipple
)
2549 //struct panfrost_context *panfrost = pan_context(pipe);
2553 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2556 //struct panfrost_context *panfrost = pan_context(pipe);
2560 panfrost_destroy(struct pipe_context
*pipe
)
2562 struct panfrost_context
*panfrost
= pan_context(pipe
);
2563 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2565 if (panfrost
->blitter
)
2566 util_blitter_destroy(panfrost
->blitter
);
2568 panfrost_drm_free_slab(screen
, &panfrost
->scratchpad
);
2569 panfrost_drm_free_slab(screen
, &panfrost
->varying_mem
);
2570 panfrost_drm_free_slab(screen
, &panfrost
->shaders
);
2571 panfrost_drm_free_slab(screen
, &panfrost
->tiler_heap
);
2572 panfrost_drm_free_slab(screen
, &panfrost
->tiler_polygon_list
);
2573 panfrost_drm_free_slab(screen
, &panfrost
->tiler_dummy
);
2575 for (int i
= 0; i
< ARRAY_SIZE(panfrost
->transient_pools
); ++i
) {
2576 struct panfrost_memory_entry
*entry
;
2577 entry
= panfrost
->transient_pools
[i
].entries
[0];
2578 pb_slab_free(&screen
->slabs
, (struct pb_slab_entry
*)entry
);
2584 static struct pipe_query
*
2585 panfrost_create_query(struct pipe_context
*pipe
,
2589 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2594 return (struct pipe_query
*) q
;
2598 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2604 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2606 struct panfrost_context
*ctx
= pan_context(pipe
);
2607 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2609 switch (query
->type
) {
2610 case PIPE_QUERY_OCCLUSION_COUNTER
:
2611 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2612 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2614 /* Allocate a word for the query results to be stored */
2615 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2617 ctx
->occlusion_query
= query
;
2623 DBG("Skipping query %d\n", query
->type
);
2631 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2633 struct panfrost_context
*ctx
= pan_context(pipe
);
2634 ctx
->occlusion_query
= NULL
;
2639 panfrost_get_query_result(struct pipe_context
*pipe
,
2640 struct pipe_query
*q
,
2642 union pipe_query_result
*vresult
)
2645 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2647 /* We need to flush out the jobs to actually run the counter, TODO
2648 * check wait, TODO wallpaper after if needed */
2650 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2652 switch (query
->type
) {
2653 case PIPE_QUERY_OCCLUSION_COUNTER
:
2654 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2655 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2656 /* Read back the query results */
2657 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2658 unsigned passed
= *result
;
2660 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2661 vresult
->u64
= passed
;
2663 vresult
->b
= !!passed
;
2669 DBG("Skipped query get %d\n", query
->type
);
2676 static struct pipe_stream_output_target
*
2677 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2678 struct pipe_resource
*prsc
,
2679 unsigned buffer_offset
,
2680 unsigned buffer_size
)
2682 struct pipe_stream_output_target
*target
;
2684 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2689 pipe_reference_init(&target
->reference
, 1);
2690 pipe_resource_reference(&target
->buffer
, prsc
);
2692 target
->context
= pctx
;
2693 target
->buffer_offset
= buffer_offset
;
2694 target
->buffer_size
= buffer_size
;
2700 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2701 struct pipe_stream_output_target
*target
)
2703 pipe_resource_reference(&target
->buffer
, NULL
);
2704 ralloc_free(target
);
2708 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2709 unsigned num_targets
,
2710 struct pipe_stream_output_target
**targets
,
2711 const unsigned *offsets
)
2717 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2719 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2720 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2722 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2723 /* Allocate the beginning of the transient pool */
2724 int entry_size
= (1 << 22); /* 4MB */
2726 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2727 ctx
->transient_pools
[i
].entry_count
= 1;
2729 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2732 panfrost_drm_allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2733 panfrost_drm_allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2734 panfrost_drm_allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2735 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2736 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_polygon_list
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2737 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2740 /* New context creation, which also does hardware initialisation since I don't
2741 * know the better way to structure this :smirk: */
2743 struct pipe_context
*
2744 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2746 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2747 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2748 memset(ctx
, 0, sizeof(*ctx
));
2749 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2752 gpu_id
= panfrost_drm_query_gpu_version(pscreen
);
2754 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2755 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2757 gallium
->screen
= screen
;
2759 gallium
->destroy
= panfrost_destroy
;
2761 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2763 gallium
->flush
= panfrost_flush
;
2764 gallium
->clear
= panfrost_clear
;
2765 gallium
->draw_vbo
= panfrost_draw_vbo
;
2767 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2768 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2770 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2772 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2773 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2774 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2776 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2777 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2778 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2780 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2781 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2782 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2784 gallium
->create_fs_state
= panfrost_create_shader_state
;
2785 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2786 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2788 gallium
->create_vs_state
= panfrost_create_shader_state
;
2789 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2790 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2792 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2793 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2794 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2796 gallium
->create_blend_state
= panfrost_create_blend_state
;
2797 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2798 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2800 gallium
->set_blend_color
= panfrost_set_blend_color
;
2802 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2803 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2804 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2806 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2808 gallium
->set_clip_state
= panfrost_set_clip_state
;
2809 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2810 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2811 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2812 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2814 gallium
->create_query
= panfrost_create_query
;
2815 gallium
->destroy_query
= panfrost_destroy_query
;
2816 gallium
->begin_query
= panfrost_begin_query
;
2817 gallium
->end_query
= panfrost_end_query
;
2818 gallium
->get_query_result
= panfrost_get_query_result
;
2820 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2821 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2822 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2824 panfrost_resource_context_init(gallium
);
2826 panfrost_drm_init_context(ctx
);
2828 panfrost_setup_hardware(ctx
);
2831 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2832 gallium
->const_uploader
= gallium
->stream_uploader
;
2833 assert(gallium
->stream_uploader
);
2835 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2836 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2838 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2840 ctx
->blitter
= util_blitter_create(gallium
);
2841 assert(ctx
->blitter
);
2843 /* Prepare for render! */
2845 panfrost_job_init(ctx
);
2846 panfrost_emit_vertex_payload(ctx
);
2847 panfrost_emit_tiler_payload(ctx
);
2848 panfrost_invalidate_frame(ctx
);
2849 panfrost_default_shader_backend(ctx
);