panfrost: Group SFBD state together
[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 */
26
27 #include <sys/poll.h>
28 #include <errno.h>
29
30 #include "pan_bo.h"
31 #include "pan_context.h"
32 #include "pan_minmax_cache.h"
33 #include "panfrost-quirks.h"
34
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
50
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
54 #include "pan_cmdstream.h"
55 #include "pan_util.h"
56 #include "decode.h"
57 #include "util/pan_lower_framebuffer.h"
58
59 struct midgard_tiler_descriptor
60 panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
61 {
62 struct panfrost_device *device = pan_device(batch->ctx->base.screen);
63 bool hierarchy = !(device->quirks & MIDGARD_NO_HIER_TILING);
64 struct midgard_tiler_descriptor t = {0};
65 unsigned height = batch->key.height;
66 unsigned width = batch->key.width;
67
68 t.hierarchy_mask =
69 panfrost_choose_hierarchy_mask(width, height, vertex_count, hierarchy);
70
71 /* Compute the polygon header size and use that to offset the body */
72
73 unsigned header_size = panfrost_tiler_header_size(
74 width, height, t.hierarchy_mask, hierarchy);
75
76 t.polygon_list_size = panfrost_tiler_full_size(
77 width, height, t.hierarchy_mask, hierarchy);
78
79 if (vertex_count) {
80 t.polygon_list = panfrost_batch_get_polygon_list(batch,
81 header_size +
82 t.polygon_list_size);
83
84
85 t.heap_start = device->tiler_heap->gpu;
86 t.heap_end = device->tiler_heap->gpu + device->tiler_heap->size;
87 } else {
88 struct panfrost_bo *tiler_dummy;
89
90 tiler_dummy = panfrost_batch_get_tiler_dummy(batch);
91 header_size = MALI_TILER_MINIMUM_HEADER_SIZE;
92
93 /* The tiler is disabled, so don't allow the tiler heap */
94 t.heap_start = tiler_dummy->gpu;
95 t.heap_end = t.heap_start;
96
97 /* Use a dummy polygon list */
98 t.polygon_list = tiler_dummy->gpu;
99
100 /* Disable the tiler */
101 if (hierarchy)
102 t.hierarchy_mask |= MALI_TILER_DISABLED;
103 else {
104 t.hierarchy_mask = MALI_TILER_USER;
105 t.polygon_list_size = MALI_TILER_MINIMUM_HEADER_SIZE + 4;
106
107 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
108 uint32_t *polygon_list_body = (uint32_t *) (tiler_dummy->cpu + header_size);
109 polygon_list_body[0] = 0xa0000000; /* TODO: Just that? */
110 }
111 }
112
113 t.polygon_list_body =
114 t.polygon_list + header_size;
115
116 return t;
117 }
118
119 static void
120 panfrost_clear(
121 struct pipe_context *pipe,
122 unsigned buffers,
123 const struct pipe_scissor_state *scissor_state,
124 const union pipe_color_union *color,
125 double depth, unsigned stencil)
126 {
127 struct panfrost_context *ctx = pan_context(pipe);
128
129 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
130 * the existing batch targeting this FBO has draws. We could probably
131 * avoid that by replacing plain clears by quad-draws with a specific
132 * color/depth/stencil value, thus avoiding the generation of extra
133 * fragment jobs.
134 */
135 struct panfrost_batch *batch = panfrost_get_fresh_batch_for_fbo(ctx);
136 panfrost_batch_clear(batch, buffers, color, depth, stencil);
137 }
138
139 bool
140 panfrost_writes_point_size(struct panfrost_context *ctx)
141 {
142 assert(ctx->shader[PIPE_SHADER_VERTEX]);
143 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
144
145 return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS;
146 }
147
148 /* Compute number of UBOs active (more specifically, compute the highest UBO
149 * number addressable -- if there are gaps, include them in the count anyway).
150 * We always include UBO #0 in the count, since we *need* uniforms enabled for
151 * sysvals. */
152
153 unsigned
154 panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage)
155 {
156 unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1;
157 return 32 - __builtin_clz(mask);
158 }
159
160 /* The entire frame is in memory -- send it off to the kernel! */
161
162 void
163 panfrost_flush(
164 struct pipe_context *pipe,
165 struct pipe_fence_handle **fence,
166 unsigned flags)
167 {
168 struct panfrost_context *ctx = pan_context(pipe);
169 struct panfrost_device *dev = pan_device(pipe->screen);
170 uint32_t syncobj = 0;
171
172 if (fence)
173 drmSyncobjCreate(dev->fd, 0, &syncobj);
174
175 /* Submit all pending jobs */
176 panfrost_flush_all_batches(ctx, syncobj);
177
178 if (fence) {
179 struct panfrost_fence *f = panfrost_fence_create(ctx, syncobj);
180 pipe->screen->fence_reference(pipe->screen, fence, NULL);
181 *fence = (struct pipe_fence_handle *)f;
182 }
183
184 if (dev->debug & PAN_DBG_TRACE)
185 pandecode_next_frame();
186 }
187
188 static void
189 panfrost_texture_barrier(struct pipe_context *pipe, unsigned flags)
190 {
191 struct panfrost_context *ctx = pan_context(pipe);
192 panfrost_flush_all_batches(ctx, 0);
193 }
194
195 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_DRAW_MODE_##c;
196
197 static int
198 g2m_draw_mode(enum pipe_prim_type mode)
199 {
200 switch (mode) {
201 DEFINE_CASE(POINTS);
202 DEFINE_CASE(LINES);
203 DEFINE_CASE(LINE_LOOP);
204 DEFINE_CASE(LINE_STRIP);
205 DEFINE_CASE(TRIANGLES);
206 DEFINE_CASE(TRIANGLE_STRIP);
207 DEFINE_CASE(TRIANGLE_FAN);
208 DEFINE_CASE(QUADS);
209 DEFINE_CASE(QUAD_STRIP);
210 DEFINE_CASE(POLYGON);
211
212 default:
213 unreachable("Invalid draw mode");
214 }
215 }
216
217 #undef DEFINE_CASE
218
219 static bool
220 panfrost_scissor_culls_everything(struct panfrost_context *ctx)
221 {
222 const struct pipe_scissor_state *ss = &ctx->scissor;
223
224 /* Check if we're scissoring at all */
225
226 if (!ctx->rasterizer->base.scissor)
227 return false;
228
229 return (ss->minx == ss->maxx) || (ss->miny == ss->maxy);
230 }
231
232 /* Count generated primitives (when there is no geom/tess shaders) for
233 * transform feedback */
234
235 static void
236 panfrost_statistics_record(
237 struct panfrost_context *ctx,
238 const struct pipe_draw_info *info)
239 {
240 if (!ctx->active_queries)
241 return;
242
243 uint32_t prims = u_prims_for_vertices(info->mode, info->count);
244 ctx->prims_generated += prims;
245
246 if (!ctx->streamout.num_targets)
247 return;
248
249 ctx->tf_prims_generated += prims;
250 }
251
252 static void
253 panfrost_update_streamout_offsets(struct panfrost_context *ctx)
254 {
255 for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) {
256 unsigned count;
257
258 count = u_stream_outputs_for_vertices(ctx->active_prim,
259 ctx->vertex_count);
260 ctx->streamout.offsets[i] += count;
261 }
262 }
263
264 static void
265 panfrost_draw_vbo(
266 struct pipe_context *pipe,
267 const struct pipe_draw_info *info)
268 {
269 struct panfrost_context *ctx = pan_context(pipe);
270
271 /* First of all, check the scissor to see if anything is drawn at all.
272 * If it's not, we drop the draw (mostly a conformance issue;
273 * well-behaved apps shouldn't hit this) */
274
275 if (panfrost_scissor_culls_everything(ctx))
276 return;
277
278 int mode = info->mode;
279
280 /* Fallback unsupported restart index */
281 unsigned primitive_index = (1 << (info->index_size * 8)) - 1;
282
283 if (info->primitive_restart && info->index_size
284 && info->restart_index != primitive_index) {
285 util_draw_vbo_without_prim_restart(pipe, info);
286 return;
287 }
288
289 /* Fallback for unsupported modes */
290
291 assert(ctx->rasterizer != NULL);
292
293 if (!(ctx->draw_modes & (1 << mode))) {
294 if (info->count < 4) {
295 /* Degenerate case? */
296 return;
297 }
298
299 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
300 util_primconvert_draw_vbo(ctx->primconvert, info);
301 return;
302 }
303
304 /* Now that we have a guaranteed terminating path, find the job. */
305
306 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
307 panfrost_batch_set_requirements(batch);
308
309 /* Take into account a negative bias */
310 ctx->vertex_count = info->count + abs(info->index_bias);
311 ctx->instance_count = info->instance_count;
312 ctx->active_prim = info->mode;
313
314 struct mali_vertex_tiler_prefix vertex_prefix, tiler_prefix;
315 struct mali_vertex_tiler_postfix vertex_postfix, tiler_postfix;
316 union midgard_primitive_size primitive_size;
317 unsigned vertex_count;
318
319 panfrost_vt_init(ctx, PIPE_SHADER_VERTEX, &vertex_prefix, &vertex_postfix);
320 panfrost_vt_init(ctx, PIPE_SHADER_FRAGMENT, &tiler_prefix, &tiler_postfix);
321
322 panfrost_vt_set_draw_info(ctx, info, g2m_draw_mode(mode),
323 &vertex_postfix, &tiler_prefix,
324 &tiler_postfix, &vertex_count,
325 &ctx->padded_count);
326
327 panfrost_statistics_record(ctx, info);
328
329 panfrost_pack_work_groups_fused(&vertex_prefix, &tiler_prefix,
330 1, vertex_count, info->instance_count,
331 1, 1, 1);
332
333 /* Emit all sort of descriptors. */
334 panfrost_emit_vertex_data(batch, &vertex_postfix);
335 panfrost_emit_varying_descriptor(batch,
336 ctx->padded_count *
337 ctx->instance_count,
338 &vertex_postfix, &tiler_postfix,
339 &primitive_size);
340 panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
341 panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
342 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
343 panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
344 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
345 panfrost_emit_texture_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
346 panfrost_emit_const_buf(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
347 panfrost_emit_const_buf(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
348 panfrost_emit_viewport(batch, &tiler_postfix);
349
350 panfrost_vt_update_primitive_size(ctx, &tiler_prefix, &primitive_size);
351
352 /* Fire off the draw itself */
353 panfrost_emit_vertex_tiler_jobs(batch, &vertex_prefix, &vertex_postfix,
354 &tiler_prefix, &tiler_postfix,
355 &primitive_size);
356
357 /* Adjust the batch stack size based on the new shader stack sizes. */
358 panfrost_batch_adjust_stack_size(batch);
359
360 /* Increment transform feedback offsets */
361 panfrost_update_streamout_offsets(ctx);
362 }
363
364 /* CSO state */
365
366 static void
367 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
368 {
369 free(hwcso);
370 }
371
372 static void *
373 panfrost_create_rasterizer_state(
374 struct pipe_context *pctx,
375 const struct pipe_rasterizer_state *cso)
376 {
377 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
378
379 so->base = *cso;
380
381 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
382 assert(cso->offset_clamp == 0.0);
383
384 return so;
385 }
386
387 static void
388 panfrost_bind_rasterizer_state(
389 struct pipe_context *pctx,
390 void *hwcso)
391 {
392 struct panfrost_context *ctx = pan_context(pctx);
393
394 ctx->rasterizer = hwcso;
395
396 if (!hwcso)
397 return;
398
399 /* Point sprites are emulated */
400
401 struct panfrost_shader_state *variant = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
402
403 if (ctx->rasterizer->base.sprite_coord_enable || (variant && variant->point_sprite_mask))
404 ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
405 }
406
407 static void *
408 panfrost_create_vertex_elements_state(
409 struct pipe_context *pctx,
410 unsigned num_elements,
411 const struct pipe_vertex_element *elements)
412 {
413 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
414 struct panfrost_device *dev = pan_device(pctx->screen);
415
416 so->num_elements = num_elements;
417 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
418
419 for (int i = 0; i < num_elements; ++i) {
420 enum pipe_format fmt = elements[i].src_format;
421 const struct util_format_description *desc = util_format_description(fmt);
422 unsigned swizzle = 0;
423 if (dev->quirks & HAS_SWIZZLES)
424 swizzle = panfrost_translate_swizzle_4(desc->swizzle);
425 else
426 swizzle = panfrost_bifrost_swizzle(desc->nr_channels);
427
428 enum mali_format hw_format = panfrost_pipe_format_table[desc->format].hw;
429 so->formats[i] = (hw_format << 12) | swizzle;
430 assert(hw_format);
431 }
432
433 /* Let's also prepare vertex builtins */
434 if (dev->quirks & HAS_SWIZZLES)
435 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
436 else
437 so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
438
439 if (dev->quirks & HAS_SWIZZLES)
440 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1);
441 else
442 so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1);
443
444 return so;
445 }
446
447 static void
448 panfrost_bind_vertex_elements_state(
449 struct pipe_context *pctx,
450 void *hwcso)
451 {
452 struct panfrost_context *ctx = pan_context(pctx);
453 ctx->vertex = hwcso;
454 }
455
456 static void *
457 panfrost_create_shader_state(
458 struct pipe_context *pctx,
459 const struct pipe_shader_state *cso,
460 enum pipe_shader_type stage)
461 {
462 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
463 struct panfrost_device *dev = pan_device(pctx->screen);
464 so->base = *cso;
465
466 /* Token deep copy to prevent memory corruption */
467
468 if (cso->type == PIPE_SHADER_IR_TGSI)
469 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
470
471 /* Precompile for shader-db if we need to */
472 if (unlikely((dev->debug & PAN_DBG_PRECOMPILE) && cso->type == PIPE_SHADER_IR_NIR)) {
473 struct panfrost_context *ctx = pan_context(pctx);
474
475 struct panfrost_shader_state state;
476 uint64_t outputs_written;
477
478 panfrost_shader_compile(ctx, PIPE_SHADER_IR_NIR,
479 so->base.ir.nir,
480 tgsi_processor_to_shader_stage(stage),
481 &state, &outputs_written);
482 }
483
484 return so;
485 }
486
487 static void
488 panfrost_delete_shader_state(
489 struct pipe_context *pctx,
490 void *so)
491 {
492 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
493
494 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
495 /* TODO: leaks TGSI tokens! */
496 }
497
498 for (unsigned i = 0; i < cso->variant_count; ++i) {
499 struct panfrost_shader_state *shader_state = &cso->variants[i];
500 panfrost_bo_unreference(shader_state->bo);
501 shader_state->bo = NULL;
502 }
503 free(cso->variants);
504
505 free(so);
506 }
507
508 static void *
509 panfrost_create_sampler_state(
510 struct pipe_context *pctx,
511 const struct pipe_sampler_state *cso)
512 {
513 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
514 struct panfrost_device *device = pan_device(pctx->screen);
515
516 so->base = *cso;
517
518 if (device->quirks & IS_BIFROST)
519 panfrost_sampler_desc_init_bifrost(cso, (struct mali_bifrost_sampler_packed *) &so->hw);
520 else
521 panfrost_sampler_desc_init(cso, &so->hw);
522
523 return so;
524 }
525
526 static void
527 panfrost_bind_sampler_states(
528 struct pipe_context *pctx,
529 enum pipe_shader_type shader,
530 unsigned start_slot, unsigned num_sampler,
531 void **sampler)
532 {
533 assert(start_slot == 0);
534
535 struct panfrost_context *ctx = pan_context(pctx);
536
537 /* XXX: Should upload, not just copy? */
538 ctx->sampler_count[shader] = num_sampler;
539 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
540 }
541
542 static bool
543 panfrost_variant_matches(
544 struct panfrost_context *ctx,
545 struct panfrost_shader_state *variant,
546 enum pipe_shader_type type)
547 {
548 struct panfrost_device *dev = pan_device(ctx->base.screen);
549 struct pipe_rasterizer_state *rasterizer = &ctx->rasterizer->base;
550
551 bool is_fragment = (type == PIPE_SHADER_FRAGMENT);
552
553 if (variant->outputs_read) {
554 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
555
556 unsigned i;
557 BITSET_FOREACH_SET(i, &variant->outputs_read, 8) {
558 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
559
560 if ((fb->nr_cbufs > i) && fb->cbufs[i])
561 fmt = fb->cbufs[i]->format;
562
563 const struct util_format_description *desc =
564 util_format_description(fmt);
565
566 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
567 fmt = PIPE_FORMAT_NONE;
568
569 if (variant->rt_formats[i] != fmt)
570 return false;
571 }
572 }
573
574 /* Point sprites TODO on bifrost, always pass */
575 if (is_fragment && rasterizer && (rasterizer->sprite_coord_enable |
576 variant->point_sprite_mask)
577 && !(dev->quirks & IS_BIFROST)) {
578 /* Ensure the same varyings are turned to point sprites */
579 if (rasterizer->sprite_coord_enable != variant->point_sprite_mask)
580 return false;
581
582 /* Ensure the orientation is correct */
583 bool upper_left =
584 rasterizer->sprite_coord_mode ==
585 PIPE_SPRITE_COORD_UPPER_LEFT;
586
587 if (variant->point_sprite_upper_left != upper_left)
588 return false;
589 }
590
591 /* Otherwise, we're good to go */
592 return true;
593 }
594
595 /**
596 * Fix an uncompiled shader's stream output info, and produce a bitmask
597 * of which VARYING_SLOT_* are captured for stream output.
598 *
599 * Core Gallium stores output->register_index as a "slot" number, where
600 * slots are assigned consecutively to all outputs in info->outputs_written.
601 * This naive packing of outputs doesn't work for us - we too have slots,
602 * but the layout is defined by the VUE map, which we won't have until we
603 * compile a specific shader variant. So, we remap these and simply store
604 * VARYING_SLOT_* in our copy's output->register_index fields.
605 *
606 * We then produce a bitmask of outputs which are used for SO.
607 *
608 * Implementation from iris.
609 */
610
611 static uint64_t
612 update_so_info(struct pipe_stream_output_info *so_info,
613 uint64_t outputs_written)
614 {
615 uint64_t so_outputs = 0;
616 uint8_t reverse_map[64] = {0};
617 unsigned slot = 0;
618
619 while (outputs_written)
620 reverse_map[slot++] = u_bit_scan64(&outputs_written);
621
622 for (unsigned i = 0; i < so_info->num_outputs; i++) {
623 struct pipe_stream_output *output = &so_info->output[i];
624
625 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
626 output->register_index = reverse_map[output->register_index];
627
628 so_outputs |= 1ull << output->register_index;
629 }
630
631 return so_outputs;
632 }
633
634 static void
635 panfrost_bind_shader_state(
636 struct pipe_context *pctx,
637 void *hwcso,
638 enum pipe_shader_type type)
639 {
640 struct panfrost_context *ctx = pan_context(pctx);
641 struct panfrost_device *dev = pan_device(ctx->base.screen);
642 ctx->shader[type] = hwcso;
643
644 if (!hwcso) return;
645
646 /* Match the appropriate variant */
647
648 signed variant = -1;
649 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
650
651 for (unsigned i = 0; i < variants->variant_count; ++i) {
652 if (panfrost_variant_matches(ctx, &variants->variants[i], type)) {
653 variant = i;
654 break;
655 }
656 }
657
658 if (variant == -1) {
659 /* No variant matched, so create a new one */
660 variant = variants->variant_count++;
661
662 if (variants->variant_count > variants->variant_space) {
663 unsigned old_space = variants->variant_space;
664
665 variants->variant_space *= 2;
666 if (variants->variant_space == 0)
667 variants->variant_space = 1;
668
669 /* Arbitrary limit to stop runaway programs from
670 * creating an unbounded number of shader variants. */
671 assert(variants->variant_space < 1024);
672
673 unsigned msize = sizeof(struct panfrost_shader_state);
674 variants->variants = realloc(variants->variants,
675 variants->variant_space * msize);
676
677 memset(&variants->variants[old_space], 0,
678 (variants->variant_space - old_space) * msize);
679 }
680
681 struct panfrost_shader_state *v =
682 &variants->variants[variant];
683
684 if (type == PIPE_SHADER_FRAGMENT) {
685 struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
686 for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
687 enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
688
689 if ((fb->nr_cbufs > i) && fb->cbufs[i])
690 fmt = fb->cbufs[i]->format;
691
692 const struct util_format_description *desc =
693 util_format_description(fmt);
694
695 if (pan_format_class_load(desc, dev->quirks) == PAN_FORMAT_NATIVE)
696 fmt = PIPE_FORMAT_NONE;
697
698 v->rt_formats[i] = fmt;
699 }
700
701 /* Point sprites are TODO on Bifrost */
702 if (ctx->rasterizer && !(dev->quirks & IS_BIFROST)) {
703 v->point_sprite_mask = ctx->rasterizer->base.sprite_coord_enable;
704 v->point_sprite_upper_left =
705 ctx->rasterizer->base.sprite_coord_mode ==
706 PIPE_SPRITE_COORD_UPPER_LEFT;
707 }
708 }
709 }
710
711 /* Select this variant */
712 variants->active_variant = variant;
713
714 struct panfrost_shader_state *shader_state = &variants->variants[variant];
715 assert(panfrost_variant_matches(ctx, shader_state, type));
716
717 /* We finally have a variant, so compile it */
718
719 if (!shader_state->compiled) {
720 uint64_t outputs_written = 0;
721
722 panfrost_shader_compile(ctx, variants->base.type,
723 variants->base.type == PIPE_SHADER_IR_NIR ?
724 variants->base.ir.nir :
725 variants->base.tokens,
726 tgsi_processor_to_shader_stage(type),
727 shader_state,
728 &outputs_written);
729
730 shader_state->compiled = true;
731
732 /* Fixup the stream out information, since what Gallium returns
733 * normally is mildly insane */
734
735 shader_state->stream_output = variants->base.stream_output;
736 shader_state->so_mask =
737 update_so_info(&shader_state->stream_output, outputs_written);
738 }
739 }
740
741 static void *
742 panfrost_create_vs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
743 {
744 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
745 }
746
747 static void *
748 panfrost_create_fs_state(struct pipe_context *pctx, const struct pipe_shader_state *hwcso)
749 {
750 return panfrost_create_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
751 }
752
753 static void
754 panfrost_bind_vs_state(struct pipe_context *pctx, void *hwcso)
755 {
756 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_VERTEX);
757 }
758
759 static void
760 panfrost_bind_fs_state(struct pipe_context *pctx, void *hwcso)
761 {
762 panfrost_bind_shader_state(pctx, hwcso, PIPE_SHADER_FRAGMENT);
763 }
764
765 static void
766 panfrost_set_vertex_buffers(
767 struct pipe_context *pctx,
768 unsigned start_slot,
769 unsigned num_buffers,
770 const struct pipe_vertex_buffer *buffers)
771 {
772 struct panfrost_context *ctx = pan_context(pctx);
773
774 util_set_vertex_buffers_mask(ctx->vertex_buffers, &ctx->vb_mask, buffers, start_slot, num_buffers);
775 }
776
777 static void
778 panfrost_set_constant_buffer(
779 struct pipe_context *pctx,
780 enum pipe_shader_type shader, uint index,
781 const struct pipe_constant_buffer *buf)
782 {
783 struct panfrost_context *ctx = pan_context(pctx);
784 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
785
786 util_copy_constant_buffer(&pbuf->cb[index], buf);
787
788 unsigned mask = (1 << index);
789
790 if (unlikely(!buf)) {
791 pbuf->enabled_mask &= ~mask;
792 pbuf->dirty_mask &= ~mask;
793 return;
794 }
795
796 pbuf->enabled_mask |= mask;
797 pbuf->dirty_mask |= mask;
798 }
799
800 static void
801 panfrost_set_stencil_ref(
802 struct pipe_context *pctx,
803 const struct pipe_stencil_ref *ref)
804 {
805 struct panfrost_context *ctx = pan_context(pctx);
806 ctx->stencil_ref = *ref;
807 }
808
809 void
810 panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so,
811 struct pipe_context *pctx,
812 struct pipe_resource *texture)
813 {
814 struct panfrost_device *device = pan_device(pctx->screen);
815 struct panfrost_resource *prsrc = (struct panfrost_resource *)texture;
816 enum pipe_format format = so->base.format;
817 assert(prsrc->bo);
818
819 /* Format to access the stencil portion of a Z32_S8 texture */
820 if (format == PIPE_FORMAT_X32_S8X24_UINT) {
821 assert(prsrc->separate_stencil);
822 texture = &prsrc->separate_stencil->base;
823 prsrc = (struct panfrost_resource *)texture;
824 format = texture->format;
825 }
826
827 const struct util_format_description *desc = util_format_description(format);
828
829 bool fake_rgtc = !panfrost_supports_compressed_format(device, MALI_BC4_UNORM);
830
831 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC && fake_rgtc) {
832 if (desc->is_snorm)
833 format = PIPE_FORMAT_R8G8B8A8_SNORM;
834 else
835 format = PIPE_FORMAT_R8G8B8A8_UNORM;
836 desc = util_format_description(format);
837 }
838
839 so->texture_bo = prsrc->bo->gpu;
840 so->modifier = prsrc->modifier;
841
842 unsigned char user_swizzle[4] = {
843 so->base.swizzle_r,
844 so->base.swizzle_g,
845 so->base.swizzle_b,
846 so->base.swizzle_a
847 };
848
849 /* In the hardware, array_size refers specifically to array textures,
850 * whereas in Gallium, it also covers cubemaps */
851
852 unsigned array_size = texture->array_size;
853 unsigned depth = texture->depth0;
854
855 if (so->base.target == PIPE_TEXTURE_CUBE) {
856 /* TODO: Cubemap arrays */
857 assert(array_size == 6);
858 array_size /= 6;
859 }
860
861 /* MSAA only supported for 2D textures (and 2D texture arrays via an
862 * extension currently unimplemented */
863
864 if (so->base.target == PIPE_TEXTURE_2D) {
865 assert(depth == 1);
866 depth = texture->nr_samples;
867 } else {
868 /* MSAA only supported for 2D textures */
869 assert(texture->nr_samples <= 1);
870 }
871
872 enum mali_texture_dimension type =
873 panfrost_translate_texture_dimension(so->base.target);
874
875 if (device->quirks & IS_BIFROST) {
876 unsigned char composed_swizzle[4];
877 util_format_compose_swizzles(desc->swizzle, user_swizzle, composed_swizzle);
878
879 unsigned size = panfrost_estimate_texture_payload_size(
880 so->base.u.tex.first_level,
881 so->base.u.tex.last_level,
882 so->base.u.tex.first_layer,
883 so->base.u.tex.last_layer,
884 texture->nr_samples,
885 type, prsrc->modifier);
886
887 so->bo = panfrost_bo_create(device, size, 0);
888
889 panfrost_new_texture_bifrost(
890 &so->bifrost_descriptor,
891 texture->width0, texture->height0,
892 depth, array_size,
893 format,
894 type, prsrc->modifier,
895 so->base.u.tex.first_level,
896 so->base.u.tex.last_level,
897 so->base.u.tex.first_layer,
898 so->base.u.tex.last_layer,
899 texture->nr_samples,
900 prsrc->cubemap_stride,
901 panfrost_translate_swizzle_4(composed_swizzle),
902 prsrc->bo->gpu,
903 prsrc->slices,
904 so->bo);
905 } else {
906 unsigned size = panfrost_estimate_texture_payload_size(
907 so->base.u.tex.first_level,
908 so->base.u.tex.last_level,
909 so->base.u.tex.first_layer,
910 so->base.u.tex.last_layer,
911 texture->nr_samples,
912 type, prsrc->modifier);
913 size += MALI_MIDGARD_TEXTURE_LENGTH;
914
915 so->bo = panfrost_bo_create(device, size, 0);
916
917 panfrost_new_texture(
918 so->bo->cpu,
919 texture->width0, texture->height0,
920 depth, array_size,
921 format,
922 type, prsrc->modifier,
923 so->base.u.tex.first_level,
924 so->base.u.tex.last_level,
925 so->base.u.tex.first_layer,
926 so->base.u.tex.last_layer,
927 texture->nr_samples,
928 prsrc->cubemap_stride,
929 panfrost_translate_swizzle_4(user_swizzle),
930 prsrc->bo->gpu,
931 prsrc->slices);
932 }
933 }
934
935 static struct pipe_sampler_view *
936 panfrost_create_sampler_view(
937 struct pipe_context *pctx,
938 struct pipe_resource *texture,
939 const struct pipe_sampler_view *template)
940 {
941 struct panfrost_sampler_view *so = rzalloc(pctx, struct panfrost_sampler_view);
942
943 pipe_reference(NULL, &texture->reference);
944
945 so->base = *template;
946 so->base.texture = texture;
947 so->base.reference.count = 1;
948 so->base.context = pctx;
949
950 panfrost_create_sampler_view_bo(so, pctx, texture);
951
952 return (struct pipe_sampler_view *) so;
953 }
954
955 static void
956 panfrost_set_sampler_views(
957 struct pipe_context *pctx,
958 enum pipe_shader_type shader,
959 unsigned start_slot, unsigned num_views,
960 struct pipe_sampler_view **views)
961 {
962 struct panfrost_context *ctx = pan_context(pctx);
963 unsigned new_nr = 0;
964 unsigned i;
965
966 assert(start_slot == 0);
967
968 for (i = 0; i < num_views; ++i) {
969 if (views[i])
970 new_nr = i + 1;
971 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
972 views[i]);
973 }
974
975 for (; i < ctx->sampler_view_count[shader]; i++) {
976 pipe_sampler_view_reference((struct pipe_sampler_view **)&ctx->sampler_views[shader][i],
977 NULL);
978 }
979 ctx->sampler_view_count[shader] = new_nr;
980 }
981
982 static void
983 panfrost_sampler_view_destroy(
984 struct pipe_context *pctx,
985 struct pipe_sampler_view *pview)
986 {
987 struct panfrost_sampler_view *view = (struct panfrost_sampler_view *) pview;
988
989 pipe_resource_reference(&pview->texture, NULL);
990 panfrost_bo_unreference(view->bo);
991 ralloc_free(view);
992 }
993
994 static void
995 panfrost_set_shader_buffers(
996 struct pipe_context *pctx,
997 enum pipe_shader_type shader,
998 unsigned start, unsigned count,
999 const struct pipe_shader_buffer *buffers,
1000 unsigned writable_bitmask)
1001 {
1002 struct panfrost_context *ctx = pan_context(pctx);
1003
1004 util_set_shader_buffers_mask(ctx->ssbo[shader], &ctx->ssbo_mask[shader],
1005 buffers, start, count);
1006 }
1007
1008 static void
1009 panfrost_set_framebuffer_state(struct pipe_context *pctx,
1010 const struct pipe_framebuffer_state *fb)
1011 {
1012 struct panfrost_context *ctx = pan_context(pctx);
1013
1014 util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb);
1015 ctx->batch = NULL;
1016
1017 /* We may need to generate a new variant if the fragment shader is
1018 * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */
1019 struct panfrost_shader_variants *fs = ctx->shader[PIPE_SHADER_FRAGMENT];
1020
1021 if (fs && fs->variant_count && fs->variants[fs->active_variant].outputs_read)
1022 ctx->base.bind_fs_state(&ctx->base, fs);
1023 }
1024
1025 static inline unsigned
1026 pan_pipe_to_stencil_op(enum pipe_stencil_op in)
1027 {
1028 switch (in) {
1029 case PIPE_STENCIL_OP_KEEP: return MALI_STENCIL_OP_KEEP;
1030 case PIPE_STENCIL_OP_ZERO: return MALI_STENCIL_OP_ZERO;
1031 case PIPE_STENCIL_OP_REPLACE: return MALI_STENCIL_OP_REPLACE;
1032 case PIPE_STENCIL_OP_INCR: return MALI_STENCIL_OP_INCR_SAT;
1033 case PIPE_STENCIL_OP_DECR: return MALI_STENCIL_OP_DECR_SAT;
1034 case PIPE_STENCIL_OP_INCR_WRAP: return MALI_STENCIL_OP_INCR_WRAP;
1035 case PIPE_STENCIL_OP_DECR_WRAP: return MALI_STENCIL_OP_DECR_WRAP;
1036 case PIPE_STENCIL_OP_INVERT: return MALI_STENCIL_OP_INVERT;
1037 default: unreachable("Invalid stencil op");
1038 }
1039 }
1040
1041 static inline void
1042 pan_pipe_to_stencil(const struct pipe_stencil_state *in, void *out)
1043 {
1044 pan_pack(out, STENCIL, cfg) {
1045 cfg.mask = in->valuemask;
1046 cfg.compare_function = panfrost_translate_compare_func(in->func);
1047 cfg.stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
1048 cfg.depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
1049 cfg.depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
1050 }
1051 }
1052
1053 static void *
1054 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
1055 const struct pipe_depth_stencil_alpha_state *zsa)
1056 {
1057 struct panfrost_zsa_state *so = CALLOC_STRUCT(panfrost_zsa_state);
1058 so->base = *zsa;
1059
1060 pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
1061 pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
1062
1063 so->stencil_mask_front = zsa->stencil[0].writemask;
1064
1065 if (zsa->stencil[1].enabled)
1066 so->stencil_mask_back = zsa->stencil[1].writemask;
1067 else
1068 so->stencil_mask_back = so->stencil_mask_front;
1069
1070 /* Alpha lowered by frontend */
1071 assert(!zsa->alpha.enabled);
1072
1073 /* TODO: Bounds test should be easy */
1074 assert(!zsa->depth.bounds_test);
1075
1076 return so;
1077 }
1078
1079 static void
1080 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
1081 void *cso)
1082 {
1083 struct panfrost_context *ctx = pan_context(pipe);
1084 struct panfrost_zsa_state *zsa = cso;
1085 ctx->depth_stencil = zsa;
1086 }
1087
1088 static void
1089 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
1090 {
1091 free( depth );
1092 }
1093
1094 static void
1095 panfrost_set_sample_mask(struct pipe_context *pipe,
1096 unsigned sample_mask)
1097 {
1098 struct panfrost_context *ctx = pan_context(pipe);
1099 ctx->sample_mask = sample_mask;
1100 }
1101
1102 static void
1103 panfrost_set_min_samples(struct pipe_context *pipe,
1104 unsigned min_samples)
1105 {
1106 struct panfrost_context *ctx = pan_context(pipe);
1107 ctx->min_samples = min_samples;
1108 }
1109
1110
1111 static void
1112 panfrost_set_clip_state(struct pipe_context *pipe,
1113 const struct pipe_clip_state *clip)
1114 {
1115 //struct panfrost_context *panfrost = pan_context(pipe);
1116 }
1117
1118 static void
1119 panfrost_set_viewport_states(struct pipe_context *pipe,
1120 unsigned start_slot,
1121 unsigned num_viewports,
1122 const struct pipe_viewport_state *viewports)
1123 {
1124 struct panfrost_context *ctx = pan_context(pipe);
1125
1126 assert(start_slot == 0);
1127 assert(num_viewports == 1);
1128
1129 ctx->pipe_viewport = *viewports;
1130 }
1131
1132 static void
1133 panfrost_set_scissor_states(struct pipe_context *pipe,
1134 unsigned start_slot,
1135 unsigned num_scissors,
1136 const struct pipe_scissor_state *scissors)
1137 {
1138 struct panfrost_context *ctx = pan_context(pipe);
1139
1140 assert(start_slot == 0);
1141 assert(num_scissors == 1);
1142
1143 ctx->scissor = *scissors;
1144 }
1145
1146 static void
1147 panfrost_set_polygon_stipple(struct pipe_context *pipe,
1148 const struct pipe_poly_stipple *stipple)
1149 {
1150 //struct panfrost_context *panfrost = pan_context(pipe);
1151 }
1152
1153 static void
1154 panfrost_set_active_query_state(struct pipe_context *pipe,
1155 bool enable)
1156 {
1157 struct panfrost_context *ctx = pan_context(pipe);
1158 ctx->active_queries = enable;
1159 }
1160
1161 static void
1162 panfrost_destroy(struct pipe_context *pipe)
1163 {
1164 struct panfrost_context *panfrost = pan_context(pipe);
1165
1166 if (panfrost->blitter)
1167 util_blitter_destroy(panfrost->blitter);
1168
1169 if (panfrost->blitter_wallpaper)
1170 util_blitter_destroy(panfrost->blitter_wallpaper);
1171
1172 util_unreference_framebuffer_state(&panfrost->pipe_framebuffer);
1173 u_upload_destroy(pipe->stream_uploader);
1174
1175 ralloc_free(pipe);
1176 }
1177
1178 static struct pipe_query *
1179 panfrost_create_query(struct pipe_context *pipe,
1180 unsigned type,
1181 unsigned index)
1182 {
1183 struct panfrost_query *q = rzalloc(pipe, struct panfrost_query);
1184
1185 q->type = type;
1186 q->index = index;
1187
1188 return (struct pipe_query *) q;
1189 }
1190
1191 static void
1192 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
1193 {
1194 struct panfrost_query *query = (struct panfrost_query *) q;
1195
1196 if (query->bo) {
1197 panfrost_bo_unreference(query->bo);
1198 query->bo = NULL;
1199 }
1200
1201 ralloc_free(q);
1202 }
1203
1204 static bool
1205 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
1206 {
1207 struct panfrost_context *ctx = pan_context(pipe);
1208 struct panfrost_query *query = (struct panfrost_query *) q;
1209
1210 switch (query->type) {
1211 case PIPE_QUERY_OCCLUSION_COUNTER:
1212 case PIPE_QUERY_OCCLUSION_PREDICATE:
1213 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1214 /* Allocate a bo for the query results to be stored */
1215 if (!query->bo) {
1216 query->bo = panfrost_bo_create(
1217 pan_device(ctx->base.screen),
1218 sizeof(unsigned), 0);
1219 }
1220
1221 unsigned *result = (unsigned *)query->bo->cpu;
1222 *result = 0; /* Default to 0 if nothing at all drawn. */
1223 ctx->occlusion_query = query;
1224 break;
1225
1226 /* Geometry statistics are computed in the driver. XXX: geom/tess
1227 * shaders.. */
1228
1229 case PIPE_QUERY_PRIMITIVES_GENERATED:
1230 query->start = ctx->prims_generated;
1231 break;
1232 case PIPE_QUERY_PRIMITIVES_EMITTED:
1233 query->start = ctx->tf_prims_generated;
1234 break;
1235
1236 default:
1237 /* TODO: timestamp queries, etc? */
1238 break;
1239 }
1240
1241 return true;
1242 }
1243
1244 static bool
1245 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
1246 {
1247 struct panfrost_context *ctx = pan_context(pipe);
1248 struct panfrost_query *query = (struct panfrost_query *) q;
1249
1250 switch (query->type) {
1251 case PIPE_QUERY_OCCLUSION_COUNTER:
1252 case PIPE_QUERY_OCCLUSION_PREDICATE:
1253 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1254 ctx->occlusion_query = NULL;
1255 break;
1256 case PIPE_QUERY_PRIMITIVES_GENERATED:
1257 query->end = ctx->prims_generated;
1258 break;
1259 case PIPE_QUERY_PRIMITIVES_EMITTED:
1260 query->end = ctx->tf_prims_generated;
1261 break;
1262 }
1263
1264 return true;
1265 }
1266
1267 static bool
1268 panfrost_get_query_result(struct pipe_context *pipe,
1269 struct pipe_query *q,
1270 bool wait,
1271 union pipe_query_result *vresult)
1272 {
1273 struct panfrost_query *query = (struct panfrost_query *) q;
1274 struct panfrost_context *ctx = pan_context(pipe);
1275
1276
1277 switch (query->type) {
1278 case PIPE_QUERY_OCCLUSION_COUNTER:
1279 case PIPE_QUERY_OCCLUSION_PREDICATE:
1280 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1281 panfrost_flush_batches_accessing_bo(ctx, query->bo, false);
1282 panfrost_bo_wait(query->bo, INT64_MAX, false);
1283
1284 /* Read back the query results */
1285 unsigned *result = (unsigned *) query->bo->cpu;
1286 unsigned passed = *result;
1287
1288 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1289 vresult->u64 = passed;
1290 } else {
1291 vresult->b = !!passed;
1292 }
1293
1294 break;
1295
1296 case PIPE_QUERY_PRIMITIVES_GENERATED:
1297 case PIPE_QUERY_PRIMITIVES_EMITTED:
1298 panfrost_flush_all_batches(ctx, 0);
1299 vresult->u64 = query->end - query->start;
1300 break;
1301
1302 default:
1303 /* TODO: more queries */
1304 break;
1305 }
1306
1307 return true;
1308 }
1309
1310 static struct pipe_stream_output_target *
1311 panfrost_create_stream_output_target(struct pipe_context *pctx,
1312 struct pipe_resource *prsc,
1313 unsigned buffer_offset,
1314 unsigned buffer_size)
1315 {
1316 struct pipe_stream_output_target *target;
1317
1318 target = rzalloc(pctx, struct pipe_stream_output_target);
1319
1320 if (!target)
1321 return NULL;
1322
1323 pipe_reference_init(&target->reference, 1);
1324 pipe_resource_reference(&target->buffer, prsc);
1325
1326 target->context = pctx;
1327 target->buffer_offset = buffer_offset;
1328 target->buffer_size = buffer_size;
1329
1330 return target;
1331 }
1332
1333 static void
1334 panfrost_stream_output_target_destroy(struct pipe_context *pctx,
1335 struct pipe_stream_output_target *target)
1336 {
1337 pipe_resource_reference(&target->buffer, NULL);
1338 ralloc_free(target);
1339 }
1340
1341 static void
1342 panfrost_set_stream_output_targets(struct pipe_context *pctx,
1343 unsigned num_targets,
1344 struct pipe_stream_output_target **targets,
1345 const unsigned *offsets)
1346 {
1347 struct panfrost_context *ctx = pan_context(pctx);
1348 struct panfrost_streamout *so = &ctx->streamout;
1349
1350 assert(num_targets <= ARRAY_SIZE(so->targets));
1351
1352 for (unsigned i = 0; i < num_targets; i++) {
1353 if (offsets[i] != -1)
1354 so->offsets[i] = offsets[i];
1355
1356 pipe_so_target_reference(&so->targets[i], targets[i]);
1357 }
1358
1359 for (unsigned i = 0; i < so->num_targets; i++)
1360 pipe_so_target_reference(&so->targets[i], NULL);
1361
1362 so->num_targets = num_targets;
1363 }
1364
1365 struct pipe_context *
1366 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
1367 {
1368 struct panfrost_context *ctx = rzalloc(screen, struct panfrost_context);
1369 struct pipe_context *gallium = (struct pipe_context *) ctx;
1370 struct panfrost_device *dev = pan_device(screen);
1371
1372 gallium->screen = screen;
1373
1374 gallium->destroy = panfrost_destroy;
1375
1376 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
1377
1378 gallium->flush = panfrost_flush;
1379 gallium->clear = panfrost_clear;
1380 gallium->draw_vbo = panfrost_draw_vbo;
1381 gallium->texture_barrier = panfrost_texture_barrier;
1382
1383 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
1384 gallium->set_constant_buffer = panfrost_set_constant_buffer;
1385 gallium->set_shader_buffers = panfrost_set_shader_buffers;
1386
1387 gallium->set_stencil_ref = panfrost_set_stencil_ref;
1388
1389 gallium->create_sampler_view = panfrost_create_sampler_view;
1390 gallium->set_sampler_views = panfrost_set_sampler_views;
1391 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
1392
1393 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
1394 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
1395 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
1396
1397 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
1398 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
1399 gallium->delete_vertex_elements_state = panfrost_generic_cso_delete;
1400
1401 gallium->create_fs_state = panfrost_create_fs_state;
1402 gallium->delete_fs_state = panfrost_delete_shader_state;
1403 gallium->bind_fs_state = panfrost_bind_fs_state;
1404
1405 gallium->create_vs_state = panfrost_create_vs_state;
1406 gallium->delete_vs_state = panfrost_delete_shader_state;
1407 gallium->bind_vs_state = panfrost_bind_vs_state;
1408
1409 gallium->create_sampler_state = panfrost_create_sampler_state;
1410 gallium->delete_sampler_state = panfrost_generic_cso_delete;
1411 gallium->bind_sampler_states = panfrost_bind_sampler_states;
1412
1413 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
1414 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
1415 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
1416
1417 gallium->set_sample_mask = panfrost_set_sample_mask;
1418 gallium->set_min_samples = panfrost_set_min_samples;
1419
1420 gallium->set_clip_state = panfrost_set_clip_state;
1421 gallium->set_viewport_states = panfrost_set_viewport_states;
1422 gallium->set_scissor_states = panfrost_set_scissor_states;
1423 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
1424 gallium->set_active_query_state = panfrost_set_active_query_state;
1425
1426 gallium->create_query = panfrost_create_query;
1427 gallium->destroy_query = panfrost_destroy_query;
1428 gallium->begin_query = panfrost_begin_query;
1429 gallium->end_query = panfrost_end_query;
1430 gallium->get_query_result = panfrost_get_query_result;
1431
1432 gallium->create_stream_output_target = panfrost_create_stream_output_target;
1433 gallium->stream_output_target_destroy = panfrost_stream_output_target_destroy;
1434 gallium->set_stream_output_targets = panfrost_set_stream_output_targets;
1435
1436 panfrost_resource_context_init(gallium);
1437 panfrost_blend_context_init(gallium);
1438 panfrost_compute_context_init(gallium);
1439
1440 gallium->stream_uploader = u_upload_create_default(gallium);
1441 gallium->const_uploader = gallium->stream_uploader;
1442 assert(gallium->stream_uploader);
1443
1444 /* All of our GPUs support ES mode. Midgard supports additionally
1445 * QUADS/QUAD_STRIPS/POLYGON. Bifrost supports just QUADS. */
1446
1447 ctx->draw_modes = (1 << (PIPE_PRIM_QUADS + 1)) - 1;
1448
1449 if (!(dev->quirks & IS_BIFROST)) {
1450 ctx->draw_modes |= (1 << PIPE_PRIM_QUAD_STRIP);
1451 ctx->draw_modes |= (1 << PIPE_PRIM_POLYGON);
1452 }
1453
1454 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
1455
1456 ctx->blitter = util_blitter_create(gallium);
1457 ctx->blitter_wallpaper = util_blitter_create(gallium);
1458
1459 assert(ctx->blitter);
1460 assert(ctx->blitter_wallpaper);
1461
1462 /* Prepare for render! */
1463
1464 panfrost_batch_init(ctx);
1465
1466 if (!(dev->quirks & IS_BIFROST)) {
1467 for (unsigned c = 0; c < PIPE_MAX_COLOR_BUFS; ++c)
1468 ctx->blit_blend.rt[c].shaders = _mesa_hash_table_u64_create(ctx);
1469 }
1470
1471 /* By default mask everything on */
1472 ctx->sample_mask = ~0;
1473 ctx->active_queries = true;
1474
1475 return gallium;
1476 }