2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "pan_context.h"
31 #include "pan_format.h"
33 #include "util/macros.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_memory.h"
38 #include "util/u_vbuf.h"
39 #include "util/half_float.h"
40 #include "util/u_helpers.h"
41 #include "util/u_format.h"
42 #include "util/u_prim.h"
43 #include "util/u_prim_restart.h"
44 #include "indices/u_primconvert.h"
45 #include "tgsi/tgsi_parse.h"
46 #include "tgsi/tgsi_from_mesa.h"
47 #include "util/u_math.h"
49 #include "pan_screen.h"
50 #include "pan_blending.h"
51 #include "pan_blend_shaders.h"
54 /* Framebuffer descriptor */
56 static struct midgard_tiler_descriptor
57 panfrost_emit_midg_tiler(
58 struct panfrost_context
*ctx
,
61 unsigned vertex_count
)
63 struct midgard_tiler_descriptor t
= {};
64 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
67 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
69 /* Compute the polygon header size and use that to offset the body */
71 unsigned header_size
= panfrost_tiler_header_size(
72 width
, height
, t
.hierarchy_mask
);
74 t
.polygon_list_size
= panfrost_tiler_full_size(
75 width
, height
, t
.hierarchy_mask
);
79 if (t
.hierarchy_mask
) {
80 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
85 /* Allow the entire tiler heap */
86 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
88 ctx
->tiler_heap
.bo
->gpu
+ ctx
->tiler_heap
.bo
->size
;
90 /* The tiler is disabled, so don't allow the tiler heap */
91 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
92 t
.heap_end
= t
.heap_start
;
94 /* Use a dummy polygon list */
95 t
.polygon_list
= ctx
->tiler_dummy
.bo
->gpu
;
97 /* Disable the tiler */
98 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
101 t
.polygon_list_body
=
102 t
.polygon_list
+ header_size
;
107 struct mali_single_framebuffer
108 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
110 unsigned width
= ctx
->pipe_framebuffer
.width
;
111 unsigned height
= ctx
->pipe_framebuffer
.height
;
113 struct mali_single_framebuffer framebuffer
= {
114 .width
= MALI_POSITIVE(width
),
115 .height
= MALI_POSITIVE(height
),
117 .format
= 0x30000000,
118 .clear_flags
= 0x1000,
119 .unknown_address_0
= ctx
->scratchpad
.bo
->gpu
,
120 .tiler
= panfrost_emit_midg_tiler(ctx
,
121 width
, height
, vertex_count
),
127 struct bifrost_framebuffer
128 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
130 unsigned width
= ctx
->pipe_framebuffer
.width
;
131 unsigned height
= ctx
->pipe_framebuffer
.height
;
133 struct bifrost_framebuffer framebuffer
= {
134 .unk0
= 0x1e5, /* 1e4 if no spill */
135 .width1
= MALI_POSITIVE(width
),
136 .height1
= MALI_POSITIVE(height
),
137 .width2
= MALI_POSITIVE(width
),
138 .height2
= MALI_POSITIVE(height
),
142 .rt_count_1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.nr_cbufs
),
147 .scratchpad
= ctx
->scratchpad
.bo
->gpu
,
148 .tiler
= panfrost_emit_midg_tiler(ctx
,
149 width
, height
, vertex_count
)
155 /* Are we currently rendering to the screen (rather than an FBO)? */
158 panfrost_is_scanout(struct panfrost_context
*ctx
)
160 /* If there is no color buffer, it's an FBO */
161 if (ctx
->pipe_framebuffer
.nr_cbufs
!= 1)
164 /* If we're too early that no framebuffer was sent, it's scanout */
165 if (!ctx
->pipe_framebuffer
.cbufs
[0])
168 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
169 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
170 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
175 struct pipe_context
*pipe
,
177 const union pipe_color_union
*color
,
178 double depth
, unsigned stencil
)
180 struct panfrost_context
*ctx
= pan_context(pipe
);
181 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
183 panfrost_batch_clear(ctx
, batch
, buffers
, color
, depth
, stencil
);
187 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
189 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(ctx
, ~0);
191 return panfrost_upload_transient(ctx
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
195 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
197 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(ctx
, ~0);
199 return panfrost_upload_transient(ctx
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
203 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
205 /* Skip the attach if we can */
207 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
208 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
212 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
213 mali_ptr framebuffer
= screen
->require_sfbd
?
214 panfrost_attach_vt_sfbd(ctx
) :
215 panfrost_attach_vt_mfbd(ctx
);
217 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
218 ctx
->payloads
[i
].postfix
.framebuffer
= framebuffer
;
221 /* Reset per-frame context, called on context initialisation as well as after
222 * flushing a frame */
225 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
227 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
228 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
231 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
234 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
236 /* TODO: When does this need to be handled? */
237 ctx
->active_queries
= true;
240 /* In practice, every field of these payloads should be configurable
241 * arbitrarily, which means these functions are basically catch-all's for
242 * as-of-yet unwavering unknowns */
245 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
247 /* 0x2 bit clear on 32-bit T6XX */
249 struct midgard_payload_vertex_tiler payload
= {
250 .gl_enables
= 0x4 | 0x2,
253 /* Vertex and compute are closely coupled, so share a payload */
255 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
256 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
260 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
262 struct midgard_payload_vertex_tiler payload
= {
264 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
268 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
272 translate_tex_wrap(enum pipe_tex_wrap w
)
275 case PIPE_TEX_WRAP_REPEAT
:
276 return MALI_WRAP_REPEAT
;
278 /* TODO: lower GL_CLAMP? */
279 case PIPE_TEX_WRAP_CLAMP
:
280 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
281 return MALI_WRAP_CLAMP_TO_EDGE
;
283 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
284 return MALI_WRAP_CLAMP_TO_BORDER
;
286 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
287 return MALI_WRAP_MIRRORED_REPEAT
;
290 unreachable("Invalid wrap");
295 panfrost_translate_compare_func(enum pipe_compare_func in
)
298 case PIPE_FUNC_NEVER
:
299 return MALI_FUNC_NEVER
;
302 return MALI_FUNC_LESS
;
304 case PIPE_FUNC_EQUAL
:
305 return MALI_FUNC_EQUAL
;
307 case PIPE_FUNC_LEQUAL
:
308 return MALI_FUNC_LEQUAL
;
310 case PIPE_FUNC_GREATER
:
311 return MALI_FUNC_GREATER
;
313 case PIPE_FUNC_NOTEQUAL
:
314 return MALI_FUNC_NOTEQUAL
;
316 case PIPE_FUNC_GEQUAL
:
317 return MALI_FUNC_GEQUAL
;
319 case PIPE_FUNC_ALWAYS
:
320 return MALI_FUNC_ALWAYS
;
323 unreachable("Invalid func");
328 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
331 case PIPE_FUNC_NEVER
:
332 return MALI_ALT_FUNC_NEVER
;
335 return MALI_ALT_FUNC_LESS
;
337 case PIPE_FUNC_EQUAL
:
338 return MALI_ALT_FUNC_EQUAL
;
340 case PIPE_FUNC_LEQUAL
:
341 return MALI_ALT_FUNC_LEQUAL
;
343 case PIPE_FUNC_GREATER
:
344 return MALI_ALT_FUNC_GREATER
;
346 case PIPE_FUNC_NOTEQUAL
:
347 return MALI_ALT_FUNC_NOTEQUAL
;
349 case PIPE_FUNC_GEQUAL
:
350 return MALI_ALT_FUNC_GEQUAL
;
352 case PIPE_FUNC_ALWAYS
:
353 return MALI_ALT_FUNC_ALWAYS
;
356 unreachable("Invalid alt func");
361 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
364 case PIPE_STENCIL_OP_KEEP
:
365 return MALI_STENCIL_KEEP
;
367 case PIPE_STENCIL_OP_ZERO
:
368 return MALI_STENCIL_ZERO
;
370 case PIPE_STENCIL_OP_REPLACE
:
371 return MALI_STENCIL_REPLACE
;
373 case PIPE_STENCIL_OP_INCR
:
374 return MALI_STENCIL_INCR
;
376 case PIPE_STENCIL_OP_DECR
:
377 return MALI_STENCIL_DECR
;
379 case PIPE_STENCIL_OP_INCR_WRAP
:
380 return MALI_STENCIL_INCR_WRAP
;
382 case PIPE_STENCIL_OP_DECR_WRAP
:
383 return MALI_STENCIL_DECR_WRAP
;
385 case PIPE_STENCIL_OP_INVERT
:
386 return MALI_STENCIL_INVERT
;
389 unreachable("Invalid stencil op");
394 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
396 out
->ref
= 0; /* Gallium gets it from elsewhere */
398 out
->mask
= in
->valuemask
;
399 out
->func
= panfrost_translate_compare_func(in
->func
);
400 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
401 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
402 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
406 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
408 struct mali_shader_meta shader
= {
409 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
411 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
412 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
415 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
416 * required (independent of 32-bit/64-bit descriptors), or why it's not
417 * used on later GPU revisions. Otherwise, all shader jobs fault on
418 * these earlier chips (perhaps this is a chicken bit of some kind).
419 * More investigation is needed. */
422 shader
.unknown2_4
|= 0x10;
425 struct pipe_stencil_state default_stencil
= {
427 .func
= PIPE_FUNC_ALWAYS
,
428 .fail_op
= MALI_STENCIL_KEEP
,
429 .zfail_op
= MALI_STENCIL_KEEP
,
430 .zpass_op
= MALI_STENCIL_KEEP
,
435 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
436 shader
.stencil_mask_front
= default_stencil
.writemask
;
438 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
439 shader
.stencil_mask_back
= default_stencil
.writemask
;
441 if (default_stencil
.enabled
)
442 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
444 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
447 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
448 * graphics command stream. It should be called once per draw, accordding to
449 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
450 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
453 struct panfrost_transfer
454 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
456 struct mali_job_descriptor_header job
= {
457 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
458 .job_descriptor_size
= 1,
461 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
463 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
464 memcpy(transfer
.cpu
, &job
, sizeof(job
));
465 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
470 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
472 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
473 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
475 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
479 panfrost_writes_point_size(struct panfrost_context
*ctx
)
481 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
482 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
484 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
487 /* Stage the attribute descriptors so we can adjust src_offset
488 * to let BOs align nicely */
491 panfrost_stage_attributes(struct panfrost_context
*ctx
)
493 struct panfrost_vertex_state
*so
= ctx
->vertex
;
495 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
496 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
497 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
499 /* Copy as-is for the first pass */
500 memcpy(target
, so
->hw
, sz
);
502 /* Fixup offsets for the second pass. Recall that the hardware
503 * calculates attribute addresses as:
505 * addr = base + (stride * vtx) + src_offset;
507 * However, on Mali, base must be aligned to 64-bytes, so we
510 * base' = base & ~63 = base - (base & 63)
512 * To compensate when using base' (see emit_vertex_data), we have
513 * to adjust src_offset by the masked off piece:
515 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
516 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
517 * = base + (stride * vtx) + src_offset
523 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
525 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
526 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
527 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
528 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
530 /* Adjust by the masked off bits of the offset */
531 target
[i
].src_offset
+= (addr
& 63);
533 /* Also, somewhat obscurely per-instance data needs to be
534 * offset in response to a delayed start in an indexed draw */
536 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
537 target
[i
].src_offset
-= buf
->stride
* start
;
543 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
547 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
549 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
551 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
554 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
555 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
557 struct panfrost_transfer transfer
=
558 panfrost_allocate_transient(ctx
, transfer_size
);
560 struct mali_sampler_descriptor
*desc
=
561 (struct mali_sampler_descriptor
*) transfer
.cpu
;
563 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
564 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
566 upload
= transfer
.gpu
;
569 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
573 static enum mali_texture_layout
574 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
576 /* TODO: other linear depth textures */
577 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
579 switch (rsrc
->layout
) {
581 return MALI_TEXTURE_AFBC
;
584 return MALI_TEXTURE_TILED
;
586 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
588 unreachable("Invalid texture layout");
594 struct panfrost_context
*ctx
,
595 struct panfrost_sampler_view
*view
)
600 struct pipe_sampler_view
*pview
= &view
->base
;
601 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
603 /* Do we interleave an explicit stride with every element? */
605 bool has_manual_stride
= view
->manual_stride
;
607 /* For easy access */
609 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
610 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
611 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
612 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
613 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
615 /* Lower-bit is set when sampling from colour AFBC */
616 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
617 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
618 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
620 /* Add the BO to the job so it's retained until the job is done. */
621 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
622 panfrost_batch_add_bo(batch
, rsrc
->bo
);
624 /* Add the usage flags in, since they can change across the CSO
625 * lifetime due to layout switches */
627 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
628 view
->hw
.format
.manual_stride
= has_manual_stride
;
630 /* Inject the addresses in, interleaving mip levels, cube faces, and
631 * strides in that order */
635 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
636 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
638 view
->hw
.payload
[idx
++] =
639 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
641 if (has_manual_stride
) {
642 view
->hw
.payload
[idx
++] =
643 rsrc
->slices
[l
].stride
;
648 return panfrost_upload_transient(ctx
, &view
->hw
,
649 sizeof(struct mali_texture_descriptor
));
653 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
655 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
656 mali_ptr trampoline
= 0;
658 if (ctx
->sampler_view_count
[t
]) {
659 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
661 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
663 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
665 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
668 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
672 struct sysval_uniform
{
681 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
682 struct sysval_uniform
*uniform
)
684 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
686 uniform
->f
[0] = vp
->scale
[0];
687 uniform
->f
[1] = vp
->scale
[1];
688 uniform
->f
[2] = vp
->scale
[2];
691 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
692 struct sysval_uniform
*uniform
)
694 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
696 uniform
->f
[0] = vp
->translate
[0];
697 uniform
->f
[1] = vp
->translate
[1];
698 uniform
->f
[2] = vp
->translate
[2];
701 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
702 enum pipe_shader_type st
,
703 unsigned int sysvalid
,
704 struct sysval_uniform
*uniform
)
706 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
707 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
708 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
709 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
712 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
715 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
716 tex
->u
.tex
.first_level
);
719 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
720 tex
->u
.tex
.first_level
);
723 uniform
->i
[dim
] = tex
->texture
->array_size
;
726 static void panfrost_upload_ssbo_sysval(
727 struct panfrost_context
*ctx
,
728 enum pipe_shader_type st
,
730 struct sysval_uniform
*uniform
)
732 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
733 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
735 /* Compute address */
736 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
737 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
739 panfrost_batch_add_bo(batch
, bo
);
741 /* Upload address and size as sysval */
742 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
743 uniform
->u
[2] = sb
.buffer_size
;
746 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
747 struct sysval_uniform
*uniform
)
749 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
750 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
751 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
754 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
755 struct panfrost_shader_state
*ss
,
756 enum pipe_shader_type st
)
758 struct sysval_uniform
*uniforms
= (void *)buf
;
760 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
761 int sysval
= ss
->sysval
[i
];
763 switch (PAN_SYSVAL_TYPE(sysval
)) {
764 case PAN_SYSVAL_VIEWPORT_SCALE
:
765 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
767 case PAN_SYSVAL_VIEWPORT_OFFSET
:
768 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
770 case PAN_SYSVAL_TEXTURE_SIZE
:
771 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
774 case PAN_SYSVAL_SSBO
:
775 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
778 case PAN_SYSVAL_NUM_WORK_GROUPS
:
779 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
789 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
791 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
792 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
795 return rsrc
->bo
->cpu
;
796 else if (cb
->user_buffer
)
797 return cb
->user_buffer
;
799 unreachable("No constant buffer");
803 panfrost_map_constant_buffer_gpu(
804 struct panfrost_context
*ctx
,
805 struct panfrost_constant_buffer
*buf
,
808 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
809 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
812 return rsrc
->bo
->gpu
;
813 else if (cb
->user_buffer
)
814 return panfrost_upload_transient(ctx
, cb
->user_buffer
, cb
->buffer_size
);
816 unreachable("No constant buffer");
819 /* Compute number of UBOs active (more specifically, compute the highest UBO
820 * number addressable -- if there are gaps, include them in the count anyway).
821 * We always include UBO #0 in the count, since we *need* uniforms enabled for
825 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
827 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
828 return 32 - __builtin_clz(mask
);
831 /* Fixes up a shader state with current state, returning a GPU address to the
835 panfrost_patch_shader_state(
836 struct panfrost_context
*ctx
,
837 struct panfrost_shader_state
*ss
,
838 enum pipe_shader_type stage
,
841 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
842 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
844 ss
->tripipe
->midgard1
.flags
= 0x220;
846 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
847 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
849 /* We can't reuse over frames; that's not safe. The descriptor must be
850 * transient uploaded */
853 return panfrost_upload_transient(ctx
,
855 sizeof(struct mali_shader_meta
));
858 /* If we don't need an upload, don't bother */
864 panfrost_patch_shader_state_compute(
865 struct panfrost_context
*ctx
,
866 enum pipe_shader_type stage
,
869 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
872 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
876 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
878 ctx
->payloads
[stage
].postfix
._shader_upper
=
879 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
882 /* Go through dirty flags and actualise them in the cmdstream. */
885 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
887 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
888 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
890 panfrost_attach_vt_framebuffer(ctx
);
892 if (with_vertex_data
) {
893 panfrost_emit_vertex_data(batch
);
895 /* Varyings emitted for -all- geometry */
896 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
897 panfrost_emit_varying_descriptor(ctx
, total_count
);
900 bool msaa
= ctx
->rasterizer
->base
.multisample
;
902 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
903 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
905 /* TODO: Sample size */
906 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
907 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
910 panfrost_batch_set_requirements(ctx
, batch
);
912 if (ctx
->occlusion_query
) {
913 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
914 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
917 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
918 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
920 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
921 /* Check if we need to link the gl_PointSize varying */
922 if (!panfrost_writes_point_size(ctx
)) {
923 /* If the size is constant, write it out. Otherwise,
924 * don't touch primitive_size (since we would clobber
925 * the pointer there) */
927 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
931 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
932 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
933 ctx
->dirty
|= PAN_DIRTY_FS
;
935 if (ctx
->dirty
& PAN_DIRTY_FS
) {
936 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
937 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
939 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
941 panfrost_batch_add_bo(batch
, variant
->bo
);
943 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
946 COPY(attribute_count
);
950 COPY(midgard1
.uniform_count
);
951 COPY(midgard1
.uniform_buffer_count
);
952 COPY(midgard1
.work_count
);
953 COPY(midgard1
.flags
);
954 COPY(midgard1
.unknown2
);
958 /* Get blending setup */
959 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
961 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
963 for (unsigned c
= 0; c
< rt_count
; ++c
)
964 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
966 /* If there is a blend shader, work registers are shared. XXX: opt */
968 for (unsigned c
= 0; c
< rt_count
; ++c
) {
969 if (blend
[c
].is_shader
)
970 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
973 /* Set late due to depending on render state */
974 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
976 /* Depending on whether it's legal to in the given shader, we
977 * try to enable early-z testing (or forward-pixel kill?) */
979 if (!variant
->can_discard
)
980 flags
|= MALI_EARLY_Z
;
982 /* Any time texturing is used, derivatives are implicitly
983 * calculated, so we need to enable helper invocations */
985 if (variant
->helper_invocations
)
986 flags
|= MALI_HELPER_INVOCATIONS
;
988 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
990 /* Assign the stencil refs late */
992 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
993 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
994 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
996 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
997 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
999 /* CAN_DISCARD should be set if the fragment shader possibly
1000 * contains a 'discard' instruction. It is likely this is
1001 * related to optimizations related to forward-pixel kill, as
1002 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1003 * thing?" by Peter Harris
1006 if (variant
->can_discard
) {
1007 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1008 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1011 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1012 * *also* copied to the blend_meta appended (by convention),
1013 * but this is the field actually read by the hardware. (Or
1014 * maybe both are read...?) */
1016 if (blend
[0].is_shader
) {
1017 ctx
->fragment_shader_core
.blend
.shader
=
1018 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1020 ctx
->fragment_shader_core
.blend
.shader
= 0;
1023 if (screen
->require_sfbd
) {
1024 /* When only a single render target platform is used, the blend
1025 * information is inside the shader meta itself. We
1026 * additionally need to signal CAN_DISCARD for nontrivial blend
1027 * modes (so we're able to read back the destination buffer) */
1029 if (!blend
[0].is_shader
) {
1030 ctx
->fragment_shader_core
.blend
.equation
=
1031 *blend
[0].equation
.equation
;
1032 ctx
->fragment_shader_core
.blend
.constant
=
1033 blend
[0].equation
.constant
;
1036 if (!blend
[0].no_blending
) {
1037 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1041 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1042 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1043 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1045 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1047 if (!screen
->require_sfbd
) {
1048 /* Additional blend descriptor tacked on for jobs using MFBD */
1050 struct midgard_blend_rt rts
[4];
1052 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1053 unsigned blend_count
= 0x200;
1055 if (blend
[i
].is_shader
) {
1056 /* For a blend shader, the bottom nibble corresponds to
1057 * the number of work registers used, which signals the
1058 * -existence- of a blend shader */
1060 assert(blend
[i
].shader
.work_count
>= 2);
1061 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1063 /* Otherwise, the bottom bit simply specifies if
1064 * blending (anything other than REPLACE) is enabled */
1066 if (!blend
[i
].no_blending
)
1072 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1073 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1074 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1076 rts
[i
].flags
= blend_count
;
1079 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1081 if (!ctx
->blend
->base
.dither
)
1082 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1084 /* TODO: sRGB in blend shaders is currently
1085 * unimplemented. Contact me (Alyssa) if you're
1086 * interested in working on this. We have
1087 * native Midgard ops for helping here, but
1088 * they're not well-understood yet. */
1090 assert(!(is_srgb
&& blend
[i
].is_shader
));
1092 if (blend
[i
].is_shader
) {
1093 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1095 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1096 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1100 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1104 /* We stage to transient, so always dirty.. */
1106 panfrost_stage_attributes(ctx
);
1108 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1109 panfrost_upload_sampler_descriptors(ctx
);
1111 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1112 panfrost_upload_texture_descriptors(ctx
);
1114 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1116 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1117 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1122 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1124 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1126 /* Uniforms are implicitly UBO #0 */
1127 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1129 /* Allocate room for the sysval and the uniforms */
1130 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1131 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1132 size_t size
= sys_size
+ uniform_size
;
1133 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1135 /* Upload sysvals requested by the shader */
1136 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1138 /* Upload uniforms */
1140 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1141 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1145 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1147 struct mali_vertex_tiler_postfix
*postfix
=
1148 &ctx
->payloads
[i
].postfix
;
1150 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1153 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1154 assert(ubo_count
>= 1);
1156 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1157 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1159 /* Upload uniforms as a UBO */
1160 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1161 ubos
[0].ptr
= transfer
.gpu
>> 2;
1163 /* The rest are honest-to-goodness UBOs */
1165 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1166 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1168 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1169 bool empty
= usz
== 0;
1171 if (!enabled
|| empty
) {
1172 /* Stub out disabled UBOs to catch accesses */
1175 ubos
[ubo
].ptr
= 0xDEAD0000;
1179 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1181 unsigned bytes_per_field
= 16;
1182 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1183 unsigned fields
= aligned
/ bytes_per_field
;
1185 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1186 ubos
[ubo
].ptr
= gpu
>> 2;
1189 mali_ptr ubufs
= panfrost_upload_transient(ctx
, ubos
, sz
);
1190 postfix
->uniforms
= transfer
.gpu
;
1191 postfix
->uniform_buffers
= ubufs
;
1193 buf
->dirty_mask
= 0;
1196 /* TODO: Upload the viewport somewhere more appropriate */
1198 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1199 * (somewhat) asymmetric ints. */
1200 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1202 struct mali_viewport view
= {
1203 /* By default, do no viewport clipping, i.e. clip to (-inf,
1204 * inf) in each direction. Clipping to the viewport in theory
1205 * should work, but in practice causes issues when we're not
1206 * explicitly trying to scissor */
1208 .clip_minx
= -INFINITY
,
1209 .clip_miny
= -INFINITY
,
1210 .clip_maxx
= INFINITY
,
1211 .clip_maxy
= INFINITY
,
1214 /* Always scissor to the viewport by default. */
1215 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1216 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1218 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1219 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1221 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1222 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1224 /* Apply the scissor test */
1226 unsigned minx
, miny
, maxx
, maxy
;
1228 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1229 minx
= MAX2(ss
->minx
, vp_minx
);
1230 miny
= MAX2(ss
->miny
, vp_miny
);
1231 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1232 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1240 /* Hardware needs the min/max to be strictly ordered, so flip if we
1241 * need to. The viewport transformation in the vertex shader will
1242 * handle the negatives if we don't */
1245 unsigned temp
= miny
;
1251 unsigned temp
= minx
;
1262 /* Clamp to the framebuffer size as a last check */
1264 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1265 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1267 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1268 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1270 /* Update the job, unless we're doing wallpapering (whose lack of
1271 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1272 * just... be faster :) */
1274 if (!ctx
->wallpaper_batch
)
1275 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1279 view
.viewport0
[0] = minx
;
1280 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1282 view
.viewport0
[1] = miny
;
1283 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1285 view
.clip_minz
= minz
;
1286 view
.clip_maxz
= maxz
;
1288 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1289 panfrost_upload_transient(ctx
,
1291 sizeof(struct mali_viewport
));
1296 /* Corresponds to exactly one draw, but does not submit anything */
1299 panfrost_queue_draw(struct panfrost_context
*ctx
)
1301 /* Handle dirty flags now */
1302 panfrost_emit_for_draw(ctx
, true);
1304 /* If rasterizer discard is enable, only submit the vertex */
1306 bool rasterizer_discard
= ctx
->rasterizer
1307 && ctx
->rasterizer
->base
.rasterizer_discard
;
1309 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1310 struct panfrost_transfer tiler
;
1312 if (!rasterizer_discard
)
1313 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1315 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1317 if (rasterizer_discard
)
1318 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1319 else if (ctx
->wallpaper_batch
)
1320 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1322 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1325 /* The entire frame is in memory -- send it off to the kernel! */
1328 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1329 struct pipe_fence_handle
**fence
,
1330 struct panfrost_batch
*batch
)
1332 panfrost_batch_submit(ctx
, batch
);
1334 /* If visual, we can stall a frame */
1336 if (!flush_immediate
)
1337 panfrost_drm_force_flush_fragment(ctx
, fence
);
1339 ctx
->last_fragment_flushed
= false;
1340 ctx
->last_batch
= batch
;
1342 /* If readback, flush now (hurts the pipelined performance) */
1343 if (flush_immediate
)
1344 panfrost_drm_force_flush_fragment(ctx
, fence
);
1348 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1350 struct panfrost_context
*ctx
= pan_context(pipe
);
1352 /* Nothing to reload? TODO: MRT wallpapers */
1353 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1356 /* Check if the buffer has any content on it worth preserving */
1358 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1359 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1360 unsigned level
= surf
->u
.tex
.level
;
1362 if (!rsrc
->slices
[level
].initialized
)
1365 /* Save the batch */
1366 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1368 ctx
->wallpaper_batch
= batch
;
1370 /* Clamp the rendering area to the damage extent. The
1371 * KHR_partial_update() spec states that trying to render outside of
1372 * the damage region is "undefined behavior", so we should be safe.
1374 unsigned damage_width
= (rsrc
->damage
.extent
.maxx
- rsrc
->damage
.extent
.minx
);
1375 unsigned damage_height
= (rsrc
->damage
.extent
.maxy
- rsrc
->damage
.extent
.miny
);
1377 if (damage_width
&& damage_height
) {
1378 panfrost_batch_intersection_scissor(batch
,
1379 rsrc
->damage
.extent
.minx
,
1380 rsrc
->damage
.extent
.miny
,
1381 rsrc
->damage
.extent
.maxx
,
1382 rsrc
->damage
.extent
.maxy
);
1385 /* FIXME: Looks like aligning on a tile is not enough, but
1386 * aligning on twice the tile size seems to works. We don't
1387 * know exactly what happens here but this deserves extra
1388 * investigation to figure it out.
1390 batch
->minx
= batch
->minx
& ~((MALI_TILE_LENGTH
* 2) - 1);
1391 batch
->miny
= batch
->miny
& ~((MALI_TILE_LENGTH
* 2) - 1);
1392 batch
->maxx
= MIN2(ALIGN_POT(batch
->maxx
, MALI_TILE_LENGTH
* 2),
1394 batch
->maxy
= MIN2(ALIGN_POT(batch
->maxy
, MALI_TILE_LENGTH
* 2),
1395 rsrc
->base
.height0
);
1397 struct pipe_scissor_state damage
;
1398 struct pipe_box rects
[4];
1400 /* Clamp the damage box to the rendering area. */
1401 damage
.minx
= MAX2(batch
->minx
, rsrc
->damage
.biggest_rect
.x
);
1402 damage
.miny
= MAX2(batch
->miny
, rsrc
->damage
.biggest_rect
.y
);
1403 damage
.maxx
= MIN2(batch
->maxx
,
1404 rsrc
->damage
.biggest_rect
.x
+
1405 rsrc
->damage
.biggest_rect
.width
);
1406 damage
.maxy
= MIN2(batch
->maxy
,
1407 rsrc
->damage
.biggest_rect
.y
+
1408 rsrc
->damage
.biggest_rect
.height
);
1410 /* One damage rectangle means we can end up with at most 4 reload
1412 * 1: left region, only exists if damage.x > 0
1413 * 2: right region, only exists if damage.x + damage.width < fb->width
1414 * 3: top region, only exists if damage.y > 0. The intersection with
1415 * the left and right regions are dropped
1416 * 4: bottom region, only exists if damage.y + damage.height < fb->height.
1417 * The intersection with the left and right regions are dropped
1419 * ____________________________
1426 * |_______|___________|______|
1428 u_box_2d(batch
->minx
, batch
->miny
, damage
.minx
- batch
->minx
,
1429 batch
->maxy
- batch
->miny
, &rects
[0]);
1430 u_box_2d(damage
.maxx
, batch
->miny
, batch
->maxx
- damage
.maxx
,
1431 batch
->maxy
- batch
->miny
, &rects
[1]);
1432 u_box_2d(damage
.minx
, batch
->miny
, damage
.maxx
- damage
.minx
,
1433 damage
.miny
- batch
->miny
, &rects
[2]);
1434 u_box_2d(damage
.minx
, damage
.maxy
, damage
.maxx
- damage
.minx
,
1435 batch
->maxy
- damage
.maxy
, &rects
[3]);
1437 for (unsigned i
= 0; i
< 4; i
++) {
1438 /* Width and height are always >= 0 even if width is declared as a
1439 * signed integer: u_box_2d() helper takes unsigned args and
1440 * panfrost_set_damage_region() is taking care of clamping
1443 if (!rects
[i
].width
|| !rects
[i
].height
)
1446 /* Blit the wallpaper in */
1447 panfrost_blit_wallpaper(ctx
, &rects
[i
]);
1449 ctx
->wallpaper_batch
= NULL
;
1454 struct pipe_context
*pipe
,
1455 struct pipe_fence_handle
**fence
,
1458 struct panfrost_context
*ctx
= pan_context(pipe
);
1459 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1461 /* Nothing to do! */
1462 if (!batch
->last_job
.gpu
&& !batch
->clear
) return;
1464 if (!batch
->clear
&& batch
->last_tiler
.gpu
)
1465 panfrost_draw_wallpaper(&ctx
->base
);
1467 /* Whether to stall the pipeline for immediately correct results. Since
1468 * pipelined rendering is quite broken right now (to be fixed by the
1469 * panfrost_job refactor, just take the perf hit for correctness) */
1470 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1472 /* Submit the frame itself */
1473 panfrost_submit_frame(ctx
, flush_immediate
, fence
, batch
);
1475 /* Prepare for the next frame */
1476 panfrost_invalidate_frame(ctx
);
1479 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1482 g2m_draw_mode(enum pipe_prim_type mode
)
1485 DEFINE_CASE(POINTS
);
1487 DEFINE_CASE(LINE_LOOP
);
1488 DEFINE_CASE(LINE_STRIP
);
1489 DEFINE_CASE(TRIANGLES
);
1490 DEFINE_CASE(TRIANGLE_STRIP
);
1491 DEFINE_CASE(TRIANGLE_FAN
);
1493 DEFINE_CASE(QUAD_STRIP
);
1494 DEFINE_CASE(POLYGON
);
1497 unreachable("Invalid draw mode");
1504 panfrost_translate_index_size(unsigned size
)
1508 return MALI_DRAW_INDEXED_UINT8
;
1511 return MALI_DRAW_INDEXED_UINT16
;
1514 return MALI_DRAW_INDEXED_UINT32
;
1517 unreachable("Invalid index size");
1521 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1522 * good for the duration of the draw (transient), could last longer */
1525 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1527 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1529 off_t offset
= info
->start
* info
->index_size
;
1530 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1532 if (!info
->has_user_indices
) {
1533 /* Only resources can be directly mapped */
1534 panfrost_batch_add_bo(batch
, rsrc
->bo
);
1535 return rsrc
->bo
->gpu
+ offset
;
1537 /* Otherwise, we need to upload to transient memory */
1538 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1539 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1544 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1546 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1548 /* Check if we're scissoring at all */
1550 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1553 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1556 /* Count generated primitives (when there is no geom/tess shaders) for
1557 * transform feedback */
1560 panfrost_statistics_record(
1561 struct panfrost_context
*ctx
,
1562 const struct pipe_draw_info
*info
)
1564 if (!ctx
->active_queries
)
1567 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1568 ctx
->prims_generated
+= prims
;
1570 if (!ctx
->streamout
.num_targets
)
1573 ctx
->tf_prims_generated
+= prims
;
1578 struct pipe_context
*pipe
,
1579 const struct pipe_draw_info
*info
)
1581 struct panfrost_context
*ctx
= pan_context(pipe
);
1583 /* First of all, check the scissor to see if anything is drawn at all.
1584 * If it's not, we drop the draw (mostly a conformance issue;
1585 * well-behaved apps shouldn't hit this) */
1587 if (panfrost_scissor_culls_everything(ctx
))
1590 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1591 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1593 int mode
= info
->mode
;
1595 /* Fallback unsupported restart index */
1596 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1598 if (info
->primitive_restart
&& info
->index_size
1599 && info
->restart_index
!= primitive_index
) {
1600 util_draw_vbo_without_prim_restart(pipe
, info
);
1604 /* Fallback for unsupported modes */
1606 assert(ctx
->rasterizer
!= NULL
);
1608 if (!(ctx
->draw_modes
& (1 << mode
))) {
1609 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1610 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1612 if (info
->count
< 4) {
1613 /* Degenerate case? */
1617 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1618 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1623 /* Now that we have a guaranteed terminating path, find the job.
1624 * Assignment commented out to prevent unused warning */
1626 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1628 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1630 /* Take into account a negative bias */
1631 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1632 ctx
->instance_count
= info
->instance_count
;
1633 ctx
->active_prim
= info
->mode
;
1635 /* For non-indexed draws, they're the same */
1636 unsigned vertex_count
= ctx
->vertex_count
;
1638 unsigned draw_flags
= 0;
1640 /* The draw flags interpret how primitive size is interpreted */
1642 if (panfrost_writes_point_size(ctx
))
1643 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1645 if (info
->primitive_restart
)
1646 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1648 /* For higher amounts of vertices (greater than what fits in a 16-bit
1649 * short), the other value is needed, otherwise there will be bizarre
1650 * rendering artefacts. It's not clear what these values mean yet. This
1651 * change is also needed for instancing and sometimes points (perhaps
1652 * related to dynamically setting gl_PointSize) */
1654 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1655 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1656 bool instanced
= ctx
->instance_count
> 1;
1658 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1660 /* This doesn't make much sense */
1661 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1662 draw_flags
|= 0x800;
1665 panfrost_statistics_record(ctx
, info
);
1667 if (info
->index_size
) {
1668 /* Calculate the min/max index used so we can figure out how
1669 * many times to invoke the vertex shader */
1671 /* Fetch / calculate index bounds */
1672 unsigned min_index
= 0, max_index
= 0;
1674 if (info
->max_index
== ~0u) {
1675 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1677 min_index
= info
->min_index
;
1678 max_index
= info
->max_index
;
1681 /* Use the corresponding values */
1682 vertex_count
= max_index
- min_index
+ 1;
1683 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1684 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1686 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1687 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1689 //assert(!info->restart_index); /* TODO: Research */
1691 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1692 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1694 /* Index count == vertex count, if no indexing is applied, as
1695 * if it is internally indexed in the expected order */
1697 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1698 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1700 /* Reverse index state */
1701 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1704 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1705 * vertex_count, 1) */
1707 panfrost_pack_work_groups_fused(
1708 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1709 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1710 1, vertex_count
, info
->instance_count
,
1713 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1715 /* Encode the padded vertex count */
1717 if (info
->instance_count
> 1) {
1718 /* Triangles have non-even vertex counts so they change how
1719 * padding works internally */
1722 mode
== PIPE_PRIM_TRIANGLES
||
1723 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1724 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1726 struct pan_shift_odd so
=
1727 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1729 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1730 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1732 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1733 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1735 ctx
->padded_count
= pan_expand_shift_odd(so
);
1737 ctx
->padded_count
= ctx
->vertex_count
;
1739 /* Reset instancing state */
1740 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1741 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1742 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1743 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1746 /* Fire off the draw itself */
1747 panfrost_queue_draw(ctx
);
1749 /* Increment transform feedback offsets */
1751 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1752 unsigned output_count
= u_stream_outputs_for_vertices(
1753 ctx
->active_prim
, ctx
->vertex_count
);
1755 ctx
->streamout
.offsets
[i
] += output_count
;
1762 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1768 panfrost_create_rasterizer_state(
1769 struct pipe_context
*pctx
,
1770 const struct pipe_rasterizer_state
*cso
)
1772 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1776 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1777 so
->tiler_gl_enables
= 0x7;
1780 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1782 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1783 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1785 if (cso
->cull_face
& PIPE_FACE_BACK
)
1786 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1792 panfrost_bind_rasterizer_state(
1793 struct pipe_context
*pctx
,
1796 struct panfrost_context
*ctx
= pan_context(pctx
);
1798 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1802 ctx
->rasterizer
= hwcso
;
1803 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1805 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1806 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1808 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1809 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1811 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1813 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1814 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1816 /* Point sprites are emulated */
1818 struct panfrost_shader_state
*variant
=
1819 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1821 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1822 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1826 panfrost_create_vertex_elements_state(
1827 struct pipe_context
*pctx
,
1828 unsigned num_elements
,
1829 const struct pipe_vertex_element
*elements
)
1831 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1833 so
->num_elements
= num_elements
;
1834 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1836 for (int i
= 0; i
< num_elements
; ++i
) {
1837 so
->hw
[i
].index
= i
;
1839 enum pipe_format fmt
= elements
[i
].src_format
;
1840 const struct util_format_description
*desc
= util_format_description(fmt
);
1841 so
->hw
[i
].unknown1
= 0x2;
1842 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1844 so
->hw
[i
].format
= panfrost_find_format(desc
);
1846 /* The field itself should probably be shifted over */
1847 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1854 panfrost_bind_vertex_elements_state(
1855 struct pipe_context
*pctx
,
1858 struct panfrost_context
*ctx
= pan_context(pctx
);
1860 ctx
->vertex
= hwcso
;
1861 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1865 panfrost_create_shader_state(
1866 struct pipe_context
*pctx
,
1867 const struct pipe_shader_state
*cso
)
1869 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1872 /* Token deep copy to prevent memory corruption */
1874 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1875 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1881 panfrost_delete_shader_state(
1882 struct pipe_context
*pctx
,
1885 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1887 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1888 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1891 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1892 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1893 panfrost_bo_unreference(pctx
->screen
, shader_state
->bo
);
1894 shader_state
->bo
= NULL
;
1901 panfrost_create_sampler_state(
1902 struct pipe_context
*pctx
,
1903 const struct pipe_sampler_state
*cso
)
1905 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1908 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1910 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1911 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1912 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1914 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1915 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1916 unsigned mip_filter
= mip_linear
?
1917 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1918 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1920 struct mali_sampler_descriptor sampler_descriptor
= {
1921 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1922 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1923 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1924 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1925 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1927 cso
->border_color
.f
[0],
1928 cso
->border_color
.f
[1],
1929 cso
->border_color
.f
[2],
1930 cso
->border_color
.f
[3]
1932 .min_lod
= FIXED_16(cso
->min_lod
),
1933 .max_lod
= FIXED_16(cso
->max_lod
),
1934 .seamless_cube_map
= cso
->seamless_cube_map
,
1937 /* If necessary, we disable mipmapping in the sampler descriptor by
1938 * clamping the LOD as tight as possible (from 0 to epsilon,
1939 * essentially -- remember these are fixed point numbers, so
1942 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1943 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1945 /* Enforce that there is something in the middle by adding epsilon*/
1947 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1948 sampler_descriptor
.max_lod
++;
1951 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1953 so
->hw
= sampler_descriptor
;
1959 panfrost_bind_sampler_states(
1960 struct pipe_context
*pctx
,
1961 enum pipe_shader_type shader
,
1962 unsigned start_slot
, unsigned num_sampler
,
1965 assert(start_slot
== 0);
1967 struct panfrost_context
*ctx
= pan_context(pctx
);
1969 /* XXX: Should upload, not just copy? */
1970 ctx
->sampler_count
[shader
] = num_sampler
;
1971 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1973 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1977 panfrost_variant_matches(
1978 struct panfrost_context
*ctx
,
1979 struct panfrost_shader_state
*variant
,
1980 enum pipe_shader_type type
)
1982 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1983 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1985 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1987 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1988 /* Make sure enable state is at least the same */
1989 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1993 /* Check that the contents of the test are the same */
1994 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1995 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1997 if (!(same_func
&& same_ref
)) {
2002 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
2003 variant
->point_sprite_mask
)) {
2004 /* Ensure the same varyings are turned to point sprites */
2005 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
2008 /* Ensure the orientation is correct */
2010 rasterizer
->sprite_coord_mode
==
2011 PIPE_SPRITE_COORD_UPPER_LEFT
;
2013 if (variant
->point_sprite_upper_left
!= upper_left
)
2017 /* Otherwise, we're good to go */
2022 * Fix an uncompiled shader's stream output info, and produce a bitmask
2023 * of which VARYING_SLOT_* are captured for stream output.
2025 * Core Gallium stores output->register_index as a "slot" number, where
2026 * slots are assigned consecutively to all outputs in info->outputs_written.
2027 * This naive packing of outputs doesn't work for us - we too have slots,
2028 * but the layout is defined by the VUE map, which we won't have until we
2029 * compile a specific shader variant. So, we remap these and simply store
2030 * VARYING_SLOT_* in our copy's output->register_index fields.
2032 * We then produce a bitmask of outputs which are used for SO.
2034 * Implementation from iris.
2038 update_so_info(struct pipe_stream_output_info
*so_info
,
2039 uint64_t outputs_written
)
2041 uint64_t so_outputs
= 0;
2042 uint8_t reverse_map
[64] = {};
2045 while (outputs_written
)
2046 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
2048 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
2049 struct pipe_stream_output
*output
= &so_info
->output
[i
];
2051 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
2052 output
->register_index
= reverse_map
[output
->register_index
];
2054 so_outputs
|= 1ull << output
->register_index
;
2061 panfrost_bind_shader_state(
2062 struct pipe_context
*pctx
,
2064 enum pipe_shader_type type
)
2066 struct panfrost_context
*ctx
= pan_context(pctx
);
2068 ctx
->shader
[type
] = hwcso
;
2070 if (type
== PIPE_SHADER_FRAGMENT
)
2071 ctx
->dirty
|= PAN_DIRTY_FS
;
2073 ctx
->dirty
|= PAN_DIRTY_VS
;
2077 /* Match the appropriate variant */
2079 signed variant
= -1;
2080 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2082 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2083 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2089 if (variant
== -1) {
2090 /* No variant matched, so create a new one */
2091 variant
= variants
->variant_count
++;
2092 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2094 struct panfrost_shader_state
*v
=
2095 &variants
->variants
[variant
];
2097 if (type
== PIPE_SHADER_FRAGMENT
) {
2098 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2100 if (ctx
->rasterizer
) {
2101 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2102 v
->point_sprite_upper_left
=
2103 ctx
->rasterizer
->base
.sprite_coord_mode
==
2104 PIPE_SPRITE_COORD_UPPER_LEFT
;
2108 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
2112 /* Select this variant */
2113 variants
->active_variant
= variant
;
2115 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2116 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2118 /* We finally have a variant, so compile it */
2120 if (!shader_state
->compiled
) {
2121 uint64_t outputs_written
= 0;
2123 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2124 variants
->base
.type
,
2125 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2126 variants
->base
.ir
.nir
:
2127 variants
->base
.tokens
,
2128 tgsi_processor_to_shader_stage(type
), shader_state
,
2131 shader_state
->compiled
= true;
2133 /* Fixup the stream out information, since what Gallium returns
2134 * normally is mildly insane */
2136 shader_state
->stream_output
= variants
->base
.stream_output
;
2137 shader_state
->so_mask
=
2138 update_so_info(&shader_state
->stream_output
, outputs_written
);
2143 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2145 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2149 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2151 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2155 panfrost_set_vertex_buffers(
2156 struct pipe_context
*pctx
,
2157 unsigned start_slot
,
2158 unsigned num_buffers
,
2159 const struct pipe_vertex_buffer
*buffers
)
2161 struct panfrost_context
*ctx
= pan_context(pctx
);
2163 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2167 panfrost_set_constant_buffer(
2168 struct pipe_context
*pctx
,
2169 enum pipe_shader_type shader
, uint index
,
2170 const struct pipe_constant_buffer
*buf
)
2172 struct panfrost_context
*ctx
= pan_context(pctx
);
2173 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2175 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2177 unsigned mask
= (1 << index
);
2179 if (unlikely(!buf
)) {
2180 pbuf
->enabled_mask
&= ~mask
;
2181 pbuf
->dirty_mask
&= ~mask
;
2185 pbuf
->enabled_mask
|= mask
;
2186 pbuf
->dirty_mask
|= mask
;
2190 panfrost_set_stencil_ref(
2191 struct pipe_context
*pctx
,
2192 const struct pipe_stencil_ref
*ref
)
2194 struct panfrost_context
*ctx
= pan_context(pctx
);
2195 ctx
->stencil_ref
= *ref
;
2197 /* Shader core dirty */
2198 ctx
->dirty
|= PAN_DIRTY_FS
;
2201 static enum mali_texture_type
2202 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2206 case PIPE_TEXTURE_1D
:
2207 case PIPE_TEXTURE_1D_ARRAY
:
2210 case PIPE_TEXTURE_2D
:
2211 case PIPE_TEXTURE_2D_ARRAY
:
2212 case PIPE_TEXTURE_RECT
:
2215 case PIPE_TEXTURE_3D
:
2218 case PIPE_TEXTURE_CUBE
:
2219 case PIPE_TEXTURE_CUBE_ARRAY
:
2220 return MALI_TEX_CUBE
;
2223 unreachable("Unknown target");
2227 static struct pipe_sampler_view
*
2228 panfrost_create_sampler_view(
2229 struct pipe_context
*pctx
,
2230 struct pipe_resource
*texture
,
2231 const struct pipe_sampler_view
*template)
2233 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2234 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2236 pipe_reference(NULL
, &texture
->reference
);
2238 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2241 so
->base
= *template;
2242 so
->base
.texture
= texture
;
2243 so
->base
.reference
.count
= 1;
2244 so
->base
.context
= pctx
;
2246 /* sampler_views correspond to texture descriptors, minus the texture
2247 * (data) itself. So, we serialise the descriptor here and cache it for
2250 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2252 unsigned char user_swizzle
[4] = {
2253 template->swizzle_r
,
2254 template->swizzle_g
,
2255 template->swizzle_b
,
2259 enum mali_format format
= panfrost_find_format(desc
);
2261 /* Check if we need to set a custom stride by computing the "expected"
2262 * stride and comparing it to what the BO actually wants. Only applies
2263 * to linear textures, since tiled/compressed textures have strict
2264 * alignment requirements for their strides as it is */
2266 unsigned first_level
= template->u
.tex
.first_level
;
2267 unsigned last_level
= template->u
.tex
.last_level
;
2269 if (prsrc
->layout
== PAN_LINEAR
) {
2270 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2271 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2272 unsigned width
= u_minify(texture
->width0
, l
);
2273 unsigned comp_stride
= width
* bytes_per_pixel
;
2275 if (comp_stride
!= actual_stride
) {
2276 so
->manual_stride
= true;
2282 /* In the hardware, array_size refers specifically to array textures,
2283 * whereas in Gallium, it also covers cubemaps */
2285 unsigned array_size
= texture
->array_size
;
2287 if (template->target
== PIPE_TEXTURE_CUBE
) {
2288 /* TODO: Cubemap arrays */
2289 assert(array_size
== 6);
2293 struct mali_texture_descriptor texture_descriptor
= {
2294 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2295 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2296 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2297 .array_size
= MALI_POSITIVE(array_size
),
2300 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2302 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2303 .type
= panfrost_translate_texture_type(template->target
),
2307 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2310 texture_descriptor
.levels
= last_level
- first_level
;
2312 so
->hw
= texture_descriptor
;
2314 return (struct pipe_sampler_view
*) so
;
2318 panfrost_set_sampler_views(
2319 struct pipe_context
*pctx
,
2320 enum pipe_shader_type shader
,
2321 unsigned start_slot
, unsigned num_views
,
2322 struct pipe_sampler_view
**views
)
2324 struct panfrost_context
*ctx
= pan_context(pctx
);
2326 assert(start_slot
== 0);
2328 unsigned new_nr
= 0;
2329 for (unsigned i
= 0; i
< num_views
; ++i
) {
2334 ctx
->sampler_view_count
[shader
] = new_nr
;
2335 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2337 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2341 panfrost_sampler_view_destroy(
2342 struct pipe_context
*pctx
,
2343 struct pipe_sampler_view
*view
)
2345 pipe_resource_reference(&view
->texture
, NULL
);
2350 panfrost_set_shader_buffers(
2351 struct pipe_context
*pctx
,
2352 enum pipe_shader_type shader
,
2353 unsigned start
, unsigned count
,
2354 const struct pipe_shader_buffer
*buffers
,
2355 unsigned writable_bitmask
)
2357 struct panfrost_context
*ctx
= pan_context(pctx
);
2359 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2360 buffers
, start
, count
);
2363 /* Hints that a framebuffer should use AFBC where possible */
2367 struct panfrost_screen
*screen
,
2368 const struct pipe_framebuffer_state
*fb
)
2370 /* AFBC implemenation incomplete; hide it */
2371 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2373 /* Hint AFBC to the resources bound to each color buffer */
2375 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2376 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2377 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2378 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2381 /* Also hint it to the depth buffer */
2384 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2385 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2390 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2391 const struct pipe_framebuffer_state
*fb
)
2393 struct panfrost_context
*ctx
= pan_context(pctx
);
2395 /* Flush when switching framebuffers, but not if the framebuffer
2396 * state is being restored by u_blitter
2399 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2400 bool is_scanout
= panfrost_is_scanout(ctx
);
2401 bool has_draws
= batch
->last_job
.gpu
;
2403 /* Bail out early when the current and new states are the same. */
2404 if (util_framebuffer_state_equal(&ctx
->pipe_framebuffer
, fb
))
2407 /* The wallpaper logic sets a new FB state before doing the blit and
2408 * restore the old one when it's done. Those FB states are reported to
2409 * be different because the surface they are pointing to are different,
2410 * but those surfaces actually point to the same cbufs/zbufs. In that
2411 * case we definitely don't want new FB descs to be emitted/attached
2412 * since the job is expected to be flushed just after the blit is done,
2413 * so let's just copy the new state and return here.
2415 if (ctx
->wallpaper_batch
) {
2416 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2420 if (!is_scanout
|| has_draws
)
2421 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2423 assert(!ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
&&
2424 !ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
2426 /* Invalidate the FBO job cache since we've just been assigned a new
2431 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2433 /* Given that we're rendering, we'd love to have compression */
2434 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2436 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2437 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
2438 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
2442 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2443 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2445 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2449 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2452 struct panfrost_context
*ctx
= pan_context(pipe
);
2453 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2454 ctx
->depth_stencil
= depth_stencil
;
2459 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2460 * emulated in the fragment shader */
2462 if (depth_stencil
->alpha
.enabled
) {
2463 /* We need to trigger a new shader (maybe) */
2464 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2468 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2470 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2471 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2473 /* If back-stencil is not enabled, use the front values */
2474 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2475 unsigned back_index
= back_enab
? 1 : 0;
2477 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2478 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2480 /* Depth state (TODO: Refactor) */
2481 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2483 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2485 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2486 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2488 /* Bounds test not implemented */
2489 assert(!depth_stencil
->depth
.bounds_test
);
2491 ctx
->dirty
|= PAN_DIRTY_FS
;
2495 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2501 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2502 unsigned sample_mask
)
2507 panfrost_set_clip_state(struct pipe_context
*pipe
,
2508 const struct pipe_clip_state
*clip
)
2510 //struct panfrost_context *panfrost = pan_context(pipe);
2514 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2515 unsigned start_slot
,
2516 unsigned num_viewports
,
2517 const struct pipe_viewport_state
*viewports
)
2519 struct panfrost_context
*ctx
= pan_context(pipe
);
2521 assert(start_slot
== 0);
2522 assert(num_viewports
== 1);
2524 ctx
->pipe_viewport
= *viewports
;
2528 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2529 unsigned start_slot
,
2530 unsigned num_scissors
,
2531 const struct pipe_scissor_state
*scissors
)
2533 struct panfrost_context
*ctx
= pan_context(pipe
);
2535 assert(start_slot
== 0);
2536 assert(num_scissors
== 1);
2538 ctx
->scissor
= *scissors
;
2542 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2543 const struct pipe_poly_stipple
*stipple
)
2545 //struct panfrost_context *panfrost = pan_context(pipe);
2549 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2552 struct panfrost_context
*ctx
= pan_context(pipe
);
2553 ctx
->active_queries
= enable
;
2557 panfrost_destroy(struct pipe_context
*pipe
)
2559 struct panfrost_context
*panfrost
= pan_context(pipe
);
2560 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2562 if (panfrost
->blitter
)
2563 util_blitter_destroy(panfrost
->blitter
);
2565 if (panfrost
->blitter_wallpaper
)
2566 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2568 panfrost_drm_free_slab(screen
, &panfrost
->scratchpad
);
2569 panfrost_drm_free_slab(screen
, &panfrost
->tiler_heap
);
2570 panfrost_drm_free_slab(screen
, &panfrost
->tiler_dummy
);
2575 static struct pipe_query
*
2576 panfrost_create_query(struct pipe_context
*pipe
,
2580 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2585 return (struct pipe_query
*) q
;
2589 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2595 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2597 struct panfrost_context
*ctx
= pan_context(pipe
);
2598 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2600 switch (query
->type
) {
2601 case PIPE_QUERY_OCCLUSION_COUNTER
:
2602 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2603 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2604 /* Allocate a word for the query results to be stored */
2605 query
->transfer
= panfrost_allocate_transient(ctx
, sizeof(unsigned));
2606 ctx
->occlusion_query
= query
;
2609 /* Geometry statistics are computed in the driver. XXX: geom/tess
2612 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2613 query
->start
= ctx
->prims_generated
;
2615 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2616 query
->start
= ctx
->tf_prims_generated
;
2620 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2628 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2630 struct panfrost_context
*ctx
= pan_context(pipe
);
2631 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2633 switch (query
->type
) {
2634 case PIPE_QUERY_OCCLUSION_COUNTER
:
2635 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2636 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2637 ctx
->occlusion_query
= NULL
;
2639 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2640 query
->end
= ctx
->prims_generated
;
2642 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2643 query
->end
= ctx
->tf_prims_generated
;
2651 panfrost_get_query_result(struct pipe_context
*pipe
,
2652 struct pipe_query
*q
,
2654 union pipe_query_result
*vresult
)
2656 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2659 switch (query
->type
) {
2660 case PIPE_QUERY_OCCLUSION_COUNTER
:
2661 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2662 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2664 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2666 /* Read back the query results */
2667 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2668 unsigned passed
= *result
;
2670 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2671 vresult
->u64
= passed
;
2673 vresult
->b
= !!passed
;
2678 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2679 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2680 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2681 vresult
->u64
= query
->end
- query
->start
;
2685 DBG("Skipped query get %u\n", query
->type
);
2692 static struct pipe_stream_output_target
*
2693 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2694 struct pipe_resource
*prsc
,
2695 unsigned buffer_offset
,
2696 unsigned buffer_size
)
2698 struct pipe_stream_output_target
*target
;
2700 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2705 pipe_reference_init(&target
->reference
, 1);
2706 pipe_resource_reference(&target
->buffer
, prsc
);
2708 target
->context
= pctx
;
2709 target
->buffer_offset
= buffer_offset
;
2710 target
->buffer_size
= buffer_size
;
2716 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2717 struct pipe_stream_output_target
*target
)
2719 pipe_resource_reference(&target
->buffer
, NULL
);
2720 ralloc_free(target
);
2724 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2725 unsigned num_targets
,
2726 struct pipe_stream_output_target
**targets
,
2727 const unsigned *offsets
)
2729 struct panfrost_context
*ctx
= pan_context(pctx
);
2730 struct panfrost_streamout
*so
= &ctx
->streamout
;
2732 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2734 for (unsigned i
= 0; i
< num_targets
; i
++) {
2735 if (offsets
[i
] != -1)
2736 so
->offsets
[i
] = offsets
[i
];
2738 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2741 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2742 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2744 so
->num_targets
= num_targets
;
2748 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2750 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2751 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2753 panfrost_drm_allocate_slab(screen
, &ctx
->scratchpad
, 64*4, false, 0, 0, 0);
2754 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_heap
, 4096, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2755 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2758 /* New context creation, which also does hardware initialisation since I don't
2759 * know the better way to structure this :smirk: */
2761 struct pipe_context
*
2762 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2764 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2765 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2766 memset(ctx
, 0, sizeof(*ctx
));
2767 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2769 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2771 gallium
->screen
= screen
;
2773 gallium
->destroy
= panfrost_destroy
;
2775 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2777 gallium
->flush
= panfrost_flush
;
2778 gallium
->clear
= panfrost_clear
;
2779 gallium
->draw_vbo
= panfrost_draw_vbo
;
2781 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2782 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2783 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2785 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2787 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2788 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2789 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2791 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2792 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2793 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2795 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2796 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2797 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2799 gallium
->create_fs_state
= panfrost_create_shader_state
;
2800 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2801 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2803 gallium
->create_vs_state
= panfrost_create_shader_state
;
2804 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2805 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2807 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2808 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2809 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2811 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2812 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2813 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2815 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2817 gallium
->set_clip_state
= panfrost_set_clip_state
;
2818 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2819 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2820 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2821 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2823 gallium
->create_query
= panfrost_create_query
;
2824 gallium
->destroy_query
= panfrost_destroy_query
;
2825 gallium
->begin_query
= panfrost_begin_query
;
2826 gallium
->end_query
= panfrost_end_query
;
2827 gallium
->get_query_result
= panfrost_get_query_result
;
2829 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2830 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2831 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2833 panfrost_resource_context_init(gallium
);
2834 panfrost_blend_context_init(gallium
);
2835 panfrost_compute_context_init(gallium
);
2837 panfrost_drm_init_context(ctx
);
2839 panfrost_setup_hardware(ctx
);
2842 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2843 gallium
->const_uploader
= gallium
->stream_uploader
;
2844 assert(gallium
->stream_uploader
);
2846 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2847 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2849 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2851 ctx
->blitter
= util_blitter_create(gallium
);
2852 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2854 assert(ctx
->blitter
);
2855 assert(ctx
->blitter_wallpaper
);
2857 ctx
->last_fragment_flushed
= true;
2858 ctx
->last_batch
= NULL
;
2860 /* Prepare for render! */
2862 panfrost_batch_init(ctx
);
2863 panfrost_emit_vertex_payload(ctx
);
2864 panfrost_emit_tiler_payload(ctx
);
2865 panfrost_invalidate_frame(ctx
);
2866 panfrost_default_shader_backend(ctx
);