2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 #include "pan_context.h"
31 #include "pan_format.h"
33 #include "util/macros.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_memory.h"
38 #include "util/u_vbuf.h"
39 #include "util/half_float.h"
40 #include "util/u_helpers.h"
41 #include "util/u_format.h"
42 #include "util/u_prim.h"
43 #include "util/u_prim_restart.h"
44 #include "indices/u_primconvert.h"
45 #include "tgsi/tgsi_parse.h"
46 #include "tgsi/tgsi_from_mesa.h"
47 #include "util/u_math.h"
49 #include "pan_screen.h"
50 #include "pan_blending.h"
51 #include "pan_blend_shaders.h"
54 /* Framebuffer descriptor */
56 static struct midgard_tiler_descriptor
57 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
59 struct panfrost_context
*ctx
= batch
->ctx
;
60 struct midgard_tiler_descriptor t
= {};
61 unsigned height
= batch
->key
.height
;
62 unsigned width
= batch
->key
.width
;
65 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
67 /* Compute the polygon header size and use that to offset the body */
69 unsigned header_size
= panfrost_tiler_header_size(
70 width
, height
, t
.hierarchy_mask
);
72 t
.polygon_list_size
= panfrost_tiler_full_size(
73 width
, height
, t
.hierarchy_mask
);
77 if (t
.hierarchy_mask
) {
78 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
83 /* Allow the entire tiler heap */
84 t
.heap_start
= ctx
->tiler_heap
->gpu
;
85 t
.heap_end
= ctx
->tiler_heap
->gpu
+ ctx
->tiler_heap
->size
;
87 /* The tiler is disabled, so don't allow the tiler heap */
88 t
.heap_start
= ctx
->tiler_heap
->gpu
;
89 t
.heap_end
= t
.heap_start
;
91 /* Use a dummy polygon list */
92 t
.polygon_list
= ctx
->tiler_dummy
->gpu
;
94 /* Disable the tiler */
95 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
99 t
.polygon_list
+ header_size
;
104 struct mali_single_framebuffer
105 panfrost_emit_sfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
107 struct panfrost_context
*ctx
= batch
->ctx
;
108 unsigned width
= batch
->key
.width
;
109 unsigned height
= batch
->key
.height
;
111 struct mali_single_framebuffer framebuffer
= {
112 .width
= MALI_POSITIVE(width
),
113 .height
= MALI_POSITIVE(height
),
115 .format
= 0x30000000,
116 .clear_flags
= 0x1000,
117 .unknown_address_0
= ctx
->scratchpad
->gpu
,
118 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
),
124 struct bifrost_framebuffer
125 panfrost_emit_mfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
127 struct panfrost_context
*ctx
= batch
->ctx
;
128 unsigned width
= batch
->key
.width
;
129 unsigned height
= batch
->key
.height
;
131 struct bifrost_framebuffer framebuffer
= {
132 .unk0
= 0x1e5, /* 1e4 if no spill */
133 .width1
= MALI_POSITIVE(width
),
134 .height1
= MALI_POSITIVE(height
),
135 .width2
= MALI_POSITIVE(width
),
136 .height2
= MALI_POSITIVE(height
),
140 .rt_count_1
= MALI_POSITIVE(batch
->key
.nr_cbufs
),
145 .scratchpad
= ctx
->scratchpad
->gpu
,
146 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
)
154 struct pipe_context
*pipe
,
156 const union pipe_color_union
*color
,
157 double depth
, unsigned stencil
)
159 struct panfrost_context
*ctx
= pan_context(pipe
);
160 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
162 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
166 panfrost_attach_vt_mfbd(struct panfrost_batch
*batch
)
168 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(batch
, ~0);
170 return panfrost_upload_transient(batch
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
174 panfrost_attach_vt_sfbd(struct panfrost_batch
*batch
)
176 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(batch
, ~0);
178 return panfrost_upload_transient(batch
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
182 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
184 /* Skip the attach if we can */
186 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
187 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
191 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
192 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
194 if (!batch
->framebuffer
)
195 batch
->framebuffer
= screen
->require_sfbd
?
196 panfrost_attach_vt_sfbd(batch
) :
197 panfrost_attach_vt_mfbd(batch
);
199 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
200 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
;
203 /* Reset per-frame context, called on context initialisation as well as after
204 * flushing a frame */
207 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
209 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
210 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
213 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
216 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
218 /* TODO: When does this need to be handled? */
219 ctx
->active_queries
= true;
222 /* In practice, every field of these payloads should be configurable
223 * arbitrarily, which means these functions are basically catch-all's for
224 * as-of-yet unwavering unknowns */
227 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
229 /* 0x2 bit clear on 32-bit T6XX */
231 struct midgard_payload_vertex_tiler payload
= {
232 .gl_enables
= 0x4 | 0x2,
235 /* Vertex and compute are closely coupled, so share a payload */
237 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
238 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
242 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
244 struct midgard_payload_vertex_tiler payload
= {
246 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
250 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
254 translate_tex_wrap(enum pipe_tex_wrap w
)
257 case PIPE_TEX_WRAP_REPEAT
:
258 return MALI_WRAP_REPEAT
;
260 /* TODO: lower GL_CLAMP? */
261 case PIPE_TEX_WRAP_CLAMP
:
262 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
263 return MALI_WRAP_CLAMP_TO_EDGE
;
265 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
266 return MALI_WRAP_CLAMP_TO_BORDER
;
268 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
269 return MALI_WRAP_MIRRORED_REPEAT
;
272 unreachable("Invalid wrap");
277 panfrost_translate_compare_func(enum pipe_compare_func in
)
280 case PIPE_FUNC_NEVER
:
281 return MALI_FUNC_NEVER
;
284 return MALI_FUNC_LESS
;
286 case PIPE_FUNC_EQUAL
:
287 return MALI_FUNC_EQUAL
;
289 case PIPE_FUNC_LEQUAL
:
290 return MALI_FUNC_LEQUAL
;
292 case PIPE_FUNC_GREATER
:
293 return MALI_FUNC_GREATER
;
295 case PIPE_FUNC_NOTEQUAL
:
296 return MALI_FUNC_NOTEQUAL
;
298 case PIPE_FUNC_GEQUAL
:
299 return MALI_FUNC_GEQUAL
;
301 case PIPE_FUNC_ALWAYS
:
302 return MALI_FUNC_ALWAYS
;
305 unreachable("Invalid func");
310 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
313 case PIPE_FUNC_NEVER
:
314 return MALI_ALT_FUNC_NEVER
;
317 return MALI_ALT_FUNC_LESS
;
319 case PIPE_FUNC_EQUAL
:
320 return MALI_ALT_FUNC_EQUAL
;
322 case PIPE_FUNC_LEQUAL
:
323 return MALI_ALT_FUNC_LEQUAL
;
325 case PIPE_FUNC_GREATER
:
326 return MALI_ALT_FUNC_GREATER
;
328 case PIPE_FUNC_NOTEQUAL
:
329 return MALI_ALT_FUNC_NOTEQUAL
;
331 case PIPE_FUNC_GEQUAL
:
332 return MALI_ALT_FUNC_GEQUAL
;
334 case PIPE_FUNC_ALWAYS
:
335 return MALI_ALT_FUNC_ALWAYS
;
338 unreachable("Invalid alt func");
343 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
346 case PIPE_STENCIL_OP_KEEP
:
347 return MALI_STENCIL_KEEP
;
349 case PIPE_STENCIL_OP_ZERO
:
350 return MALI_STENCIL_ZERO
;
352 case PIPE_STENCIL_OP_REPLACE
:
353 return MALI_STENCIL_REPLACE
;
355 case PIPE_STENCIL_OP_INCR
:
356 return MALI_STENCIL_INCR
;
358 case PIPE_STENCIL_OP_DECR
:
359 return MALI_STENCIL_DECR
;
361 case PIPE_STENCIL_OP_INCR_WRAP
:
362 return MALI_STENCIL_INCR_WRAP
;
364 case PIPE_STENCIL_OP_DECR_WRAP
:
365 return MALI_STENCIL_DECR_WRAP
;
367 case PIPE_STENCIL_OP_INVERT
:
368 return MALI_STENCIL_INVERT
;
371 unreachable("Invalid stencil op");
376 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
378 out
->ref
= 0; /* Gallium gets it from elsewhere */
380 out
->mask
= in
->valuemask
;
381 out
->func
= panfrost_translate_compare_func(in
->func
);
382 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
383 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
384 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
388 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
390 struct mali_shader_meta shader
= {
391 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
393 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
394 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
397 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
398 * required (independent of 32-bit/64-bit descriptors), or why it's not
399 * used on later GPU revisions. Otherwise, all shader jobs fault on
400 * these earlier chips (perhaps this is a chicken bit of some kind).
401 * More investigation is needed. */
404 shader
.unknown2_4
|= 0x10;
407 struct pipe_stencil_state default_stencil
= {
409 .func
= PIPE_FUNC_ALWAYS
,
410 .fail_op
= MALI_STENCIL_KEEP
,
411 .zfail_op
= MALI_STENCIL_KEEP
,
412 .zpass_op
= MALI_STENCIL_KEEP
,
417 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
418 shader
.stencil_mask_front
= default_stencil
.writemask
;
420 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
421 shader
.stencil_mask_back
= default_stencil
.writemask
;
423 if (default_stencil
.enabled
)
424 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
426 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
429 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
430 * graphics command stream. It should be called once per draw, accordding to
431 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
432 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
435 struct panfrost_transfer
436 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
438 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
439 struct mali_job_descriptor_header job
= {
440 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
441 .job_descriptor_size
= 1,
444 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
446 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
447 memcpy(transfer
.cpu
, &job
, sizeof(job
));
448 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
453 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
455 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
456 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
458 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
462 panfrost_writes_point_size(struct panfrost_context
*ctx
)
464 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
465 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
467 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
470 /* Stage the attribute descriptors so we can adjust src_offset
471 * to let BOs align nicely */
474 panfrost_stage_attributes(struct panfrost_context
*ctx
)
476 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
477 struct panfrost_vertex_state
*so
= ctx
->vertex
;
479 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
480 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
481 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
483 /* Copy as-is for the first pass */
484 memcpy(target
, so
->hw
, sz
);
486 /* Fixup offsets for the second pass. Recall that the hardware
487 * calculates attribute addresses as:
489 * addr = base + (stride * vtx) + src_offset;
491 * However, on Mali, base must be aligned to 64-bytes, so we
494 * base' = base & ~63 = base - (base & 63)
496 * To compensate when using base' (see emit_vertex_data), we have
497 * to adjust src_offset by the masked off piece:
499 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
500 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
501 * = base + (stride * vtx) + src_offset
507 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
509 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
510 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
511 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
512 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
514 /* Adjust by the masked off bits of the offset */
515 target
[i
].src_offset
+= (addr
& 63);
517 /* Also, somewhat obscurely per-instance data needs to be
518 * offset in response to a delayed start in an indexed draw */
520 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
521 target
[i
].src_offset
-= buf
->stride
* start
;
527 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
531 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
533 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
534 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
536 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
539 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
540 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
542 struct panfrost_transfer transfer
=
543 panfrost_allocate_transient(batch
, transfer_size
);
545 struct mali_sampler_descriptor
*desc
=
546 (struct mali_sampler_descriptor
*) transfer
.cpu
;
548 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
549 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
551 upload
= transfer
.gpu
;
554 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
558 static enum mali_texture_layout
559 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
561 /* TODO: other linear depth textures */
562 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
564 switch (rsrc
->layout
) {
566 return MALI_TEXTURE_AFBC
;
569 return MALI_TEXTURE_TILED
;
571 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
573 unreachable("Invalid texture layout");
579 struct panfrost_context
*ctx
,
580 struct panfrost_sampler_view
*view
)
585 struct pipe_sampler_view
*pview
= &view
->base
;
586 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
588 /* Do we interleave an explicit stride with every element? */
590 bool has_manual_stride
= view
->manual_stride
;
592 /* For easy access */
594 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
595 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
596 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
597 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
598 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
600 /* Lower-bit is set when sampling from colour AFBC */
601 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
602 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
603 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
605 /* Add the BO to the job so it's retained until the job is done. */
606 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
607 panfrost_batch_add_bo(batch
, rsrc
->bo
);
609 /* Add the usage flags in, since they can change across the CSO
610 * lifetime due to layout switches */
612 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
613 view
->hw
.format
.manual_stride
= has_manual_stride
;
615 /* Inject the addresses in, interleaving mip levels, cube faces, and
616 * strides in that order */
620 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
621 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
623 view
->hw
.payload
[idx
++] =
624 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
626 if (has_manual_stride
) {
627 view
->hw
.payload
[idx
++] =
628 rsrc
->slices
[l
].stride
;
633 return panfrost_upload_transient(batch
, &view
->hw
,
634 sizeof(struct mali_texture_descriptor
));
638 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
640 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
642 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
643 mali_ptr trampoline
= 0;
645 if (ctx
->sampler_view_count
[t
]) {
646 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
648 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
650 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
652 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
655 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
659 struct sysval_uniform
{
668 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
669 struct sysval_uniform
*uniform
)
671 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
673 uniform
->f
[0] = vp
->scale
[0];
674 uniform
->f
[1] = vp
->scale
[1];
675 uniform
->f
[2] = vp
->scale
[2];
678 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
679 struct sysval_uniform
*uniform
)
681 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
683 uniform
->f
[0] = vp
->translate
[0];
684 uniform
->f
[1] = vp
->translate
[1];
685 uniform
->f
[2] = vp
->translate
[2];
688 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
689 enum pipe_shader_type st
,
690 unsigned int sysvalid
,
691 struct sysval_uniform
*uniform
)
693 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
694 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
695 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
696 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
699 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
702 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
703 tex
->u
.tex
.first_level
);
706 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
707 tex
->u
.tex
.first_level
);
710 uniform
->i
[dim
] = tex
->texture
->array_size
;
713 static void panfrost_upload_ssbo_sysval(
714 struct panfrost_context
*ctx
,
715 enum pipe_shader_type st
,
717 struct sysval_uniform
*uniform
)
719 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
720 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
722 /* Compute address */
723 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
724 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
726 panfrost_batch_add_bo(batch
, bo
);
728 /* Upload address and size as sysval */
729 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
730 uniform
->u
[2] = sb
.buffer_size
;
733 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
734 struct sysval_uniform
*uniform
)
736 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
737 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
738 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
741 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
742 struct panfrost_shader_state
*ss
,
743 enum pipe_shader_type st
)
745 struct sysval_uniform
*uniforms
= (void *)buf
;
747 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
748 int sysval
= ss
->sysval
[i
];
750 switch (PAN_SYSVAL_TYPE(sysval
)) {
751 case PAN_SYSVAL_VIEWPORT_SCALE
:
752 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
754 case PAN_SYSVAL_VIEWPORT_OFFSET
:
755 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
757 case PAN_SYSVAL_TEXTURE_SIZE
:
758 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
761 case PAN_SYSVAL_SSBO
:
762 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
765 case PAN_SYSVAL_NUM_WORK_GROUPS
:
766 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
776 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
778 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
779 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
782 return rsrc
->bo
->cpu
;
783 else if (cb
->user_buffer
)
784 return cb
->user_buffer
;
786 unreachable("No constant buffer");
790 panfrost_map_constant_buffer_gpu(
791 struct panfrost_context
*ctx
,
792 struct panfrost_constant_buffer
*buf
,
795 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
796 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
799 return rsrc
->bo
->gpu
;
800 } else if (cb
->user_buffer
) {
801 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
802 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
804 unreachable("No constant buffer");
808 /* Compute number of UBOs active (more specifically, compute the highest UBO
809 * number addressable -- if there are gaps, include them in the count anyway).
810 * We always include UBO #0 in the count, since we *need* uniforms enabled for
814 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
816 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
817 return 32 - __builtin_clz(mask
);
820 /* Fixes up a shader state with current state, returning a GPU address to the
824 panfrost_patch_shader_state(
825 struct panfrost_context
*ctx
,
826 struct panfrost_shader_state
*ss
,
827 enum pipe_shader_type stage
,
830 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
831 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
833 ss
->tripipe
->midgard1
.flags
= 0x220;
835 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
836 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
838 /* We can't reuse over frames; that's not safe. The descriptor must be
839 * transient uploaded */
842 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
844 return panfrost_upload_transient(batch
, ss
->tripipe
,
845 sizeof(struct mali_shader_meta
));
848 /* If we don't need an upload, don't bother */
854 panfrost_patch_shader_state_compute(
855 struct panfrost_context
*ctx
,
856 enum pipe_shader_type stage
,
859 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
862 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
866 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
868 ctx
->payloads
[stage
].postfix
._shader_upper
=
869 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
872 /* Go through dirty flags and actualise them in the cmdstream. */
875 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
877 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
878 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
880 panfrost_attach_vt_framebuffer(ctx
);
882 if (with_vertex_data
) {
883 panfrost_emit_vertex_data(batch
);
885 /* Varyings emitted for -all- geometry */
886 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
887 panfrost_emit_varying_descriptor(ctx
, total_count
);
890 bool msaa
= ctx
->rasterizer
->base
.multisample
;
892 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
893 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
895 /* TODO: Sample size */
896 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
897 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
900 panfrost_batch_set_requirements(batch
);
902 if (ctx
->occlusion_query
) {
903 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
904 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
907 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
908 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
910 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
911 /* Check if we need to link the gl_PointSize varying */
912 if (!panfrost_writes_point_size(ctx
)) {
913 /* If the size is constant, write it out. Otherwise,
914 * don't touch primitive_size (since we would clobber
915 * the pointer there) */
917 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
921 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
922 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
923 ctx
->dirty
|= PAN_DIRTY_FS
;
925 if (ctx
->dirty
& PAN_DIRTY_FS
) {
926 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
927 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
929 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
931 panfrost_batch_add_bo(batch
, variant
->bo
);
933 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
936 COPY(attribute_count
);
940 COPY(midgard1
.uniform_count
);
941 COPY(midgard1
.uniform_buffer_count
);
942 COPY(midgard1
.work_count
);
943 COPY(midgard1
.flags
);
944 COPY(midgard1
.unknown2
);
948 /* Get blending setup */
949 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
951 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
953 for (unsigned c
= 0; c
< rt_count
; ++c
)
954 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
956 /* If there is a blend shader, work registers are shared. XXX: opt */
958 for (unsigned c
= 0; c
< rt_count
; ++c
) {
959 if (blend
[c
].is_shader
)
960 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
963 /* Set late due to depending on render state */
964 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
966 /* Depending on whether it's legal to in the given shader, we
967 * try to enable early-z testing (or forward-pixel kill?) */
969 if (!variant
->can_discard
)
970 flags
|= MALI_EARLY_Z
;
972 /* Any time texturing is used, derivatives are implicitly
973 * calculated, so we need to enable helper invocations */
975 if (variant
->helper_invocations
)
976 flags
|= MALI_HELPER_INVOCATIONS
;
978 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
980 /* Assign the stencil refs late */
982 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
983 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
984 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
986 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
987 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
989 /* CAN_DISCARD should be set if the fragment shader possibly
990 * contains a 'discard' instruction. It is likely this is
991 * related to optimizations related to forward-pixel kill, as
992 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
993 * thing?" by Peter Harris
996 if (variant
->can_discard
) {
997 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
998 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1001 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1002 * *also* copied to the blend_meta appended (by convention),
1003 * but this is the field actually read by the hardware. (Or
1004 * maybe both are read...?) */
1006 if (blend
[0].is_shader
) {
1007 ctx
->fragment_shader_core
.blend
.shader
=
1008 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1010 ctx
->fragment_shader_core
.blend
.shader
= 0;
1013 if (screen
->require_sfbd
) {
1014 /* When only a single render target platform is used, the blend
1015 * information is inside the shader meta itself. We
1016 * additionally need to signal CAN_DISCARD for nontrivial blend
1017 * modes (so we're able to read back the destination buffer) */
1019 if (!blend
[0].is_shader
) {
1020 ctx
->fragment_shader_core
.blend
.equation
=
1021 *blend
[0].equation
.equation
;
1022 ctx
->fragment_shader_core
.blend
.constant
=
1023 blend
[0].equation
.constant
;
1026 if (!blend
[0].no_blending
) {
1027 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1031 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1032 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1033 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1035 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1037 if (!screen
->require_sfbd
) {
1038 /* Additional blend descriptor tacked on for jobs using MFBD */
1040 struct midgard_blend_rt rts
[4];
1042 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1043 unsigned blend_count
= 0x200;
1045 if (blend
[i
].is_shader
) {
1046 /* For a blend shader, the bottom nibble corresponds to
1047 * the number of work registers used, which signals the
1048 * -existence- of a blend shader */
1050 assert(blend
[i
].shader
.work_count
>= 2);
1051 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1053 /* Otherwise, the bottom bit simply specifies if
1054 * blending (anything other than REPLACE) is enabled */
1056 if (!blend
[i
].no_blending
)
1062 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1063 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1064 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1066 rts
[i
].flags
= blend_count
;
1069 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1071 if (!ctx
->blend
->base
.dither
)
1072 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1074 /* TODO: sRGB in blend shaders is currently
1075 * unimplemented. Contact me (Alyssa) if you're
1076 * interested in working on this. We have
1077 * native Midgard ops for helping here, but
1078 * they're not well-understood yet. */
1080 assert(!(is_srgb
&& blend
[i
].is_shader
));
1082 if (blend
[i
].is_shader
) {
1083 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1085 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1086 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1090 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1094 /* We stage to transient, so always dirty.. */
1096 panfrost_stage_attributes(ctx
);
1098 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1099 panfrost_upload_sampler_descriptors(ctx
);
1101 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1102 panfrost_upload_texture_descriptors(ctx
);
1104 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1106 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1107 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1112 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1114 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1116 /* Uniforms are implicitly UBO #0 */
1117 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1119 /* Allocate room for the sysval and the uniforms */
1120 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1121 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1122 size_t size
= sys_size
+ uniform_size
;
1123 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1125 /* Upload sysvals requested by the shader */
1126 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1128 /* Upload uniforms */
1130 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1131 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1135 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1137 struct mali_vertex_tiler_postfix
*postfix
=
1138 &ctx
->payloads
[i
].postfix
;
1140 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1143 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1144 assert(ubo_count
>= 1);
1146 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1147 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1149 /* Upload uniforms as a UBO */
1150 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1151 ubos
[0].ptr
= transfer
.gpu
>> 2;
1153 /* The rest are honest-to-goodness UBOs */
1155 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1156 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1158 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1159 bool empty
= usz
== 0;
1161 if (!enabled
|| empty
) {
1162 /* Stub out disabled UBOs to catch accesses */
1165 ubos
[ubo
].ptr
= 0xDEAD0000;
1169 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1171 unsigned bytes_per_field
= 16;
1172 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1173 unsigned fields
= aligned
/ bytes_per_field
;
1175 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1176 ubos
[ubo
].ptr
= gpu
>> 2;
1179 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1180 postfix
->uniforms
= transfer
.gpu
;
1181 postfix
->uniform_buffers
= ubufs
;
1183 buf
->dirty_mask
= 0;
1186 /* TODO: Upload the viewport somewhere more appropriate */
1188 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1189 * (somewhat) asymmetric ints. */
1190 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1192 struct mali_viewport view
= {
1193 /* By default, do no viewport clipping, i.e. clip to (-inf,
1194 * inf) in each direction. Clipping to the viewport in theory
1195 * should work, but in practice causes issues when we're not
1196 * explicitly trying to scissor */
1198 .clip_minx
= -INFINITY
,
1199 .clip_miny
= -INFINITY
,
1200 .clip_maxx
= INFINITY
,
1201 .clip_maxy
= INFINITY
,
1204 /* Always scissor to the viewport by default. */
1205 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1206 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1208 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1209 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1211 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1212 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1214 /* Apply the scissor test */
1216 unsigned minx
, miny
, maxx
, maxy
;
1218 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1219 minx
= MAX2(ss
->minx
, vp_minx
);
1220 miny
= MAX2(ss
->miny
, vp_miny
);
1221 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1222 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1230 /* Hardware needs the min/max to be strictly ordered, so flip if we
1231 * need to. The viewport transformation in the vertex shader will
1232 * handle the negatives if we don't */
1235 unsigned temp
= miny
;
1241 unsigned temp
= minx
;
1252 /* Clamp to the framebuffer size as a last check */
1254 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1255 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1257 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1258 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1260 /* Update the job, unless we're doing wallpapering (whose lack of
1261 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1262 * just... be faster :) */
1264 if (!ctx
->wallpaper_batch
)
1265 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1269 view
.viewport0
[0] = minx
;
1270 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1272 view
.viewport0
[1] = miny
;
1273 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1275 view
.clip_minz
= minz
;
1276 view
.clip_maxz
= maxz
;
1278 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1279 panfrost_upload_transient(batch
,
1281 sizeof(struct mali_viewport
));
1286 /* Corresponds to exactly one draw, but does not submit anything */
1289 panfrost_queue_draw(struct panfrost_context
*ctx
)
1291 /* Handle dirty flags now */
1292 panfrost_emit_for_draw(ctx
, true);
1294 /* If rasterizer discard is enable, only submit the vertex */
1296 bool rasterizer_discard
= ctx
->rasterizer
1297 && ctx
->rasterizer
->base
.rasterizer_discard
;
1299 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1300 struct panfrost_transfer tiler
;
1302 if (!rasterizer_discard
)
1303 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1305 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1307 if (rasterizer_discard
)
1308 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1309 else if (ctx
->wallpaper_batch
)
1310 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1312 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1315 /* The entire frame is in memory -- send it off to the kernel! */
1318 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1319 struct panfrost_batch
*batch
)
1321 panfrost_batch_submit(batch
);
1323 /* If visual, we can stall a frame */
1325 if (!flush_immediate
)
1326 panfrost_drm_force_flush_fragment(ctx
);
1328 ctx
->last_fragment_flushed
= false;
1329 ctx
->last_batch
= batch
;
1331 /* If readback, flush now (hurts the pipelined performance) */
1332 if (flush_immediate
)
1333 panfrost_drm_force_flush_fragment(ctx
);
1337 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1339 struct panfrost_context
*ctx
= pan_context(pipe
);
1341 /* Nothing to reload? TODO: MRT wallpapers */
1342 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1345 /* Check if the buffer has any content on it worth preserving */
1347 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1348 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1349 unsigned level
= surf
->u
.tex
.level
;
1351 if (!rsrc
->slices
[level
].initialized
)
1354 /* Save the batch */
1355 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1357 ctx
->wallpaper_batch
= batch
;
1359 /* Clamp the rendering area to the damage extent. The
1360 * KHR_partial_update() spec states that trying to render outside of
1361 * the damage region is "undefined behavior", so we should be safe.
1363 unsigned damage_width
= (rsrc
->damage
.extent
.maxx
- rsrc
->damage
.extent
.minx
);
1364 unsigned damage_height
= (rsrc
->damage
.extent
.maxy
- rsrc
->damage
.extent
.miny
);
1366 if (damage_width
&& damage_height
) {
1367 panfrost_batch_intersection_scissor(batch
,
1368 rsrc
->damage
.extent
.minx
,
1369 rsrc
->damage
.extent
.miny
,
1370 rsrc
->damage
.extent
.maxx
,
1371 rsrc
->damage
.extent
.maxy
);
1374 /* FIXME: Looks like aligning on a tile is not enough, but
1375 * aligning on twice the tile size seems to works. We don't
1376 * know exactly what happens here but this deserves extra
1377 * investigation to figure it out.
1379 batch
->minx
= batch
->minx
& ~((MALI_TILE_LENGTH
* 2) - 1);
1380 batch
->miny
= batch
->miny
& ~((MALI_TILE_LENGTH
* 2) - 1);
1381 batch
->maxx
= MIN2(ALIGN_POT(batch
->maxx
, MALI_TILE_LENGTH
* 2),
1383 batch
->maxy
= MIN2(ALIGN_POT(batch
->maxy
, MALI_TILE_LENGTH
* 2),
1384 rsrc
->base
.height0
);
1386 struct pipe_scissor_state damage
;
1387 struct pipe_box rects
[4];
1389 /* Clamp the damage box to the rendering area. */
1390 damage
.minx
= MAX2(batch
->minx
, rsrc
->damage
.biggest_rect
.x
);
1391 damage
.miny
= MAX2(batch
->miny
, rsrc
->damage
.biggest_rect
.y
);
1392 damage
.maxx
= MIN2(batch
->maxx
,
1393 rsrc
->damage
.biggest_rect
.x
+
1394 rsrc
->damage
.biggest_rect
.width
);
1395 damage
.maxy
= MIN2(batch
->maxy
,
1396 rsrc
->damage
.biggest_rect
.y
+
1397 rsrc
->damage
.biggest_rect
.height
);
1399 /* One damage rectangle means we can end up with at most 4 reload
1401 * 1: left region, only exists if damage.x > 0
1402 * 2: right region, only exists if damage.x + damage.width < fb->width
1403 * 3: top region, only exists if damage.y > 0. The intersection with
1404 * the left and right regions are dropped
1405 * 4: bottom region, only exists if damage.y + damage.height < fb->height.
1406 * The intersection with the left and right regions are dropped
1408 * ____________________________
1415 * |_______|___________|______|
1417 u_box_2d(batch
->minx
, batch
->miny
, damage
.minx
- batch
->minx
,
1418 batch
->maxy
- batch
->miny
, &rects
[0]);
1419 u_box_2d(damage
.maxx
, batch
->miny
, batch
->maxx
- damage
.maxx
,
1420 batch
->maxy
- batch
->miny
, &rects
[1]);
1421 u_box_2d(damage
.minx
, batch
->miny
, damage
.maxx
- damage
.minx
,
1422 damage
.miny
- batch
->miny
, &rects
[2]);
1423 u_box_2d(damage
.minx
, damage
.maxy
, damage
.maxx
- damage
.minx
,
1424 batch
->maxy
- damage
.maxy
, &rects
[3]);
1426 for (unsigned i
= 0; i
< 4; i
++) {
1427 /* Width and height are always >= 0 even if width is declared as a
1428 * signed integer: u_box_2d() helper takes unsigned args and
1429 * panfrost_set_damage_region() is taking care of clamping
1432 if (!rects
[i
].width
|| !rects
[i
].height
)
1435 /* Blit the wallpaper in */
1436 panfrost_blit_wallpaper(ctx
, &rects
[i
]);
1438 ctx
->wallpaper_batch
= NULL
;
1443 struct pipe_context
*pipe
,
1444 struct pipe_fence_handle
**fence
,
1447 struct panfrost_context
*ctx
= pan_context(pipe
);
1448 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1450 /* Nothing to do! */
1451 if (!batch
->last_job
.gpu
&& !batch
->clear
) return;
1453 if (!batch
->clear
&& batch
->last_tiler
.gpu
)
1454 panfrost_draw_wallpaper(&ctx
->base
);
1456 /* Whether to stall the pipeline for immediately correct results. Since
1457 * pipelined rendering is quite broken right now (to be fixed by the
1458 * panfrost_job refactor, just take the perf hit for correctness) */
1459 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1461 /* Submit the frame itself */
1462 panfrost_submit_frame(ctx
, flush_immediate
, batch
);
1465 struct panfrost_fence
*f
= panfrost_fence_create(ctx
);
1466 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1467 *fence
= (struct pipe_fence_handle
*)f
;
1470 /* Prepare for the next frame */
1471 panfrost_invalidate_frame(ctx
);
1474 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1477 g2m_draw_mode(enum pipe_prim_type mode
)
1480 DEFINE_CASE(POINTS
);
1482 DEFINE_CASE(LINE_LOOP
);
1483 DEFINE_CASE(LINE_STRIP
);
1484 DEFINE_CASE(TRIANGLES
);
1485 DEFINE_CASE(TRIANGLE_STRIP
);
1486 DEFINE_CASE(TRIANGLE_FAN
);
1488 DEFINE_CASE(QUAD_STRIP
);
1489 DEFINE_CASE(POLYGON
);
1492 unreachable("Invalid draw mode");
1499 panfrost_translate_index_size(unsigned size
)
1503 return MALI_DRAW_INDEXED_UINT8
;
1506 return MALI_DRAW_INDEXED_UINT16
;
1509 return MALI_DRAW_INDEXED_UINT32
;
1512 unreachable("Invalid index size");
1516 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1517 * good for the duration of the draw (transient), could last longer */
1520 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1522 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1524 off_t offset
= info
->start
* info
->index_size
;
1525 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1527 if (!info
->has_user_indices
) {
1528 /* Only resources can be directly mapped */
1529 panfrost_batch_add_bo(batch
, rsrc
->bo
);
1530 return rsrc
->bo
->gpu
+ offset
;
1532 /* Otherwise, we need to upload to transient memory */
1533 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1534 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1539 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1541 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1543 /* Check if we're scissoring at all */
1545 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1548 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1551 /* Count generated primitives (when there is no geom/tess shaders) for
1552 * transform feedback */
1555 panfrost_statistics_record(
1556 struct panfrost_context
*ctx
,
1557 const struct pipe_draw_info
*info
)
1559 if (!ctx
->active_queries
)
1562 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1563 ctx
->prims_generated
+= prims
;
1565 if (!ctx
->streamout
.num_targets
)
1568 ctx
->tf_prims_generated
+= prims
;
1573 struct pipe_context
*pipe
,
1574 const struct pipe_draw_info
*info
)
1576 struct panfrost_context
*ctx
= pan_context(pipe
);
1578 /* First of all, check the scissor to see if anything is drawn at all.
1579 * If it's not, we drop the draw (mostly a conformance issue;
1580 * well-behaved apps shouldn't hit this) */
1582 if (panfrost_scissor_culls_everything(ctx
))
1585 int mode
= info
->mode
;
1587 /* Fallback unsupported restart index */
1588 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1590 if (info
->primitive_restart
&& info
->index_size
1591 && info
->restart_index
!= primitive_index
) {
1592 util_draw_vbo_without_prim_restart(pipe
, info
);
1596 /* Fallback for unsupported modes */
1598 assert(ctx
->rasterizer
!= NULL
);
1600 if (!(ctx
->draw_modes
& (1 << mode
))) {
1601 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1602 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1604 if (info
->count
< 4) {
1605 /* Degenerate case? */
1609 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1610 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1615 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1616 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1618 /* Now that we have a guaranteed terminating path, find the job.
1619 * Assignment commented out to prevent unused warning */
1621 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1623 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1625 /* Take into account a negative bias */
1626 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1627 ctx
->instance_count
= info
->instance_count
;
1628 ctx
->active_prim
= info
->mode
;
1630 /* For non-indexed draws, they're the same */
1631 unsigned vertex_count
= ctx
->vertex_count
;
1633 unsigned draw_flags
= 0;
1635 /* The draw flags interpret how primitive size is interpreted */
1637 if (panfrost_writes_point_size(ctx
))
1638 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1640 if (info
->primitive_restart
)
1641 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1643 /* For higher amounts of vertices (greater than what fits in a 16-bit
1644 * short), the other value is needed, otherwise there will be bizarre
1645 * rendering artefacts. It's not clear what these values mean yet. This
1646 * change is also needed for instancing and sometimes points (perhaps
1647 * related to dynamically setting gl_PointSize) */
1649 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1650 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1651 bool instanced
= ctx
->instance_count
> 1;
1653 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1655 /* This doesn't make much sense */
1656 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1657 draw_flags
|= 0x800;
1660 panfrost_statistics_record(ctx
, info
);
1662 if (info
->index_size
) {
1663 /* Calculate the min/max index used so we can figure out how
1664 * many times to invoke the vertex shader */
1666 /* Fetch / calculate index bounds */
1667 unsigned min_index
= 0, max_index
= 0;
1669 if (info
->max_index
== ~0u) {
1670 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1672 min_index
= info
->min_index
;
1673 max_index
= info
->max_index
;
1676 /* Use the corresponding values */
1677 vertex_count
= max_index
- min_index
+ 1;
1678 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1679 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1681 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1682 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1684 //assert(!info->restart_index); /* TODO: Research */
1686 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1687 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1689 /* Index count == vertex count, if no indexing is applied, as
1690 * if it is internally indexed in the expected order */
1692 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1693 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1695 /* Reverse index state */
1696 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1699 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1700 * vertex_count, 1) */
1702 panfrost_pack_work_groups_fused(
1703 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1704 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1705 1, vertex_count
, info
->instance_count
,
1708 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1710 /* Encode the padded vertex count */
1712 if (info
->instance_count
> 1) {
1713 /* Triangles have non-even vertex counts so they change how
1714 * padding works internally */
1717 mode
== PIPE_PRIM_TRIANGLES
||
1718 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1719 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1721 struct pan_shift_odd so
=
1722 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1724 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1725 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1727 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1728 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1730 ctx
->padded_count
= pan_expand_shift_odd(so
);
1732 ctx
->padded_count
= ctx
->vertex_count
;
1734 /* Reset instancing state */
1735 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1736 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1737 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1738 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1741 /* Fire off the draw itself */
1742 panfrost_queue_draw(ctx
);
1744 /* Increment transform feedback offsets */
1746 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1747 unsigned output_count
= u_stream_outputs_for_vertices(
1748 ctx
->active_prim
, ctx
->vertex_count
);
1750 ctx
->streamout
.offsets
[i
] += output_count
;
1757 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1763 panfrost_create_rasterizer_state(
1764 struct pipe_context
*pctx
,
1765 const struct pipe_rasterizer_state
*cso
)
1767 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1771 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1772 so
->tiler_gl_enables
= 0x7;
1775 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1777 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1778 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1780 if (cso
->cull_face
& PIPE_FACE_BACK
)
1781 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1787 panfrost_bind_rasterizer_state(
1788 struct pipe_context
*pctx
,
1791 struct panfrost_context
*ctx
= pan_context(pctx
);
1793 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1797 ctx
->rasterizer
= hwcso
;
1798 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1800 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1801 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1803 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1804 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1806 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1808 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1809 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1811 /* Point sprites are emulated */
1813 struct panfrost_shader_state
*variant
=
1814 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1816 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1817 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1821 panfrost_create_vertex_elements_state(
1822 struct pipe_context
*pctx
,
1823 unsigned num_elements
,
1824 const struct pipe_vertex_element
*elements
)
1826 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1828 so
->num_elements
= num_elements
;
1829 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1831 for (int i
= 0; i
< num_elements
; ++i
) {
1832 so
->hw
[i
].index
= i
;
1834 enum pipe_format fmt
= elements
[i
].src_format
;
1835 const struct util_format_description
*desc
= util_format_description(fmt
);
1836 so
->hw
[i
].unknown1
= 0x2;
1837 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1839 so
->hw
[i
].format
= panfrost_find_format(desc
);
1841 /* The field itself should probably be shifted over */
1842 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1849 panfrost_bind_vertex_elements_state(
1850 struct pipe_context
*pctx
,
1853 struct panfrost_context
*ctx
= pan_context(pctx
);
1855 ctx
->vertex
= hwcso
;
1856 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1860 panfrost_create_shader_state(
1861 struct pipe_context
*pctx
,
1862 const struct pipe_shader_state
*cso
)
1864 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1867 /* Token deep copy to prevent memory corruption */
1869 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1870 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1876 panfrost_delete_shader_state(
1877 struct pipe_context
*pctx
,
1880 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1882 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1883 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1886 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1887 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1888 panfrost_bo_unreference(pctx
->screen
, shader_state
->bo
);
1889 shader_state
->bo
= NULL
;
1896 panfrost_create_sampler_state(
1897 struct pipe_context
*pctx
,
1898 const struct pipe_sampler_state
*cso
)
1900 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1903 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1905 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1906 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1907 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1909 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1910 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1911 unsigned mip_filter
= mip_linear
?
1912 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1913 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1915 struct mali_sampler_descriptor sampler_descriptor
= {
1916 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1917 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1918 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1919 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1920 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1922 cso
->border_color
.f
[0],
1923 cso
->border_color
.f
[1],
1924 cso
->border_color
.f
[2],
1925 cso
->border_color
.f
[3]
1927 .min_lod
= FIXED_16(cso
->min_lod
),
1928 .max_lod
= FIXED_16(cso
->max_lod
),
1929 .seamless_cube_map
= cso
->seamless_cube_map
,
1932 /* If necessary, we disable mipmapping in the sampler descriptor by
1933 * clamping the LOD as tight as possible (from 0 to epsilon,
1934 * essentially -- remember these are fixed point numbers, so
1937 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1938 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1940 /* Enforce that there is something in the middle by adding epsilon*/
1942 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1943 sampler_descriptor
.max_lod
++;
1946 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1948 so
->hw
= sampler_descriptor
;
1954 panfrost_bind_sampler_states(
1955 struct pipe_context
*pctx
,
1956 enum pipe_shader_type shader
,
1957 unsigned start_slot
, unsigned num_sampler
,
1960 assert(start_slot
== 0);
1962 struct panfrost_context
*ctx
= pan_context(pctx
);
1964 /* XXX: Should upload, not just copy? */
1965 ctx
->sampler_count
[shader
] = num_sampler
;
1966 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1968 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1972 panfrost_variant_matches(
1973 struct panfrost_context
*ctx
,
1974 struct panfrost_shader_state
*variant
,
1975 enum pipe_shader_type type
)
1977 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1978 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1980 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1982 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1983 /* Make sure enable state is at least the same */
1984 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1988 /* Check that the contents of the test are the same */
1989 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1990 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1992 if (!(same_func
&& same_ref
)) {
1997 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1998 variant
->point_sprite_mask
)) {
1999 /* Ensure the same varyings are turned to point sprites */
2000 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
2003 /* Ensure the orientation is correct */
2005 rasterizer
->sprite_coord_mode
==
2006 PIPE_SPRITE_COORD_UPPER_LEFT
;
2008 if (variant
->point_sprite_upper_left
!= upper_left
)
2012 /* Otherwise, we're good to go */
2017 * Fix an uncompiled shader's stream output info, and produce a bitmask
2018 * of which VARYING_SLOT_* are captured for stream output.
2020 * Core Gallium stores output->register_index as a "slot" number, where
2021 * slots are assigned consecutively to all outputs in info->outputs_written.
2022 * This naive packing of outputs doesn't work for us - we too have slots,
2023 * but the layout is defined by the VUE map, which we won't have until we
2024 * compile a specific shader variant. So, we remap these and simply store
2025 * VARYING_SLOT_* in our copy's output->register_index fields.
2027 * We then produce a bitmask of outputs which are used for SO.
2029 * Implementation from iris.
2033 update_so_info(struct pipe_stream_output_info
*so_info
,
2034 uint64_t outputs_written
)
2036 uint64_t so_outputs
= 0;
2037 uint8_t reverse_map
[64] = {};
2040 while (outputs_written
)
2041 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
2043 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
2044 struct pipe_stream_output
*output
= &so_info
->output
[i
];
2046 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
2047 output
->register_index
= reverse_map
[output
->register_index
];
2049 so_outputs
|= 1ull << output
->register_index
;
2056 panfrost_bind_shader_state(
2057 struct pipe_context
*pctx
,
2059 enum pipe_shader_type type
)
2061 struct panfrost_context
*ctx
= pan_context(pctx
);
2063 ctx
->shader
[type
] = hwcso
;
2065 if (type
== PIPE_SHADER_FRAGMENT
)
2066 ctx
->dirty
|= PAN_DIRTY_FS
;
2068 ctx
->dirty
|= PAN_DIRTY_VS
;
2072 /* Match the appropriate variant */
2074 signed variant
= -1;
2075 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2077 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2078 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2084 if (variant
== -1) {
2085 /* No variant matched, so create a new one */
2086 variant
= variants
->variant_count
++;
2087 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2089 struct panfrost_shader_state
*v
=
2090 &variants
->variants
[variant
];
2092 if (type
== PIPE_SHADER_FRAGMENT
) {
2093 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2095 if (ctx
->rasterizer
) {
2096 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2097 v
->point_sprite_upper_left
=
2098 ctx
->rasterizer
->base
.sprite_coord_mode
==
2099 PIPE_SPRITE_COORD_UPPER_LEFT
;
2103 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
2107 /* Select this variant */
2108 variants
->active_variant
= variant
;
2110 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2111 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2113 /* We finally have a variant, so compile it */
2115 if (!shader_state
->compiled
) {
2116 uint64_t outputs_written
= 0;
2118 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2119 variants
->base
.type
,
2120 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2121 variants
->base
.ir
.nir
:
2122 variants
->base
.tokens
,
2123 tgsi_processor_to_shader_stage(type
), shader_state
,
2126 shader_state
->compiled
= true;
2128 /* Fixup the stream out information, since what Gallium returns
2129 * normally is mildly insane */
2131 shader_state
->stream_output
= variants
->base
.stream_output
;
2132 shader_state
->so_mask
=
2133 update_so_info(&shader_state
->stream_output
, outputs_written
);
2138 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2140 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2144 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2146 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2150 panfrost_set_vertex_buffers(
2151 struct pipe_context
*pctx
,
2152 unsigned start_slot
,
2153 unsigned num_buffers
,
2154 const struct pipe_vertex_buffer
*buffers
)
2156 struct panfrost_context
*ctx
= pan_context(pctx
);
2158 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2162 panfrost_set_constant_buffer(
2163 struct pipe_context
*pctx
,
2164 enum pipe_shader_type shader
, uint index
,
2165 const struct pipe_constant_buffer
*buf
)
2167 struct panfrost_context
*ctx
= pan_context(pctx
);
2168 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2170 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2172 unsigned mask
= (1 << index
);
2174 if (unlikely(!buf
)) {
2175 pbuf
->enabled_mask
&= ~mask
;
2176 pbuf
->dirty_mask
&= ~mask
;
2180 pbuf
->enabled_mask
|= mask
;
2181 pbuf
->dirty_mask
|= mask
;
2185 panfrost_set_stencil_ref(
2186 struct pipe_context
*pctx
,
2187 const struct pipe_stencil_ref
*ref
)
2189 struct panfrost_context
*ctx
= pan_context(pctx
);
2190 ctx
->stencil_ref
= *ref
;
2192 /* Shader core dirty */
2193 ctx
->dirty
|= PAN_DIRTY_FS
;
2196 static enum mali_texture_type
2197 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2201 case PIPE_TEXTURE_1D
:
2202 case PIPE_TEXTURE_1D_ARRAY
:
2205 case PIPE_TEXTURE_2D
:
2206 case PIPE_TEXTURE_2D_ARRAY
:
2207 case PIPE_TEXTURE_RECT
:
2210 case PIPE_TEXTURE_3D
:
2213 case PIPE_TEXTURE_CUBE
:
2214 case PIPE_TEXTURE_CUBE_ARRAY
:
2215 return MALI_TEX_CUBE
;
2218 unreachable("Unknown target");
2222 static struct pipe_sampler_view
*
2223 panfrost_create_sampler_view(
2224 struct pipe_context
*pctx
,
2225 struct pipe_resource
*texture
,
2226 const struct pipe_sampler_view
*template)
2228 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2229 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2231 pipe_reference(NULL
, &texture
->reference
);
2233 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2236 so
->base
= *template;
2237 so
->base
.texture
= texture
;
2238 so
->base
.reference
.count
= 1;
2239 so
->base
.context
= pctx
;
2241 /* sampler_views correspond to texture descriptors, minus the texture
2242 * (data) itself. So, we serialise the descriptor here and cache it for
2245 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2247 unsigned char user_swizzle
[4] = {
2248 template->swizzle_r
,
2249 template->swizzle_g
,
2250 template->swizzle_b
,
2254 enum mali_format format
= panfrost_find_format(desc
);
2256 /* Check if we need to set a custom stride by computing the "expected"
2257 * stride and comparing it to what the BO actually wants. Only applies
2258 * to linear textures, since tiled/compressed textures have strict
2259 * alignment requirements for their strides as it is */
2261 unsigned first_level
= template->u
.tex
.first_level
;
2262 unsigned last_level
= template->u
.tex
.last_level
;
2264 if (prsrc
->layout
== PAN_LINEAR
) {
2265 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2266 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2267 unsigned width
= u_minify(texture
->width0
, l
);
2268 unsigned comp_stride
= width
* bytes_per_pixel
;
2270 if (comp_stride
!= actual_stride
) {
2271 so
->manual_stride
= true;
2277 /* In the hardware, array_size refers specifically to array textures,
2278 * whereas in Gallium, it also covers cubemaps */
2280 unsigned array_size
= texture
->array_size
;
2282 if (template->target
== PIPE_TEXTURE_CUBE
) {
2283 /* TODO: Cubemap arrays */
2284 assert(array_size
== 6);
2288 struct mali_texture_descriptor texture_descriptor
= {
2289 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2290 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2291 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2292 .array_size
= MALI_POSITIVE(array_size
),
2295 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2297 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2298 .type
= panfrost_translate_texture_type(template->target
),
2302 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2305 texture_descriptor
.levels
= last_level
- first_level
;
2307 so
->hw
= texture_descriptor
;
2309 return (struct pipe_sampler_view
*) so
;
2313 panfrost_set_sampler_views(
2314 struct pipe_context
*pctx
,
2315 enum pipe_shader_type shader
,
2316 unsigned start_slot
, unsigned num_views
,
2317 struct pipe_sampler_view
**views
)
2319 struct panfrost_context
*ctx
= pan_context(pctx
);
2321 assert(start_slot
== 0);
2323 unsigned new_nr
= 0;
2324 for (unsigned i
= 0; i
< num_views
; ++i
) {
2329 ctx
->sampler_view_count
[shader
] = new_nr
;
2330 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2332 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2336 panfrost_sampler_view_destroy(
2337 struct pipe_context
*pctx
,
2338 struct pipe_sampler_view
*view
)
2340 pipe_resource_reference(&view
->texture
, NULL
);
2345 panfrost_set_shader_buffers(
2346 struct pipe_context
*pctx
,
2347 enum pipe_shader_type shader
,
2348 unsigned start
, unsigned count
,
2349 const struct pipe_shader_buffer
*buffers
,
2350 unsigned writable_bitmask
)
2352 struct panfrost_context
*ctx
= pan_context(pctx
);
2354 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2355 buffers
, start
, count
);
2358 /* Hints that a framebuffer should use AFBC where possible */
2362 struct panfrost_screen
*screen
,
2363 const struct pipe_framebuffer_state
*fb
)
2365 /* AFBC implemenation incomplete; hide it */
2366 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2368 /* Hint AFBC to the resources bound to each color buffer */
2370 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2371 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2372 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2373 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2376 /* Also hint it to the depth buffer */
2379 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2380 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2385 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2386 const struct pipe_framebuffer_state
*fb
)
2388 struct panfrost_context
*ctx
= pan_context(pctx
);
2390 /* Flush when switching framebuffers, but not if the framebuffer
2391 * state is being restored by u_blitter
2394 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2395 bool is_scanout
= panfrost_batch_is_scanout(batch
);
2396 bool has_draws
= batch
->last_job
.gpu
;
2398 /* Bail out early when the current and new states are the same. */
2399 if (util_framebuffer_state_equal(&ctx
->pipe_framebuffer
, fb
))
2402 /* The wallpaper logic sets a new FB state before doing the blit and
2403 * restore the old one when it's done. Those FB states are reported to
2404 * be different because the surface they are pointing to are different,
2405 * but those surfaces actually point to the same cbufs/zbufs. In that
2406 * case we definitely don't want new FB descs to be emitted/attached
2407 * since the job is expected to be flushed just after the blit is done,
2408 * so let's just copy the new state and return here.
2410 if (ctx
->wallpaper_batch
) {
2411 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2415 if (!is_scanout
|| has_draws
)
2416 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2418 assert(!ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
&&
2419 !ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
2421 /* Invalidate the FBO job cache since we've just been assigned a new
2426 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2428 /* Given that we're rendering, we'd love to have compression */
2429 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2431 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2432 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
2433 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
2437 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2438 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2440 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2444 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2447 struct panfrost_context
*ctx
= pan_context(pipe
);
2448 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2449 ctx
->depth_stencil
= depth_stencil
;
2454 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2455 * emulated in the fragment shader */
2457 if (depth_stencil
->alpha
.enabled
) {
2458 /* We need to trigger a new shader (maybe) */
2459 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2463 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2465 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2466 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2468 /* If back-stencil is not enabled, use the front values */
2469 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2470 unsigned back_index
= back_enab
? 1 : 0;
2472 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2473 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2475 /* Depth state (TODO: Refactor) */
2476 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2478 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2480 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2481 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2483 /* Bounds test not implemented */
2484 assert(!depth_stencil
->depth
.bounds_test
);
2486 ctx
->dirty
|= PAN_DIRTY_FS
;
2490 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2496 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2497 unsigned sample_mask
)
2502 panfrost_set_clip_state(struct pipe_context
*pipe
,
2503 const struct pipe_clip_state
*clip
)
2505 //struct panfrost_context *panfrost = pan_context(pipe);
2509 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2510 unsigned start_slot
,
2511 unsigned num_viewports
,
2512 const struct pipe_viewport_state
*viewports
)
2514 struct panfrost_context
*ctx
= pan_context(pipe
);
2516 assert(start_slot
== 0);
2517 assert(num_viewports
== 1);
2519 ctx
->pipe_viewport
= *viewports
;
2523 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2524 unsigned start_slot
,
2525 unsigned num_scissors
,
2526 const struct pipe_scissor_state
*scissors
)
2528 struct panfrost_context
*ctx
= pan_context(pipe
);
2530 assert(start_slot
== 0);
2531 assert(num_scissors
== 1);
2533 ctx
->scissor
= *scissors
;
2537 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2538 const struct pipe_poly_stipple
*stipple
)
2540 //struct panfrost_context *panfrost = pan_context(pipe);
2544 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2547 struct panfrost_context
*ctx
= pan_context(pipe
);
2548 ctx
->active_queries
= enable
;
2552 panfrost_destroy(struct pipe_context
*pipe
)
2554 struct panfrost_context
*panfrost
= pan_context(pipe
);
2555 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2557 if (panfrost
->blitter
)
2558 util_blitter_destroy(panfrost
->blitter
);
2560 if (panfrost
->blitter_wallpaper
)
2561 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2563 panfrost_drm_release_bo(screen
, panfrost
->scratchpad
, false);
2564 panfrost_drm_release_bo(screen
, panfrost
->tiler_heap
, false);
2565 panfrost_drm_release_bo(screen
, panfrost
->tiler_dummy
, false);
2570 static struct pipe_query
*
2571 panfrost_create_query(struct pipe_context
*pipe
,
2575 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2580 return (struct pipe_query
*) q
;
2584 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2590 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2592 struct panfrost_context
*ctx
= pan_context(pipe
);
2593 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2594 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2596 switch (query
->type
) {
2597 case PIPE_QUERY_OCCLUSION_COUNTER
:
2598 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2599 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2600 /* Allocate a word for the query results to be stored */
2601 query
->transfer
= panfrost_allocate_transient(batch
, sizeof(unsigned));
2602 ctx
->occlusion_query
= query
;
2605 /* Geometry statistics are computed in the driver. XXX: geom/tess
2608 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2609 query
->start
= ctx
->prims_generated
;
2611 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2612 query
->start
= ctx
->tf_prims_generated
;
2616 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2624 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2626 struct panfrost_context
*ctx
= pan_context(pipe
);
2627 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2629 switch (query
->type
) {
2630 case PIPE_QUERY_OCCLUSION_COUNTER
:
2631 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2632 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2633 ctx
->occlusion_query
= NULL
;
2635 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2636 query
->end
= ctx
->prims_generated
;
2638 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2639 query
->end
= ctx
->tf_prims_generated
;
2647 panfrost_get_query_result(struct pipe_context
*pipe
,
2648 struct pipe_query
*q
,
2650 union pipe_query_result
*vresult
)
2652 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2655 switch (query
->type
) {
2656 case PIPE_QUERY_OCCLUSION_COUNTER
:
2657 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2658 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2660 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2662 /* Read back the query results */
2663 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2664 unsigned passed
= *result
;
2666 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2667 vresult
->u64
= passed
;
2669 vresult
->b
= !!passed
;
2674 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2675 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2676 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2677 vresult
->u64
= query
->end
- query
->start
;
2681 DBG("Skipped query get %u\n", query
->type
);
2688 static struct pipe_stream_output_target
*
2689 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2690 struct pipe_resource
*prsc
,
2691 unsigned buffer_offset
,
2692 unsigned buffer_size
)
2694 struct pipe_stream_output_target
*target
;
2696 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2701 pipe_reference_init(&target
->reference
, 1);
2702 pipe_resource_reference(&target
->buffer
, prsc
);
2704 target
->context
= pctx
;
2705 target
->buffer_offset
= buffer_offset
;
2706 target
->buffer_size
= buffer_size
;
2712 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2713 struct pipe_stream_output_target
*target
)
2715 pipe_resource_reference(&target
->buffer
, NULL
);
2716 ralloc_free(target
);
2720 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2721 unsigned num_targets
,
2722 struct pipe_stream_output_target
**targets
,
2723 const unsigned *offsets
)
2725 struct panfrost_context
*ctx
= pan_context(pctx
);
2726 struct panfrost_streamout
*so
= &ctx
->streamout
;
2728 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2730 for (unsigned i
= 0; i
< num_targets
; i
++) {
2731 if (offsets
[i
] != -1)
2732 so
->offsets
[i
] = offsets
[i
];
2734 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2737 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2738 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2740 so
->num_targets
= num_targets
;
2744 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2746 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2747 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2749 ctx
->scratchpad
= panfrost_drm_create_bo(screen
, 64 * 4 * 4096, 0);
2750 ctx
->tiler_heap
= panfrost_drm_create_bo(screen
, 4096 * 4096,
2751 PAN_ALLOCATE_INVISIBLE
|
2752 PAN_ALLOCATE_GROWABLE
);
2753 ctx
->tiler_dummy
= panfrost_drm_create_bo(screen
, 4096,
2754 PAN_ALLOCATE_INVISIBLE
);
2755 assert(ctx
->scratchpad
&& ctx
->tiler_heap
&& ctx
->tiler_dummy
);
2758 /* New context creation, which also does hardware initialisation since I don't
2759 * know the better way to structure this :smirk: */
2761 struct pipe_context
*
2762 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2764 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2765 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2766 memset(ctx
, 0, sizeof(*ctx
));
2767 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2769 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2771 gallium
->screen
= screen
;
2773 gallium
->destroy
= panfrost_destroy
;
2775 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2777 gallium
->flush
= panfrost_flush
;
2778 gallium
->clear
= panfrost_clear
;
2779 gallium
->draw_vbo
= panfrost_draw_vbo
;
2781 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2782 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2783 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2785 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2787 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2788 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2789 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2791 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2792 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2793 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2795 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2796 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2797 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2799 gallium
->create_fs_state
= panfrost_create_shader_state
;
2800 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2801 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2803 gallium
->create_vs_state
= panfrost_create_shader_state
;
2804 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2805 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2807 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2808 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2809 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2811 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2812 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2813 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2815 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2817 gallium
->set_clip_state
= panfrost_set_clip_state
;
2818 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2819 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2820 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2821 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2823 gallium
->create_query
= panfrost_create_query
;
2824 gallium
->destroy_query
= panfrost_destroy_query
;
2825 gallium
->begin_query
= panfrost_begin_query
;
2826 gallium
->end_query
= panfrost_end_query
;
2827 gallium
->get_query_result
= panfrost_get_query_result
;
2829 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2830 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2831 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2833 panfrost_resource_context_init(gallium
);
2834 panfrost_blend_context_init(gallium
);
2835 panfrost_compute_context_init(gallium
);
2837 panfrost_drm_init_context(ctx
);
2839 panfrost_setup_hardware(ctx
);
2842 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2843 gallium
->const_uploader
= gallium
->stream_uploader
;
2844 assert(gallium
->stream_uploader
);
2846 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2847 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2849 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2851 ctx
->blitter
= util_blitter_create(gallium
);
2852 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2854 assert(ctx
->blitter
);
2855 assert(ctx
->blitter_wallpaper
);
2857 ctx
->last_fragment_flushed
= true;
2858 ctx
->last_batch
= NULL
;
2860 /* Prepare for render! */
2862 panfrost_batch_init(ctx
);
2863 panfrost_emit_vertex_payload(ctx
);
2864 panfrost_emit_tiler_payload(ctx
);
2865 panfrost_invalidate_frame(ctx
);
2866 panfrost_default_shader_backend(ctx
);