2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
49 #include "pan_tiler.h"
51 static int performance_counter_number
= 0;
52 extern const char *pan_counters_base
;
54 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
57 static enum mali_job_type
58 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
61 case PIPE_SHADER_VERTEX
:
62 return JOB_TYPE_VERTEX
;
64 case PIPE_SHADER_FRAGMENT
:
65 /* Note: JOB_TYPE_FRAGMENT is different.
66 * JOB_TYPE_FRAGMENT actually executes the
67 * fragment shader, but JOB_TYPE_TILER is how you
69 return JOB_TYPE_TILER
;
71 case PIPE_SHADER_GEOMETRY
:
72 return JOB_TYPE_GEOMETRY
;
74 case PIPE_SHADER_COMPUTE
:
75 return JOB_TYPE_COMPUTE
;
78 unreachable("Unsupported shader stage");
83 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
85 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
86 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
87 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
88 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
90 /* 8 byte checksum per tile */
91 rsrc
->bo
->checksum_stride
= tile_w
* 8;
92 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
93 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
95 rsrc
->bo
->has_checksum
= true;
98 /* Framebuffer descriptor */
101 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
103 fb
->width
= MALI_POSITIVE(w
);
104 fb
->height
= MALI_POSITIVE(h
);
106 /* No idea why this is needed, but it's how resolution_check is
107 * calculated. It's not clear to us yet why the hardware wants this.
108 * The formula itself was discovered mostly by manual bruteforce and
109 * aggressive algebraic simplification. */
111 fb
->tiler_resolution_check
= ((w
+ h
) / 3) << 4;
114 struct mali_single_framebuffer
115 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
117 struct mali_single_framebuffer framebuffer
= {
119 .format
= 0x30000000,
120 .clear_flags
= 0x1000,
121 .unknown_address_0
= ctx
->scratchpad
.gpu
,
122 .tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
,
123 .tiler_polygon_list_body
= ctx
->tiler_polygon_list
.gpu
+ 40960,
124 .tiler_hierarchy_mask
= 0xF0,
126 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
127 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
130 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
135 struct bifrost_framebuffer
136 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
138 unsigned width
= ctx
->pipe_framebuffer
.width
;
139 unsigned height
= ctx
->pipe_framebuffer
.height
;
141 struct bifrost_framebuffer framebuffer
= {
142 .width1
= MALI_POSITIVE(width
),
143 .height1
= MALI_POSITIVE(height
),
144 .width2
= MALI_POSITIVE(width
),
145 .height2
= MALI_POSITIVE(height
),
150 .rt_count_1
= MALI_POSITIVE(1),
155 .scratchpad
= ctx
->scratchpad
.gpu
,
158 framebuffer
.tiler_hierarchy_mask
=
159 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
161 /* Compute the polygon header size and use that to offset the body */
163 unsigned header_size
= panfrost_tiler_header_size(
164 width
, height
, framebuffer
.tiler_hierarchy_mask
);
166 unsigned body_size
= panfrost_tiler_body_size(
167 width
, height
, framebuffer
.tiler_hierarchy_mask
);
171 unsigned total_size
= header_size
+ body_size
;
173 if (framebuffer
.tiler_hierarchy_mask
) {
174 assert(ctx
->tiler_polygon_list
.size
>= total_size
);
176 /* Specify allocated tiler structures */
177 framebuffer
.tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
;
179 /* Allow the entire tiler heap */
180 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
181 framebuffer
.tiler_heap_end
=
182 ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
;
184 /* The tiler is disabled, so don't allow the tiler heap */
185 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
186 framebuffer
.tiler_heap_end
= framebuffer
.tiler_heap_start
;
188 /* Use a dummy polygon list */
189 framebuffer
.tiler_polygon_list
= ctx
->tiler_dummy
.gpu
;
191 /* Also, set a "tiler disabled?" flag? */
192 framebuffer
.tiler_hierarchy_mask
|= 0x1000;
195 framebuffer
.tiler_polygon_list_body
=
196 framebuffer
.tiler_polygon_list
+ header_size
;
198 framebuffer
.tiler_polygon_list_size
=
199 header_size
+ body_size
;
206 /* Are we currently rendering to the screen (rather than an FBO)? */
209 panfrost_is_scanout(struct panfrost_context
*ctx
)
211 /* If there is no color buffer, it's an FBO */
212 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
215 /* If we're too early that no framebuffer was sent, it's scanout */
216 if (!ctx
->pipe_framebuffer
.cbufs
[0])
219 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
220 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
221 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
225 pan_pack_color(const union pipe_color_union
*color
, enum pipe_format format
)
227 /* Alpha magicked to 1.0 if there is no alpha */
229 bool has_alpha
= util_format_has_alpha(format
);
230 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
232 /* Packed color depends on the framebuffer format */
234 const struct util_format_description
*desc
=
235 util_format_description(format
);
237 if (util_format_is_rgba8_variant(desc
)) {
238 return (float_to_ubyte(clear_alpha
) << 24) |
239 (float_to_ubyte(color
->f
[2]) << 16) |
240 (float_to_ubyte(color
->f
[1]) << 8) |
241 (float_to_ubyte(color
->f
[0]) << 0);
242 } else if (format
== PIPE_FORMAT_B5G6R5_UNORM
) {
243 /* First, we convert the components to R5, G6, B5 separately */
244 unsigned r5
= CLAMP(color
->f
[0], 0.0, 1.0) * 31.0;
245 unsigned g6
= CLAMP(color
->f
[1], 0.0, 1.0) * 63.0;
246 unsigned b5
= CLAMP(color
->f
[2], 0.0, 1.0) * 31.0;
248 /* Then we pack into a sparse u32. TODO: Why these shifts? */
249 return (b5
<< 25) | (g6
<< 14) | (r5
<< 5);
260 struct pipe_context
*pipe
,
262 const union pipe_color_union
*color
,
263 double depth
, unsigned stencil
)
265 struct panfrost_context
*ctx
= pan_context(pipe
);
266 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
268 if (buffers
& PIPE_CLEAR_COLOR
) {
269 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[0]->format
;
270 job
->clear_color
= pan_pack_color(color
, format
);
273 if (buffers
& PIPE_CLEAR_DEPTH
) {
274 job
->clear_depth
= depth
;
277 if (buffers
& PIPE_CLEAR_STENCIL
) {
278 job
->clear_stencil
= stencil
;
281 job
->clear
|= buffers
;
285 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
287 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
291 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
293 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
297 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
299 mali_ptr framebuffer
= ctx
->require_sfbd
?
300 panfrost_attach_vt_sfbd(ctx
) :
301 panfrost_attach_vt_mfbd(ctx
);
303 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
304 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
307 /* Reset per-frame context, called on context initialisation as well as after
308 * flushing a frame */
311 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
313 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
314 DBG("Uploaded transient %d bytes\n", transient_count
);
316 /* Rotate cmdstream */
317 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
318 ctx
->cmdstream_i
= 0;
320 if (ctx
->require_sfbd
)
321 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
323 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
325 /* Reset varyings allocated */
326 ctx
->varying_height
= 0;
328 /* The transient cmdstream is dirty every frame; the only bits worth preserving
329 * (textures, shaders, etc) are in other buffers anyways */
331 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
332 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
334 /* Regenerate payloads */
335 panfrost_attach_vt_framebuffer(ctx
);
338 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
341 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
344 /* In practice, every field of these payloads should be configurable
345 * arbitrarily, which means these functions are basically catch-all's for
346 * as-of-yet unwavering unknowns */
349 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
351 struct midgard_payload_vertex_tiler payload
= {
353 .workgroups_z_shift
= 32,
354 .workgroups_x_shift_2
= 0x2,
355 .workgroups_x_shift_3
= 0x5,
357 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
360 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
364 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
366 struct midgard_payload_vertex_tiler payload
= {
368 .workgroups_z_shift
= 32,
369 .workgroups_x_shift_2
= 0x2,
370 .workgroups_x_shift_3
= 0x6,
372 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
376 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
380 translate_tex_wrap(enum pipe_tex_wrap w
)
383 case PIPE_TEX_WRAP_REPEAT
:
384 return MALI_WRAP_REPEAT
;
386 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
387 return MALI_WRAP_CLAMP_TO_EDGE
;
389 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
390 return MALI_WRAP_CLAMP_TO_BORDER
;
392 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
393 return MALI_WRAP_MIRRORED_REPEAT
;
396 unreachable("Invalid wrap");
401 translate_tex_filter(enum pipe_tex_filter f
)
404 case PIPE_TEX_FILTER_NEAREST
:
407 case PIPE_TEX_FILTER_LINEAR
:
411 unreachable("Invalid filter");
416 translate_mip_filter(enum pipe_tex_mipfilter f
)
418 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
422 panfrost_translate_compare_func(enum pipe_compare_func in
)
425 case PIPE_FUNC_NEVER
:
426 return MALI_FUNC_NEVER
;
429 return MALI_FUNC_LESS
;
431 case PIPE_FUNC_EQUAL
:
432 return MALI_FUNC_EQUAL
;
434 case PIPE_FUNC_LEQUAL
:
435 return MALI_FUNC_LEQUAL
;
437 case PIPE_FUNC_GREATER
:
438 return MALI_FUNC_GREATER
;
440 case PIPE_FUNC_NOTEQUAL
:
441 return MALI_FUNC_NOTEQUAL
;
443 case PIPE_FUNC_GEQUAL
:
444 return MALI_FUNC_GEQUAL
;
446 case PIPE_FUNC_ALWAYS
:
447 return MALI_FUNC_ALWAYS
;
450 unreachable("Invalid func");
455 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
458 case PIPE_FUNC_NEVER
:
459 return MALI_ALT_FUNC_NEVER
;
462 return MALI_ALT_FUNC_LESS
;
464 case PIPE_FUNC_EQUAL
:
465 return MALI_ALT_FUNC_EQUAL
;
467 case PIPE_FUNC_LEQUAL
:
468 return MALI_ALT_FUNC_LEQUAL
;
470 case PIPE_FUNC_GREATER
:
471 return MALI_ALT_FUNC_GREATER
;
473 case PIPE_FUNC_NOTEQUAL
:
474 return MALI_ALT_FUNC_NOTEQUAL
;
476 case PIPE_FUNC_GEQUAL
:
477 return MALI_ALT_FUNC_GEQUAL
;
479 case PIPE_FUNC_ALWAYS
:
480 return MALI_ALT_FUNC_ALWAYS
;
483 unreachable("Invalid alt func");
488 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
491 case PIPE_STENCIL_OP_KEEP
:
492 return MALI_STENCIL_KEEP
;
494 case PIPE_STENCIL_OP_ZERO
:
495 return MALI_STENCIL_ZERO
;
497 case PIPE_STENCIL_OP_REPLACE
:
498 return MALI_STENCIL_REPLACE
;
500 case PIPE_STENCIL_OP_INCR
:
501 return MALI_STENCIL_INCR
;
503 case PIPE_STENCIL_OP_DECR
:
504 return MALI_STENCIL_DECR
;
506 case PIPE_STENCIL_OP_INCR_WRAP
:
507 return MALI_STENCIL_INCR_WRAP
;
509 case PIPE_STENCIL_OP_DECR_WRAP
:
510 return MALI_STENCIL_DECR_WRAP
;
512 case PIPE_STENCIL_OP_INVERT
:
513 return MALI_STENCIL_INVERT
;
516 unreachable("Invalid stencil op");
521 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
523 out
->ref
= 0; /* Gallium gets it from elsewhere */
525 out
->mask
= in
->valuemask
;
526 out
->func
= panfrost_translate_compare_func(in
->func
);
527 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
528 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
529 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
533 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
535 struct mali_shader_meta shader
= {
536 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
538 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
539 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
543 shader
.unknown2_4
|= 0x10;
546 struct pipe_stencil_state default_stencil
= {
548 .func
= PIPE_FUNC_ALWAYS
,
549 .fail_op
= MALI_STENCIL_KEEP
,
550 .zfail_op
= MALI_STENCIL_KEEP
,
551 .zpass_op
= MALI_STENCIL_KEEP
,
556 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
557 shader
.stencil_mask_front
= default_stencil
.writemask
;
559 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
560 shader
.stencil_mask_back
= default_stencil
.writemask
;
562 if (default_stencil
.enabled
)
563 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
565 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
569 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
571 if (first
->job_descriptor_size
)
572 first
->next_job_64
= (u64
) (uintptr_t) next
;
574 first
->next_job_32
= (u32
) (uintptr_t) next
;
577 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
578 * graphics command stream. It should be called once per draw, accordding to
579 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
580 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
583 struct panfrost_transfer
584 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
586 /* Each draw call corresponds to two jobs, and the set-value job is first */
587 int draw_job_index
= 1 + (2 * ctx
->draw_count
) + 1;
589 struct mali_job_descriptor_header job
= {
590 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
591 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
593 .job_descriptor_size
= 1,
597 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
599 /* There's some padding hacks on 32-bit */
606 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
609 /* Tiler jobs depend on vertex jobs */
611 job
.job_dependency_index_1
= draw_job_index
;
613 /* Tiler jobs also depend on the previous tiler job */
615 if (ctx
->draw_count
) {
616 job
.job_dependency_index_2
= draw_job_index
- 1;
617 /* Previous tiler job points to this tiler job */
618 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
620 /* The only vertex job so far points to first tiler job */
621 panfrost_link_job_pair(ctx
->u_vertex_jobs
[0], transfer
.gpu
);
624 if (ctx
->draw_count
) {
625 /* Previous vertex job points to this vertex job */
626 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
628 /* Last vertex job points to first tiler job */
629 panfrost_link_job_pair(&job
, ctx
->tiler_jobs
[0]);
631 /* Have the first vertex job depend on the set value job */
632 job
.job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
633 panfrost_link_job_pair(ctx
->u_set_value_job
, transfer
.gpu
);
637 memcpy(transfer
.cpu
, &job
, sizeof(job
));
638 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
642 /* Generates a set value job. It's unclear what exactly this does, why it's
643 * necessary, and when to call it. */
646 panfrost_set_value_job(struct panfrost_context
*ctx
)
648 struct mali_job_descriptor_header job
= {
649 .job_type
= JOB_TYPE_SET_VALUE
,
650 .job_descriptor_size
= 1,
654 struct mali_payload_set_value payload
= {
655 .out
= ctx
->tiler_polygon_list
.gpu
,
659 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
660 memcpy(transfer
.cpu
, &job
, sizeof(job
));
661 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
663 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
664 ctx
->set_value_job
= transfer
.gpu
;
668 panfrost_emit_varyings(
669 struct panfrost_context
*ctx
,
670 union mali_attr
*slot
,
674 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
676 /* Fill out the descriptor */
677 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
678 slot
->stride
= stride
;
679 slot
->size
= stride
* count
;
681 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
682 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
684 return varying_address
;
688 panfrost_emit_point_coord(union mali_attr
*slot
)
690 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
691 slot
->stride
= slot
->size
= 0;
695 panfrost_emit_varying_descriptor(
696 struct panfrost_context
*ctx
,
697 unsigned invocation_count
)
699 /* Load the shaders */
701 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
702 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
703 unsigned int num_gen_varyings
= 0;
705 /* Allocate the varying descriptor */
707 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
708 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
710 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
714 * Assign ->src_offset now that we know about all the general purpose
715 * varyings that will be used by the fragment and vertex shaders.
717 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
719 * General purpose varyings have ->index set to 0, skip other
722 if (vs
->varyings
[i
].index
)
725 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
728 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
731 if (fs
->varyings
[i
].index
)
735 * Re-use the VS general purpose varying pos if it exists,
736 * create a new one otherwise.
738 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
739 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
743 if (j
< vs
->tripipe
->varying_count
)
744 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
746 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
749 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
750 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
752 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
753 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
755 /* Buffer indices must be in this order per our convention */
756 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
759 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
762 /* fp32 vec4 gl_Position */
763 ctx
->payload_tiler
.postfix
.position_varying
=
764 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
765 sizeof(float) * 4, invocation_count
);
768 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
769 /* fp16 vec1 gl_PointSize */
770 ctx
->payload_tiler
.primitive_size
.pointer
=
771 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
772 2, invocation_count
);
775 if (fs
->reads_point_coord
) {
776 /* Special descriptor */
777 panfrost_emit_point_coord(&varyings
[idx
++]);
780 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
781 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
782 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
786 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
788 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
789 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
791 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
794 /* Emits attributes and varying descriptors, which should be called every draw,
795 * excepting some obscure circumstances */
798 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
800 /* Staged mali_attr, and index into them. i =/= k, depending on the
801 * vertex buffer mask */
802 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
805 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
807 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
808 if (!(ctx
->vb_mask
& (1 << i
))) continue;
810 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
811 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
815 /* Align to 64 bytes by masking off the lower bits. This
816 * will be adjusted back when we fixup the src_offset in
819 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
821 /* Offset vertex count by draw_start to make sure we upload enough */
822 attrs
[k
].stride
= buf
->stride
;
823 attrs
[k
].size
= rsrc
->base
.width0
;
825 panfrost_job_add_bo(job
, rsrc
->bo
);
826 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
831 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
833 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
837 panfrost_writes_point_size(struct panfrost_context
*ctx
)
840 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
842 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
845 /* Stage the attribute descriptors so we can adjust src_offset
846 * to let BOs align nicely */
849 panfrost_stage_attributes(struct panfrost_context
*ctx
)
851 struct panfrost_vertex_state
*so
= ctx
->vertex
;
853 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
854 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
855 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
857 /* Copy as-is for the first pass */
858 memcpy(target
, so
->hw
, sz
);
860 /* Fixup offsets for the second pass. Recall that the hardware
861 * calculates attribute addresses as:
863 * addr = base + (stride * vtx) + src_offset;
865 * However, on Mali, base must be aligned to 64-bytes, so we
868 * base' = base & ~63 = base - (base & 63)
870 * To compensate when using base' (see emit_vertex_data), we have
871 * to adjust src_offset by the masked off piece:
873 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
874 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
875 * = base + (stride * vtx) + src_offset
881 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
882 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
883 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
885 /* Adjust by the masked off bits of the offset */
886 target
[i
].src_offset
+= (addr
& 63);
889 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
893 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
895 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
897 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
900 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
901 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
903 struct panfrost_transfer transfer
=
904 panfrost_allocate_transient(ctx
, transfer_size
);
906 struct mali_sampler_descriptor
*desc
=
907 (struct mali_sampler_descriptor
*) transfer
.cpu
;
909 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
910 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
912 upload
= transfer
.gpu
;
915 if (t
== PIPE_SHADER_FRAGMENT
)
916 ctx
->payload_tiler
.postfix
.sampler_descriptor
= upload
;
917 else if (t
== PIPE_SHADER_VERTEX
)
918 ctx
->payload_vertex
.postfix
.sampler_descriptor
= upload
;
924 /* Computes the address to a texture at a particular slice */
927 panfrost_get_texture_address(
928 struct panfrost_resource
*rsrc
,
929 unsigned level
, unsigned face
)
931 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
932 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
934 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
940 struct panfrost_context
*ctx
,
941 struct panfrost_sampler_view
*view
)
944 return (mali_ptr
) NULL
;
946 struct pipe_sampler_view
*pview
= &view
->base
;
947 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
949 /* Do we interleave an explicit stride with every element? */
951 bool has_manual_stride
=
952 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
954 /* For easy access */
956 assert(pview
->target
!= PIPE_BUFFER
);
957 unsigned first_level
= pview
->u
.tex
.first_level
;
958 unsigned last_level
= pview
->u
.tex
.last_level
;
960 /* Inject the addresses in, interleaving mip levels, cube faces, and
961 * strides in that order */
965 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
966 for (unsigned f
= 0; f
< pview
->texture
->array_size
; ++f
) {
967 view
->hw
.payload
[idx
++] =
968 panfrost_get_texture_address(rsrc
, l
, f
);
970 if (has_manual_stride
) {
971 view
->hw
.payload
[idx
++] =
972 rsrc
->bo
->slices
[l
].stride
;
977 return panfrost_upload_transient(ctx
, &view
->hw
,
978 sizeof(struct mali_texture_descriptor
));
982 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
984 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
985 mali_ptr trampoline
= 0;
987 if (ctx
->sampler_view_count
[t
]) {
988 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
990 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
992 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
994 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
997 if (t
== PIPE_SHADER_FRAGMENT
)
998 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
999 else if (t
== PIPE_SHADER_VERTEX
)
1000 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1006 struct sysval_uniform
{
1014 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
1015 struct sysval_uniform
*uniform
)
1017 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1019 uniform
->f
[0] = vp
->scale
[0];
1020 uniform
->f
[1] = vp
->scale
[1];
1021 uniform
->f
[2] = vp
->scale
[2];
1024 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
1025 struct sysval_uniform
*uniform
)
1027 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1029 uniform
->f
[0] = vp
->translate
[0];
1030 uniform
->f
[1] = vp
->translate
[1];
1031 uniform
->f
[2] = vp
->translate
[2];
1034 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
1035 enum pipe_shader_type st
,
1036 unsigned int sysvalid
,
1037 struct sysval_uniform
*uniform
)
1039 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
1040 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
1041 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
1042 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
1045 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
1048 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
1049 tex
->u
.tex
.first_level
);
1052 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
1053 tex
->u
.tex
.first_level
);
1056 uniform
->i
[dim
] = tex
->texture
->array_size
;
1059 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
1060 struct panfrost_shader_state
*ss
,
1061 enum pipe_shader_type st
)
1063 struct sysval_uniform
*uniforms
= (void *)buf
;
1065 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1066 int sysval
= ss
->sysval
[i
];
1068 switch (PAN_SYSVAL_TYPE(sysval
)) {
1069 case PAN_SYSVAL_VIEWPORT_SCALE
:
1070 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
1072 case PAN_SYSVAL_VIEWPORT_OFFSET
:
1073 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
1075 case PAN_SYSVAL_TEXTURE_SIZE
:
1076 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
1085 /* Go through dirty flags and actualise them in the cmdstream. */
1088 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1090 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1092 if (with_vertex_data
) {
1093 panfrost_emit_vertex_data(ctx
, job
);
1096 bool msaa
= ctx
->rasterizer
->base
.multisample
;
1098 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1099 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1101 /* TODO: Sample size */
1102 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1103 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1106 if (ctx
->occlusion_query
) {
1107 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1108 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1111 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1114 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1116 /* Late shader descriptor assignments */
1118 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1119 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1122 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1124 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1127 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1128 /* Check if we need to link the gl_PointSize varying */
1129 if (!panfrost_writes_point_size(ctx
)) {
1130 /* If the size is constant, write it out. Otherwise,
1131 * don't touch primitive_size (since we would clobber
1132 * the pointer there) */
1134 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1138 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1140 ctx
->dirty
|= PAN_DIRTY_FS
;
1142 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1144 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1146 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1149 COPY(attribute_count
);
1150 COPY(varying_count
);
1151 COPY(midgard1
.uniform_count
);
1152 COPY(midgard1
.work_count
);
1153 COPY(midgard1
.unknown2
);
1156 /* If there is a blend shader, work registers are shared */
1158 if (ctx
->blend
->has_blend_shader
)
1159 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1161 /* Set late due to depending on render state */
1162 /* The one at the end seems to mean "1 UBO" */
1163 unsigned flags
= MALI_EARLY_Z
| 0x200 | 0x2000 | 0x1;
1165 /* Any time texturing is used, derivatives are implicitly
1166 * calculated, so we need to enable helper invocations */
1168 if (ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
])
1169 flags
|= MALI_HELPER_INVOCATIONS
;
1171 ctx
->fragment_shader_core
.midgard1
.unknown1
= flags
;
1173 /* Assign texture/sample count right before upload */
1174 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1175 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1177 /* Assign the stencil refs late */
1178 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1179 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1181 /* CAN_DISCARD should be set if the fragment shader possibly
1182 * contains a 'discard' instruction. It is likely this is
1183 * related to optimizations related to forward-pixel kill, as
1184 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1185 * thing?" by Peter Harris
1188 if (variant
->can_discard
) {
1189 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1190 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_EARLY_Z
;
1191 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1192 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1195 /* Check if we're using the default blend descriptor (fast path) */
1198 !ctx
->blend
->has_blend_shader
&&
1199 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1200 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1201 (ctx
->blend
->equation
.color_mask
== 0xf);
1203 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1204 * *also* copied to the blend_meta appended (by convention),
1205 * but this is the field actually read by the hardware. (Or
1206 * maybe both are read...?) */
1208 if (ctx
->blend
->has_blend_shader
) {
1209 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1211 ctx
->fragment_shader_core
.blend
.shader
= 0;
1214 if (ctx
->require_sfbd
) {
1215 /* When only a single render target platform is used, the blend
1216 * information is inside the shader meta itself. We
1217 * additionally need to signal CAN_DISCARD for nontrivial blend
1218 * modes (so we're able to read back the destination buffer) */
1220 if (!ctx
->blend
->has_blend_shader
) {
1221 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1222 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1226 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1230 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1231 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1232 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1234 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1236 if (!ctx
->require_sfbd
) {
1237 /* Additional blend descriptor tacked on for jobs using MFBD */
1239 unsigned blend_count
= 0x200;
1241 if (ctx
->blend
->has_blend_shader
) {
1242 /* For a blend shader, the bottom nibble corresponds to
1243 * the number of work registers used, which signals the
1244 * -existence- of a blend shader */
1246 assert(ctx
->blend
->blend_work_count
>= 2);
1247 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1249 /* Otherwise, the bottom bit simply specifies if
1250 * blending (anything other than REPLACE) is enabled */
1257 struct midgard_blend_rt rts
[4];
1261 for (unsigned i
= 0; i
< 1; ++i
) {
1262 rts
[i
].flags
= blend_count
;
1264 if (ctx
->blend
->has_blend_shader
) {
1265 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1267 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1268 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1272 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1276 /* We stage to transient, so always dirty.. */
1277 panfrost_stage_attributes(ctx
);
1279 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1280 panfrost_upload_sampler_descriptors(ctx
);
1282 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1283 panfrost_upload_texture_descriptors(ctx
);
1285 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1287 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1288 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1290 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1291 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1292 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1294 /* Allocate room for the sysval and the uniforms */
1295 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1296 size_t size
= sys_size
+ buf
->size
;
1297 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1299 /* Upload sysvals requested by the shader */
1300 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1302 /* Upload uniforms */
1303 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1305 int uniform_count
= 0;
1307 struct mali_vertex_tiler_postfix
*postfix
;
1310 case PIPE_SHADER_VERTEX
:
1311 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1312 postfix
= &ctx
->payload_vertex
.postfix
;
1315 case PIPE_SHADER_FRAGMENT
:
1316 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1317 postfix
= &ctx
->payload_tiler
.postfix
;
1321 unreachable("Invalid shader stage\n");
1324 /* Also attach the same buffer as a UBO for extended access */
1326 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1328 .size
= MALI_POSITIVE((2 + uniform_count
)),
1329 .ptr
= transfer
.gpu
>> 2,
1333 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1334 postfix
->uniforms
= transfer
.gpu
;
1335 postfix
->uniform_buffers
= ubufs
;
1340 /* TODO: Upload the viewport somewhere more appropriate */
1342 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1343 * (somewhat) asymmetric ints. */
1344 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1346 struct mali_viewport view
= {
1347 /* By default, do no viewport clipping, i.e. clip to (-inf,
1348 * inf) in each direction. Clipping to the viewport in theory
1349 * should work, but in practice causes issues when we're not
1350 * explicitly trying to scissor */
1361 /* Always scissor to the viewport by default. */
1362 int minx
= (int) (vp
->translate
[0] - vp
->scale
[0]);
1363 int maxx
= (int) (vp
->translate
[0] + vp
->scale
[0]);
1365 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1366 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1368 /* Apply the scissor test */
1370 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1377 /* Hardware needs the min/max to be strictly ordered, so flip if we
1378 * need to. The viewport transformation in the vertex shader will
1379 * handle the negatives if we don't */
1393 /* Clamp everything positive, just in case */
1395 maxx
= MAX2(0, maxx
);
1396 maxy
= MAX2(0, maxy
);
1397 minx
= MAX2(0, minx
);
1398 miny
= MAX2(0, miny
);
1400 /* Clamp to the framebuffer size as a last check */
1402 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1403 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1405 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1406 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1410 view
.viewport0
[0] = minx
;
1411 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1413 view
.viewport0
[1] = miny
;
1414 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1416 ctx
->payload_tiler
.postfix
.viewport
=
1417 panfrost_upload_transient(ctx
,
1419 sizeof(struct mali_viewport
));
1424 /* Corresponds to exactly one draw, but does not submit anything */
1427 panfrost_queue_draw(struct panfrost_context
*ctx
)
1429 /* TODO: Expand the array? */
1430 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1431 DBG("Job buffer overflow, ignoring draw\n");
1435 /* Handle dirty flags now */
1436 panfrost_emit_for_draw(ctx
, true);
1438 /* We need a set_value job before any other draw jobs */
1439 if (ctx
->draw_count
== 0)
1440 panfrost_set_value_job(ctx
);
1442 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1443 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1444 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1446 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true);
1447 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1448 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1453 /* The entire frame is in memory -- send it off to the kernel! */
1456 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1457 struct pipe_fence_handle
**fence
,
1458 struct panfrost_job
*job
)
1460 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1461 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1465 panfrost_job_submit(ctx
, job
);
1467 /* If visual, we can stall a frame */
1469 if (!flush_immediate
)
1470 screen
->driver
->force_flush_fragment(ctx
, fence
);
1472 screen
->last_fragment_flushed
= false;
1473 screen
->last_job
= job
;
1475 /* If readback, flush now (hurts the pipelined performance) */
1476 if (flush_immediate
)
1477 screen
->driver
->force_flush_fragment(ctx
, fence
);
1479 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1480 screen
->driver
->dump_counters(screen
);
1483 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1484 FILE *fp
= fopen(filename
, "wb");
1485 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1493 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1495 struct panfrost_context
*ctx
= pan_context(pipe
);
1497 /* Nothing to reload? */
1498 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1501 /* Blit the wallpaper in */
1502 panfrost_blit_wallpaper(ctx
);
1504 /* We are flushing all queued draws and we know that no more jobs will
1505 * be added until the next frame.
1506 * We also know that the last jobs are the wallpaper jobs, and they
1507 * need to be linked so they execute right after the set_value job.
1510 /* set_value job to wallpaper vertex job */
1511 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[ctx
->vertex_job_count
- 1]);
1512 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1514 /* wallpaper vertex job to first vertex job */
1515 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1], ctx
->vertex_jobs
[0]);
1516 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1518 /* last vertex job to wallpaper tiler job */
1519 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 2], ctx
->tiler_jobs
[ctx
->tiler_job_count
- 1]);
1520 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_1
= ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_index
;
1521 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_2
= 0;
1523 /* wallpaper tiler job to first tiler job */
1524 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1], ctx
->tiler_jobs
[0]);
1525 ctx
->u_tiler_jobs
[0]->job_dependency_index_1
= ctx
->u_vertex_jobs
[0]->job_index
;
1526 ctx
->u_tiler_jobs
[0]->job_dependency_index_2
= ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_index
;
1528 /* last tiler job to NULL */
1529 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 2], 0);
1534 struct pipe_context
*pipe
,
1535 struct pipe_fence_handle
**fence
,
1538 struct panfrost_context
*ctx
= pan_context(pipe
);
1539 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1541 /* Nothing to do! */
1542 if (!ctx
->draw_count
&& !job
->clear
) return;
1545 panfrost_draw_wallpaper(&ctx
->base
);
1547 /* Whether to stall the pipeline for immediately correct results. Since
1548 * pipelined rendering is quite broken right now (to be fixed by the
1549 * panfrost_job refactor, just take the perf hit for correctness) */
1550 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1552 /* Submit the frame itself */
1553 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1555 /* Prepare for the next frame */
1556 panfrost_invalidate_frame(ctx
);
1559 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1562 g2m_draw_mode(enum pipe_prim_type mode
)
1565 DEFINE_CASE(POINTS
);
1567 DEFINE_CASE(LINE_LOOP
);
1568 DEFINE_CASE(LINE_STRIP
);
1569 DEFINE_CASE(TRIANGLES
);
1570 DEFINE_CASE(TRIANGLE_STRIP
);
1571 DEFINE_CASE(TRIANGLE_FAN
);
1573 DEFINE_CASE(QUAD_STRIP
);
1574 DEFINE_CASE(POLYGON
);
1577 unreachable("Invalid draw mode");
1584 panfrost_translate_index_size(unsigned size
)
1588 return MALI_DRAW_INDEXED_UINT8
;
1591 return MALI_DRAW_INDEXED_UINT16
;
1594 return MALI_DRAW_INDEXED_UINT32
;
1597 unreachable("Invalid index size");
1601 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1602 * good for the duration of the draw (transient), could last longer */
1605 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1607 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1609 off_t offset
= info
->start
* info
->index_size
;
1611 if (!info
->has_user_indices
) {
1612 /* Only resources can be directly mapped */
1613 return rsrc
->bo
->gpu
+ offset
;
1615 /* Otherwise, we need to upload to transient memory */
1616 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1617 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1622 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1624 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1626 /* Check if we're scissoring at all */
1628 if (!(ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1631 return (ss
->minx
== ss
->maxx
) && (ss
->miny
== ss
->maxy
);
1636 struct pipe_context
*pipe
,
1637 const struct pipe_draw_info
*info
)
1639 struct panfrost_context
*ctx
= pan_context(pipe
);
1641 /* First of all, check the scissor to see if anything is drawn at all.
1642 * If it's not, we drop the draw (mostly a conformance issue;
1643 * well-behaved apps shouldn't hit this) */
1645 if (panfrost_scissor_culls_everything(ctx
))
1648 ctx
->payload_vertex
.draw_start
= info
->start
;
1649 ctx
->payload_tiler
.draw_start
= info
->start
;
1651 int mode
= info
->mode
;
1653 /* Fallback for unsupported modes */
1655 if (!(ctx
->draw_modes
& (1 << mode
))) {
1656 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1657 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1659 if (info
->count
< 4) {
1660 /* Degenerate case? */
1664 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1665 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1670 /* Now that we have a guaranteed terminating path, find the job.
1671 * Assignment commented out to prevent unused warning */
1673 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1675 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1677 ctx
->vertex_count
= info
->count
;
1679 /* For non-indexed draws, they're the same */
1680 unsigned invocation_count
= ctx
->vertex_count
;
1682 unsigned draw_flags
= 0;
1684 /* The draw flags interpret how primitive size is interpreted */
1686 if (panfrost_writes_point_size(ctx
))
1687 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1689 /* For higher amounts of vertices (greater than what fits in a 16-bit
1690 * short), the other value is needed, otherwise there will be bizarre
1691 * rendering artefacts. It's not clear what these values mean yet. */
1693 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1695 if (info
->index_size
) {
1696 /* Calculate the min/max index used so we can figure out how
1697 * many times to invoke the vertex shader */
1699 /* Fetch / calculate index bounds */
1700 unsigned min_index
= 0, max_index
= 0;
1702 if (info
->max_index
== ~0u) {
1703 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1705 min_index
= info
->min_index
;
1706 max_index
= info
->max_index
;
1709 /* Use the corresponding values */
1710 invocation_count
= max_index
- min_index
+ 1;
1711 ctx
->payload_vertex
.draw_start
= min_index
;
1712 ctx
->payload_tiler
.draw_start
= min_index
;
1714 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1715 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1717 //assert(!info->restart_index); /* TODO: Research */
1718 assert(!info
->index_bias
);
1720 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1721 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1723 /* Index count == vertex count, if no indexing is applied, as
1724 * if it is internally indexed in the expected order */
1726 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1727 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1729 /* Reverse index state */
1730 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1733 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1734 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1735 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1737 /* Fire off the draw itself */
1738 panfrost_queue_draw(ctx
);
1744 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1750 panfrost_create_rasterizer_state(
1751 struct pipe_context
*pctx
,
1752 const struct pipe_rasterizer_state
*cso
)
1754 struct panfrost_context
*ctx
= pan_context(pctx
);
1755 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1759 /* Bitmask, unknown meaning of the start value */
1760 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1763 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1765 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1766 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1768 if (cso
->cull_face
& PIPE_FACE_BACK
)
1769 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1775 panfrost_bind_rasterizer_state(
1776 struct pipe_context
*pctx
,
1779 struct panfrost_context
*ctx
= pan_context(pctx
);
1781 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1785 ctx
->rasterizer
= hwcso
;
1786 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1790 panfrost_create_vertex_elements_state(
1791 struct pipe_context
*pctx
,
1792 unsigned num_elements
,
1793 const struct pipe_vertex_element
*elements
)
1795 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1797 so
->num_elements
= num_elements
;
1798 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1800 /* XXX: What the cornball? This is totally, 100%, unapologetically
1801 * nonsense. And yet it somehow fixes a regression in -bshadow
1802 * (previously, we allocated the descriptor here... a newer commit
1803 * removed that allocation, and then memory corruption led to
1804 * shader_meta getting overwritten in bad ways and then the whole test
1805 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1807 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1809 for (int i
= 0; i
< num_elements
; ++i
) {
1810 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1812 enum pipe_format fmt
= elements
[i
].src_format
;
1813 const struct util_format_description
*desc
= util_format_description(fmt
);
1814 so
->hw
[i
].unknown1
= 0x2;
1815 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1817 so
->hw
[i
].format
= panfrost_find_format(desc
);
1819 /* The field itself should probably be shifted over */
1820 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1827 panfrost_bind_vertex_elements_state(
1828 struct pipe_context
*pctx
,
1831 struct panfrost_context
*ctx
= pan_context(pctx
);
1833 ctx
->vertex
= hwcso
;
1834 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1838 panfrost_create_shader_state(
1839 struct pipe_context
*pctx
,
1840 const struct pipe_shader_state
*cso
)
1842 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1845 /* Token deep copy to prevent memory corruption */
1847 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1848 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1854 panfrost_delete_shader_state(
1855 struct pipe_context
*pctx
,
1858 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1860 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1861 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1868 panfrost_create_sampler_state(
1869 struct pipe_context
*pctx
,
1870 const struct pipe_sampler_state
*cso
)
1872 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1875 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1877 struct mali_sampler_descriptor sampler_descriptor
= {
1878 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1879 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1880 | translate_mip_filter(cso
->min_mip_filter
)
1883 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1884 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1885 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1886 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1888 cso
->border_color
.f
[0],
1889 cso
->border_color
.f
[1],
1890 cso
->border_color
.f
[2],
1891 cso
->border_color
.f
[3]
1893 .min_lod
= FIXED_16(cso
->min_lod
),
1894 .max_lod
= FIXED_16(cso
->max_lod
),
1898 so
->hw
= sampler_descriptor
;
1904 panfrost_bind_sampler_states(
1905 struct pipe_context
*pctx
,
1906 enum pipe_shader_type shader
,
1907 unsigned start_slot
, unsigned num_sampler
,
1910 assert(start_slot
== 0);
1912 struct panfrost_context
*ctx
= pan_context(pctx
);
1914 /* XXX: Should upload, not just copy? */
1915 ctx
->sampler_count
[shader
] = num_sampler
;
1916 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1918 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1922 panfrost_variant_matches(
1923 struct panfrost_context
*ctx
,
1924 struct panfrost_shader_state
*variant
,
1925 enum pipe_shader_type type
)
1927 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1929 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1931 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1932 /* Make sure enable state is at least the same */
1933 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1937 /* Check that the contents of the test are the same */
1938 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1939 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1941 if (!(same_func
&& same_ref
)) {
1945 /* Otherwise, we're good to go */
1950 panfrost_bind_shader_state(
1951 struct pipe_context
*pctx
,
1953 enum pipe_shader_type type
)
1955 struct panfrost_context
*ctx
= pan_context(pctx
);
1957 if (type
== PIPE_SHADER_FRAGMENT
) {
1959 ctx
->dirty
|= PAN_DIRTY_FS
;
1961 assert(type
== PIPE_SHADER_VERTEX
);
1963 ctx
->dirty
|= PAN_DIRTY_VS
;
1968 /* Match the appropriate variant */
1970 signed variant
= -1;
1971 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1973 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1974 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1980 if (variant
== -1) {
1981 /* No variant matched, so create a new one */
1982 variant
= variants
->variant_count
++;
1983 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1985 variants
->variants
[variant
].base
= hwcso
;
1987 if (type
== PIPE_SHADER_FRAGMENT
)
1988 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1990 /* Allocate the mapped descriptor ahead-of-time. */
1991 struct panfrost_context
*ctx
= pan_context(pctx
);
1992 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1994 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1995 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1999 /* Select this variant */
2000 variants
->active_variant
= variant
;
2002 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2003 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2005 /* We finally have a variant, so compile it */
2007 if (!shader_state
->compiled
) {
2008 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
2009 panfrost_job_type_for_pipe(type
), shader_state
);
2011 shader_state
->compiled
= true;
2016 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2018 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2022 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2024 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2028 panfrost_set_vertex_buffers(
2029 struct pipe_context
*pctx
,
2030 unsigned start_slot
,
2031 unsigned num_buffers
,
2032 const struct pipe_vertex_buffer
*buffers
)
2034 struct panfrost_context
*ctx
= pan_context(pctx
);
2036 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2040 panfrost_set_constant_buffer(
2041 struct pipe_context
*pctx
,
2042 enum pipe_shader_type shader
, uint index
,
2043 const struct pipe_constant_buffer
*buf
)
2045 struct panfrost_context
*ctx
= pan_context(pctx
);
2046 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2048 size_t sz
= buf
? buf
->buffer_size
: 0;
2050 /* Free previous buffer */
2057 pbuf
->buffer
= NULL
;
2060 /* If unbinding, we're done */
2065 /* Multiple constant buffers not yet supported */
2070 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
2073 cpu
= rsrc
->bo
->cpu
;
2074 } else if (buf
->user_buffer
) {
2075 cpu
= buf
->user_buffer
;
2077 DBG("No constant buffer?\n");
2081 /* Copy the constant buffer into the driver context for later upload */
2083 pbuf
->buffer
= malloc(sz
);
2084 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
2088 panfrost_set_stencil_ref(
2089 struct pipe_context
*pctx
,
2090 const struct pipe_stencil_ref
*ref
)
2092 struct panfrost_context
*ctx
= pan_context(pctx
);
2093 ctx
->stencil_ref
= *ref
;
2095 /* Shader core dirty */
2096 ctx
->dirty
|= PAN_DIRTY_FS
;
2099 static enum mali_texture_type
2100 panfrost_translate_texture_type(enum pipe_texture_target t
)
2104 case PIPE_TEXTURE_1D
:
2105 case PIPE_TEXTURE_1D_ARRAY
:
2108 case PIPE_TEXTURE_2D
:
2109 case PIPE_TEXTURE_2D_ARRAY
:
2110 case PIPE_TEXTURE_RECT
:
2113 case PIPE_TEXTURE_3D
:
2116 case PIPE_TEXTURE_CUBE
:
2117 case PIPE_TEXTURE_CUBE_ARRAY
:
2118 return MALI_TEX_CUBE
;
2121 unreachable("Unknown target");
2125 static struct pipe_sampler_view
*
2126 panfrost_create_sampler_view(
2127 struct pipe_context
*pctx
,
2128 struct pipe_resource
*texture
,
2129 const struct pipe_sampler_view
*template)
2131 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
2132 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2134 pipe_reference(NULL
, &texture
->reference
);
2136 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2139 so
->base
= *template;
2140 so
->base
.texture
= texture
;
2141 so
->base
.reference
.count
= 1;
2142 so
->base
.context
= pctx
;
2144 /* sampler_views correspond to texture descriptors, minus the texture
2145 * (data) itself. So, we serialise the descriptor here and cache it for
2148 /* Make sure it's something with which we're familiar */
2149 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2151 /* TODO: Detect from format better */
2152 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2154 unsigned char user_swizzle
[4] = {
2155 template->swizzle_r
,
2156 template->swizzle_g
,
2157 template->swizzle_b
,
2161 enum mali_format format
= panfrost_find_format(desc
);
2163 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2165 unsigned usage2_layout
= 0x10;
2167 switch (prsrc
->bo
->layout
) {
2169 usage2_layout
|= 0x8 | 0x4;
2172 usage2_layout
|= 0x1;
2175 usage2_layout
|= is_depth
? 0x1 : 0x2;
2182 /* Check if we need to set a custom stride by computing the "expected"
2183 * stride and comparing it to what the BO actually wants. Only applies
2184 * to linear textures, since tiled/compressed textures have strict
2185 * alignment requirements for their strides as it is */
2187 unsigned first_level
= template->u
.tex
.first_level
;
2188 unsigned last_level
= template->u
.tex
.last_level
;
2190 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
2191 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2192 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
2193 unsigned width
= u_minify(texture
->width0
, l
);
2194 unsigned comp_stride
= width
* bytes_per_pixel
;
2196 if (comp_stride
!= actual_stride
) {
2197 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2203 /* In the hardware, array_size refers specifically to array textures,
2204 * whereas in Gallium, it also covers cubemaps */
2206 unsigned array_size
= texture
->array_size
;
2208 if (texture
->target
== PIPE_TEXTURE_CUBE
) {
2209 /* TODO: Cubemap arrays */
2210 assert(array_size
== 6);
2213 struct mali_texture_descriptor texture_descriptor
= {
2214 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2215 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2216 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2217 .array_size
= MALI_POSITIVE(array_size
),
2221 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2224 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2225 .type
= panfrost_translate_texture_type(texture
->target
),
2227 .usage2
= usage2_layout
2230 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2233 //texture_descriptor.nr_mipmap_levels = last_level - first_level;
2235 so
->hw
= texture_descriptor
;
2237 return (struct pipe_sampler_view
*) so
;
2241 panfrost_set_sampler_views(
2242 struct pipe_context
*pctx
,
2243 enum pipe_shader_type shader
,
2244 unsigned start_slot
, unsigned num_views
,
2245 struct pipe_sampler_view
**views
)
2247 struct panfrost_context
*ctx
= pan_context(pctx
);
2249 assert(start_slot
== 0);
2251 unsigned new_nr
= 0;
2252 for (unsigned i
= 0; i
< num_views
; ++i
) {
2257 ctx
->sampler_view_count
[shader
] = new_nr
;
2258 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2260 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2264 panfrost_sampler_view_destroy(
2265 struct pipe_context
*pctx
,
2266 struct pipe_sampler_view
*view
)
2268 pipe_resource_reference(&view
->texture
, NULL
);
2273 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2274 const struct pipe_framebuffer_state
*fb
)
2276 struct panfrost_context
*ctx
= pan_context(pctx
);
2278 /* Flush when switching framebuffers, but not if the framebuffer
2279 * state is being restored by u_blitter
2282 bool is_scanout
= panfrost_is_scanout(ctx
);
2283 bool has_draws
= ctx
->draw_count
> 0;
2285 if (!ctx
->blitter
->running
&& (!is_scanout
|| has_draws
)) {
2286 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2289 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2290 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2291 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2292 ctx
->pipe_framebuffer
.width
= fb
->width
;
2293 ctx
->pipe_framebuffer
.height
= fb
->height
;
2295 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2296 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2298 /* check if changing cbuf */
2299 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2301 if (cb
&& (i
!= 0)) {
2302 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2307 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2312 if (ctx
->require_sfbd
)
2313 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2315 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2317 panfrost_attach_vt_framebuffer(ctx
);
2319 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2320 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2322 bool can_afbc
= panfrost_format_supports_afbc(format
);
2323 bool is_scanout
= panfrost_is_scanout(ctx
);
2325 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2326 panfrost_enable_afbc(ctx
, tex
, false);
2328 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2329 panfrost_enable_checksum(ctx
, tex
);
2333 struct pipe_surface
*zb
= fb
->zsbuf
;
2335 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2336 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2339 if (ctx
->require_sfbd
)
2340 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2342 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2344 panfrost_attach_vt_framebuffer(ctx
);
2346 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2347 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2348 bool is_scanout
= panfrost_is_scanout(ctx
);
2350 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2351 panfrost_enable_afbc(ctx
, tex
, true);
2358 panfrost_create_blend_state(struct pipe_context
*pipe
,
2359 const struct pipe_blend_state
*blend
)
2361 struct panfrost_context
*ctx
= pan_context(pipe
);
2362 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2365 /* TODO: The following features are not yet implemented */
2366 assert(!blend
->logicop_enable
);
2367 assert(!blend
->alpha_to_coverage
);
2368 assert(!blend
->alpha_to_one
);
2370 /* Compile the blend state, first as fixed-function if we can */
2372 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2375 /* If we can't, compile a blend shader instead */
2377 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2383 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2386 struct panfrost_context
*ctx
= pan_context(pipe
);
2387 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2388 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2389 ctx
->blend
= pblend
;
2394 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2396 /* TODO: Attach color */
2398 /* Shader itself is not dirty, but the shader core is */
2399 ctx
->dirty
|= PAN_DIRTY_FS
;
2403 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2406 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2408 if (so
->has_blend_shader
) {
2409 DBG("Deleting blend state leak blend shaders bytecode\n");
2416 panfrost_set_blend_color(struct pipe_context
*pipe
,
2417 const struct pipe_blend_color
*blend_color
)
2419 struct panfrost_context
*ctx
= pan_context(pipe
);
2421 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2424 ctx
->blend_color
= *blend_color
;
2426 /* The blend mode depends on the blend constant color, due to the
2427 * fixed/programmable split. So, we're forced to regenerate the blend
2430 /* TODO: Attach color */
2435 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2436 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2438 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2442 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2445 struct panfrost_context
*ctx
= pan_context(pipe
);
2446 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2447 ctx
->depth_stencil
= depth_stencil
;
2452 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2453 * emulated in the fragment shader */
2455 if (depth_stencil
->alpha
.enabled
) {
2456 /* We need to trigger a new shader (maybe) */
2457 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2461 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2463 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2464 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2466 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2467 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2469 /* Depth state (TODO: Refactor) */
2470 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2472 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2474 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2475 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2477 /* Bounds test not implemented */
2478 assert(!depth_stencil
->depth
.bounds_test
);
2480 ctx
->dirty
|= PAN_DIRTY_FS
;
2484 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2490 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2491 unsigned sample_mask
)
2496 panfrost_set_clip_state(struct pipe_context
*pipe
,
2497 const struct pipe_clip_state
*clip
)
2499 //struct panfrost_context *panfrost = pan_context(pipe);
2503 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2504 unsigned start_slot
,
2505 unsigned num_viewports
,
2506 const struct pipe_viewport_state
*viewports
)
2508 struct panfrost_context
*ctx
= pan_context(pipe
);
2510 assert(start_slot
== 0);
2511 assert(num_viewports
== 1);
2513 ctx
->pipe_viewport
= *viewports
;
2517 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2518 unsigned start_slot
,
2519 unsigned num_scissors
,
2520 const struct pipe_scissor_state
*scissors
)
2522 struct panfrost_context
*ctx
= pan_context(pipe
);
2524 assert(start_slot
== 0);
2525 assert(num_scissors
== 1);
2527 ctx
->scissor
= *scissors
;
2531 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2532 const struct pipe_poly_stipple
*stipple
)
2534 //struct panfrost_context *panfrost = pan_context(pipe);
2538 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2541 //struct panfrost_context *panfrost = pan_context(pipe);
2545 panfrost_destroy(struct pipe_context
*pipe
)
2547 struct panfrost_context
*panfrost
= pan_context(pipe
);
2548 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2550 if (panfrost
->blitter
)
2551 util_blitter_destroy(panfrost
->blitter
);
2553 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2554 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2555 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2556 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2557 screen
->driver
->free_slab(screen
, &panfrost
->tiler_polygon_list
);
2560 static struct pipe_query
*
2561 panfrost_create_query(struct pipe_context
*pipe
,
2565 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2570 return (struct pipe_query
*) q
;
2574 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2580 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2582 struct panfrost_context
*ctx
= pan_context(pipe
);
2583 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2585 switch (query
->type
) {
2586 case PIPE_QUERY_OCCLUSION_COUNTER
:
2587 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2588 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2590 /* Allocate a word for the query results to be stored */
2591 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2593 ctx
->occlusion_query
= query
;
2599 DBG("Skipping query %d\n", query
->type
);
2607 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2609 struct panfrost_context
*ctx
= pan_context(pipe
);
2610 ctx
->occlusion_query
= NULL
;
2615 panfrost_get_query_result(struct pipe_context
*pipe
,
2616 struct pipe_query
*q
,
2618 union pipe_query_result
*vresult
)
2621 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2623 /* We need to flush out the jobs to actually run the counter, TODO
2624 * check wait, TODO wallpaper after if needed */
2626 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2628 switch (query
->type
) {
2629 case PIPE_QUERY_OCCLUSION_COUNTER
:
2630 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2631 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2632 /* Read back the query results */
2633 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2634 unsigned passed
= *result
;
2636 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2637 vresult
->u64
= passed
;
2639 vresult
->b
= !!passed
;
2645 DBG("Skipped query get %d\n", query
->type
);
2652 static struct pipe_stream_output_target
*
2653 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2654 struct pipe_resource
*prsc
,
2655 unsigned buffer_offset
,
2656 unsigned buffer_size
)
2658 struct pipe_stream_output_target
*target
;
2660 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2665 pipe_reference_init(&target
->reference
, 1);
2666 pipe_resource_reference(&target
->buffer
, prsc
);
2668 target
->context
= pctx
;
2669 target
->buffer_offset
= buffer_offset
;
2670 target
->buffer_size
= buffer_size
;
2676 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2677 struct pipe_stream_output_target
*target
)
2679 pipe_resource_reference(&target
->buffer
, NULL
);
2684 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2685 unsigned num_targets
,
2686 struct pipe_stream_output_target
**targets
,
2687 const unsigned *offsets
)
2693 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2695 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2696 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2698 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2699 /* Allocate the beginning of the transient pool */
2700 int entry_size
= (1 << 22); /* 4MB */
2702 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2703 ctx
->transient_pools
[i
].entry_count
= 1;
2705 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2708 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2709 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2710 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2711 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2712 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_polygon_list
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2713 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2717 /* New context creation, which also does hardware initialisation since I don't
2718 * know the better way to structure this :smirk: */
2720 struct pipe_context
*
2721 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2723 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2724 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2725 memset(ctx
, 0, sizeof(*ctx
));
2726 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2729 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2731 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2732 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2734 gallium
->screen
= screen
;
2736 gallium
->destroy
= panfrost_destroy
;
2738 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2740 gallium
->flush
= panfrost_flush
;
2741 gallium
->clear
= panfrost_clear
;
2742 gallium
->draw_vbo
= panfrost_draw_vbo
;
2744 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2745 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2747 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2749 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2750 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2751 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2753 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2754 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2755 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2757 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2758 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2759 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2761 gallium
->create_fs_state
= panfrost_create_shader_state
;
2762 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2763 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2765 gallium
->create_vs_state
= panfrost_create_shader_state
;
2766 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2767 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2769 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2770 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2771 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2773 gallium
->create_blend_state
= panfrost_create_blend_state
;
2774 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2775 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2777 gallium
->set_blend_color
= panfrost_set_blend_color
;
2779 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2780 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2781 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2783 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2785 gallium
->set_clip_state
= panfrost_set_clip_state
;
2786 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2787 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2788 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2789 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2791 gallium
->create_query
= panfrost_create_query
;
2792 gallium
->destroy_query
= panfrost_destroy_query
;
2793 gallium
->begin_query
= panfrost_begin_query
;
2794 gallium
->end_query
= panfrost_end_query
;
2795 gallium
->get_query_result
= panfrost_get_query_result
;
2797 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2798 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2799 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2801 panfrost_resource_context_init(gallium
);
2803 pscreen
->driver
->init_context(ctx
);
2805 panfrost_setup_hardware(ctx
);
2808 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2809 gallium
->const_uploader
= gallium
->stream_uploader
;
2810 assert(gallium
->stream_uploader
);
2812 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2813 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2815 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2817 ctx
->blitter
= util_blitter_create(gallium
);
2818 assert(ctx
->blitter
);
2820 /* Prepare for render! */
2822 panfrost_job_init(ctx
);
2823 panfrost_emit_vertex_payload(ctx
);
2824 panfrost_emit_tiler_payload(ctx
);
2825 panfrost_invalidate_frame(ctx
);
2826 panfrost_default_shader_backend(ctx
);
2827 panfrost_generate_space_filler_indices();