2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_format.h"
31 #include "util/macros.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_memory.h"
36 #include "util/u_vbuf.h"
37 #include "util/half_float.h"
38 #include "util/u_helpers.h"
39 #include "util/u_format.h"
40 #include "indices/u_primconvert.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "util/u_math.h"
44 #include "pan_screen.h"
45 #include "pan_blending.h"
46 #include "pan_blend_shaders.h"
48 #include "pan_tiler.h"
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
53 static enum mali_job_type
54 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
57 case PIPE_SHADER_VERTEX
:
58 return JOB_TYPE_VERTEX
;
60 case PIPE_SHADER_FRAGMENT
:
61 /* Note: JOB_TYPE_FRAGMENT is different.
62 * JOB_TYPE_FRAGMENT actually executes the
63 * fragment shader, but JOB_TYPE_TILER is how you
65 return JOB_TYPE_TILER
;
67 case PIPE_SHADER_GEOMETRY
:
68 return JOB_TYPE_GEOMETRY
;
70 case PIPE_SHADER_COMPUTE
:
71 return JOB_TYPE_COMPUTE
;
74 unreachable("Unsupported shader stage");
79 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
81 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
82 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
83 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
84 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
86 /* 8 byte checksum per tile */
87 rsrc
->bo
->checksum_stride
= tile_w
* 8;
88 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
89 panfrost_drm_allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
91 rsrc
->bo
->has_checksum
= true;
94 /* Framebuffer descriptor */
97 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
99 fb
->width
= MALI_POSITIVE(w
);
100 fb
->height
= MALI_POSITIVE(h
);
102 /* No idea why this is needed, but it's how resolution_check is
103 * calculated. It's not clear to us yet why the hardware wants this.
104 * The formula itself was discovered mostly by manual bruteforce and
105 * aggressive algebraic simplification. */
107 fb
->tiler_resolution_check
= ((w
+ h
) / 3) << 4;
110 struct mali_single_framebuffer
111 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
113 struct mali_single_framebuffer framebuffer
= {
115 .format
= 0x30000000,
116 .clear_flags
= 0x1000,
117 .unknown_address_0
= ctx
->scratchpad
.gpu
,
118 .tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
,
119 .tiler_polygon_list_body
= ctx
->tiler_polygon_list
.gpu
+ 40960,
120 .tiler_hierarchy_mask
= 0xF0,
122 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
123 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
126 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
131 struct bifrost_framebuffer
132 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
134 unsigned width
= ctx
->pipe_framebuffer
.width
;
135 unsigned height
= ctx
->pipe_framebuffer
.height
;
137 struct bifrost_framebuffer framebuffer
= {
138 .width1
= MALI_POSITIVE(width
),
139 .height1
= MALI_POSITIVE(height
),
140 .width2
= MALI_POSITIVE(width
),
141 .height2
= MALI_POSITIVE(height
),
146 .rt_count_1
= MALI_POSITIVE(1),
151 .scratchpad
= ctx
->scratchpad
.gpu
,
154 framebuffer
.tiler_hierarchy_mask
=
155 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
157 /* Compute the polygon header size and use that to offset the body */
159 unsigned header_size
= panfrost_tiler_header_size(
160 width
, height
, framebuffer
.tiler_hierarchy_mask
);
162 unsigned body_size
= panfrost_tiler_body_size(
163 width
, height
, framebuffer
.tiler_hierarchy_mask
);
167 unsigned total_size
= header_size
+ body_size
;
169 if (framebuffer
.tiler_hierarchy_mask
) {
170 assert(ctx
->tiler_polygon_list
.size
>= total_size
);
172 /* Specify allocated tiler structures */
173 framebuffer
.tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
;
175 /* Allow the entire tiler heap */
176 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
177 framebuffer
.tiler_heap_end
=
178 ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
;
180 /* The tiler is disabled, so don't allow the tiler heap */
181 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
182 framebuffer
.tiler_heap_end
= framebuffer
.tiler_heap_start
;
184 /* Use a dummy polygon list */
185 framebuffer
.tiler_polygon_list
= ctx
->tiler_dummy
.gpu
;
187 /* Also, set a "tiler disabled?" flag? */
188 framebuffer
.tiler_hierarchy_mask
|= 0x1000;
191 framebuffer
.tiler_polygon_list_body
=
192 framebuffer
.tiler_polygon_list
+ header_size
;
194 framebuffer
.tiler_polygon_list_size
=
195 header_size
+ body_size
;
202 /* Are we currently rendering to the screen (rather than an FBO)? */
205 panfrost_is_scanout(struct panfrost_context
*ctx
)
207 /* If there is no color buffer, it's an FBO */
208 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
211 /* If we're too early that no framebuffer was sent, it's scanout */
212 if (!ctx
->pipe_framebuffer
.cbufs
[0])
215 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
216 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
217 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
222 struct pipe_context
*pipe
,
224 const union pipe_color_union
*color
,
225 double depth
, unsigned stencil
)
227 struct panfrost_context
*ctx
= pan_context(pipe
);
228 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
230 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
234 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
236 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
240 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
242 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
246 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
248 mali_ptr framebuffer
= ctx
->require_sfbd
?
249 panfrost_attach_vt_sfbd(ctx
) :
250 panfrost_attach_vt_mfbd(ctx
);
252 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
253 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
256 /* Reset per-frame context, called on context initialisation as well as after
257 * flushing a frame */
260 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
262 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
263 DBG("Uploaded transient %d bytes\n", transient_count
);
265 /* Rotate cmdstream */
266 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
267 ctx
->cmdstream_i
= 0;
269 if (ctx
->require_sfbd
)
270 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
272 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
274 /* Reset varyings allocated */
275 ctx
->varying_height
= 0;
277 /* The transient cmdstream is dirty every frame; the only bits worth preserving
278 * (textures, shaders, etc) are in other buffers anyways */
280 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
281 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
283 /* Regenerate payloads */
284 panfrost_attach_vt_framebuffer(ctx
);
287 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
290 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
293 /* In practice, every field of these payloads should be configurable
294 * arbitrarily, which means these functions are basically catch-all's for
295 * as-of-yet unwavering unknowns */
298 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
300 struct midgard_payload_vertex_tiler payload
= {
302 .workgroups_z_shift
= 32,
303 .workgroups_x_shift_2
= 0x2,
304 .workgroups_x_shift_3
= 0x5,
306 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
309 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
313 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
315 struct midgard_payload_vertex_tiler payload
= {
317 .workgroups_z_shift
= 32,
318 .workgroups_x_shift_2
= 0x2,
319 .workgroups_x_shift_3
= 0x6,
321 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
325 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
329 translate_tex_wrap(enum pipe_tex_wrap w
)
332 case PIPE_TEX_WRAP_REPEAT
:
333 return MALI_WRAP_REPEAT
;
335 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
336 return MALI_WRAP_CLAMP_TO_EDGE
;
338 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
339 return MALI_WRAP_CLAMP_TO_BORDER
;
341 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
342 return MALI_WRAP_MIRRORED_REPEAT
;
345 unreachable("Invalid wrap");
350 translate_tex_filter(enum pipe_tex_filter f
)
353 case PIPE_TEX_FILTER_NEAREST
:
356 case PIPE_TEX_FILTER_LINEAR
:
360 unreachable("Invalid filter");
365 translate_mip_filter(enum pipe_tex_mipfilter f
)
367 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
371 panfrost_translate_compare_func(enum pipe_compare_func in
)
374 case PIPE_FUNC_NEVER
:
375 return MALI_FUNC_NEVER
;
378 return MALI_FUNC_LESS
;
380 case PIPE_FUNC_EQUAL
:
381 return MALI_FUNC_EQUAL
;
383 case PIPE_FUNC_LEQUAL
:
384 return MALI_FUNC_LEQUAL
;
386 case PIPE_FUNC_GREATER
:
387 return MALI_FUNC_GREATER
;
389 case PIPE_FUNC_NOTEQUAL
:
390 return MALI_FUNC_NOTEQUAL
;
392 case PIPE_FUNC_GEQUAL
:
393 return MALI_FUNC_GEQUAL
;
395 case PIPE_FUNC_ALWAYS
:
396 return MALI_FUNC_ALWAYS
;
399 unreachable("Invalid func");
404 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
407 case PIPE_FUNC_NEVER
:
408 return MALI_ALT_FUNC_NEVER
;
411 return MALI_ALT_FUNC_LESS
;
413 case PIPE_FUNC_EQUAL
:
414 return MALI_ALT_FUNC_EQUAL
;
416 case PIPE_FUNC_LEQUAL
:
417 return MALI_ALT_FUNC_LEQUAL
;
419 case PIPE_FUNC_GREATER
:
420 return MALI_ALT_FUNC_GREATER
;
422 case PIPE_FUNC_NOTEQUAL
:
423 return MALI_ALT_FUNC_NOTEQUAL
;
425 case PIPE_FUNC_GEQUAL
:
426 return MALI_ALT_FUNC_GEQUAL
;
428 case PIPE_FUNC_ALWAYS
:
429 return MALI_ALT_FUNC_ALWAYS
;
432 unreachable("Invalid alt func");
437 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
440 case PIPE_STENCIL_OP_KEEP
:
441 return MALI_STENCIL_KEEP
;
443 case PIPE_STENCIL_OP_ZERO
:
444 return MALI_STENCIL_ZERO
;
446 case PIPE_STENCIL_OP_REPLACE
:
447 return MALI_STENCIL_REPLACE
;
449 case PIPE_STENCIL_OP_INCR
:
450 return MALI_STENCIL_INCR
;
452 case PIPE_STENCIL_OP_DECR
:
453 return MALI_STENCIL_DECR
;
455 case PIPE_STENCIL_OP_INCR_WRAP
:
456 return MALI_STENCIL_INCR_WRAP
;
458 case PIPE_STENCIL_OP_DECR_WRAP
:
459 return MALI_STENCIL_DECR_WRAP
;
461 case PIPE_STENCIL_OP_INVERT
:
462 return MALI_STENCIL_INVERT
;
465 unreachable("Invalid stencil op");
470 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
472 out
->ref
= 0; /* Gallium gets it from elsewhere */
474 out
->mask
= in
->valuemask
;
475 out
->func
= panfrost_translate_compare_func(in
->func
);
476 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
477 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
478 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
482 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
484 struct mali_shader_meta shader
= {
485 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
487 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
488 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
492 shader
.unknown2_4
|= 0x10;
495 struct pipe_stencil_state default_stencil
= {
497 .func
= PIPE_FUNC_ALWAYS
,
498 .fail_op
= MALI_STENCIL_KEEP
,
499 .zfail_op
= MALI_STENCIL_KEEP
,
500 .zpass_op
= MALI_STENCIL_KEEP
,
505 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
506 shader
.stencil_mask_front
= default_stencil
.writemask
;
508 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
509 shader
.stencil_mask_back
= default_stencil
.writemask
;
511 if (default_stencil
.enabled
)
512 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
514 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
517 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
518 * graphics command stream. It should be called once per draw, accordding to
519 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
520 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
523 struct panfrost_transfer
524 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
526 struct mali_job_descriptor_header job
= {
527 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
529 .job_descriptor_size
= 1,
533 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
535 /* There's some padding hacks on 32-bit */
542 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
544 memcpy(transfer
.cpu
, &job
, sizeof(job
));
545 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
550 panfrost_emit_varyings(
551 struct panfrost_context
*ctx
,
552 union mali_attr
*slot
,
556 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
558 /* Fill out the descriptor */
559 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
560 slot
->stride
= stride
;
561 slot
->size
= stride
* count
;
563 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
564 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
566 return varying_address
;
570 panfrost_emit_point_coord(union mali_attr
*slot
)
572 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
573 slot
->stride
= slot
->size
= 0;
577 panfrost_emit_varying_descriptor(
578 struct panfrost_context
*ctx
,
579 unsigned invocation_count
)
581 /* Load the shaders */
583 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
584 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
585 unsigned int num_gen_varyings
= 0;
587 /* Allocate the varying descriptor */
589 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
590 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
592 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
596 * Assign ->src_offset now that we know about all the general purpose
597 * varyings that will be used by the fragment and vertex shaders.
599 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
601 * General purpose varyings have ->index set to 0, skip other
604 if (vs
->varyings
[i
].index
)
607 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
610 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
613 if (fs
->varyings
[i
].index
)
617 * Re-use the VS general purpose varying pos if it exists,
618 * create a new one otherwise.
620 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
621 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
625 if (j
< vs
->tripipe
->varying_count
)
626 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
628 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
631 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
632 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
634 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
635 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
637 /* Buffer indices must be in this order per our convention */
638 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
641 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
644 /* fp32 vec4 gl_Position */
645 ctx
->payload_tiler
.postfix
.position_varying
=
646 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
647 sizeof(float) * 4, invocation_count
);
650 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
651 /* fp16 vec1 gl_PointSize */
652 ctx
->payload_tiler
.primitive_size
.pointer
=
653 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
654 2, invocation_count
);
657 if (fs
->reads_point_coord
) {
658 /* Special descriptor */
659 panfrost_emit_point_coord(&varyings
[idx
++]);
662 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
663 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
664 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
668 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
670 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
671 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
673 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
676 /* Emits attributes and varying descriptors, which should be called every draw,
677 * excepting some obscure circumstances */
680 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
682 /* Staged mali_attr, and index into them. i =/= k, depending on the
683 * vertex buffer mask */
684 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
687 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
689 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
690 if (!(ctx
->vb_mask
& (1 << i
))) continue;
692 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
693 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
697 /* Align to 64 bytes by masking off the lower bits. This
698 * will be adjusted back when we fixup the src_offset in
701 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
703 /* Offset vertex count by draw_start to make sure we upload enough */
704 attrs
[k
].stride
= buf
->stride
;
705 attrs
[k
].size
= rsrc
->base
.width0
;
707 panfrost_job_add_bo(job
, rsrc
->bo
);
708 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
713 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
715 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
719 panfrost_writes_point_size(struct panfrost_context
*ctx
)
722 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
724 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
727 /* Stage the attribute descriptors so we can adjust src_offset
728 * to let BOs align nicely */
731 panfrost_stage_attributes(struct panfrost_context
*ctx
)
733 struct panfrost_vertex_state
*so
= ctx
->vertex
;
735 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
736 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
737 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
739 /* Copy as-is for the first pass */
740 memcpy(target
, so
->hw
, sz
);
742 /* Fixup offsets for the second pass. Recall that the hardware
743 * calculates attribute addresses as:
745 * addr = base + (stride * vtx) + src_offset;
747 * However, on Mali, base must be aligned to 64-bytes, so we
750 * base' = base & ~63 = base - (base & 63)
752 * To compensate when using base' (see emit_vertex_data), we have
753 * to adjust src_offset by the masked off piece:
755 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
756 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
757 * = base + (stride * vtx) + src_offset
763 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
764 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
765 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
767 /* Adjust by the masked off bits of the offset */
768 target
[i
].src_offset
+= (addr
& 63);
771 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
775 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
777 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
779 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
782 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
783 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
785 struct panfrost_transfer transfer
=
786 panfrost_allocate_transient(ctx
, transfer_size
);
788 struct mali_sampler_descriptor
*desc
=
789 (struct mali_sampler_descriptor
*) transfer
.cpu
;
791 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
792 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
794 upload
= transfer
.gpu
;
797 if (t
== PIPE_SHADER_FRAGMENT
)
798 ctx
->payload_tiler
.postfix
.sampler_descriptor
= upload
;
799 else if (t
== PIPE_SHADER_VERTEX
)
800 ctx
->payload_vertex
.postfix
.sampler_descriptor
= upload
;
806 /* Computes the address to a texture at a particular slice */
809 panfrost_get_texture_address(
810 struct panfrost_resource
*rsrc
,
811 unsigned level
, unsigned face
)
813 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
814 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
816 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
822 struct panfrost_context
*ctx
,
823 struct panfrost_sampler_view
*view
)
826 return (mali_ptr
) NULL
;
828 struct pipe_sampler_view
*pview
= &view
->base
;
829 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
831 /* Do we interleave an explicit stride with every element? */
833 bool has_manual_stride
=
834 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
836 /* For easy access */
838 assert(pview
->target
!= PIPE_BUFFER
);
839 unsigned first_level
= pview
->u
.tex
.first_level
;
840 unsigned last_level
= pview
->u
.tex
.last_level
;
842 /* Inject the addresses in, interleaving mip levels, cube faces, and
843 * strides in that order */
847 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
848 for (unsigned f
= 0; f
< pview
->texture
->array_size
; ++f
) {
849 view
->hw
.payload
[idx
++] =
850 panfrost_get_texture_address(rsrc
, l
, f
);
852 if (has_manual_stride
) {
853 view
->hw
.payload
[idx
++] =
854 rsrc
->bo
->slices
[l
].stride
;
859 return panfrost_upload_transient(ctx
, &view
->hw
,
860 sizeof(struct mali_texture_descriptor
));
864 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
866 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
867 mali_ptr trampoline
= 0;
869 if (ctx
->sampler_view_count
[t
]) {
870 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
872 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
874 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
876 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
879 if (t
== PIPE_SHADER_FRAGMENT
)
880 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
881 else if (t
== PIPE_SHADER_VERTEX
)
882 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
888 struct sysval_uniform
{
896 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
897 struct sysval_uniform
*uniform
)
899 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
901 uniform
->f
[0] = vp
->scale
[0];
902 uniform
->f
[1] = vp
->scale
[1];
903 uniform
->f
[2] = vp
->scale
[2];
906 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
907 struct sysval_uniform
*uniform
)
909 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
911 uniform
->f
[0] = vp
->translate
[0];
912 uniform
->f
[1] = vp
->translate
[1];
913 uniform
->f
[2] = vp
->translate
[2];
916 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
917 enum pipe_shader_type st
,
918 unsigned int sysvalid
,
919 struct sysval_uniform
*uniform
)
921 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
922 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
923 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
924 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
927 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
930 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
931 tex
->u
.tex
.first_level
);
934 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
935 tex
->u
.tex
.first_level
);
938 uniform
->i
[dim
] = tex
->texture
->array_size
;
941 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
942 struct panfrost_shader_state
*ss
,
943 enum pipe_shader_type st
)
945 struct sysval_uniform
*uniforms
= (void *)buf
;
947 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
948 int sysval
= ss
->sysval
[i
];
950 switch (PAN_SYSVAL_TYPE(sysval
)) {
951 case PAN_SYSVAL_VIEWPORT_SCALE
:
952 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
954 case PAN_SYSVAL_VIEWPORT_OFFSET
:
955 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
957 case PAN_SYSVAL_TEXTURE_SIZE
:
958 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
967 /* Go through dirty flags and actualise them in the cmdstream. */
970 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
972 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
974 if (with_vertex_data
) {
975 panfrost_emit_vertex_data(ctx
, job
);
978 bool msaa
= ctx
->rasterizer
->base
.multisample
;
980 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
981 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
983 /* TODO: Sample size */
984 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
985 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
988 panfrost_job_set_requirements(ctx
, job
);
990 if (ctx
->occlusion_query
) {
991 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
992 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
995 if (ctx
->dirty
& PAN_DIRTY_VS
) {
998 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1000 /* Late shader descriptor assignments */
1002 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1003 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1006 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1008 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1011 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1012 /* Check if we need to link the gl_PointSize varying */
1013 if (!panfrost_writes_point_size(ctx
)) {
1014 /* If the size is constant, write it out. Otherwise,
1015 * don't touch primitive_size (since we would clobber
1016 * the pointer there) */
1018 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1022 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1024 ctx
->dirty
|= PAN_DIRTY_FS
;
1026 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1028 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1030 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1033 COPY(attribute_count
);
1034 COPY(varying_count
);
1035 COPY(midgard1
.uniform_count
);
1036 COPY(midgard1
.work_count
);
1037 COPY(midgard1
.unknown2
);
1040 /* If there is a blend shader, work registers are shared */
1042 if (ctx
->blend
->has_blend_shader
)
1043 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1045 /* Set late due to depending on render state */
1046 /* The one at the end seems to mean "1 UBO" */
1047 unsigned flags
= MALI_EARLY_Z
| 0x200 | 0x2000 | 0x1;
1049 /* Any time texturing is used, derivatives are implicitly
1050 * calculated, so we need to enable helper invocations */
1052 if (ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
])
1053 flags
|= MALI_HELPER_INVOCATIONS
;
1055 ctx
->fragment_shader_core
.midgard1
.unknown1
= flags
;
1057 /* Assign texture/sample count right before upload */
1058 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1059 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1061 /* Assign the stencil refs late */
1062 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1063 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1065 /* CAN_DISCARD should be set if the fragment shader possibly
1066 * contains a 'discard' instruction. It is likely this is
1067 * related to optimizations related to forward-pixel kill, as
1068 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1069 * thing?" by Peter Harris
1072 if (variant
->can_discard
) {
1073 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1074 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_EARLY_Z
;
1075 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1076 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1079 /* Check if we're using the default blend descriptor (fast path) */
1082 !ctx
->blend
->has_blend_shader
&&
1083 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1084 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1085 (ctx
->blend
->equation
.color_mask
== 0xf);
1087 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1088 * *also* copied to the blend_meta appended (by convention),
1089 * but this is the field actually read by the hardware. (Or
1090 * maybe both are read...?) */
1092 if (ctx
->blend
->has_blend_shader
) {
1093 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1095 ctx
->fragment_shader_core
.blend
.shader
= 0;
1098 if (ctx
->require_sfbd
) {
1099 /* When only a single render target platform is used, the blend
1100 * information is inside the shader meta itself. We
1101 * additionally need to signal CAN_DISCARD for nontrivial blend
1102 * modes (so we're able to read back the destination buffer) */
1104 if (!ctx
->blend
->has_blend_shader
) {
1105 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1106 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1110 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1114 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1115 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1116 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1118 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1120 if (!ctx
->require_sfbd
) {
1121 /* Additional blend descriptor tacked on for jobs using MFBD */
1123 unsigned blend_count
= 0x200;
1125 if (ctx
->blend
->has_blend_shader
) {
1126 /* For a blend shader, the bottom nibble corresponds to
1127 * the number of work registers used, which signals the
1128 * -existence- of a blend shader */
1130 assert(ctx
->blend
->blend_work_count
>= 2);
1131 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1133 /* Otherwise, the bottom bit simply specifies if
1134 * blending (anything other than REPLACE) is enabled */
1141 struct midgard_blend_rt rts
[4];
1145 for (unsigned i
= 0; i
< 1; ++i
) {
1147 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1148 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1150 rts
[i
].flags
= blend_count
;
1153 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1155 /* TODO: sRGB in blend shaders is currently
1156 * unimplemented. Contact me (Alyssa) if you're
1157 * interested in working on this. We have
1158 * native Midgard ops for helping here, but
1159 * they're not well-understood yet. */
1161 assert(!(is_srgb
&& ctx
->blend
->has_blend_shader
));
1163 if (ctx
->blend
->has_blend_shader
) {
1164 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1166 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1167 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1171 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1175 /* We stage to transient, so always dirty.. */
1176 panfrost_stage_attributes(ctx
);
1178 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1179 panfrost_upload_sampler_descriptors(ctx
);
1181 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1182 panfrost_upload_texture_descriptors(ctx
);
1184 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1186 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1187 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1189 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1190 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1191 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1193 /* Allocate room for the sysval and the uniforms */
1194 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1195 size_t size
= sys_size
+ buf
->size
;
1196 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1198 /* Upload sysvals requested by the shader */
1199 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1201 /* Upload uniforms */
1202 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1204 int uniform_count
= 0;
1206 struct mali_vertex_tiler_postfix
*postfix
;
1209 case PIPE_SHADER_VERTEX
:
1210 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1211 postfix
= &ctx
->payload_vertex
.postfix
;
1214 case PIPE_SHADER_FRAGMENT
:
1215 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1216 postfix
= &ctx
->payload_tiler
.postfix
;
1220 unreachable("Invalid shader stage\n");
1223 /* Also attach the same buffer as a UBO for extended access */
1225 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1227 .size
= MALI_POSITIVE((2 + uniform_count
)),
1228 .ptr
= transfer
.gpu
>> 2,
1232 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1233 postfix
->uniforms
= transfer
.gpu
;
1234 postfix
->uniform_buffers
= ubufs
;
1239 /* TODO: Upload the viewport somewhere more appropriate */
1241 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1242 * (somewhat) asymmetric ints. */
1243 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1245 struct mali_viewport view
= {
1246 /* By default, do no viewport clipping, i.e. clip to (-inf,
1247 * inf) in each direction. Clipping to the viewport in theory
1248 * should work, but in practice causes issues when we're not
1249 * explicitly trying to scissor */
1260 /* Always scissor to the viewport by default. */
1261 int minx
= (int) (vp
->translate
[0] - vp
->scale
[0]);
1262 int maxx
= (int) (vp
->translate
[0] + vp
->scale
[0]);
1264 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1265 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1267 /* Apply the scissor test */
1269 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1276 /* Hardware needs the min/max to be strictly ordered, so flip if we
1277 * need to. The viewport transformation in the vertex shader will
1278 * handle the negatives if we don't */
1292 /* Clamp everything positive, just in case */
1294 maxx
= MAX2(0, maxx
);
1295 maxy
= MAX2(0, maxy
);
1296 minx
= MAX2(0, minx
);
1297 miny
= MAX2(0, miny
);
1299 /* Clamp to the framebuffer size as a last check */
1301 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1302 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1304 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1305 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1307 /* Update the job, unless we're doing wallpapering (whose lack of
1308 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1309 * just... be faster :) */
1311 if (!ctx
->wallpaper_batch
)
1312 panfrost_job_union_scissor(job
, minx
, miny
, maxx
, maxy
);
1316 view
.viewport0
[0] = minx
;
1317 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1319 view
.viewport0
[1] = miny
;
1320 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1322 ctx
->payload_tiler
.postfix
.viewport
=
1323 panfrost_upload_transient(ctx
,
1325 sizeof(struct mali_viewport
));
1330 /* Corresponds to exactly one draw, but does not submit anything */
1333 panfrost_queue_draw(struct panfrost_context
*ctx
)
1335 /* Handle dirty flags now */
1336 panfrost_emit_for_draw(ctx
, true);
1338 /* If rasterizer discard is enable, only submit the vertex */
1340 bool rasterizer_discard
= ctx
->rasterizer
1341 && ctx
->rasterizer
->base
.rasterizer_discard
;
1343 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1344 struct panfrost_transfer tiler
;
1346 if (!rasterizer_discard
)
1347 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1349 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1351 if (rasterizer_discard
)
1352 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1353 else if (ctx
->wallpaper_batch
)
1354 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1356 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1359 /* The entire frame is in memory -- send it off to the kernel! */
1362 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1363 struct pipe_fence_handle
**fence
,
1364 struct panfrost_job
*job
)
1366 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1367 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1371 panfrost_job_submit(ctx
, job
);
1373 /* If visual, we can stall a frame */
1375 if (!flush_immediate
)
1376 panfrost_drm_force_flush_fragment(ctx
, fence
);
1378 screen
->last_fragment_flushed
= false;
1379 screen
->last_job
= job
;
1381 /* If readback, flush now (hurts the pipelined performance) */
1382 if (flush_immediate
)
1383 panfrost_drm_force_flush_fragment(ctx
, fence
);
1388 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1390 struct panfrost_context
*ctx
= pan_context(pipe
);
1392 /* Nothing to reload? */
1393 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1396 /* Check if the buffer has any content on it worth preserving */
1398 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1399 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1400 unsigned level
= surf
->u
.tex
.level
;
1402 if (!rsrc
->bo
->slices
[level
].initialized
)
1405 /* Save the batch */
1406 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1408 ctx
->wallpaper_batch
= batch
;
1409 panfrost_blit_wallpaper(ctx
);
1410 ctx
->wallpaper_batch
= NULL
;
1415 struct pipe_context
*pipe
,
1416 struct pipe_fence_handle
**fence
,
1419 struct panfrost_context
*ctx
= pan_context(pipe
);
1420 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1422 /* Nothing to do! */
1423 if (!job
->last_job
.gpu
&& !job
->clear
) return;
1426 panfrost_draw_wallpaper(&ctx
->base
);
1428 /* Whether to stall the pipeline for immediately correct results. Since
1429 * pipelined rendering is quite broken right now (to be fixed by the
1430 * panfrost_job refactor, just take the perf hit for correctness) */
1431 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1433 /* Submit the frame itself */
1434 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1436 /* Prepare for the next frame */
1437 panfrost_invalidate_frame(ctx
);
1440 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1443 g2m_draw_mode(enum pipe_prim_type mode
)
1446 DEFINE_CASE(POINTS
);
1448 DEFINE_CASE(LINE_LOOP
);
1449 DEFINE_CASE(LINE_STRIP
);
1450 DEFINE_CASE(TRIANGLES
);
1451 DEFINE_CASE(TRIANGLE_STRIP
);
1452 DEFINE_CASE(TRIANGLE_FAN
);
1454 DEFINE_CASE(QUAD_STRIP
);
1455 DEFINE_CASE(POLYGON
);
1458 unreachable("Invalid draw mode");
1465 panfrost_translate_index_size(unsigned size
)
1469 return MALI_DRAW_INDEXED_UINT8
;
1472 return MALI_DRAW_INDEXED_UINT16
;
1475 return MALI_DRAW_INDEXED_UINT32
;
1478 unreachable("Invalid index size");
1482 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1483 * good for the duration of the draw (transient), could last longer */
1486 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1488 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1490 off_t offset
= info
->start
* info
->index_size
;
1492 if (!info
->has_user_indices
) {
1493 /* Only resources can be directly mapped */
1494 return rsrc
->bo
->gpu
+ offset
;
1496 /* Otherwise, we need to upload to transient memory */
1497 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1498 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1503 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1505 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1507 /* Check if we're scissoring at all */
1509 if (!(ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1512 return (ss
->minx
== ss
->maxx
) && (ss
->miny
== ss
->maxy
);
1517 struct pipe_context
*pipe
,
1518 const struct pipe_draw_info
*info
)
1520 struct panfrost_context
*ctx
= pan_context(pipe
);
1522 /* First of all, check the scissor to see if anything is drawn at all.
1523 * If it's not, we drop the draw (mostly a conformance issue;
1524 * well-behaved apps shouldn't hit this) */
1526 if (panfrost_scissor_culls_everything(ctx
))
1529 ctx
->payload_vertex
.draw_start
= info
->start
;
1530 ctx
->payload_tiler
.draw_start
= info
->start
;
1532 int mode
= info
->mode
;
1534 /* Fallback for unsupported modes */
1536 if (!(ctx
->draw_modes
& (1 << mode
))) {
1537 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1538 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1540 if (info
->count
< 4) {
1541 /* Degenerate case? */
1545 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1546 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1551 /* Now that we have a guaranteed terminating path, find the job.
1552 * Assignment commented out to prevent unused warning */
1554 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1556 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1558 ctx
->vertex_count
= info
->count
;
1560 /* For non-indexed draws, they're the same */
1561 unsigned invocation_count
= ctx
->vertex_count
;
1563 unsigned draw_flags
= 0;
1565 /* The draw flags interpret how primitive size is interpreted */
1567 if (panfrost_writes_point_size(ctx
))
1568 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1570 /* For higher amounts of vertices (greater than what fits in a 16-bit
1571 * short), the other value is needed, otherwise there will be bizarre
1572 * rendering artefacts. It's not clear what these values mean yet. */
1574 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1576 if (info
->index_size
) {
1577 /* Calculate the min/max index used so we can figure out how
1578 * many times to invoke the vertex shader */
1580 /* Fetch / calculate index bounds */
1581 unsigned min_index
= 0, max_index
= 0;
1583 if (info
->max_index
== ~0u) {
1584 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1586 min_index
= info
->min_index
;
1587 max_index
= info
->max_index
;
1590 /* Use the corresponding values */
1591 invocation_count
= max_index
- min_index
+ 1;
1592 ctx
->payload_vertex
.draw_start
= min_index
;
1593 ctx
->payload_tiler
.draw_start
= min_index
;
1595 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1596 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1598 //assert(!info->restart_index); /* TODO: Research */
1599 assert(!info
->index_bias
);
1601 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1602 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1604 /* Index count == vertex count, if no indexing is applied, as
1605 * if it is internally indexed in the expected order */
1607 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1608 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1610 /* Reverse index state */
1611 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1614 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1615 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1616 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1618 /* Fire off the draw itself */
1619 panfrost_queue_draw(ctx
);
1625 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1631 panfrost_create_rasterizer_state(
1632 struct pipe_context
*pctx
,
1633 const struct pipe_rasterizer_state
*cso
)
1635 struct panfrost_context
*ctx
= pan_context(pctx
);
1636 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1640 /* Bitmask, unknown meaning of the start value */
1641 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1644 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1646 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1647 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1649 if (cso
->cull_face
& PIPE_FACE_BACK
)
1650 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1656 panfrost_bind_rasterizer_state(
1657 struct pipe_context
*pctx
,
1660 struct panfrost_context
*ctx
= pan_context(pctx
);
1662 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1666 ctx
->rasterizer
= hwcso
;
1667 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1671 panfrost_create_vertex_elements_state(
1672 struct pipe_context
*pctx
,
1673 unsigned num_elements
,
1674 const struct pipe_vertex_element
*elements
)
1676 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1678 so
->num_elements
= num_elements
;
1679 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1681 /* XXX: What the cornball? This is totally, 100%, unapologetically
1682 * nonsense. And yet it somehow fixes a regression in -bshadow
1683 * (previously, we allocated the descriptor here... a newer commit
1684 * removed that allocation, and then memory corruption led to
1685 * shader_meta getting overwritten in bad ways and then the whole test
1686 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1688 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1690 for (int i
= 0; i
< num_elements
; ++i
) {
1691 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1693 enum pipe_format fmt
= elements
[i
].src_format
;
1694 const struct util_format_description
*desc
= util_format_description(fmt
);
1695 so
->hw
[i
].unknown1
= 0x2;
1696 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1698 so
->hw
[i
].format
= panfrost_find_format(desc
);
1700 /* The field itself should probably be shifted over */
1701 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1708 panfrost_bind_vertex_elements_state(
1709 struct pipe_context
*pctx
,
1712 struct panfrost_context
*ctx
= pan_context(pctx
);
1714 ctx
->vertex
= hwcso
;
1715 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1719 panfrost_create_shader_state(
1720 struct pipe_context
*pctx
,
1721 const struct pipe_shader_state
*cso
)
1723 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1726 /* Token deep copy to prevent memory corruption */
1728 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1729 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1735 panfrost_delete_shader_state(
1736 struct pipe_context
*pctx
,
1739 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1741 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1742 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1749 panfrost_create_sampler_state(
1750 struct pipe_context
*pctx
,
1751 const struct pipe_sampler_state
*cso
)
1753 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1756 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1758 struct mali_sampler_descriptor sampler_descriptor
= {
1759 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1760 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1761 | translate_mip_filter(cso
->min_mip_filter
)
1764 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1765 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1766 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1767 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1769 cso
->border_color
.f
[0],
1770 cso
->border_color
.f
[1],
1771 cso
->border_color
.f
[2],
1772 cso
->border_color
.f
[3]
1774 .min_lod
= FIXED_16(cso
->min_lod
),
1775 .max_lod
= FIXED_16(cso
->max_lod
),
1779 so
->hw
= sampler_descriptor
;
1785 panfrost_bind_sampler_states(
1786 struct pipe_context
*pctx
,
1787 enum pipe_shader_type shader
,
1788 unsigned start_slot
, unsigned num_sampler
,
1791 assert(start_slot
== 0);
1793 struct panfrost_context
*ctx
= pan_context(pctx
);
1795 /* XXX: Should upload, not just copy? */
1796 ctx
->sampler_count
[shader
] = num_sampler
;
1797 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1799 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1803 panfrost_variant_matches(
1804 struct panfrost_context
*ctx
,
1805 struct panfrost_shader_state
*variant
,
1806 enum pipe_shader_type type
)
1808 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1810 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1812 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1813 /* Make sure enable state is at least the same */
1814 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1818 /* Check that the contents of the test are the same */
1819 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1820 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1822 if (!(same_func
&& same_ref
)) {
1826 /* Otherwise, we're good to go */
1831 panfrost_bind_shader_state(
1832 struct pipe_context
*pctx
,
1834 enum pipe_shader_type type
)
1836 struct panfrost_context
*ctx
= pan_context(pctx
);
1838 if (type
== PIPE_SHADER_FRAGMENT
) {
1840 ctx
->dirty
|= PAN_DIRTY_FS
;
1842 assert(type
== PIPE_SHADER_VERTEX
);
1844 ctx
->dirty
|= PAN_DIRTY_VS
;
1849 /* Match the appropriate variant */
1851 signed variant
= -1;
1852 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1854 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1855 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1861 if (variant
== -1) {
1862 /* No variant matched, so create a new one */
1863 variant
= variants
->variant_count
++;
1864 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1866 variants
->variants
[variant
].base
= hwcso
;
1868 if (type
== PIPE_SHADER_FRAGMENT
)
1869 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1871 /* Allocate the mapped descriptor ahead-of-time. */
1872 struct panfrost_context
*ctx
= pan_context(pctx
);
1873 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1875 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1876 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1880 /* Select this variant */
1881 variants
->active_variant
= variant
;
1883 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1884 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1886 /* We finally have a variant, so compile it */
1888 if (!shader_state
->compiled
) {
1889 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
1890 panfrost_job_type_for_pipe(type
), shader_state
);
1892 shader_state
->compiled
= true;
1897 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1899 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1903 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1905 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1909 panfrost_set_vertex_buffers(
1910 struct pipe_context
*pctx
,
1911 unsigned start_slot
,
1912 unsigned num_buffers
,
1913 const struct pipe_vertex_buffer
*buffers
)
1915 struct panfrost_context
*ctx
= pan_context(pctx
);
1917 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1921 panfrost_set_constant_buffer(
1922 struct pipe_context
*pctx
,
1923 enum pipe_shader_type shader
, uint index
,
1924 const struct pipe_constant_buffer
*buf
)
1926 struct panfrost_context
*ctx
= pan_context(pctx
);
1927 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1929 size_t sz
= buf
? buf
->buffer_size
: 0;
1931 /* Free previous buffer */
1937 ralloc_free(pbuf
->buffer
);
1938 pbuf
->buffer
= NULL
;
1941 /* If unbinding, we're done */
1946 /* Multiple constant buffers not yet supported */
1951 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1954 cpu
= rsrc
->bo
->cpu
;
1955 } else if (buf
->user_buffer
) {
1956 cpu
= buf
->user_buffer
;
1958 DBG("No constant buffer?\n");
1962 /* Copy the constant buffer into the driver context for later upload */
1964 pbuf
->buffer
= rzalloc_size(ctx
, sz
);
1965 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1969 panfrost_set_stencil_ref(
1970 struct pipe_context
*pctx
,
1971 const struct pipe_stencil_ref
*ref
)
1973 struct panfrost_context
*ctx
= pan_context(pctx
);
1974 ctx
->stencil_ref
= *ref
;
1976 /* Shader core dirty */
1977 ctx
->dirty
|= PAN_DIRTY_FS
;
1980 static enum mali_texture_type
1981 panfrost_translate_texture_type(enum pipe_texture_target t
)
1985 case PIPE_TEXTURE_1D
:
1986 case PIPE_TEXTURE_1D_ARRAY
:
1989 case PIPE_TEXTURE_2D
:
1990 case PIPE_TEXTURE_2D_ARRAY
:
1991 case PIPE_TEXTURE_RECT
:
1994 case PIPE_TEXTURE_3D
:
1997 case PIPE_TEXTURE_CUBE
:
1998 case PIPE_TEXTURE_CUBE_ARRAY
:
1999 return MALI_TEX_CUBE
;
2002 unreachable("Unknown target");
2006 static struct pipe_sampler_view
*
2007 panfrost_create_sampler_view(
2008 struct pipe_context
*pctx
,
2009 struct pipe_resource
*texture
,
2010 const struct pipe_sampler_view
*template)
2012 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2013 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2015 pipe_reference(NULL
, &texture
->reference
);
2017 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2020 so
->base
= *template;
2021 so
->base
.texture
= texture
;
2022 so
->base
.reference
.count
= 1;
2023 so
->base
.context
= pctx
;
2025 /* sampler_views correspond to texture descriptors, minus the texture
2026 * (data) itself. So, we serialise the descriptor here and cache it for
2029 /* Make sure it's something with which we're familiar */
2030 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2032 /* TODO: Detect from format better */
2033 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2035 unsigned char user_swizzle
[4] = {
2036 template->swizzle_r
,
2037 template->swizzle_g
,
2038 template->swizzle_b
,
2042 enum mali_format format
= panfrost_find_format(desc
);
2044 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2046 unsigned usage2_layout
= 0x10;
2048 switch (prsrc
->bo
->layout
) {
2050 usage2_layout
|= 0x8 | 0x4;
2053 usage2_layout
|= 0x1;
2056 usage2_layout
|= is_depth
? 0x1 : 0x2;
2063 /* Check if we need to set a custom stride by computing the "expected"
2064 * stride and comparing it to what the BO actually wants. Only applies
2065 * to linear textures, since tiled/compressed textures have strict
2066 * alignment requirements for their strides as it is */
2068 unsigned first_level
= template->u
.tex
.first_level
;
2069 unsigned last_level
= template->u
.tex
.last_level
;
2071 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
2072 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2073 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
2074 unsigned width
= u_minify(texture
->width0
, l
);
2075 unsigned comp_stride
= width
* bytes_per_pixel
;
2077 if (comp_stride
!= actual_stride
) {
2078 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2084 /* In the hardware, array_size refers specifically to array textures,
2085 * whereas in Gallium, it also covers cubemaps */
2087 unsigned array_size
= texture
->array_size
;
2089 if (texture
->target
== PIPE_TEXTURE_CUBE
) {
2090 /* TODO: Cubemap arrays */
2091 assert(array_size
== 6);
2094 struct mali_texture_descriptor texture_descriptor
= {
2095 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2096 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2097 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2098 .array_size
= MALI_POSITIVE(array_size
),
2102 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2105 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2106 .type
= panfrost_translate_texture_type(texture
->target
),
2108 .usage2
= usage2_layout
2111 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2114 //texture_descriptor.nr_mipmap_levels = last_level - first_level;
2116 so
->hw
= texture_descriptor
;
2118 return (struct pipe_sampler_view
*) so
;
2122 panfrost_set_sampler_views(
2123 struct pipe_context
*pctx
,
2124 enum pipe_shader_type shader
,
2125 unsigned start_slot
, unsigned num_views
,
2126 struct pipe_sampler_view
**views
)
2128 struct panfrost_context
*ctx
= pan_context(pctx
);
2130 assert(start_slot
== 0);
2132 unsigned new_nr
= 0;
2133 for (unsigned i
= 0; i
< num_views
; ++i
) {
2138 ctx
->sampler_view_count
[shader
] = new_nr
;
2139 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2141 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2145 panfrost_sampler_view_destroy(
2146 struct pipe_context
*pctx
,
2147 struct pipe_sampler_view
*view
)
2149 pipe_resource_reference(&view
->texture
, NULL
);
2154 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2155 const struct pipe_framebuffer_state
*fb
)
2157 struct panfrost_context
*ctx
= pan_context(pctx
);
2159 /* Flush when switching framebuffers, but not if the framebuffer
2160 * state is being restored by u_blitter
2163 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
2164 bool is_scanout
= panfrost_is_scanout(ctx
);
2165 bool has_draws
= job
->last_job
.gpu
;
2167 if (!ctx
->blitter
->running
&& (!is_scanout
|| has_draws
)) {
2168 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2171 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2172 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2173 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2174 ctx
->pipe_framebuffer
.width
= fb
->width
;
2175 ctx
->pipe_framebuffer
.height
= fb
->height
;
2177 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2178 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2180 /* check if changing cbuf */
2181 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2183 if (cb
&& (i
!= 0)) {
2184 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2189 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2194 if (ctx
->require_sfbd
)
2195 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2197 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2199 panfrost_attach_vt_framebuffer(ctx
);
2201 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2202 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2204 bool can_afbc
= panfrost_format_supports_afbc(format
);
2205 bool is_scanout
= panfrost_is_scanout(ctx
);
2207 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2208 panfrost_enable_afbc(ctx
, tex
, false);
2210 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2211 panfrost_enable_checksum(ctx
, tex
);
2215 struct pipe_surface
*zb
= fb
->zsbuf
;
2217 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2218 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2221 if (ctx
->require_sfbd
)
2222 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2224 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2226 panfrost_attach_vt_framebuffer(ctx
);
2228 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2229 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2230 bool is_scanout
= panfrost_is_scanout(ctx
);
2232 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2233 panfrost_enable_afbc(ctx
, tex
, true);
2240 panfrost_create_blend_state(struct pipe_context
*pipe
,
2241 const struct pipe_blend_state
*blend
)
2243 struct panfrost_context
*ctx
= pan_context(pipe
);
2244 struct panfrost_blend_state
*so
= rzalloc(ctx
, struct panfrost_blend_state
);
2247 /* TODO: The following features are not yet implemented */
2248 assert(!blend
->logicop_enable
);
2249 assert(!blend
->alpha_to_coverage
);
2250 assert(!blend
->alpha_to_one
);
2252 /* Compile the blend state, first as fixed-function if we can */
2254 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2257 /* If we can't, compile a blend shader instead */
2259 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2265 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2268 struct panfrost_context
*ctx
= pan_context(pipe
);
2269 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2270 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2271 ctx
->blend
= pblend
;
2276 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2278 /* TODO: Attach color */
2280 /* Shader itself is not dirty, but the shader core is */
2281 ctx
->dirty
|= PAN_DIRTY_FS
;
2285 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2288 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2290 if (so
->has_blend_shader
) {
2291 DBG("Deleting blend state leak blend shaders bytecode\n");
2298 panfrost_set_blend_color(struct pipe_context
*pipe
,
2299 const struct pipe_blend_color
*blend_color
)
2301 struct panfrost_context
*ctx
= pan_context(pipe
);
2303 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2306 ctx
->blend_color
= *blend_color
;
2308 /* The blend mode depends on the blend constant color, due to the
2309 * fixed/programmable split. So, we're forced to regenerate the blend
2312 /* TODO: Attach color */
2317 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2318 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2320 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2324 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2327 struct panfrost_context
*ctx
= pan_context(pipe
);
2328 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2329 ctx
->depth_stencil
= depth_stencil
;
2334 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2335 * emulated in the fragment shader */
2337 if (depth_stencil
->alpha
.enabled
) {
2338 /* We need to trigger a new shader (maybe) */
2339 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2343 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2345 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2346 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2348 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2349 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2351 /* Depth state (TODO: Refactor) */
2352 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2354 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2356 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2357 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2359 /* Bounds test not implemented */
2360 assert(!depth_stencil
->depth
.bounds_test
);
2362 ctx
->dirty
|= PAN_DIRTY_FS
;
2366 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2372 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2373 unsigned sample_mask
)
2378 panfrost_set_clip_state(struct pipe_context
*pipe
,
2379 const struct pipe_clip_state
*clip
)
2381 //struct panfrost_context *panfrost = pan_context(pipe);
2385 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2386 unsigned start_slot
,
2387 unsigned num_viewports
,
2388 const struct pipe_viewport_state
*viewports
)
2390 struct panfrost_context
*ctx
= pan_context(pipe
);
2392 assert(start_slot
== 0);
2393 assert(num_viewports
== 1);
2395 ctx
->pipe_viewport
= *viewports
;
2399 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2400 unsigned start_slot
,
2401 unsigned num_scissors
,
2402 const struct pipe_scissor_state
*scissors
)
2404 struct panfrost_context
*ctx
= pan_context(pipe
);
2406 assert(start_slot
== 0);
2407 assert(num_scissors
== 1);
2409 ctx
->scissor
= *scissors
;
2413 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2414 const struct pipe_poly_stipple
*stipple
)
2416 //struct panfrost_context *panfrost = pan_context(pipe);
2420 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2423 //struct panfrost_context *panfrost = pan_context(pipe);
2427 panfrost_destroy(struct pipe_context
*pipe
)
2429 struct panfrost_context
*panfrost
= pan_context(pipe
);
2430 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2432 if (panfrost
->blitter
)
2433 util_blitter_destroy(panfrost
->blitter
);
2435 panfrost_drm_free_slab(screen
, &panfrost
->scratchpad
);
2436 panfrost_drm_free_slab(screen
, &panfrost
->varying_mem
);
2437 panfrost_drm_free_slab(screen
, &panfrost
->shaders
);
2438 panfrost_drm_free_slab(screen
, &panfrost
->tiler_heap
);
2439 panfrost_drm_free_slab(screen
, &panfrost
->tiler_polygon_list
);
2440 panfrost_drm_free_slab(screen
, &panfrost
->tiler_dummy
);
2442 for (int i
= 0; i
< ARRAY_SIZE(panfrost
->transient_pools
); ++i
) {
2443 struct panfrost_memory_entry
*entry
;
2444 entry
= panfrost
->transient_pools
[i
].entries
[0];
2445 pb_slab_free(&screen
->slabs
, (struct pb_slab_entry
*)entry
);
2451 static struct pipe_query
*
2452 panfrost_create_query(struct pipe_context
*pipe
,
2456 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2461 return (struct pipe_query
*) q
;
2465 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2471 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2473 struct panfrost_context
*ctx
= pan_context(pipe
);
2474 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2476 switch (query
->type
) {
2477 case PIPE_QUERY_OCCLUSION_COUNTER
:
2478 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2479 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2481 /* Allocate a word for the query results to be stored */
2482 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2484 ctx
->occlusion_query
= query
;
2490 DBG("Skipping query %d\n", query
->type
);
2498 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2500 struct panfrost_context
*ctx
= pan_context(pipe
);
2501 ctx
->occlusion_query
= NULL
;
2506 panfrost_get_query_result(struct pipe_context
*pipe
,
2507 struct pipe_query
*q
,
2509 union pipe_query_result
*vresult
)
2512 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2514 /* We need to flush out the jobs to actually run the counter, TODO
2515 * check wait, TODO wallpaper after if needed */
2517 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2519 switch (query
->type
) {
2520 case PIPE_QUERY_OCCLUSION_COUNTER
:
2521 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2522 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2523 /* Read back the query results */
2524 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2525 unsigned passed
= *result
;
2527 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2528 vresult
->u64
= passed
;
2530 vresult
->b
= !!passed
;
2536 DBG("Skipped query get %d\n", query
->type
);
2543 static struct pipe_stream_output_target
*
2544 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2545 struct pipe_resource
*prsc
,
2546 unsigned buffer_offset
,
2547 unsigned buffer_size
)
2549 struct pipe_stream_output_target
*target
;
2551 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2556 pipe_reference_init(&target
->reference
, 1);
2557 pipe_resource_reference(&target
->buffer
, prsc
);
2559 target
->context
= pctx
;
2560 target
->buffer_offset
= buffer_offset
;
2561 target
->buffer_size
= buffer_size
;
2567 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2568 struct pipe_stream_output_target
*target
)
2570 pipe_resource_reference(&target
->buffer
, NULL
);
2571 ralloc_free(target
);
2575 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2576 unsigned num_targets
,
2577 struct pipe_stream_output_target
**targets
,
2578 const unsigned *offsets
)
2584 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2586 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2587 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2589 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2590 /* Allocate the beginning of the transient pool */
2591 int entry_size
= (1 << 22); /* 4MB */
2593 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2594 ctx
->transient_pools
[i
].entry_count
= 1;
2596 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2599 panfrost_drm_allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2600 panfrost_drm_allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2601 panfrost_drm_allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2602 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2603 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_polygon_list
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2604 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2607 /* New context creation, which also does hardware initialisation since I don't
2608 * know the better way to structure this :smirk: */
2610 struct pipe_context
*
2611 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2613 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2614 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2615 memset(ctx
, 0, sizeof(*ctx
));
2616 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2619 gpu_id
= panfrost_drm_query_gpu_version(pscreen
);
2621 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2622 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2624 gallium
->screen
= screen
;
2626 gallium
->destroy
= panfrost_destroy
;
2628 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2630 gallium
->flush
= panfrost_flush
;
2631 gallium
->clear
= panfrost_clear
;
2632 gallium
->draw_vbo
= panfrost_draw_vbo
;
2634 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2635 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2637 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2639 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2640 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2641 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2643 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2644 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2645 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2647 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2648 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2649 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2651 gallium
->create_fs_state
= panfrost_create_shader_state
;
2652 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2653 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2655 gallium
->create_vs_state
= panfrost_create_shader_state
;
2656 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2657 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2659 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2660 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2661 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2663 gallium
->create_blend_state
= panfrost_create_blend_state
;
2664 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2665 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2667 gallium
->set_blend_color
= panfrost_set_blend_color
;
2669 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2670 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2671 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2673 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2675 gallium
->set_clip_state
= panfrost_set_clip_state
;
2676 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2677 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2678 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2679 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2681 gallium
->create_query
= panfrost_create_query
;
2682 gallium
->destroy_query
= panfrost_destroy_query
;
2683 gallium
->begin_query
= panfrost_begin_query
;
2684 gallium
->end_query
= panfrost_end_query
;
2685 gallium
->get_query_result
= panfrost_get_query_result
;
2687 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2688 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2689 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2691 panfrost_resource_context_init(gallium
);
2693 panfrost_drm_init_context(ctx
);
2695 panfrost_setup_hardware(ctx
);
2698 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2699 gallium
->const_uploader
= gallium
->stream_uploader
;
2700 assert(gallium
->stream_uploader
);
2702 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2703 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2705 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2707 ctx
->blitter
= util_blitter_create(gallium
);
2708 assert(ctx
->blitter
);
2710 /* Prepare for render! */
2712 panfrost_job_init(ctx
);
2713 panfrost_emit_vertex_payload(ctx
);
2714 panfrost_emit_tiler_payload(ctx
);
2715 panfrost_invalidate_frame(ctx
);
2716 panfrost_default_shader_backend(ctx
);