2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
56 struct midgard_tiler_descriptor
57 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
59 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
60 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
61 struct midgard_tiler_descriptor t
= {0};
62 unsigned height
= batch
->key
.height
;
63 unsigned width
= batch
->key
.width
;
66 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
68 /* Compute the polygon header size and use that to offset the body */
70 unsigned header_size
= panfrost_tiler_header_size(
71 width
, height
, t
.hierarchy_mask
, hierarchy
);
73 t
.polygon_list_size
= panfrost_tiler_full_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
79 struct panfrost_bo
*tiler_heap
;
81 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
82 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
87 /* Allow the entire tiler heap */
88 t
.heap_start
= tiler_heap
->gpu
;
89 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
91 struct panfrost_bo
*tiler_dummy
;
93 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
94 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
96 /* The tiler is disabled, so don't allow the tiler heap */
97 t
.heap_start
= tiler_dummy
->gpu
;
98 t
.heap_end
= t
.heap_start
;
100 /* Use a dummy polygon list */
101 t
.polygon_list
= tiler_dummy
->gpu
;
103 /* Disable the tiler */
105 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
107 t
.hierarchy_mask
= MALI_TILER_USER
;
108 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
110 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
111 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
112 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
116 t
.polygon_list_body
=
117 t
.polygon_list
+ header_size
;
124 struct pipe_context
*pipe
,
126 const union pipe_color_union
*color
,
127 double depth
, unsigned stencil
)
129 struct panfrost_context
*ctx
= pan_context(pipe
);
131 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
132 * the existing batch targeting this FBO has draws. We could probably
133 * avoid that by replacing plain clears by quad-draws with a specific
134 * color/depth/stencil value, thus avoiding the generation of extra
137 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
139 panfrost_batch_add_fbo_bos(batch
);
140 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
144 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
146 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
147 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
149 /* If we haven't, reserve space for the framebuffer */
151 if (!batch
->framebuffer
.gpu
) {
152 unsigned size
= (screen
->quirks
& MIDGARD_SFBD
) ?
153 sizeof(struct mali_single_framebuffer
) :
154 sizeof(struct bifrost_framebuffer
);
156 batch
->framebuffer
= panfrost_allocate_transient(batch
, size
);
158 /* Tag the pointer */
159 if (!(screen
->quirks
& MIDGARD_SFBD
))
160 batch
->framebuffer
.gpu
|= MALI_MFBD
;
163 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
164 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
.gpu
;
167 /* Reset per-frame context, called on context initialisation as well as after
168 * flushing a frame */
171 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
173 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
174 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
177 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
180 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
182 /* TODO: When does this need to be handled? */
183 ctx
->active_queries
= true;
186 /* In practice, every field of these payloads should be configurable
187 * arbitrarily, which means these functions are basically catch-all's for
188 * as-of-yet unwavering unknowns */
191 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
193 /* 0x2 bit clear on 32-bit T6XX */
195 struct midgard_payload_vertex_tiler payload
= {
196 .gl_enables
= 0x4 | 0x2,
199 /* Vertex and compute are closely coupled, so share a payload */
201 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
202 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
206 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
208 struct midgard_payload_vertex_tiler payload
= {
210 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
214 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
218 translate_tex_wrap(enum pipe_tex_wrap w
)
221 case PIPE_TEX_WRAP_REPEAT
:
222 return MALI_WRAP_REPEAT
;
224 case PIPE_TEX_WRAP_CLAMP
:
225 return MALI_WRAP_CLAMP
;
227 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
228 return MALI_WRAP_CLAMP_TO_EDGE
;
230 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
231 return MALI_WRAP_CLAMP_TO_BORDER
;
233 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
234 return MALI_WRAP_MIRRORED_REPEAT
;
236 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
237 return MALI_WRAP_MIRRORED_CLAMP
;
239 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
240 return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
;
242 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
243 return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
;
246 unreachable("Invalid wrap");
251 panfrost_translate_compare_func(enum pipe_compare_func in
)
254 case PIPE_FUNC_NEVER
:
255 return MALI_FUNC_NEVER
;
258 return MALI_FUNC_LESS
;
260 case PIPE_FUNC_EQUAL
:
261 return MALI_FUNC_EQUAL
;
263 case PIPE_FUNC_LEQUAL
:
264 return MALI_FUNC_LEQUAL
;
266 case PIPE_FUNC_GREATER
:
267 return MALI_FUNC_GREATER
;
269 case PIPE_FUNC_NOTEQUAL
:
270 return MALI_FUNC_NOTEQUAL
;
272 case PIPE_FUNC_GEQUAL
:
273 return MALI_FUNC_GEQUAL
;
275 case PIPE_FUNC_ALWAYS
:
276 return MALI_FUNC_ALWAYS
;
279 unreachable("Invalid func");
284 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
287 case PIPE_FUNC_NEVER
:
288 return MALI_ALT_FUNC_NEVER
;
291 return MALI_ALT_FUNC_LESS
;
293 case PIPE_FUNC_EQUAL
:
294 return MALI_ALT_FUNC_EQUAL
;
296 case PIPE_FUNC_LEQUAL
:
297 return MALI_ALT_FUNC_LEQUAL
;
299 case PIPE_FUNC_GREATER
:
300 return MALI_ALT_FUNC_GREATER
;
302 case PIPE_FUNC_NOTEQUAL
:
303 return MALI_ALT_FUNC_NOTEQUAL
;
305 case PIPE_FUNC_GEQUAL
:
306 return MALI_ALT_FUNC_GEQUAL
;
308 case PIPE_FUNC_ALWAYS
:
309 return MALI_ALT_FUNC_ALWAYS
;
312 unreachable("Invalid alt func");
317 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
320 case PIPE_STENCIL_OP_KEEP
:
321 return MALI_STENCIL_KEEP
;
323 case PIPE_STENCIL_OP_ZERO
:
324 return MALI_STENCIL_ZERO
;
326 case PIPE_STENCIL_OP_REPLACE
:
327 return MALI_STENCIL_REPLACE
;
329 case PIPE_STENCIL_OP_INCR
:
330 return MALI_STENCIL_INCR
;
332 case PIPE_STENCIL_OP_DECR
:
333 return MALI_STENCIL_DECR
;
335 case PIPE_STENCIL_OP_INCR_WRAP
:
336 return MALI_STENCIL_INCR_WRAP
;
338 case PIPE_STENCIL_OP_DECR_WRAP
:
339 return MALI_STENCIL_DECR_WRAP
;
341 case PIPE_STENCIL_OP_INVERT
:
342 return MALI_STENCIL_INVERT
;
345 unreachable("Invalid stencil op");
350 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
352 out
->ref
= 0; /* Gallium gets it from elsewhere */
354 out
->mask
= in
->valuemask
;
355 out
->func
= panfrost_translate_compare_func(in
->func
);
356 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
357 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
358 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
362 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
364 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
365 struct mali_shader_meta shader
= {
366 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
368 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
369 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
372 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
373 * required (independent of 32-bit/64-bit descriptors), or why it's not
374 * used on later GPU revisions. Otherwise, all shader jobs fault on
375 * these earlier chips (perhaps this is a chicken bit of some kind).
376 * More investigation is needed. */
378 if (screen
->quirks
& MIDGARD_SFBD
)
379 shader
.unknown2_4
|= 0x10;
381 struct pipe_stencil_state default_stencil
= {
383 .func
= PIPE_FUNC_ALWAYS
,
384 .fail_op
= MALI_STENCIL_KEEP
,
385 .zfail_op
= MALI_STENCIL_KEEP
,
386 .zpass_op
= MALI_STENCIL_KEEP
,
391 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
392 shader
.stencil_mask_front
= default_stencil
.writemask
;
394 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
395 shader
.stencil_mask_back
= default_stencil
.writemask
;
397 if (default_stencil
.enabled
)
398 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
400 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
403 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
404 * graphics command stream. It should be called once per draw, accordding to
405 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
406 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
409 struct panfrost_transfer
410 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
412 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
413 struct mali_job_descriptor_header job
= {
414 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
415 .job_descriptor_size
= 1,
418 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
420 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
421 memcpy(transfer
.cpu
, &job
, sizeof(job
));
422 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
427 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
429 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
430 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
432 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
436 panfrost_writes_point_size(struct panfrost_context
*ctx
)
438 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
439 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
441 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
444 /* Stage the attribute descriptors so we can adjust src_offset
445 * to let BOs align nicely */
448 panfrost_stage_attributes(struct panfrost_context
*ctx
)
450 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
451 struct panfrost_vertex_state
*so
= ctx
->vertex
;
453 size_t sz
= sizeof(struct mali_attr_meta
) * PAN_MAX_ATTRIBUTE
;
454 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
455 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
457 /* Copy as-is for the first pass */
458 memcpy(target
, so
->hw
, sz
);
460 /* Fixup offsets for the second pass. Recall that the hardware
461 * calculates attribute addresses as:
463 * addr = base + (stride * vtx) + src_offset;
465 * However, on Mali, base must be aligned to 64-bytes, so we
468 * base' = base & ~63 = base - (base & 63)
470 * To compensate when using base' (see emit_vertex_data), we have
471 * to adjust src_offset by the masked off piece:
473 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
474 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
475 * = base + (stride * vtx) + src_offset
481 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
483 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
484 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
485 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
486 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
488 /* Adjust by the masked off bits of the offset */
489 target
[i
].src_offset
+= (addr
& 63);
491 /* Also, somewhat obscurely per-instance data needs to be
492 * offset in response to a delayed start in an indexed draw */
494 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
)
495 target
[i
].src_offset
-= buf
->stride
* start
;
498 /* Let's also include vertex builtins */
500 target
[PAN_VERTEX_ID
].format
= MALI_R32UI
;
501 target
[PAN_VERTEX_ID
].swizzle
= panfrost_get_default_swizzle(1);
503 target
[PAN_INSTANCE_ID
].format
= MALI_R32UI
;
504 target
[PAN_INSTANCE_ID
].swizzle
= panfrost_get_default_swizzle(1);
506 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
510 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
512 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
513 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
515 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
518 if (ctx
->sampler_count
[t
]) {
519 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
521 struct panfrost_transfer transfer
=
522 panfrost_allocate_transient(batch
, transfer_size
);
524 struct mali_sampler_descriptor
*desc
=
525 (struct mali_sampler_descriptor
*) transfer
.cpu
;
527 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
528 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
530 upload
= transfer
.gpu
;
533 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
537 static enum mali_texture_layout
538 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
540 /* TODO: other linear depth textures */
541 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
543 switch (rsrc
->layout
) {
545 return MALI_TEXTURE_AFBC
;
548 return MALI_TEXTURE_TILED
;
550 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
552 unreachable("Invalid texture layout");
558 struct panfrost_context
*ctx
,
559 enum pipe_shader_type st
,
560 struct panfrost_sampler_view
*view
)
565 struct pipe_sampler_view
*pview
= &view
->base
;
566 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
568 /* Do we interleave an explicit stride with every element? */
570 bool has_manual_stride
= view
->manual_stride
;
572 /* For easy access */
574 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
575 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
576 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
577 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
578 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
580 /* Lower-bit is set when sampling from colour AFBC */
581 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
582 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
583 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
585 /* Add the BO to the job so it's retained until the job is done. */
586 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
587 panfrost_batch_add_bo(batch
, rsrc
->bo
,
588 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
589 panfrost_bo_access_for_stage(st
));
591 /* Add the usage flags in, since they can change across the CSO
592 * lifetime due to layout switches */
594 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
595 view
->hw
.format
.manual_stride
= has_manual_stride
;
597 /* Inject the addresses in, interleaving mip levels, cube faces, and
598 * strides in that order */
602 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
603 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
605 view
->hw
.payload
[idx
++] =
606 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
608 if (has_manual_stride
) {
609 view
->hw
.payload
[idx
++] =
610 rsrc
->slices
[l
].stride
;
615 return panfrost_upload_transient(batch
, &view
->hw
,
616 sizeof(struct mali_texture_descriptor
));
620 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
622 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
624 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
625 mali_ptr trampoline
= 0;
627 if (ctx
->sampler_view_count
[t
]) {
628 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
630 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
632 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
634 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
637 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
641 struct sysval_uniform
{
650 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
651 struct sysval_uniform
*uniform
)
653 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
655 uniform
->f
[0] = vp
->scale
[0];
656 uniform
->f
[1] = vp
->scale
[1];
657 uniform
->f
[2] = vp
->scale
[2];
660 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
661 struct sysval_uniform
*uniform
)
663 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
665 uniform
->f
[0] = vp
->translate
[0];
666 uniform
->f
[1] = vp
->translate
[1];
667 uniform
->f
[2] = vp
->translate
[2];
670 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
671 enum pipe_shader_type st
,
672 unsigned int sysvalid
,
673 struct sysval_uniform
*uniform
)
675 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
676 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
677 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
678 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
681 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
684 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
685 tex
->u
.tex
.first_level
);
688 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
689 tex
->u
.tex
.first_level
);
692 uniform
->i
[dim
] = tex
->texture
->array_size
;
695 static void panfrost_upload_ssbo_sysval(
696 struct panfrost_context
*ctx
,
697 enum pipe_shader_type st
,
699 struct sysval_uniform
*uniform
)
701 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
702 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
704 /* Compute address */
705 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
706 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
708 panfrost_batch_add_bo(batch
, bo
,
709 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
710 panfrost_bo_access_for_stage(st
));
712 /* Upload address and size as sysval */
713 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
714 uniform
->u
[2] = sb
.buffer_size
;
718 panfrost_upload_sampler_sysval(
719 struct panfrost_context
*ctx
,
720 enum pipe_shader_type st
,
721 unsigned sampler_index
,
722 struct sysval_uniform
*uniform
)
724 struct pipe_sampler_state
*sampl
=
725 &ctx
->samplers
[st
][sampler_index
]->base
;
727 uniform
->f
[0] = sampl
->min_lod
;
728 uniform
->f
[1] = sampl
->max_lod
;
729 uniform
->f
[2] = sampl
->lod_bias
;
731 /* Even without any errata, Midgard represents "no mipmapping" as
732 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
733 * panfrost_create_sampler_state which also explains our choice of
734 * epsilon value (again to keep behaviour consistent) */
736 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
737 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
740 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
741 struct sysval_uniform
*uniform
)
743 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
744 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
745 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
748 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
749 struct panfrost_shader_state
*ss
,
750 enum pipe_shader_type st
)
752 struct sysval_uniform
*uniforms
= (void *)buf
;
754 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
755 int sysval
= ss
->sysval
[i
];
757 switch (PAN_SYSVAL_TYPE(sysval
)) {
758 case PAN_SYSVAL_VIEWPORT_SCALE
:
759 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
761 case PAN_SYSVAL_VIEWPORT_OFFSET
:
762 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
764 case PAN_SYSVAL_TEXTURE_SIZE
:
765 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
768 case PAN_SYSVAL_SSBO
:
769 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
772 case PAN_SYSVAL_NUM_WORK_GROUPS
:
773 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
775 case PAN_SYSVAL_SAMPLER
:
776 panfrost_upload_sampler_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
786 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
788 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
789 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
792 return rsrc
->bo
->cpu
;
793 else if (cb
->user_buffer
)
794 return cb
->user_buffer
;
796 unreachable("No constant buffer");
800 panfrost_map_constant_buffer_gpu(
801 struct panfrost_context
*ctx
,
802 enum pipe_shader_type st
,
803 struct panfrost_constant_buffer
*buf
,
806 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
807 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
808 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
811 panfrost_batch_add_bo(batch
, rsrc
->bo
,
812 PAN_BO_ACCESS_SHARED
|
814 panfrost_bo_access_for_stage(st
));
815 return rsrc
->bo
->gpu
;
816 } else if (cb
->user_buffer
) {
817 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
819 unreachable("No constant buffer");
823 /* Compute number of UBOs active (more specifically, compute the highest UBO
824 * number addressable -- if there are gaps, include them in the count anyway).
825 * We always include UBO #0 in the count, since we *need* uniforms enabled for
829 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
831 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
832 return 32 - __builtin_clz(mask
);
835 /* Fixes up a shader state with current state */
838 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
839 enum pipe_shader_type stage
)
841 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
844 ctx
->payloads
[stage
].postfix
.shader
= 0;
848 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
850 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
851 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
853 ss
->tripipe
->midgard1
.flags
= 0x220;
855 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
856 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
858 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
860 /* Add the shader BO to the batch. */
861 panfrost_batch_add_bo(batch
, ss
->bo
,
862 PAN_BO_ACCESS_PRIVATE
|
864 panfrost_bo_access_for_stage(stage
));
866 ctx
->payloads
[stage
].postfix
.shader
= panfrost_upload_transient(batch
,
868 sizeof(struct mali_shader_meta
));
871 /* Go through dirty flags and actualise them in the cmdstream. */
874 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
876 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
877 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
879 panfrost_batch_add_fbo_bos(batch
);
880 panfrost_attach_vt_framebuffer(ctx
);
882 if (with_vertex_data
) {
883 panfrost_emit_vertex_data(batch
);
885 /* Varyings emitted for -all- geometry */
886 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
887 panfrost_emit_varying_descriptor(ctx
, total_count
);
890 bool msaa
= ctx
->rasterizer
->base
.multisample
;
892 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
893 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
895 /* TODO: Sample size */
896 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
897 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
900 panfrost_batch_set_requirements(batch
);
902 if (ctx
->occlusion_query
) {
903 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
904 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
907 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
908 panfrost_patch_shader_state(ctx
, PIPE_SHADER_COMPUTE
);
910 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
911 /* Check if we need to link the gl_PointSize varying */
912 if (!panfrost_writes_point_size(ctx
)) {
913 /* If the size is constant, write it out. Otherwise,
914 * don't touch primitive_size (since we would clobber
915 * the pointer there) */
917 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
921 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
922 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
923 ctx
->dirty
|= PAN_DIRTY_FS
;
925 if (ctx
->dirty
& PAN_DIRTY_FS
) {
926 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
927 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
929 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
931 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
934 COPY(attribute_count
);
938 COPY(midgard1
.uniform_count
);
939 COPY(midgard1
.uniform_buffer_count
);
940 COPY(midgard1
.work_count
);
941 COPY(midgard1
.flags
);
942 COPY(midgard1
.unknown2
);
946 /* Get blending setup */
947 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
949 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
951 for (unsigned c
= 0; c
< rt_count
; ++c
)
952 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
954 /* If there is a blend shader, work registers are shared. XXX: opt */
956 for (unsigned c
= 0; c
< rt_count
; ++c
) {
957 if (blend
[c
].is_shader
)
958 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
961 /* Depending on whether it's legal to in the given shader, we
962 * try to enable early-z testing (or forward-pixel kill?) */
964 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags
, MALI_EARLY_Z
, !variant
->can_discard
);
966 /* Any time texturing is used, derivatives are implicitly
967 * calculated, so we need to enable helper invocations */
969 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
971 /* Assign the stencil refs late */
973 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
974 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
975 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
977 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
978 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
980 /* CAN_DISCARD should be set if the fragment shader possibly
981 * contains a 'discard' instruction. It is likely this is
982 * related to optimizations related to forward-pixel kill, as
983 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
984 * thing?" by Peter Harris
987 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
988 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags
, 0x400, variant
->can_discard
);
990 /* Even on MFBD, the shader descriptor gets blend shaders. It's
991 * *also* copied to the blend_meta appended (by convention),
992 * but this is the field actually read by the hardware. (Or
993 * maybe both are read...?) */
995 if (blend
[0].is_shader
) {
996 ctx
->fragment_shader_core
.blend
.shader
=
997 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
999 ctx
->fragment_shader_core
.blend
.shader
= 0;
1002 if (screen
->quirks
& MIDGARD_SFBD
) {
1003 /* When only a single render target platform is used, the blend
1004 * information is inside the shader meta itself. We
1005 * additionally need to signal CAN_DISCARD for nontrivial blend
1006 * modes (so we're able to read back the destination buffer) */
1008 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
1010 if (!blend
[0].is_shader
) {
1011 ctx
->fragment_shader_core
.blend
.equation
=
1012 *blend
[0].equation
.equation
;
1013 ctx
->fragment_shader_core
.blend
.constant
=
1014 blend
[0].equation
.constant
;
1017 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
1020 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1021 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1022 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1024 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
1026 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
1027 /* Additional blend descriptor tacked on for jobs using MFBD */
1029 struct midgard_blend_rt rts
[4];
1031 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1032 rts
[i
].flags
= 0x200;
1035 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1036 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1037 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1039 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
1040 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
1041 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
1042 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
1044 /* TODO: sRGB in blend shaders is currently
1045 * unimplemented. Contact me (Alyssa) if you're
1046 * interested in working on this. We have
1047 * native Midgard ops for helping here, but
1048 * they're not well-understood yet. */
1050 assert(!(is_srgb
&& blend
[i
].is_shader
));
1052 if (blend
[i
].is_shader
) {
1053 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1055 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1056 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1060 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1064 /* We stage to transient, so always dirty.. */
1066 panfrost_stage_attributes(ctx
);
1068 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1069 panfrost_upload_sampler_descriptors(ctx
);
1071 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1072 panfrost_upload_texture_descriptors(ctx
);
1074 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1076 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1077 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1082 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1084 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1086 /* Uniforms are implicitly UBO #0 */
1087 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1089 /* Allocate room for the sysval and the uniforms */
1090 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1091 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1092 size_t size
= sys_size
+ uniform_size
;
1093 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1095 /* Upload sysvals requested by the shader */
1096 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1098 /* Upload uniforms */
1100 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1101 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1105 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1107 struct mali_vertex_tiler_postfix
*postfix
=
1108 &ctx
->payloads
[i
].postfix
;
1110 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1113 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1114 assert(ubo_count
>= 1);
1116 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1117 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1119 /* Upload uniforms as a UBO */
1120 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1121 ubos
[0].ptr
= transfer
.gpu
>> 2;
1123 /* The rest are honest-to-goodness UBOs */
1125 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1126 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1128 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1129 bool empty
= usz
== 0;
1131 if (!enabled
|| empty
) {
1132 /* Stub out disabled UBOs to catch accesses */
1135 ubos
[ubo
].ptr
= 0xDEAD0000;
1139 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1141 unsigned bytes_per_field
= 16;
1142 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1143 unsigned fields
= aligned
/ bytes_per_field
;
1145 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1146 ubos
[ubo
].ptr
= gpu
>> 2;
1149 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1150 postfix
->uniforms
= transfer
.gpu
;
1151 postfix
->uniform_buffers
= ubufs
;
1153 buf
->dirty_mask
= 0;
1156 /* TODO: Upload the viewport somewhere more appropriate */
1158 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1159 * (somewhat) asymmetric ints. */
1160 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1162 struct mali_viewport view
= {
1163 /* By default, do no viewport clipping, i.e. clip to (-inf,
1164 * inf) in each direction. Clipping to the viewport in theory
1165 * should work, but in practice causes issues when we're not
1166 * explicitly trying to scissor */
1168 .clip_minx
= -INFINITY
,
1169 .clip_miny
= -INFINITY
,
1170 .clip_maxx
= INFINITY
,
1171 .clip_maxy
= INFINITY
,
1174 /* Always scissor to the viewport by default. */
1175 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1176 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1178 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1179 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1181 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1182 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1184 /* Apply the scissor test */
1186 unsigned minx
, miny
, maxx
, maxy
;
1188 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1189 minx
= MAX2(ss
->minx
, vp_minx
);
1190 miny
= MAX2(ss
->miny
, vp_miny
);
1191 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1192 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1200 /* Hardware needs the min/max to be strictly ordered, so flip if we
1201 * need to. The viewport transformation in the vertex shader will
1202 * handle the negatives if we don't */
1205 unsigned temp
= miny
;
1211 unsigned temp
= minx
;
1222 /* Clamp to the framebuffer size as a last check */
1224 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1225 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1227 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1228 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1230 /* Update the job, unless we're doing wallpapering (whose lack of
1231 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1232 * just... be faster :) */
1234 if (!ctx
->wallpaper_batch
)
1235 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1239 view
.viewport0
[0] = minx
;
1240 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1242 view
.viewport0
[1] = miny
;
1243 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1245 view
.clip_minz
= minz
;
1246 view
.clip_maxz
= maxz
;
1248 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1249 panfrost_upload_transient(batch
,
1251 sizeof(struct mali_viewport
));
1256 /* Corresponds to exactly one draw, but does not submit anything */
1259 panfrost_queue_draw(struct panfrost_context
*ctx
)
1261 /* Handle dirty flags now */
1262 panfrost_emit_for_draw(ctx
, true);
1264 /* If rasterizer discard is enable, only submit the vertex */
1266 bool rasterizer_discard
= ctx
->rasterizer
1267 && ctx
->rasterizer
->base
.rasterizer_discard
;
1269 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1270 struct panfrost_transfer tiler
;
1272 if (!rasterizer_discard
)
1273 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1275 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1277 if (rasterizer_discard
)
1278 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1279 else if (ctx
->wallpaper_batch
&& batch
->first_tiler
.gpu
)
1280 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1282 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1284 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1285 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1290 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1291 batch
->stack_size
= MAX2(batch
->stack_size
, ss
->stack_size
);
1295 /* The entire frame is in memory -- send it off to the kernel! */
1299 struct pipe_context
*pipe
,
1300 struct pipe_fence_handle
**fence
,
1303 struct panfrost_context
*ctx
= pan_context(pipe
);
1304 struct util_dynarray fences
;
1306 /* We must collect the fences before the flush is done, otherwise we'll
1307 * lose track of them.
1310 util_dynarray_init(&fences
, NULL
);
1311 hash_table_foreach(ctx
->batches
, hentry
) {
1312 struct panfrost_batch
*batch
= hentry
->data
;
1314 panfrost_batch_fence_reference(batch
->out_sync
);
1315 util_dynarray_append(&fences
,
1316 struct panfrost_batch_fence
*,
1321 /* Submit all pending jobs */
1322 panfrost_flush_all_batches(ctx
, false);
1325 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1326 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1327 *fence
= (struct pipe_fence_handle
*)f
;
1329 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1330 panfrost_batch_fence_unreference(*fence
);
1332 util_dynarray_fini(&fences
);
1336 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1339 g2m_draw_mode(enum pipe_prim_type mode
)
1342 DEFINE_CASE(POINTS
);
1344 DEFINE_CASE(LINE_LOOP
);
1345 DEFINE_CASE(LINE_STRIP
);
1346 DEFINE_CASE(TRIANGLES
);
1347 DEFINE_CASE(TRIANGLE_STRIP
);
1348 DEFINE_CASE(TRIANGLE_FAN
);
1350 DEFINE_CASE(QUAD_STRIP
);
1351 DEFINE_CASE(POLYGON
);
1354 unreachable("Invalid draw mode");
1361 panfrost_translate_index_size(unsigned size
)
1365 return MALI_DRAW_INDEXED_UINT8
;
1368 return MALI_DRAW_INDEXED_UINT16
;
1371 return MALI_DRAW_INDEXED_UINT32
;
1374 unreachable("Invalid index size");
1378 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1379 * good for the duration of the draw (transient), could last longer */
1382 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1384 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1386 off_t offset
= info
->start
* info
->index_size
;
1387 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1389 if (!info
->has_user_indices
) {
1390 /* Only resources can be directly mapped */
1391 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1392 PAN_BO_ACCESS_SHARED
|
1393 PAN_BO_ACCESS_READ
|
1394 PAN_BO_ACCESS_VERTEX_TILER
);
1395 return rsrc
->bo
->gpu
+ offset
;
1397 /* Otherwise, we need to upload to transient memory */
1398 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1399 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1404 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1406 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1408 /* Check if we're scissoring at all */
1410 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1413 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1416 /* Count generated primitives (when there is no geom/tess shaders) for
1417 * transform feedback */
1420 panfrost_statistics_record(
1421 struct panfrost_context
*ctx
,
1422 const struct pipe_draw_info
*info
)
1424 if (!ctx
->active_queries
)
1427 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1428 ctx
->prims_generated
+= prims
;
1430 if (!ctx
->streamout
.num_targets
)
1433 ctx
->tf_prims_generated
+= prims
;
1438 struct pipe_context
*pipe
,
1439 const struct pipe_draw_info
*info
)
1441 struct panfrost_context
*ctx
= pan_context(pipe
);
1443 /* First of all, check the scissor to see if anything is drawn at all.
1444 * If it's not, we drop the draw (mostly a conformance issue;
1445 * well-behaved apps shouldn't hit this) */
1447 if (panfrost_scissor_culls_everything(ctx
))
1450 int mode
= info
->mode
;
1452 /* Fallback unsupported restart index */
1453 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1455 if (info
->primitive_restart
&& info
->index_size
1456 && info
->restart_index
!= primitive_index
) {
1457 util_draw_vbo_without_prim_restart(pipe
, info
);
1461 /* Fallback for unsupported modes */
1463 assert(ctx
->rasterizer
!= NULL
);
1465 if (!(ctx
->draw_modes
& (1 << mode
))) {
1466 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1467 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1469 if (info
->count
< 4) {
1470 /* Degenerate case? */
1474 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1475 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1480 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1481 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1483 /* Now that we have a guaranteed terminating path, find the job.
1484 * Assignment commented out to prevent unused warning */
1486 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1488 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1490 /* Take into account a negative bias */
1491 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1492 ctx
->instance_count
= info
->instance_count
;
1493 ctx
->active_prim
= info
->mode
;
1495 /* For non-indexed draws, they're the same */
1496 unsigned vertex_count
= ctx
->vertex_count
;
1498 unsigned draw_flags
= 0;
1500 /* The draw flags interpret how primitive size is interpreted */
1502 if (panfrost_writes_point_size(ctx
))
1503 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1505 if (info
->primitive_restart
)
1506 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1508 /* These doesn't make much sense */
1510 draw_flags
|= 0x3000;
1512 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1513 draw_flags
|= 0x800;
1516 panfrost_statistics_record(ctx
, info
);
1518 if (info
->index_size
) {
1519 /* Calculate the min/max index used so we can figure out how
1520 * many times to invoke the vertex shader */
1522 /* Fetch / calculate index bounds */
1523 unsigned min_index
= 0, max_index
= 0;
1525 if (info
->max_index
== ~0u) {
1526 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1528 min_index
= info
->min_index
;
1529 max_index
= info
->max_index
;
1532 /* Use the corresponding values */
1533 vertex_count
= max_index
- min_index
+ 1;
1534 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1535 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1537 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1538 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1540 //assert(!info->restart_index); /* TODO: Research */
1542 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1543 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1545 /* Index count == vertex count, if no indexing is applied, as
1546 * if it is internally indexed in the expected order */
1548 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1549 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1551 /* Reverse index state */
1552 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1555 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1556 * vertex_count, 1) */
1558 panfrost_pack_work_groups_fused(
1559 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1560 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1561 1, vertex_count
, info
->instance_count
,
1564 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1566 /* Encode the padded vertex count */
1568 if (info
->instance_count
> 1) {
1569 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1571 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1572 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1574 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1575 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1577 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1578 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1580 ctx
->padded_count
= vertex_count
;
1582 /* Reset instancing state */
1583 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1584 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1585 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1586 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1589 /* Fire off the draw itself */
1590 panfrost_queue_draw(ctx
);
1592 /* Increment transform feedback offsets */
1594 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1595 unsigned output_count
= u_stream_outputs_for_vertices(
1596 ctx
->active_prim
, ctx
->vertex_count
);
1598 ctx
->streamout
.offsets
[i
] += output_count
;
1605 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1611 panfrost_create_rasterizer_state(
1612 struct pipe_context
*pctx
,
1613 const struct pipe_rasterizer_state
*cso
)
1615 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1619 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1620 so
->tiler_gl_enables
= 0x7;
1623 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1625 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1626 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1628 if (cso
->cull_face
& PIPE_FACE_BACK
)
1629 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1635 panfrost_bind_rasterizer_state(
1636 struct pipe_context
*pctx
,
1639 struct panfrost_context
*ctx
= pan_context(pctx
);
1641 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1645 ctx
->rasterizer
= hwcso
;
1646 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1648 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1649 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1651 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1652 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1654 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1656 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1657 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1659 /* Point sprites are emulated */
1661 struct panfrost_shader_state
*variant
=
1662 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1664 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1665 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1669 panfrost_create_vertex_elements_state(
1670 struct pipe_context
*pctx
,
1671 unsigned num_elements
,
1672 const struct pipe_vertex_element
*elements
)
1674 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1676 so
->num_elements
= num_elements
;
1677 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1679 for (int i
= 0; i
< num_elements
; ++i
) {
1680 so
->hw
[i
].index
= i
;
1682 enum pipe_format fmt
= elements
[i
].src_format
;
1683 const struct util_format_description
*desc
= util_format_description(fmt
);
1684 so
->hw
[i
].unknown1
= 0x2;
1685 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1687 so
->hw
[i
].format
= panfrost_find_format(desc
);
1689 /* The field itself should probably be shifted over */
1690 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1697 panfrost_bind_vertex_elements_state(
1698 struct pipe_context
*pctx
,
1701 struct panfrost_context
*ctx
= pan_context(pctx
);
1703 ctx
->vertex
= hwcso
;
1704 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1708 panfrost_create_shader_state(
1709 struct pipe_context
*pctx
,
1710 const struct pipe_shader_state
*cso
,
1711 enum pipe_shader_type stage
)
1713 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1716 /* Token deep copy to prevent memory corruption */
1718 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1719 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1721 /* Precompile for shader-db if we need to */
1722 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1723 struct panfrost_context
*ctx
= pan_context(pctx
);
1725 struct mali_shader_meta meta
;
1726 struct panfrost_shader_state state
;
1727 uint64_t outputs_written
;
1729 panfrost_shader_compile(ctx
, &meta
,
1732 tgsi_processor_to_shader_stage(stage
), &state
,
1740 panfrost_delete_shader_state(
1741 struct pipe_context
*pctx
,
1744 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1746 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1747 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1750 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1751 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1752 panfrost_bo_unreference(shader_state
->bo
);
1753 shader_state
->bo
= NULL
;
1760 panfrost_create_sampler_state(
1761 struct pipe_context
*pctx
,
1762 const struct pipe_sampler_state
*cso
)
1764 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1767 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1769 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1770 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1771 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1773 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1774 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1775 unsigned mip_filter
= mip_linear
?
1776 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1777 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1779 struct mali_sampler_descriptor sampler_descriptor
= {
1780 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1781 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1782 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1783 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1784 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1786 cso
->border_color
.f
[0],
1787 cso
->border_color
.f
[1],
1788 cso
->border_color
.f
[2],
1789 cso
->border_color
.f
[3]
1791 .min_lod
= FIXED_16(cso
->min_lod
),
1792 .max_lod
= FIXED_16(cso
->max_lod
),
1793 .lod_bias
= FIXED_16(cso
->lod_bias
),
1794 .seamless_cube_map
= cso
->seamless_cube_map
,
1797 /* If necessary, we disable mipmapping in the sampler descriptor by
1798 * clamping the LOD as tight as possible (from 0 to epsilon,
1799 * essentially -- remember these are fixed point numbers, so
1802 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1803 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1805 /* Enforce that there is something in the middle by adding epsilon*/
1807 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1808 sampler_descriptor
.max_lod
++;
1811 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1813 so
->hw
= sampler_descriptor
;
1819 panfrost_bind_sampler_states(
1820 struct pipe_context
*pctx
,
1821 enum pipe_shader_type shader
,
1822 unsigned start_slot
, unsigned num_sampler
,
1825 assert(start_slot
== 0);
1827 struct panfrost_context
*ctx
= pan_context(pctx
);
1829 /* XXX: Should upload, not just copy? */
1830 ctx
->sampler_count
[shader
] = num_sampler
;
1831 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1833 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1837 panfrost_variant_matches(
1838 struct panfrost_context
*ctx
,
1839 struct panfrost_shader_state
*variant
,
1840 enum pipe_shader_type type
)
1842 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1843 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1845 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1847 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1848 /* Make sure enable state is at least the same */
1849 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1853 /* Check that the contents of the test are the same */
1854 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1855 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1857 if (!(same_func
&& same_ref
)) {
1862 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1863 variant
->point_sprite_mask
)) {
1864 /* Ensure the same varyings are turned to point sprites */
1865 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1868 /* Ensure the orientation is correct */
1870 rasterizer
->sprite_coord_mode
==
1871 PIPE_SPRITE_COORD_UPPER_LEFT
;
1873 if (variant
->point_sprite_upper_left
!= upper_left
)
1877 /* Otherwise, we're good to go */
1882 * Fix an uncompiled shader's stream output info, and produce a bitmask
1883 * of which VARYING_SLOT_* are captured for stream output.
1885 * Core Gallium stores output->register_index as a "slot" number, where
1886 * slots are assigned consecutively to all outputs in info->outputs_written.
1887 * This naive packing of outputs doesn't work for us - we too have slots,
1888 * but the layout is defined by the VUE map, which we won't have until we
1889 * compile a specific shader variant. So, we remap these and simply store
1890 * VARYING_SLOT_* in our copy's output->register_index fields.
1892 * We then produce a bitmask of outputs which are used for SO.
1894 * Implementation from iris.
1898 update_so_info(struct pipe_stream_output_info
*so_info
,
1899 uint64_t outputs_written
)
1901 uint64_t so_outputs
= 0;
1902 uint8_t reverse_map
[64] = {0};
1905 while (outputs_written
)
1906 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1908 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1909 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1911 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1912 output
->register_index
= reverse_map
[output
->register_index
];
1914 so_outputs
|= 1ull << output
->register_index
;
1921 panfrost_bind_shader_state(
1922 struct pipe_context
*pctx
,
1924 enum pipe_shader_type type
)
1926 struct panfrost_context
*ctx
= pan_context(pctx
);
1928 ctx
->shader
[type
] = hwcso
;
1930 if (type
== PIPE_SHADER_FRAGMENT
)
1931 ctx
->dirty
|= PAN_DIRTY_FS
;
1933 ctx
->dirty
|= PAN_DIRTY_VS
;
1937 /* Match the appropriate variant */
1939 signed variant
= -1;
1940 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1942 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1943 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1949 if (variant
== -1) {
1950 /* No variant matched, so create a new one */
1951 variant
= variants
->variant_count
++;
1952 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1954 struct panfrost_shader_state
*v
=
1955 &variants
->variants
[variant
];
1957 if (type
== PIPE_SHADER_FRAGMENT
) {
1958 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1960 if (ctx
->rasterizer
) {
1961 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1962 v
->point_sprite_upper_left
=
1963 ctx
->rasterizer
->base
.sprite_coord_mode
==
1964 PIPE_SPRITE_COORD_UPPER_LEFT
;
1968 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1972 /* Select this variant */
1973 variants
->active_variant
= variant
;
1975 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1976 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1978 /* We finally have a variant, so compile it */
1980 if (!shader_state
->compiled
) {
1981 uint64_t outputs_written
= 0;
1983 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1984 variants
->base
.type
,
1985 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1986 variants
->base
.ir
.nir
:
1987 variants
->base
.tokens
,
1988 tgsi_processor_to_shader_stage(type
), shader_state
,
1991 shader_state
->compiled
= true;
1993 /* Fixup the stream out information, since what Gallium returns
1994 * normally is mildly insane */
1996 shader_state
->stream_output
= variants
->base
.stream_output
;
1997 shader_state
->so_mask
=
1998 update_so_info(&shader_state
->stream_output
, outputs_written
);
2003 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
2005 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2009 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
2011 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2015 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2017 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2021 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2023 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2027 panfrost_set_vertex_buffers(
2028 struct pipe_context
*pctx
,
2029 unsigned start_slot
,
2030 unsigned num_buffers
,
2031 const struct pipe_vertex_buffer
*buffers
)
2033 struct panfrost_context
*ctx
= pan_context(pctx
);
2035 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2039 panfrost_set_constant_buffer(
2040 struct pipe_context
*pctx
,
2041 enum pipe_shader_type shader
, uint index
,
2042 const struct pipe_constant_buffer
*buf
)
2044 struct panfrost_context
*ctx
= pan_context(pctx
);
2045 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2047 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2049 unsigned mask
= (1 << index
);
2051 if (unlikely(!buf
)) {
2052 pbuf
->enabled_mask
&= ~mask
;
2053 pbuf
->dirty_mask
&= ~mask
;
2057 pbuf
->enabled_mask
|= mask
;
2058 pbuf
->dirty_mask
|= mask
;
2062 panfrost_set_stencil_ref(
2063 struct pipe_context
*pctx
,
2064 const struct pipe_stencil_ref
*ref
)
2066 struct panfrost_context
*ctx
= pan_context(pctx
);
2067 ctx
->stencil_ref
= *ref
;
2069 /* Shader core dirty */
2070 ctx
->dirty
|= PAN_DIRTY_FS
;
2073 static enum mali_texture_type
2074 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2078 case PIPE_TEXTURE_1D
:
2079 case PIPE_TEXTURE_1D_ARRAY
:
2082 case PIPE_TEXTURE_2D
:
2083 case PIPE_TEXTURE_2D_ARRAY
:
2084 case PIPE_TEXTURE_RECT
:
2087 case PIPE_TEXTURE_3D
:
2090 case PIPE_TEXTURE_CUBE
:
2091 case PIPE_TEXTURE_CUBE_ARRAY
:
2092 return MALI_TEX_CUBE
;
2095 unreachable("Unknown target");
2099 static struct pipe_sampler_view
*
2100 panfrost_create_sampler_view(
2101 struct pipe_context
*pctx
,
2102 struct pipe_resource
*texture
,
2103 const struct pipe_sampler_view
*template)
2105 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2106 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2108 pipe_reference(NULL
, &texture
->reference
);
2110 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2113 so
->base
= *template;
2114 so
->base
.texture
= texture
;
2115 so
->base
.reference
.count
= 1;
2116 so
->base
.context
= pctx
;
2118 /* sampler_views correspond to texture descriptors, minus the texture
2119 * (data) itself. So, we serialise the descriptor here and cache it for
2122 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2124 unsigned char user_swizzle
[4] = {
2125 template->swizzle_r
,
2126 template->swizzle_g
,
2127 template->swizzle_b
,
2131 enum mali_format format
= panfrost_find_format(desc
);
2133 /* Check if we need to set a custom stride by computing the "expected"
2134 * stride and comparing it to what the BO actually wants. Only applies
2135 * to linear textures, since tiled/compressed textures have strict
2136 * alignment requirements for their strides as it is */
2138 unsigned first_level
= template->u
.tex
.first_level
;
2139 unsigned last_level
= template->u
.tex
.last_level
;
2141 if (prsrc
->layout
== PAN_LINEAR
) {
2142 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2143 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2144 unsigned width
= u_minify(texture
->width0
, l
);
2145 unsigned comp_stride
= width
* bytes_per_pixel
;
2147 if (comp_stride
!= actual_stride
) {
2148 so
->manual_stride
= true;
2154 /* In the hardware, array_size refers specifically to array textures,
2155 * whereas in Gallium, it also covers cubemaps */
2157 unsigned array_size
= texture
->array_size
;
2159 if (template->target
== PIPE_TEXTURE_CUBE
) {
2160 /* TODO: Cubemap arrays */
2161 assert(array_size
== 6);
2165 struct mali_texture_descriptor texture_descriptor
= {
2166 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2167 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2168 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2169 .array_size
= MALI_POSITIVE(array_size
),
2172 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2174 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2175 .type
= panfrost_translate_texture_type(template->target
),
2179 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2182 texture_descriptor
.levels
= last_level
- first_level
;
2184 so
->hw
= texture_descriptor
;
2186 return (struct pipe_sampler_view
*) so
;
2190 panfrost_set_sampler_views(
2191 struct pipe_context
*pctx
,
2192 enum pipe_shader_type shader
,
2193 unsigned start_slot
, unsigned num_views
,
2194 struct pipe_sampler_view
**views
)
2196 struct panfrost_context
*ctx
= pan_context(pctx
);
2197 unsigned new_nr
= 0;
2200 assert(start_slot
== 0);
2202 for (i
= 0; i
< num_views
; ++i
) {
2205 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2209 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
2210 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2213 ctx
->sampler_view_count
[shader
] = new_nr
;
2215 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2219 panfrost_sampler_view_destroy(
2220 struct pipe_context
*pctx
,
2221 struct pipe_sampler_view
*view
)
2223 pipe_resource_reference(&view
->texture
, NULL
);
2228 panfrost_set_shader_buffers(
2229 struct pipe_context
*pctx
,
2230 enum pipe_shader_type shader
,
2231 unsigned start
, unsigned count
,
2232 const struct pipe_shader_buffer
*buffers
,
2233 unsigned writable_bitmask
)
2235 struct panfrost_context
*ctx
= pan_context(pctx
);
2237 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2238 buffers
, start
, count
);
2241 /* Hints that a framebuffer should use AFBC where possible */
2245 struct panfrost_screen
*screen
,
2246 const struct pipe_framebuffer_state
*fb
)
2248 /* AFBC implemenation incomplete; hide it */
2249 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2251 /* Hint AFBC to the resources bound to each color buffer */
2253 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2254 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2255 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2256 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2259 /* Also hint it to the depth buffer */
2262 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2263 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2268 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2269 const struct pipe_framebuffer_state
*fb
)
2271 struct panfrost_context
*ctx
= pan_context(pctx
);
2273 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2274 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2276 panfrost_invalidate_frame(ctx
);
2280 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2281 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2283 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2287 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2290 struct panfrost_context
*ctx
= pan_context(pipe
);
2291 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2292 ctx
->depth_stencil
= depth_stencil
;
2297 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2298 * emulated in the fragment shader */
2300 if (depth_stencil
->alpha
.enabled
) {
2301 /* We need to trigger a new shader (maybe) */
2302 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2306 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2308 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2309 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2311 /* If back-stencil is not enabled, use the front values */
2312 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2313 unsigned back_index
= back_enab
? 1 : 0;
2315 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2316 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2318 /* Depth state (TODO: Refactor) */
2319 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2320 depth_stencil
->depth
.writemask
);
2322 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2324 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2325 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2327 /* Bounds test not implemented */
2328 assert(!depth_stencil
->depth
.bounds_test
);
2330 ctx
->dirty
|= PAN_DIRTY_FS
;
2334 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2340 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2341 unsigned sample_mask
)
2346 panfrost_set_clip_state(struct pipe_context
*pipe
,
2347 const struct pipe_clip_state
*clip
)
2349 //struct panfrost_context *panfrost = pan_context(pipe);
2353 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2354 unsigned start_slot
,
2355 unsigned num_viewports
,
2356 const struct pipe_viewport_state
*viewports
)
2358 struct panfrost_context
*ctx
= pan_context(pipe
);
2360 assert(start_slot
== 0);
2361 assert(num_viewports
== 1);
2363 ctx
->pipe_viewport
= *viewports
;
2367 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2368 unsigned start_slot
,
2369 unsigned num_scissors
,
2370 const struct pipe_scissor_state
*scissors
)
2372 struct panfrost_context
*ctx
= pan_context(pipe
);
2374 assert(start_slot
== 0);
2375 assert(num_scissors
== 1);
2377 ctx
->scissor
= *scissors
;
2381 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2382 const struct pipe_poly_stipple
*stipple
)
2384 //struct panfrost_context *panfrost = pan_context(pipe);
2388 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2391 struct panfrost_context
*ctx
= pan_context(pipe
);
2392 ctx
->active_queries
= enable
;
2396 panfrost_destroy(struct pipe_context
*pipe
)
2398 struct panfrost_context
*panfrost
= pan_context(pipe
);
2400 if (panfrost
->blitter
)
2401 util_blitter_destroy(panfrost
->blitter
);
2403 if (panfrost
->blitter_wallpaper
)
2404 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2406 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
2407 u_upload_destroy(pipe
->stream_uploader
);
2412 static struct pipe_query
*
2413 panfrost_create_query(struct pipe_context
*pipe
,
2417 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2422 return (struct pipe_query
*) q
;
2426 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2428 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2431 panfrost_bo_unreference(query
->bo
);
2439 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2441 struct panfrost_context
*ctx
= pan_context(pipe
);
2442 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2444 switch (query
->type
) {
2445 case PIPE_QUERY_OCCLUSION_COUNTER
:
2446 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2447 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2448 /* Allocate a bo for the query results to be stored */
2450 query
->bo
= panfrost_bo_create(
2451 pan_screen(ctx
->base
.screen
),
2452 sizeof(unsigned), 0);
2455 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2456 *result
= 0; /* Default to 0 if nothing at all drawn. */
2457 ctx
->occlusion_query
= query
;
2460 /* Geometry statistics are computed in the driver. XXX: geom/tess
2463 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2464 query
->start
= ctx
->prims_generated
;
2466 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2467 query
->start
= ctx
->tf_prims_generated
;
2471 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2479 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2481 struct panfrost_context
*ctx
= pan_context(pipe
);
2482 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2484 switch (query
->type
) {
2485 case PIPE_QUERY_OCCLUSION_COUNTER
:
2486 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2487 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2488 ctx
->occlusion_query
= NULL
;
2490 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2491 query
->end
= ctx
->prims_generated
;
2493 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2494 query
->end
= ctx
->tf_prims_generated
;
2502 panfrost_get_query_result(struct pipe_context
*pipe
,
2503 struct pipe_query
*q
,
2505 union pipe_query_result
*vresult
)
2507 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2508 struct panfrost_context
*ctx
= pan_context(pipe
);
2511 switch (query
->type
) {
2512 case PIPE_QUERY_OCCLUSION_COUNTER
:
2513 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2514 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2516 panfrost_flush_all_batches(ctx
, true);
2518 /* Read back the query results */
2519 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2520 unsigned passed
= *result
;
2522 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2523 vresult
->u64
= passed
;
2525 vresult
->b
= !!passed
;
2530 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2531 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2532 panfrost_flush_all_batches(ctx
, true);
2533 vresult
->u64
= query
->end
- query
->start
;
2537 DBG("Skipped query get %u\n", query
->type
);
2544 static struct pipe_stream_output_target
*
2545 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2546 struct pipe_resource
*prsc
,
2547 unsigned buffer_offset
,
2548 unsigned buffer_size
)
2550 struct pipe_stream_output_target
*target
;
2552 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2557 pipe_reference_init(&target
->reference
, 1);
2558 pipe_resource_reference(&target
->buffer
, prsc
);
2560 target
->context
= pctx
;
2561 target
->buffer_offset
= buffer_offset
;
2562 target
->buffer_size
= buffer_size
;
2568 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2569 struct pipe_stream_output_target
*target
)
2571 pipe_resource_reference(&target
->buffer
, NULL
);
2572 ralloc_free(target
);
2576 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2577 unsigned num_targets
,
2578 struct pipe_stream_output_target
**targets
,
2579 const unsigned *offsets
)
2581 struct panfrost_context
*ctx
= pan_context(pctx
);
2582 struct panfrost_streamout
*so
= &ctx
->streamout
;
2584 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2586 for (unsigned i
= 0; i
< num_targets
; i
++) {
2587 if (offsets
[i
] != -1)
2588 so
->offsets
[i
] = offsets
[i
];
2590 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2593 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2594 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2596 so
->num_targets
= num_targets
;
2599 struct pipe_context
*
2600 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2602 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2603 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2605 gallium
->screen
= screen
;
2607 gallium
->destroy
= panfrost_destroy
;
2609 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2611 gallium
->flush
= panfrost_flush
;
2612 gallium
->clear
= panfrost_clear
;
2613 gallium
->draw_vbo
= panfrost_draw_vbo
;
2615 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2616 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2617 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2619 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2621 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2622 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2623 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2625 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2626 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2627 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2629 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2630 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2631 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2633 gallium
->create_fs_state
= panfrost_create_fs_state
;
2634 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2635 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2637 gallium
->create_vs_state
= panfrost_create_vs_state
;
2638 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2639 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2641 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2642 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2643 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2645 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2646 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2647 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2649 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2651 gallium
->set_clip_state
= panfrost_set_clip_state
;
2652 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2653 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2654 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2655 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2657 gallium
->create_query
= panfrost_create_query
;
2658 gallium
->destroy_query
= panfrost_destroy_query
;
2659 gallium
->begin_query
= panfrost_begin_query
;
2660 gallium
->end_query
= panfrost_end_query
;
2661 gallium
->get_query_result
= panfrost_get_query_result
;
2663 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2664 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2665 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2667 panfrost_resource_context_init(gallium
);
2668 panfrost_blend_context_init(gallium
);
2669 panfrost_compute_context_init(gallium
);
2672 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2673 gallium
->const_uploader
= gallium
->stream_uploader
;
2674 assert(gallium
->stream_uploader
);
2676 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2677 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2679 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2681 ctx
->blitter
= util_blitter_create(gallium
);
2682 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2684 assert(ctx
->blitter
);
2685 assert(ctx
->blitter_wallpaper
);
2687 /* Prepare for render! */
2689 panfrost_batch_init(ctx
);
2690 panfrost_emit_vertex_payload(ctx
);
2691 panfrost_emit_tiler_payload(ctx
);
2692 panfrost_invalidate_frame(ctx
);
2693 panfrost_default_shader_backend(ctx
);