2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
34 #include "util/macros.h"
35 #include "util/u_format.h"
36 #include "util/u_inlines.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_memory.h"
39 #include "util/u_vbuf.h"
40 #include "util/half_float.h"
41 #include "util/u_helpers.h"
42 #include "util/u_format.h"
43 #include "util/u_prim.h"
44 #include "util/u_prim_restart.h"
45 #include "indices/u_primconvert.h"
46 #include "tgsi/tgsi_parse.h"
47 #include "tgsi/tgsi_from_mesa.h"
48 #include "util/u_math.h"
50 #include "pan_screen.h"
51 #include "pan_blending.h"
52 #include "pan_blend_shaders.h"
55 /* Framebuffer descriptor */
57 static struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct midgard_tiler_descriptor t
= {};
61 unsigned height
= batch
->key
.height
;
62 unsigned width
= batch
->key
.width
;
65 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
67 /* Compute the polygon header size and use that to offset the body */
69 unsigned header_size
= panfrost_tiler_header_size(
70 width
, height
, t
.hierarchy_mask
);
72 t
.polygon_list_size
= panfrost_tiler_full_size(
73 width
, height
, t
.hierarchy_mask
);
77 if (t
.hierarchy_mask
) {
78 struct panfrost_bo
*tiler_heap
;
80 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
81 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
86 /* Allow the entire tiler heap */
87 t
.heap_start
= tiler_heap
->gpu
;
88 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
90 struct panfrost_bo
*tiler_dummy
;
92 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
94 /* The tiler is disabled, so don't allow the tiler heap */
95 t
.heap_start
= tiler_dummy
->gpu
;
96 t
.heap_end
= t
.heap_start
;
98 /* Use a dummy polygon list */
99 t
.polygon_list
= tiler_dummy
->gpu
;
101 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
105 t
.polygon_list_body
=
106 t
.polygon_list
+ header_size
;
111 struct mali_single_framebuffer
112 panfrost_emit_sfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
114 unsigned width
= batch
->key
.width
;
115 unsigned height
= batch
->key
.height
;
117 struct mali_single_framebuffer framebuffer
= {
118 .width
= MALI_POSITIVE(width
),
119 .height
= MALI_POSITIVE(height
),
121 .format
= 0x30000000,
122 .clear_flags
= 0x1000,
123 .unknown_address_0
= panfrost_batch_get_scratchpad(batch
)->gpu
,
124 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
),
130 struct bifrost_framebuffer
131 panfrost_emit_mfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
133 unsigned width
= batch
->key
.width
;
134 unsigned height
= batch
->key
.height
;
136 struct bifrost_framebuffer framebuffer
= {
137 .unk0
= 0x1e5, /* 1e4 if no spill */
138 .width1
= MALI_POSITIVE(width
),
139 .height1
= MALI_POSITIVE(height
),
140 .width2
= MALI_POSITIVE(width
),
141 .height2
= MALI_POSITIVE(height
),
145 .rt_count_1
= MALI_POSITIVE(batch
->key
.nr_cbufs
),
150 .scratchpad
= panfrost_batch_get_scratchpad(batch
)->gpu
,
151 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
)
159 struct pipe_context
*pipe
,
161 const union pipe_color_union
*color
,
162 double depth
, unsigned stencil
)
164 struct panfrost_context
*ctx
= pan_context(pipe
);
165 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
167 panfrost_batch_add_fbo_bos(batch
);
168 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
172 panfrost_attach_vt_mfbd(struct panfrost_batch
*batch
)
174 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(batch
, ~0);
176 return panfrost_upload_transient(batch
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
180 panfrost_attach_vt_sfbd(struct panfrost_batch
*batch
)
182 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(batch
, ~0);
184 return panfrost_upload_transient(batch
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
188 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
190 /* Skip the attach if we can */
192 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
193 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
197 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
198 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
200 if (!batch
->framebuffer
)
201 batch
->framebuffer
= screen
->require_sfbd
?
202 panfrost_attach_vt_sfbd(batch
) :
203 panfrost_attach_vt_mfbd(batch
);
205 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
206 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
;
209 /* Reset per-frame context, called on context initialisation as well as after
210 * flushing a frame */
213 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
215 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
216 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
219 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
222 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
224 /* TODO: When does this need to be handled? */
225 ctx
->active_queries
= true;
228 /* In practice, every field of these payloads should be configurable
229 * arbitrarily, which means these functions are basically catch-all's for
230 * as-of-yet unwavering unknowns */
233 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
235 /* 0x2 bit clear on 32-bit T6XX */
237 struct midgard_payload_vertex_tiler payload
= {
238 .gl_enables
= 0x4 | 0x2,
241 /* Vertex and compute are closely coupled, so share a payload */
243 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
244 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
248 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
250 struct midgard_payload_vertex_tiler payload
= {
252 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
256 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
260 translate_tex_wrap(enum pipe_tex_wrap w
)
263 case PIPE_TEX_WRAP_REPEAT
:
264 return MALI_WRAP_REPEAT
;
266 /* TODO: lower GL_CLAMP? */
267 case PIPE_TEX_WRAP_CLAMP
:
268 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
269 return MALI_WRAP_CLAMP_TO_EDGE
;
271 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
272 return MALI_WRAP_CLAMP_TO_BORDER
;
274 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
275 return MALI_WRAP_MIRRORED_REPEAT
;
278 unreachable("Invalid wrap");
283 panfrost_translate_compare_func(enum pipe_compare_func in
)
286 case PIPE_FUNC_NEVER
:
287 return MALI_FUNC_NEVER
;
290 return MALI_FUNC_LESS
;
292 case PIPE_FUNC_EQUAL
:
293 return MALI_FUNC_EQUAL
;
295 case PIPE_FUNC_LEQUAL
:
296 return MALI_FUNC_LEQUAL
;
298 case PIPE_FUNC_GREATER
:
299 return MALI_FUNC_GREATER
;
301 case PIPE_FUNC_NOTEQUAL
:
302 return MALI_FUNC_NOTEQUAL
;
304 case PIPE_FUNC_GEQUAL
:
305 return MALI_FUNC_GEQUAL
;
307 case PIPE_FUNC_ALWAYS
:
308 return MALI_FUNC_ALWAYS
;
311 unreachable("Invalid func");
316 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
319 case PIPE_FUNC_NEVER
:
320 return MALI_ALT_FUNC_NEVER
;
323 return MALI_ALT_FUNC_LESS
;
325 case PIPE_FUNC_EQUAL
:
326 return MALI_ALT_FUNC_EQUAL
;
328 case PIPE_FUNC_LEQUAL
:
329 return MALI_ALT_FUNC_LEQUAL
;
331 case PIPE_FUNC_GREATER
:
332 return MALI_ALT_FUNC_GREATER
;
334 case PIPE_FUNC_NOTEQUAL
:
335 return MALI_ALT_FUNC_NOTEQUAL
;
337 case PIPE_FUNC_GEQUAL
:
338 return MALI_ALT_FUNC_GEQUAL
;
340 case PIPE_FUNC_ALWAYS
:
341 return MALI_ALT_FUNC_ALWAYS
;
344 unreachable("Invalid alt func");
349 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
352 case PIPE_STENCIL_OP_KEEP
:
353 return MALI_STENCIL_KEEP
;
355 case PIPE_STENCIL_OP_ZERO
:
356 return MALI_STENCIL_ZERO
;
358 case PIPE_STENCIL_OP_REPLACE
:
359 return MALI_STENCIL_REPLACE
;
361 case PIPE_STENCIL_OP_INCR
:
362 return MALI_STENCIL_INCR
;
364 case PIPE_STENCIL_OP_DECR
:
365 return MALI_STENCIL_DECR
;
367 case PIPE_STENCIL_OP_INCR_WRAP
:
368 return MALI_STENCIL_INCR_WRAP
;
370 case PIPE_STENCIL_OP_DECR_WRAP
:
371 return MALI_STENCIL_DECR_WRAP
;
373 case PIPE_STENCIL_OP_INVERT
:
374 return MALI_STENCIL_INVERT
;
377 unreachable("Invalid stencil op");
382 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
384 out
->ref
= 0; /* Gallium gets it from elsewhere */
386 out
->mask
= in
->valuemask
;
387 out
->func
= panfrost_translate_compare_func(in
->func
);
388 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
389 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
390 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
394 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
396 struct mali_shader_meta shader
= {
397 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
399 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
400 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
403 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
404 * required (independent of 32-bit/64-bit descriptors), or why it's not
405 * used on later GPU revisions. Otherwise, all shader jobs fault on
406 * these earlier chips (perhaps this is a chicken bit of some kind).
407 * More investigation is needed. */
410 shader
.unknown2_4
|= 0x10;
413 struct pipe_stencil_state default_stencil
= {
415 .func
= PIPE_FUNC_ALWAYS
,
416 .fail_op
= MALI_STENCIL_KEEP
,
417 .zfail_op
= MALI_STENCIL_KEEP
,
418 .zpass_op
= MALI_STENCIL_KEEP
,
423 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
424 shader
.stencil_mask_front
= default_stencil
.writemask
;
426 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
427 shader
.stencil_mask_back
= default_stencil
.writemask
;
429 if (default_stencil
.enabled
)
430 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
432 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
435 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
436 * graphics command stream. It should be called once per draw, accordding to
437 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
438 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
441 struct panfrost_transfer
442 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
444 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
445 struct mali_job_descriptor_header job
= {
446 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
447 .job_descriptor_size
= 1,
450 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
452 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
453 memcpy(transfer
.cpu
, &job
, sizeof(job
));
454 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
459 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
461 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
462 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
464 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
468 panfrost_writes_point_size(struct panfrost_context
*ctx
)
470 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
471 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
473 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
476 /* Stage the attribute descriptors so we can adjust src_offset
477 * to let BOs align nicely */
480 panfrost_stage_attributes(struct panfrost_context
*ctx
)
482 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
483 struct panfrost_vertex_state
*so
= ctx
->vertex
;
485 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
486 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
487 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
489 /* Copy as-is for the first pass */
490 memcpy(target
, so
->hw
, sz
);
492 /* Fixup offsets for the second pass. Recall that the hardware
493 * calculates attribute addresses as:
495 * addr = base + (stride * vtx) + src_offset;
497 * However, on Mali, base must be aligned to 64-bytes, so we
500 * base' = base & ~63 = base - (base & 63)
502 * To compensate when using base' (see emit_vertex_data), we have
503 * to adjust src_offset by the masked off piece:
505 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
506 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
507 * = base + (stride * vtx) + src_offset
513 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
515 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
516 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
517 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
518 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
520 /* Adjust by the masked off bits of the offset */
521 target
[i
].src_offset
+= (addr
& 63);
523 /* Also, somewhat obscurely per-instance data needs to be
524 * offset in response to a delayed start in an indexed draw */
526 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
527 target
[i
].src_offset
-= buf
->stride
* start
;
533 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
537 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
539 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
540 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
542 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
545 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
546 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
548 struct panfrost_transfer transfer
=
549 panfrost_allocate_transient(batch
, transfer_size
);
551 struct mali_sampler_descriptor
*desc
=
552 (struct mali_sampler_descriptor
*) transfer
.cpu
;
554 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
555 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
557 upload
= transfer
.gpu
;
560 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
564 static enum mali_texture_layout
565 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
567 /* TODO: other linear depth textures */
568 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
570 switch (rsrc
->layout
) {
572 return MALI_TEXTURE_AFBC
;
575 return MALI_TEXTURE_TILED
;
577 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
579 unreachable("Invalid texture layout");
585 struct panfrost_context
*ctx
,
586 enum pipe_shader_type st
,
587 struct panfrost_sampler_view
*view
)
592 struct pipe_sampler_view
*pview
= &view
->base
;
593 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
595 /* Do we interleave an explicit stride with every element? */
597 bool has_manual_stride
= view
->manual_stride
;
599 /* For easy access */
601 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
602 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
603 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
604 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
605 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
607 /* Lower-bit is set when sampling from colour AFBC */
608 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
609 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
610 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
612 /* Add the BO to the job so it's retained until the job is done. */
613 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
614 panfrost_batch_add_bo(batch
, rsrc
->bo
,
615 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
616 panfrost_bo_access_for_stage(st
));
618 /* Add the usage flags in, since they can change across the CSO
619 * lifetime due to layout switches */
621 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
622 view
->hw
.format
.manual_stride
= has_manual_stride
;
624 /* Inject the addresses in, interleaving mip levels, cube faces, and
625 * strides in that order */
629 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
630 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
632 view
->hw
.payload
[idx
++] =
633 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
635 if (has_manual_stride
) {
636 view
->hw
.payload
[idx
++] =
637 rsrc
->slices
[l
].stride
;
642 return panfrost_upload_transient(batch
, &view
->hw
,
643 sizeof(struct mali_texture_descriptor
));
647 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
649 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
651 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
652 mali_ptr trampoline
= 0;
654 if (ctx
->sampler_view_count
[t
]) {
655 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
657 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
659 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
661 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
664 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
668 struct sysval_uniform
{
677 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
678 struct sysval_uniform
*uniform
)
680 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
682 uniform
->f
[0] = vp
->scale
[0];
683 uniform
->f
[1] = vp
->scale
[1];
684 uniform
->f
[2] = vp
->scale
[2];
687 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
688 struct sysval_uniform
*uniform
)
690 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
692 uniform
->f
[0] = vp
->translate
[0];
693 uniform
->f
[1] = vp
->translate
[1];
694 uniform
->f
[2] = vp
->translate
[2];
697 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
698 enum pipe_shader_type st
,
699 unsigned int sysvalid
,
700 struct sysval_uniform
*uniform
)
702 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
703 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
704 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
705 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
708 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
711 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
712 tex
->u
.tex
.first_level
);
715 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
716 tex
->u
.tex
.first_level
);
719 uniform
->i
[dim
] = tex
->texture
->array_size
;
722 static void panfrost_upload_ssbo_sysval(
723 struct panfrost_context
*ctx
,
724 enum pipe_shader_type st
,
726 struct sysval_uniform
*uniform
)
728 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
729 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
731 /* Compute address */
732 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
733 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
735 panfrost_batch_add_bo(batch
, bo
,
736 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
737 panfrost_bo_access_for_stage(st
));
739 /* Upload address and size as sysval */
740 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
741 uniform
->u
[2] = sb
.buffer_size
;
744 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
745 struct sysval_uniform
*uniform
)
747 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
748 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
749 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
752 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
753 struct panfrost_shader_state
*ss
,
754 enum pipe_shader_type st
)
756 struct sysval_uniform
*uniforms
= (void *)buf
;
758 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
759 int sysval
= ss
->sysval
[i
];
761 switch (PAN_SYSVAL_TYPE(sysval
)) {
762 case PAN_SYSVAL_VIEWPORT_SCALE
:
763 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
765 case PAN_SYSVAL_VIEWPORT_OFFSET
:
766 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
768 case PAN_SYSVAL_TEXTURE_SIZE
:
769 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
772 case PAN_SYSVAL_SSBO
:
773 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
776 case PAN_SYSVAL_NUM_WORK_GROUPS
:
777 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
787 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
789 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
790 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
793 return rsrc
->bo
->cpu
;
794 else if (cb
->user_buffer
)
795 return cb
->user_buffer
;
797 unreachable("No constant buffer");
801 panfrost_map_constant_buffer_gpu(
802 struct panfrost_context
*ctx
,
803 enum pipe_shader_type st
,
804 struct panfrost_constant_buffer
*buf
,
807 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
808 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
809 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
812 panfrost_batch_add_bo(batch
, rsrc
->bo
,
813 PAN_BO_ACCESS_SHARED
|
815 panfrost_bo_access_for_stage(st
));
816 return rsrc
->bo
->gpu
;
817 } else if (cb
->user_buffer
) {
818 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
820 unreachable("No constant buffer");
824 /* Compute number of UBOs active (more specifically, compute the highest UBO
825 * number addressable -- if there are gaps, include them in the count anyway).
826 * We always include UBO #0 in the count, since we *need* uniforms enabled for
830 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
832 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
833 return 32 - __builtin_clz(mask
);
836 /* Fixes up a shader state with current state, returning a GPU address to the
840 panfrost_patch_shader_state(
841 struct panfrost_context
*ctx
,
842 struct panfrost_shader_state
*ss
,
843 enum pipe_shader_type stage
,
846 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
847 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
849 ss
->tripipe
->midgard1
.flags
= 0x220;
851 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
852 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
854 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
856 /* Add the shader BO to the batch. */
857 panfrost_batch_add_bo(batch
, ss
->bo
,
858 PAN_BO_ACCESS_PRIVATE
|
860 panfrost_bo_access_for_stage(stage
));
862 /* We can't reuse over frames; that's not safe. The descriptor must be
863 * transient uploaded */
866 return panfrost_upload_transient(batch
, ss
->tripipe
,
867 sizeof(struct mali_shader_meta
));
870 /* If we don't need an upload, don't bother */
876 panfrost_patch_shader_state_compute(
877 struct panfrost_context
*ctx
,
878 enum pipe_shader_type stage
,
881 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
884 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
888 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
890 ctx
->payloads
[stage
].postfix
._shader_upper
=
891 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
894 /* Go through dirty flags and actualise them in the cmdstream. */
897 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
899 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
900 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
902 panfrost_batch_add_fbo_bos(batch
);
903 panfrost_attach_vt_framebuffer(ctx
);
905 if (with_vertex_data
) {
906 panfrost_emit_vertex_data(batch
);
908 /* Varyings emitted for -all- geometry */
909 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
910 panfrost_emit_varying_descriptor(ctx
, total_count
);
913 bool msaa
= ctx
->rasterizer
->base
.multisample
;
915 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
916 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
918 /* TODO: Sample size */
919 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
920 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
923 panfrost_batch_set_requirements(batch
);
925 if (ctx
->occlusion_query
) {
926 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
927 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
930 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
931 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
933 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
934 /* Check if we need to link the gl_PointSize varying */
935 if (!panfrost_writes_point_size(ctx
)) {
936 /* If the size is constant, write it out. Otherwise,
937 * don't touch primitive_size (since we would clobber
938 * the pointer there) */
940 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
944 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
945 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
946 ctx
->dirty
|= PAN_DIRTY_FS
;
948 if (ctx
->dirty
& PAN_DIRTY_FS
) {
949 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
950 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
952 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
954 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
957 COPY(attribute_count
);
961 COPY(midgard1
.uniform_count
);
962 COPY(midgard1
.uniform_buffer_count
);
963 COPY(midgard1
.work_count
);
964 COPY(midgard1
.flags
);
965 COPY(midgard1
.unknown2
);
969 /* Get blending setup */
970 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
972 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
974 for (unsigned c
= 0; c
< rt_count
; ++c
)
975 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
977 /* If there is a blend shader, work registers are shared. XXX: opt */
979 for (unsigned c
= 0; c
< rt_count
; ++c
) {
980 if (blend
[c
].is_shader
)
981 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
984 /* Set late due to depending on render state */
985 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
987 /* Depending on whether it's legal to in the given shader, we
988 * try to enable early-z testing (or forward-pixel kill?) */
990 if (!variant
->can_discard
)
991 flags
|= MALI_EARLY_Z
;
993 /* Any time texturing is used, derivatives are implicitly
994 * calculated, so we need to enable helper invocations */
996 if (variant
->helper_invocations
)
997 flags
|= MALI_HELPER_INVOCATIONS
;
999 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
1001 /* Assign the stencil refs late */
1003 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
1004 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
1005 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
1007 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
1008 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
1010 /* CAN_DISCARD should be set if the fragment shader possibly
1011 * contains a 'discard' instruction. It is likely this is
1012 * related to optimizations related to forward-pixel kill, as
1013 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1014 * thing?" by Peter Harris
1017 if (variant
->can_discard
) {
1018 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1019 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1022 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1023 * *also* copied to the blend_meta appended (by convention),
1024 * but this is the field actually read by the hardware. (Or
1025 * maybe both are read...?) */
1027 if (blend
[0].is_shader
) {
1028 ctx
->fragment_shader_core
.blend
.shader
=
1029 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1031 ctx
->fragment_shader_core
.blend
.shader
= 0;
1034 if (screen
->require_sfbd
) {
1035 /* When only a single render target platform is used, the blend
1036 * information is inside the shader meta itself. We
1037 * additionally need to signal CAN_DISCARD for nontrivial blend
1038 * modes (so we're able to read back the destination buffer) */
1040 if (!blend
[0].is_shader
) {
1041 ctx
->fragment_shader_core
.blend
.equation
=
1042 *blend
[0].equation
.equation
;
1043 ctx
->fragment_shader_core
.blend
.constant
=
1044 blend
[0].equation
.constant
;
1047 if (!blend
[0].no_blending
) {
1048 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1052 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1053 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1054 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1056 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1058 if (!screen
->require_sfbd
) {
1059 /* Additional blend descriptor tacked on for jobs using MFBD */
1061 struct midgard_blend_rt rts
[4];
1063 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1064 unsigned blend_count
= 0x200;
1066 if (blend
[i
].is_shader
) {
1067 /* For a blend shader, the bottom nibble corresponds to
1068 * the number of work registers used, which signals the
1069 * -existence- of a blend shader */
1071 assert(blend
[i
].shader
.work_count
>= 2);
1072 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1074 /* Otherwise, the bottom bit simply specifies if
1075 * blending (anything other than REPLACE) is enabled */
1077 if (!blend
[i
].no_blending
)
1083 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1084 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1085 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1087 rts
[i
].flags
= blend_count
;
1090 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1092 if (!ctx
->blend
->base
.dither
)
1093 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1095 /* TODO: sRGB in blend shaders is currently
1096 * unimplemented. Contact me (Alyssa) if you're
1097 * interested in working on this. We have
1098 * native Midgard ops for helping here, but
1099 * they're not well-understood yet. */
1101 assert(!(is_srgb
&& blend
[i
].is_shader
));
1103 if (blend
[i
].is_shader
) {
1104 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1106 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1107 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1111 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1115 /* We stage to transient, so always dirty.. */
1117 panfrost_stage_attributes(ctx
);
1119 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1120 panfrost_upload_sampler_descriptors(ctx
);
1122 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1123 panfrost_upload_texture_descriptors(ctx
);
1125 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1127 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1128 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1133 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1135 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1137 /* Uniforms are implicitly UBO #0 */
1138 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1140 /* Allocate room for the sysval and the uniforms */
1141 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1142 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1143 size_t size
= sys_size
+ uniform_size
;
1144 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1146 /* Upload sysvals requested by the shader */
1147 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1149 /* Upload uniforms */
1151 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1152 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1156 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1158 struct mali_vertex_tiler_postfix
*postfix
=
1159 &ctx
->payloads
[i
].postfix
;
1161 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1164 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1165 assert(ubo_count
>= 1);
1167 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1168 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1170 /* Upload uniforms as a UBO */
1171 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1172 ubos
[0].ptr
= transfer
.gpu
>> 2;
1174 /* The rest are honest-to-goodness UBOs */
1176 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1177 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1179 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1180 bool empty
= usz
== 0;
1182 if (!enabled
|| empty
) {
1183 /* Stub out disabled UBOs to catch accesses */
1186 ubos
[ubo
].ptr
= 0xDEAD0000;
1190 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1192 unsigned bytes_per_field
= 16;
1193 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1194 unsigned fields
= aligned
/ bytes_per_field
;
1196 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1197 ubos
[ubo
].ptr
= gpu
>> 2;
1200 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1201 postfix
->uniforms
= transfer
.gpu
;
1202 postfix
->uniform_buffers
= ubufs
;
1204 buf
->dirty_mask
= 0;
1207 /* TODO: Upload the viewport somewhere more appropriate */
1209 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1210 * (somewhat) asymmetric ints. */
1211 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1213 struct mali_viewport view
= {
1214 /* By default, do no viewport clipping, i.e. clip to (-inf,
1215 * inf) in each direction. Clipping to the viewport in theory
1216 * should work, but in practice causes issues when we're not
1217 * explicitly trying to scissor */
1219 .clip_minx
= -INFINITY
,
1220 .clip_miny
= -INFINITY
,
1221 .clip_maxx
= INFINITY
,
1222 .clip_maxy
= INFINITY
,
1225 /* Always scissor to the viewport by default. */
1226 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1227 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1229 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1230 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1232 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1233 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1235 /* Apply the scissor test */
1237 unsigned minx
, miny
, maxx
, maxy
;
1239 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1240 minx
= MAX2(ss
->minx
, vp_minx
);
1241 miny
= MAX2(ss
->miny
, vp_miny
);
1242 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1243 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1251 /* Hardware needs the min/max to be strictly ordered, so flip if we
1252 * need to. The viewport transformation in the vertex shader will
1253 * handle the negatives if we don't */
1256 unsigned temp
= miny
;
1262 unsigned temp
= minx
;
1273 /* Clamp to the framebuffer size as a last check */
1275 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1276 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1278 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1279 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1281 /* Update the job, unless we're doing wallpapering (whose lack of
1282 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1283 * just... be faster :) */
1285 if (!ctx
->wallpaper_batch
)
1286 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1290 view
.viewport0
[0] = minx
;
1291 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1293 view
.viewport0
[1] = miny
;
1294 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1296 view
.clip_minz
= minz
;
1297 view
.clip_maxz
= maxz
;
1299 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1300 panfrost_upload_transient(batch
,
1302 sizeof(struct mali_viewport
));
1307 /* Corresponds to exactly one draw, but does not submit anything */
1310 panfrost_queue_draw(struct panfrost_context
*ctx
)
1312 /* Handle dirty flags now */
1313 panfrost_emit_for_draw(ctx
, true);
1315 /* If rasterizer discard is enable, only submit the vertex */
1317 bool rasterizer_discard
= ctx
->rasterizer
1318 && ctx
->rasterizer
->base
.rasterizer_discard
;
1320 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1321 struct panfrost_transfer tiler
;
1323 if (!rasterizer_discard
)
1324 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1326 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1328 if (rasterizer_discard
)
1329 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1330 else if (ctx
->wallpaper_batch
)
1331 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1333 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1336 /* The entire frame is in memory -- send it off to the kernel! */
1340 struct pipe_context
*pipe
,
1341 struct pipe_fence_handle
**fence
,
1344 struct panfrost_context
*ctx
= pan_context(pipe
);
1345 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1347 /* Submit the frame itself */
1348 panfrost_batch_submit(batch
);
1351 struct panfrost_fence
*f
= panfrost_fence_create(ctx
);
1352 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1353 *fence
= (struct pipe_fence_handle
*)f
;
1357 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1360 g2m_draw_mode(enum pipe_prim_type mode
)
1363 DEFINE_CASE(POINTS
);
1365 DEFINE_CASE(LINE_LOOP
);
1366 DEFINE_CASE(LINE_STRIP
);
1367 DEFINE_CASE(TRIANGLES
);
1368 DEFINE_CASE(TRIANGLE_STRIP
);
1369 DEFINE_CASE(TRIANGLE_FAN
);
1371 DEFINE_CASE(QUAD_STRIP
);
1372 DEFINE_CASE(POLYGON
);
1375 unreachable("Invalid draw mode");
1382 panfrost_translate_index_size(unsigned size
)
1386 return MALI_DRAW_INDEXED_UINT8
;
1389 return MALI_DRAW_INDEXED_UINT16
;
1392 return MALI_DRAW_INDEXED_UINT32
;
1395 unreachable("Invalid index size");
1399 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1400 * good for the duration of the draw (transient), could last longer */
1403 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1405 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1407 off_t offset
= info
->start
* info
->index_size
;
1408 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1410 if (!info
->has_user_indices
) {
1411 /* Only resources can be directly mapped */
1412 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1413 PAN_BO_ACCESS_SHARED
|
1414 PAN_BO_ACCESS_READ
|
1415 PAN_BO_ACCESS_VERTEX_TILER
);
1416 return rsrc
->bo
->gpu
+ offset
;
1418 /* Otherwise, we need to upload to transient memory */
1419 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1420 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1425 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1427 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1429 /* Check if we're scissoring at all */
1431 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1434 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1437 /* Count generated primitives (when there is no geom/tess shaders) for
1438 * transform feedback */
1441 panfrost_statistics_record(
1442 struct panfrost_context
*ctx
,
1443 const struct pipe_draw_info
*info
)
1445 if (!ctx
->active_queries
)
1448 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1449 ctx
->prims_generated
+= prims
;
1451 if (!ctx
->streamout
.num_targets
)
1454 ctx
->tf_prims_generated
+= prims
;
1459 struct pipe_context
*pipe
,
1460 const struct pipe_draw_info
*info
)
1462 struct panfrost_context
*ctx
= pan_context(pipe
);
1464 /* First of all, check the scissor to see if anything is drawn at all.
1465 * If it's not, we drop the draw (mostly a conformance issue;
1466 * well-behaved apps shouldn't hit this) */
1468 if (panfrost_scissor_culls_everything(ctx
))
1471 int mode
= info
->mode
;
1473 /* Fallback unsupported restart index */
1474 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1476 if (info
->primitive_restart
&& info
->index_size
1477 && info
->restart_index
!= primitive_index
) {
1478 util_draw_vbo_without_prim_restart(pipe
, info
);
1482 /* Fallback for unsupported modes */
1484 assert(ctx
->rasterizer
!= NULL
);
1486 if (!(ctx
->draw_modes
& (1 << mode
))) {
1487 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1488 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1490 if (info
->count
< 4) {
1491 /* Degenerate case? */
1495 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1496 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1501 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1502 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1504 /* Now that we have a guaranteed terminating path, find the job.
1505 * Assignment commented out to prevent unused warning */
1507 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1509 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1511 /* Take into account a negative bias */
1512 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1513 ctx
->instance_count
= info
->instance_count
;
1514 ctx
->active_prim
= info
->mode
;
1516 /* For non-indexed draws, they're the same */
1517 unsigned vertex_count
= ctx
->vertex_count
;
1519 unsigned draw_flags
= 0;
1521 /* The draw flags interpret how primitive size is interpreted */
1523 if (panfrost_writes_point_size(ctx
))
1524 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1526 if (info
->primitive_restart
)
1527 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1529 /* For higher amounts of vertices (greater than what fits in a 16-bit
1530 * short), the other value is needed, otherwise there will be bizarre
1531 * rendering artefacts. It's not clear what these values mean yet. This
1532 * change is also needed for instancing and sometimes points (perhaps
1533 * related to dynamically setting gl_PointSize) */
1535 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1536 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1537 bool instanced
= ctx
->instance_count
> 1;
1539 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1541 /* This doesn't make much sense */
1542 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1543 draw_flags
|= 0x800;
1546 panfrost_statistics_record(ctx
, info
);
1548 if (info
->index_size
) {
1549 /* Calculate the min/max index used so we can figure out how
1550 * many times to invoke the vertex shader */
1552 /* Fetch / calculate index bounds */
1553 unsigned min_index
= 0, max_index
= 0;
1555 if (info
->max_index
== ~0u) {
1556 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1558 min_index
= info
->min_index
;
1559 max_index
= info
->max_index
;
1562 /* Use the corresponding values */
1563 vertex_count
= max_index
- min_index
+ 1;
1564 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1565 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1567 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1568 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1570 //assert(!info->restart_index); /* TODO: Research */
1572 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1573 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1575 /* Index count == vertex count, if no indexing is applied, as
1576 * if it is internally indexed in the expected order */
1578 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1579 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1581 /* Reverse index state */
1582 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1585 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1586 * vertex_count, 1) */
1588 panfrost_pack_work_groups_fused(
1589 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1590 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1591 1, vertex_count
, info
->instance_count
,
1594 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1596 /* Encode the padded vertex count */
1598 if (info
->instance_count
> 1) {
1599 /* Triangles have non-even vertex counts so they change how
1600 * padding works internally */
1603 mode
== PIPE_PRIM_TRIANGLES
||
1604 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1605 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1607 struct pan_shift_odd so
=
1608 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1610 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1611 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1613 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1614 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1616 ctx
->padded_count
= pan_expand_shift_odd(so
);
1618 ctx
->padded_count
= vertex_count
;
1620 /* Reset instancing state */
1621 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1622 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1623 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1624 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1627 /* Fire off the draw itself */
1628 panfrost_queue_draw(ctx
);
1630 /* Increment transform feedback offsets */
1632 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1633 unsigned output_count
= u_stream_outputs_for_vertices(
1634 ctx
->active_prim
, ctx
->vertex_count
);
1636 ctx
->streamout
.offsets
[i
] += output_count
;
1643 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1649 panfrost_create_rasterizer_state(
1650 struct pipe_context
*pctx
,
1651 const struct pipe_rasterizer_state
*cso
)
1653 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1657 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1658 so
->tiler_gl_enables
= 0x7;
1661 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1663 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1664 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1666 if (cso
->cull_face
& PIPE_FACE_BACK
)
1667 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1673 panfrost_bind_rasterizer_state(
1674 struct pipe_context
*pctx
,
1677 struct panfrost_context
*ctx
= pan_context(pctx
);
1679 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1683 ctx
->rasterizer
= hwcso
;
1684 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1686 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1687 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1689 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1690 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1692 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1694 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1695 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1697 /* Point sprites are emulated */
1699 struct panfrost_shader_state
*variant
=
1700 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1702 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1703 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1707 panfrost_create_vertex_elements_state(
1708 struct pipe_context
*pctx
,
1709 unsigned num_elements
,
1710 const struct pipe_vertex_element
*elements
)
1712 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1714 so
->num_elements
= num_elements
;
1715 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1717 for (int i
= 0; i
< num_elements
; ++i
) {
1718 so
->hw
[i
].index
= i
;
1720 enum pipe_format fmt
= elements
[i
].src_format
;
1721 const struct util_format_description
*desc
= util_format_description(fmt
);
1722 so
->hw
[i
].unknown1
= 0x2;
1723 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1725 so
->hw
[i
].format
= panfrost_find_format(desc
);
1727 /* The field itself should probably be shifted over */
1728 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1735 panfrost_bind_vertex_elements_state(
1736 struct pipe_context
*pctx
,
1739 struct panfrost_context
*ctx
= pan_context(pctx
);
1741 ctx
->vertex
= hwcso
;
1742 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1746 panfrost_create_shader_state(
1747 struct pipe_context
*pctx
,
1748 const struct pipe_shader_state
*cso
)
1750 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1753 /* Token deep copy to prevent memory corruption */
1755 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1756 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1762 panfrost_delete_shader_state(
1763 struct pipe_context
*pctx
,
1766 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1768 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1769 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1772 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1773 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1774 panfrost_bo_unreference(shader_state
->bo
);
1775 shader_state
->bo
= NULL
;
1782 panfrost_create_sampler_state(
1783 struct pipe_context
*pctx
,
1784 const struct pipe_sampler_state
*cso
)
1786 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1789 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1791 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1792 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1793 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1795 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1796 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1797 unsigned mip_filter
= mip_linear
?
1798 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1799 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1801 struct mali_sampler_descriptor sampler_descriptor
= {
1802 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1803 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1804 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1805 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1806 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1808 cso
->border_color
.f
[0],
1809 cso
->border_color
.f
[1],
1810 cso
->border_color
.f
[2],
1811 cso
->border_color
.f
[3]
1813 .min_lod
= FIXED_16(cso
->min_lod
),
1814 .max_lod
= FIXED_16(cso
->max_lod
),
1815 .seamless_cube_map
= cso
->seamless_cube_map
,
1818 /* If necessary, we disable mipmapping in the sampler descriptor by
1819 * clamping the LOD as tight as possible (from 0 to epsilon,
1820 * essentially -- remember these are fixed point numbers, so
1823 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1824 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1826 /* Enforce that there is something in the middle by adding epsilon*/
1828 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1829 sampler_descriptor
.max_lod
++;
1832 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1834 so
->hw
= sampler_descriptor
;
1840 panfrost_bind_sampler_states(
1841 struct pipe_context
*pctx
,
1842 enum pipe_shader_type shader
,
1843 unsigned start_slot
, unsigned num_sampler
,
1846 assert(start_slot
== 0);
1848 struct panfrost_context
*ctx
= pan_context(pctx
);
1850 /* XXX: Should upload, not just copy? */
1851 ctx
->sampler_count
[shader
] = num_sampler
;
1852 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1854 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1858 panfrost_variant_matches(
1859 struct panfrost_context
*ctx
,
1860 struct panfrost_shader_state
*variant
,
1861 enum pipe_shader_type type
)
1863 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1864 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1866 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1868 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1869 /* Make sure enable state is at least the same */
1870 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1874 /* Check that the contents of the test are the same */
1875 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1876 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1878 if (!(same_func
&& same_ref
)) {
1883 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1884 variant
->point_sprite_mask
)) {
1885 /* Ensure the same varyings are turned to point sprites */
1886 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1889 /* Ensure the orientation is correct */
1891 rasterizer
->sprite_coord_mode
==
1892 PIPE_SPRITE_COORD_UPPER_LEFT
;
1894 if (variant
->point_sprite_upper_left
!= upper_left
)
1898 /* Otherwise, we're good to go */
1903 * Fix an uncompiled shader's stream output info, and produce a bitmask
1904 * of which VARYING_SLOT_* are captured for stream output.
1906 * Core Gallium stores output->register_index as a "slot" number, where
1907 * slots are assigned consecutively to all outputs in info->outputs_written.
1908 * This naive packing of outputs doesn't work for us - we too have slots,
1909 * but the layout is defined by the VUE map, which we won't have until we
1910 * compile a specific shader variant. So, we remap these and simply store
1911 * VARYING_SLOT_* in our copy's output->register_index fields.
1913 * We then produce a bitmask of outputs which are used for SO.
1915 * Implementation from iris.
1919 update_so_info(struct pipe_stream_output_info
*so_info
,
1920 uint64_t outputs_written
)
1922 uint64_t so_outputs
= 0;
1923 uint8_t reverse_map
[64] = {};
1926 while (outputs_written
)
1927 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1929 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1930 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1932 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1933 output
->register_index
= reverse_map
[output
->register_index
];
1935 so_outputs
|= 1ull << output
->register_index
;
1942 panfrost_bind_shader_state(
1943 struct pipe_context
*pctx
,
1945 enum pipe_shader_type type
)
1947 struct panfrost_context
*ctx
= pan_context(pctx
);
1949 ctx
->shader
[type
] = hwcso
;
1951 if (type
== PIPE_SHADER_FRAGMENT
)
1952 ctx
->dirty
|= PAN_DIRTY_FS
;
1954 ctx
->dirty
|= PAN_DIRTY_VS
;
1958 /* Match the appropriate variant */
1960 signed variant
= -1;
1961 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1963 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1964 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1970 if (variant
== -1) {
1971 /* No variant matched, so create a new one */
1972 variant
= variants
->variant_count
++;
1973 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1975 struct panfrost_shader_state
*v
=
1976 &variants
->variants
[variant
];
1978 if (type
== PIPE_SHADER_FRAGMENT
) {
1979 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1981 if (ctx
->rasterizer
) {
1982 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1983 v
->point_sprite_upper_left
=
1984 ctx
->rasterizer
->base
.sprite_coord_mode
==
1985 PIPE_SPRITE_COORD_UPPER_LEFT
;
1989 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1993 /* Select this variant */
1994 variants
->active_variant
= variant
;
1996 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1997 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1999 /* We finally have a variant, so compile it */
2001 if (!shader_state
->compiled
) {
2002 uint64_t outputs_written
= 0;
2004 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2005 variants
->base
.type
,
2006 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2007 variants
->base
.ir
.nir
:
2008 variants
->base
.tokens
,
2009 tgsi_processor_to_shader_stage(type
), shader_state
,
2012 shader_state
->compiled
= true;
2014 /* Fixup the stream out information, since what Gallium returns
2015 * normally is mildly insane */
2017 shader_state
->stream_output
= variants
->base
.stream_output
;
2018 shader_state
->so_mask
=
2019 update_so_info(&shader_state
->stream_output
, outputs_written
);
2024 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2026 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2030 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2032 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2036 panfrost_set_vertex_buffers(
2037 struct pipe_context
*pctx
,
2038 unsigned start_slot
,
2039 unsigned num_buffers
,
2040 const struct pipe_vertex_buffer
*buffers
)
2042 struct panfrost_context
*ctx
= pan_context(pctx
);
2044 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2048 panfrost_set_constant_buffer(
2049 struct pipe_context
*pctx
,
2050 enum pipe_shader_type shader
, uint index
,
2051 const struct pipe_constant_buffer
*buf
)
2053 struct panfrost_context
*ctx
= pan_context(pctx
);
2054 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2056 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2058 unsigned mask
= (1 << index
);
2060 if (unlikely(!buf
)) {
2061 pbuf
->enabled_mask
&= ~mask
;
2062 pbuf
->dirty_mask
&= ~mask
;
2066 pbuf
->enabled_mask
|= mask
;
2067 pbuf
->dirty_mask
|= mask
;
2071 panfrost_set_stencil_ref(
2072 struct pipe_context
*pctx
,
2073 const struct pipe_stencil_ref
*ref
)
2075 struct panfrost_context
*ctx
= pan_context(pctx
);
2076 ctx
->stencil_ref
= *ref
;
2078 /* Shader core dirty */
2079 ctx
->dirty
|= PAN_DIRTY_FS
;
2082 static enum mali_texture_type
2083 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2087 case PIPE_TEXTURE_1D
:
2088 case PIPE_TEXTURE_1D_ARRAY
:
2091 case PIPE_TEXTURE_2D
:
2092 case PIPE_TEXTURE_2D_ARRAY
:
2093 case PIPE_TEXTURE_RECT
:
2096 case PIPE_TEXTURE_3D
:
2099 case PIPE_TEXTURE_CUBE
:
2100 case PIPE_TEXTURE_CUBE_ARRAY
:
2101 return MALI_TEX_CUBE
;
2104 unreachable("Unknown target");
2108 static struct pipe_sampler_view
*
2109 panfrost_create_sampler_view(
2110 struct pipe_context
*pctx
,
2111 struct pipe_resource
*texture
,
2112 const struct pipe_sampler_view
*template)
2114 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2115 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2117 pipe_reference(NULL
, &texture
->reference
);
2119 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2122 so
->base
= *template;
2123 so
->base
.texture
= texture
;
2124 so
->base
.reference
.count
= 1;
2125 so
->base
.context
= pctx
;
2127 /* sampler_views correspond to texture descriptors, minus the texture
2128 * (data) itself. So, we serialise the descriptor here and cache it for
2131 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2133 unsigned char user_swizzle
[4] = {
2134 template->swizzle_r
,
2135 template->swizzle_g
,
2136 template->swizzle_b
,
2140 enum mali_format format
= panfrost_find_format(desc
);
2142 /* Check if we need to set a custom stride by computing the "expected"
2143 * stride and comparing it to what the BO actually wants. Only applies
2144 * to linear textures, since tiled/compressed textures have strict
2145 * alignment requirements for their strides as it is */
2147 unsigned first_level
= template->u
.tex
.first_level
;
2148 unsigned last_level
= template->u
.tex
.last_level
;
2150 if (prsrc
->layout
== PAN_LINEAR
) {
2151 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2152 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2153 unsigned width
= u_minify(texture
->width0
, l
);
2154 unsigned comp_stride
= width
* bytes_per_pixel
;
2156 if (comp_stride
!= actual_stride
) {
2157 so
->manual_stride
= true;
2163 /* In the hardware, array_size refers specifically to array textures,
2164 * whereas in Gallium, it also covers cubemaps */
2166 unsigned array_size
= texture
->array_size
;
2168 if (template->target
== PIPE_TEXTURE_CUBE
) {
2169 /* TODO: Cubemap arrays */
2170 assert(array_size
== 6);
2174 struct mali_texture_descriptor texture_descriptor
= {
2175 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2176 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2177 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2178 .array_size
= MALI_POSITIVE(array_size
),
2181 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2183 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2184 .type
= panfrost_translate_texture_type(template->target
),
2188 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2191 texture_descriptor
.levels
= last_level
- first_level
;
2193 so
->hw
= texture_descriptor
;
2195 return (struct pipe_sampler_view
*) so
;
2199 panfrost_set_sampler_views(
2200 struct pipe_context
*pctx
,
2201 enum pipe_shader_type shader
,
2202 unsigned start_slot
, unsigned num_views
,
2203 struct pipe_sampler_view
**views
)
2205 struct panfrost_context
*ctx
= pan_context(pctx
);
2207 assert(start_slot
== 0);
2209 unsigned new_nr
= 0;
2210 for (unsigned i
= 0; i
< num_views
; ++i
) {
2215 ctx
->sampler_view_count
[shader
] = new_nr
;
2216 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2218 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2222 panfrost_sampler_view_destroy(
2223 struct pipe_context
*pctx
,
2224 struct pipe_sampler_view
*view
)
2226 pipe_resource_reference(&view
->texture
, NULL
);
2231 panfrost_set_shader_buffers(
2232 struct pipe_context
*pctx
,
2233 enum pipe_shader_type shader
,
2234 unsigned start
, unsigned count
,
2235 const struct pipe_shader_buffer
*buffers
,
2236 unsigned writable_bitmask
)
2238 struct panfrost_context
*ctx
= pan_context(pctx
);
2240 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2241 buffers
, start
, count
);
2244 /* Hints that a framebuffer should use AFBC where possible */
2248 struct panfrost_screen
*screen
,
2249 const struct pipe_framebuffer_state
*fb
)
2251 /* AFBC implemenation incomplete; hide it */
2252 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2254 /* Hint AFBC to the resources bound to each color buffer */
2256 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2257 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2258 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2259 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2262 /* Also hint it to the depth buffer */
2265 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2266 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2271 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2272 const struct pipe_framebuffer_state
*fb
)
2274 struct panfrost_context
*ctx
= pan_context(pctx
);
2276 /* Flush when switching framebuffers, but not if the framebuffer
2277 * state is being restored by u_blitter
2280 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2281 bool is_scanout
= panfrost_batch_is_scanout(batch
);
2282 bool has_draws
= batch
->last_job
.gpu
;
2284 /* Bail out early when the current and new states are the same. */
2285 if (util_framebuffer_state_equal(&ctx
->pipe_framebuffer
, fb
))
2288 /* The wallpaper logic sets a new FB state before doing the blit and
2289 * restore the old one when it's done. Those FB states are reported to
2290 * be different because the surface they are pointing to are different,
2291 * but those surfaces actually point to the same cbufs/zbufs. In that
2292 * case we definitely don't want new FB descs to be emitted/attached
2293 * since the job is expected to be flushed just after the blit is done,
2294 * so let's just copy the new state and return here.
2296 if (ctx
->wallpaper_batch
) {
2297 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2301 if (!is_scanout
|| has_draws
)
2302 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2304 assert(!ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
&&
2305 !ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
2307 /* Invalidate the FBO job cache since we've just been assigned a new
2312 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2314 /* Given that we're rendering, we'd love to have compression */
2315 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2317 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2318 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
2319 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
2323 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2324 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2326 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2330 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2333 struct panfrost_context
*ctx
= pan_context(pipe
);
2334 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2335 ctx
->depth_stencil
= depth_stencil
;
2340 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2341 * emulated in the fragment shader */
2343 if (depth_stencil
->alpha
.enabled
) {
2344 /* We need to trigger a new shader (maybe) */
2345 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2349 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2351 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2352 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2354 /* If back-stencil is not enabled, use the front values */
2355 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2356 unsigned back_index
= back_enab
? 1 : 0;
2358 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2359 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2361 /* Depth state (TODO: Refactor) */
2362 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2364 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2366 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2367 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2369 /* Bounds test not implemented */
2370 assert(!depth_stencil
->depth
.bounds_test
);
2372 ctx
->dirty
|= PAN_DIRTY_FS
;
2376 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2382 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2383 unsigned sample_mask
)
2388 panfrost_set_clip_state(struct pipe_context
*pipe
,
2389 const struct pipe_clip_state
*clip
)
2391 //struct panfrost_context *panfrost = pan_context(pipe);
2395 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2396 unsigned start_slot
,
2397 unsigned num_viewports
,
2398 const struct pipe_viewport_state
*viewports
)
2400 struct panfrost_context
*ctx
= pan_context(pipe
);
2402 assert(start_slot
== 0);
2403 assert(num_viewports
== 1);
2405 ctx
->pipe_viewport
= *viewports
;
2409 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2410 unsigned start_slot
,
2411 unsigned num_scissors
,
2412 const struct pipe_scissor_state
*scissors
)
2414 struct panfrost_context
*ctx
= pan_context(pipe
);
2416 assert(start_slot
== 0);
2417 assert(num_scissors
== 1);
2419 ctx
->scissor
= *scissors
;
2423 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2424 const struct pipe_poly_stipple
*stipple
)
2426 //struct panfrost_context *panfrost = pan_context(pipe);
2430 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2433 struct panfrost_context
*ctx
= pan_context(pipe
);
2434 ctx
->active_queries
= enable
;
2438 panfrost_destroy(struct pipe_context
*pipe
)
2440 struct panfrost_context
*panfrost
= pan_context(pipe
);
2442 if (panfrost
->blitter
)
2443 util_blitter_destroy(panfrost
->blitter
);
2445 if (panfrost
->blitter_wallpaper
)
2446 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2451 static struct pipe_query
*
2452 panfrost_create_query(struct pipe_context
*pipe
,
2456 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2461 return (struct pipe_query
*) q
;
2465 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2471 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2473 struct panfrost_context
*ctx
= pan_context(pipe
);
2474 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2475 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2477 switch (query
->type
) {
2478 case PIPE_QUERY_OCCLUSION_COUNTER
:
2479 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2480 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2481 /* Allocate a word for the query results to be stored */
2482 query
->transfer
= panfrost_allocate_transient(batch
, sizeof(unsigned));
2483 ctx
->occlusion_query
= query
;
2486 /* Geometry statistics are computed in the driver. XXX: geom/tess
2489 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2490 query
->start
= ctx
->prims_generated
;
2492 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2493 query
->start
= ctx
->tf_prims_generated
;
2497 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2505 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2507 struct panfrost_context
*ctx
= pan_context(pipe
);
2508 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2510 switch (query
->type
) {
2511 case PIPE_QUERY_OCCLUSION_COUNTER
:
2512 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2513 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2514 ctx
->occlusion_query
= NULL
;
2516 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2517 query
->end
= ctx
->prims_generated
;
2519 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2520 query
->end
= ctx
->tf_prims_generated
;
2528 panfrost_get_query_result(struct pipe_context
*pipe
,
2529 struct pipe_query
*q
,
2531 union pipe_query_result
*vresult
)
2533 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2536 switch (query
->type
) {
2537 case PIPE_QUERY_OCCLUSION_COUNTER
:
2538 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2539 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2541 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2543 /* Read back the query results */
2544 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2545 unsigned passed
= *result
;
2547 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2548 vresult
->u64
= passed
;
2550 vresult
->b
= !!passed
;
2555 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2556 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2557 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2558 vresult
->u64
= query
->end
- query
->start
;
2562 DBG("Skipped query get %u\n", query
->type
);
2569 static struct pipe_stream_output_target
*
2570 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2571 struct pipe_resource
*prsc
,
2572 unsigned buffer_offset
,
2573 unsigned buffer_size
)
2575 struct pipe_stream_output_target
*target
;
2577 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2582 pipe_reference_init(&target
->reference
, 1);
2583 pipe_resource_reference(&target
->buffer
, prsc
);
2585 target
->context
= pctx
;
2586 target
->buffer_offset
= buffer_offset
;
2587 target
->buffer_size
= buffer_size
;
2593 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2594 struct pipe_stream_output_target
*target
)
2596 pipe_resource_reference(&target
->buffer
, NULL
);
2597 ralloc_free(target
);
2601 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2602 unsigned num_targets
,
2603 struct pipe_stream_output_target
**targets
,
2604 const unsigned *offsets
)
2606 struct panfrost_context
*ctx
= pan_context(pctx
);
2607 struct panfrost_streamout
*so
= &ctx
->streamout
;
2609 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2611 for (unsigned i
= 0; i
< num_targets
; i
++) {
2612 if (offsets
[i
] != -1)
2613 so
->offsets
[i
] = offsets
[i
];
2615 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2618 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2619 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2621 so
->num_targets
= num_targets
;
2624 struct pipe_context
*
2625 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2627 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2628 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2629 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2631 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2633 gallium
->screen
= screen
;
2635 gallium
->destroy
= panfrost_destroy
;
2637 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2639 gallium
->flush
= panfrost_flush
;
2640 gallium
->clear
= panfrost_clear
;
2641 gallium
->draw_vbo
= panfrost_draw_vbo
;
2643 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2644 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2645 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2647 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2649 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2650 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2651 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2653 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2654 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2655 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2657 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2658 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2659 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2661 gallium
->create_fs_state
= panfrost_create_shader_state
;
2662 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2663 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2665 gallium
->create_vs_state
= panfrost_create_shader_state
;
2666 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2667 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2669 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2670 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2671 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2673 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2674 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2675 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2677 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2679 gallium
->set_clip_state
= panfrost_set_clip_state
;
2680 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2681 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2682 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2683 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2685 gallium
->create_query
= panfrost_create_query
;
2686 gallium
->destroy_query
= panfrost_destroy_query
;
2687 gallium
->begin_query
= panfrost_begin_query
;
2688 gallium
->end_query
= panfrost_end_query
;
2689 gallium
->get_query_result
= panfrost_get_query_result
;
2691 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2692 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2693 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2695 panfrost_resource_context_init(gallium
);
2696 panfrost_blend_context_init(gallium
);
2697 panfrost_compute_context_init(gallium
);
2700 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2701 gallium
->const_uploader
= gallium
->stream_uploader
;
2702 assert(gallium
->stream_uploader
);
2704 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2705 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2707 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2709 ctx
->blitter
= util_blitter_create(gallium
);
2710 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2712 assert(ctx
->blitter
);
2713 assert(ctx
->blitter_wallpaper
);
2715 /* Prepare for render! */
2717 panfrost_batch_init(ctx
);
2718 panfrost_emit_vertex_payload(ctx
);
2719 panfrost_emit_tiler_payload(ctx
);
2720 panfrost_invalidate_frame(ctx
);
2721 panfrost_default_shader_backend(ctx
);