2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
50 static int performance_counter_number
= 0;
51 extern const char *pan_counters_base
;
53 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
56 static enum mali_job_type
57 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
60 case PIPE_SHADER_VERTEX
:
61 return JOB_TYPE_VERTEX
;
63 case PIPE_SHADER_FRAGMENT
:
64 /* Note: JOB_TYPE_FRAGMENT is different.
65 * JOB_TYPE_FRAGMENT actually executes the
66 * fragment shader, but JOB_TYPE_TILER is how you
68 return JOB_TYPE_TILER
;
70 case PIPE_SHADER_GEOMETRY
:
71 return JOB_TYPE_GEOMETRY
;
73 case PIPE_SHADER_COMPUTE
:
74 return JOB_TYPE_COMPUTE
;
77 unreachable("Unsupported shader stage");
82 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
84 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
85 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
86 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
87 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
89 /* 8 byte checksum per tile */
90 rsrc
->bo
->checksum_stride
= tile_w
* 8;
91 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
92 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
94 rsrc
->bo
->has_checksum
= true;
97 /* Framebuffer descriptor */
100 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
102 fb
->width
= MALI_POSITIVE(w
);
103 fb
->height
= MALI_POSITIVE(h
);
105 /* No idea why this is needed, but it's how resolution_check is
106 * calculated. It's not clear to us yet why the hardware wants this.
107 * The formula itself was discovered mostly by manual bruteforce and
108 * aggressive algebraic simplification. */
110 fb
->tiler_resolution_check
= ((w
+ h
) / 3) << 4;
113 struct mali_single_framebuffer
114 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
116 struct mali_single_framebuffer framebuffer
= {
118 .format
= 0x30000000,
119 .clear_flags
= 0x1000,
120 .unknown_address_0
= ctx
->scratchpad
.gpu
,
121 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
122 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 40960,
124 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
125 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
128 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
133 struct bifrost_framebuffer
134 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
136 struct bifrost_framebuffer framebuffer
= {
137 /* It is not yet clear what this means or how it's
138 * calculated, but we can tell it is a (monotonically
139 * increasing?) function of tile count and geometry complexity;
140 * I suspect it defines a memory size of some kind? for the
141 * tiler. It's really unclear at the moment... but to add to
142 * the confusion, the hardware is happy enough to accept a zero
143 * in this field, so we don't even have to worry about it right
146 .tiler_unknown
= 0x0,
148 /* The lower 0xff controls the hierarchy mask. Set more bits
149 * on for more tile granularity (which can be a performance win
150 * on some scenes, at memory bandwidth costs). For now, be lazy
151 * and enable everything. This might be a terrible idea. */
154 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
155 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
156 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
157 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
162 .rt_count_1
= MALI_POSITIVE(1),
167 /* Corresponds to unknown_address_X of SFBD */
168 .scratchpad
= ctx
->scratchpad
.gpu
,
169 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
171 /* The constant added here is, like the lower word of
172 * tiler_meta, (loosely) another product of framebuffer size
173 * and geometry complexity. It must be sufficiently large for
174 * the tiler_meta fast path to work; if it's too small, there
175 * will be DATA_INVALID_FAULTs. Conversely, it must be less
176 * than the total size of misc_0, or else there's no room. It's
177 * possible this constant configures a partition between two
178 * parts of misc_0? We haven't investigated the functionality,
179 * as these buffers are internally used by the hardware
180 * (presumably by the tiler) but not seemingly touched by the driver
183 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
185 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
186 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
192 /* Are we currently rendering to the screen (rather than an FBO)? */
195 panfrost_is_scanout(struct panfrost_context
*ctx
)
197 /* If there is no color buffer, it's an FBO */
198 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
201 /* If we're too early that no framebuffer was sent, it's scanout */
202 if (!ctx
->pipe_framebuffer
.cbufs
[0])
205 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
206 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
207 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
211 pan_pack_color(const union pipe_color_union
*color
, enum pipe_format format
)
213 /* Alpha magicked to 1.0 if there is no alpha */
215 bool has_alpha
= util_format_has_alpha(format
);
216 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
218 /* Packed color depends on the framebuffer format */
220 const struct util_format_description
*desc
=
221 util_format_description(format
);
223 if (util_format_is_rgba8_variant(desc
)) {
224 return (float_to_ubyte(clear_alpha
) << 24) |
225 (float_to_ubyte(color
->f
[2]) << 16) |
226 (float_to_ubyte(color
->f
[1]) << 8) |
227 (float_to_ubyte(color
->f
[0]) << 0);
228 } else if (format
== PIPE_FORMAT_B5G6R5_UNORM
) {
229 /* First, we convert the components to R5, G6, B5 separately */
230 unsigned r5
= CLAMP(color
->f
[0], 0.0, 1.0) * 31.0;
231 unsigned g6
= CLAMP(color
->f
[1], 0.0, 1.0) * 63.0;
232 unsigned b5
= CLAMP(color
->f
[2], 0.0, 1.0) * 31.0;
234 /* Then we pack into a sparse u32. TODO: Why these shifts? */
235 return (b5
<< 25) | (g6
<< 14) | (r5
<< 5);
246 struct pipe_context
*pipe
,
248 const union pipe_color_union
*color
,
249 double depth
, unsigned stencil
)
251 struct panfrost_context
*ctx
= pan_context(pipe
);
252 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
254 if (buffers
& PIPE_CLEAR_COLOR
) {
255 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[0]->format
;
256 job
->clear_color
= pan_pack_color(color
, format
);
259 if (buffers
& PIPE_CLEAR_DEPTH
) {
260 job
->clear_depth
= depth
;
263 if (buffers
& PIPE_CLEAR_STENCIL
) {
264 job
->clear_stencil
= stencil
;
267 job
->clear
|= buffers
;
271 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
273 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
277 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
279 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
283 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
285 mali_ptr framebuffer
= ctx
->require_sfbd
?
286 panfrost_attach_vt_sfbd(ctx
) :
287 panfrost_attach_vt_mfbd(ctx
);
289 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
290 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
293 /* Reset per-frame context, called on context initialisation as well as after
294 * flushing a frame */
297 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
299 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
300 DBG("Uploaded transient %d bytes\n", transient_count
);
302 /* Rotate cmdstream */
303 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
304 ctx
->cmdstream_i
= 0;
306 if (ctx
->require_sfbd
)
307 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
309 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
311 /* Reset varyings allocated */
312 ctx
->varying_height
= 0;
314 /* The transient cmdstream is dirty every frame; the only bits worth preserving
315 * (textures, shaders, etc) are in other buffers anyways */
317 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
318 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
320 /* Regenerate payloads */
321 panfrost_attach_vt_framebuffer(ctx
);
324 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
327 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
329 /* Reset job counters */
331 ctx
->vertex_job_count
= 0;
332 ctx
->tiler_job_count
= 0;
335 /* In practice, every field of these payloads should be configurable
336 * arbitrarily, which means these functions are basically catch-all's for
337 * as-of-yet unwavering unknowns */
340 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
342 struct midgard_payload_vertex_tiler payload
= {
344 .workgroups_z_shift
= 32,
345 .workgroups_x_shift_2
= 0x2,
346 .workgroups_x_shift_3
= 0x5,
348 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
351 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
355 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
357 struct midgard_payload_vertex_tiler payload
= {
359 .workgroups_z_shift
= 32,
360 .workgroups_x_shift_2
= 0x2,
361 .workgroups_x_shift_3
= 0x6,
363 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
367 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
371 translate_tex_wrap(enum pipe_tex_wrap w
)
374 case PIPE_TEX_WRAP_REPEAT
:
375 return MALI_WRAP_REPEAT
;
377 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
378 return MALI_WRAP_CLAMP_TO_EDGE
;
380 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
381 return MALI_WRAP_CLAMP_TO_BORDER
;
383 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
384 return MALI_WRAP_MIRRORED_REPEAT
;
387 unreachable("Invalid wrap");
392 translate_tex_filter(enum pipe_tex_filter f
)
395 case PIPE_TEX_FILTER_NEAREST
:
398 case PIPE_TEX_FILTER_LINEAR
:
402 unreachable("Invalid filter");
407 translate_mip_filter(enum pipe_tex_mipfilter f
)
409 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
413 panfrost_translate_compare_func(enum pipe_compare_func in
)
416 case PIPE_FUNC_NEVER
:
417 return MALI_FUNC_NEVER
;
420 return MALI_FUNC_LESS
;
422 case PIPE_FUNC_EQUAL
:
423 return MALI_FUNC_EQUAL
;
425 case PIPE_FUNC_LEQUAL
:
426 return MALI_FUNC_LEQUAL
;
428 case PIPE_FUNC_GREATER
:
429 return MALI_FUNC_GREATER
;
431 case PIPE_FUNC_NOTEQUAL
:
432 return MALI_FUNC_NOTEQUAL
;
434 case PIPE_FUNC_GEQUAL
:
435 return MALI_FUNC_GEQUAL
;
437 case PIPE_FUNC_ALWAYS
:
438 return MALI_FUNC_ALWAYS
;
441 unreachable("Invalid func");
446 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
449 case PIPE_FUNC_NEVER
:
450 return MALI_ALT_FUNC_NEVER
;
453 return MALI_ALT_FUNC_LESS
;
455 case PIPE_FUNC_EQUAL
:
456 return MALI_ALT_FUNC_EQUAL
;
458 case PIPE_FUNC_LEQUAL
:
459 return MALI_ALT_FUNC_LEQUAL
;
461 case PIPE_FUNC_GREATER
:
462 return MALI_ALT_FUNC_GREATER
;
464 case PIPE_FUNC_NOTEQUAL
:
465 return MALI_ALT_FUNC_NOTEQUAL
;
467 case PIPE_FUNC_GEQUAL
:
468 return MALI_ALT_FUNC_GEQUAL
;
470 case PIPE_FUNC_ALWAYS
:
471 return MALI_ALT_FUNC_ALWAYS
;
474 unreachable("Invalid alt func");
479 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
482 case PIPE_STENCIL_OP_KEEP
:
483 return MALI_STENCIL_KEEP
;
485 case PIPE_STENCIL_OP_ZERO
:
486 return MALI_STENCIL_ZERO
;
488 case PIPE_STENCIL_OP_REPLACE
:
489 return MALI_STENCIL_REPLACE
;
491 case PIPE_STENCIL_OP_INCR
:
492 return MALI_STENCIL_INCR
;
494 case PIPE_STENCIL_OP_DECR
:
495 return MALI_STENCIL_DECR
;
497 case PIPE_STENCIL_OP_INCR_WRAP
:
498 return MALI_STENCIL_INCR_WRAP
;
500 case PIPE_STENCIL_OP_DECR_WRAP
:
501 return MALI_STENCIL_DECR_WRAP
;
503 case PIPE_STENCIL_OP_INVERT
:
504 return MALI_STENCIL_INVERT
;
507 unreachable("Invalid stencil op");
512 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
514 out
->ref
= 0; /* Gallium gets it from elsewhere */
516 out
->mask
= in
->valuemask
;
517 out
->func
= panfrost_translate_compare_func(in
->func
);
518 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
519 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
520 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
524 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
526 struct mali_shader_meta shader
= {
527 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
529 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
530 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
534 shader
.unknown2_4
|= 0x10;
537 struct pipe_stencil_state default_stencil
= {
539 .func
= PIPE_FUNC_ALWAYS
,
540 .fail_op
= MALI_STENCIL_KEEP
,
541 .zfail_op
= MALI_STENCIL_KEEP
,
542 .zpass_op
= MALI_STENCIL_KEEP
,
547 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
548 shader
.stencil_mask_front
= default_stencil
.writemask
;
550 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
551 shader
.stencil_mask_back
= default_stencil
.writemask
;
553 if (default_stencil
.enabled
)
554 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
556 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
560 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
562 if (first
->job_descriptor_size
)
563 first
->next_job_64
= (u64
) (uintptr_t) next
;
565 first
->next_job_32
= (u32
) (uintptr_t) next
;
568 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
569 * graphics command stream. It should be called once per draw, accordding to
570 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
571 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
574 struct panfrost_transfer
575 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
577 /* Each draw call corresponds to two jobs, and the set-value job is first */
578 int draw_job_index
= 1 + (2 * ctx
->draw_count
) + 1;
580 struct mali_job_descriptor_header job
= {
581 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
582 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
584 .job_descriptor_size
= 1,
588 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
590 /* There's some padding hacks on 32-bit */
597 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
600 /* Tiler jobs depend on vertex jobs */
602 job
.job_dependency_index_1
= draw_job_index
;
604 /* Tiler jobs also depend on the previous tiler job */
606 if (ctx
->draw_count
) {
607 job
.job_dependency_index_2
= draw_job_index
- 1;
608 /* Previous tiler job points to this tiler job */
609 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
611 /* The only vertex job so far points to first tiler job */
612 panfrost_link_job_pair(ctx
->u_vertex_jobs
[0], transfer
.gpu
);
615 if (ctx
->draw_count
) {
616 /* Previous vertex job points to this vertex job */
617 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
619 /* Last vertex job points to first tiler job */
620 panfrost_link_job_pair(&job
, ctx
->tiler_jobs
[0]);
622 /* Have the first vertex job depend on the set value job */
623 job
.job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
624 panfrost_link_job_pair(ctx
->u_set_value_job
, transfer
.gpu
);
628 memcpy(transfer
.cpu
, &job
, sizeof(job
));
629 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
633 /* Generates a set value job. It's unclear what exactly this does, why it's
634 * necessary, and when to call it. */
637 panfrost_set_value_job(struct panfrost_context
*ctx
)
639 struct mali_job_descriptor_header job
= {
640 .job_type
= JOB_TYPE_SET_VALUE
,
641 .job_descriptor_size
= 1,
645 struct mali_payload_set_value payload
= {
646 .out
= ctx
->misc_0
.gpu
,
650 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
651 memcpy(transfer
.cpu
, &job
, sizeof(job
));
652 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
654 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
655 ctx
->set_value_job
= transfer
.gpu
;
659 panfrost_emit_varyings(
660 struct panfrost_context
*ctx
,
661 union mali_attr
*slot
,
665 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
667 /* Fill out the descriptor */
668 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
669 slot
->stride
= stride
;
670 slot
->size
= stride
* count
;
672 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
673 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
675 return varying_address
;
679 panfrost_emit_point_coord(union mali_attr
*slot
)
681 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
682 slot
->stride
= slot
->size
= 0;
686 panfrost_emit_varying_descriptor(
687 struct panfrost_context
*ctx
,
688 unsigned invocation_count
)
690 /* Load the shaders */
692 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
693 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
694 unsigned int num_gen_varyings
= 0;
696 /* Allocate the varying descriptor */
698 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
699 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
701 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
705 * Assign ->src_offset now that we know about all the general purpose
706 * varyings that will be used by the fragment and vertex shaders.
708 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
710 * General purpose varyings have ->index set to 0, skip other
713 if (vs
->varyings
[i
].index
)
716 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
719 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
722 if (fs
->varyings
[i
].index
)
726 * Re-use the VS general purpose varying pos if it exists,
727 * create a new one otherwise.
729 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
730 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
734 if (j
< vs
->tripipe
->varying_count
)
735 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
737 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
740 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
741 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
743 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
744 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
746 /* Buffer indices must be in this order per our convention */
747 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
750 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
753 /* fp32 vec4 gl_Position */
754 ctx
->payload_tiler
.postfix
.position_varying
=
755 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
756 sizeof(float) * 4, invocation_count
);
759 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
760 /* fp16 vec1 gl_PointSize */
761 ctx
->payload_tiler
.primitive_size
.pointer
=
762 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
763 2, invocation_count
);
766 if (fs
->reads_point_coord
) {
767 /* Special descriptor */
768 panfrost_emit_point_coord(&varyings
[idx
++]);
771 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
772 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
773 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
777 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
779 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
780 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
782 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
785 /* Emits attributes and varying descriptors, which should be called every draw,
786 * excepting some obscure circumstances */
789 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
791 /* Staged mali_attr, and index into them. i =/= k, depending on the
792 * vertex buffer mask */
793 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
796 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
798 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
799 if (!(ctx
->vb_mask
& (1 << i
))) continue;
801 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
802 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
806 /* Align to 64 bytes by masking off the lower bits. This
807 * will be adjusted back when we fixup the src_offset in
810 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
812 /* Offset vertex count by draw_start to make sure we upload enough */
813 attrs
[k
].stride
= buf
->stride
;
814 attrs
[k
].size
= rsrc
->base
.width0
;
816 panfrost_job_add_bo(job
, rsrc
->bo
);
817 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
822 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
824 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
828 panfrost_writes_point_size(struct panfrost_context
*ctx
)
831 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
833 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
836 /* Stage the attribute descriptors so we can adjust src_offset
837 * to let BOs align nicely */
840 panfrost_stage_attributes(struct panfrost_context
*ctx
)
842 struct panfrost_vertex_state
*so
= ctx
->vertex
;
844 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
845 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
846 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
848 /* Copy as-is for the first pass */
849 memcpy(target
, so
->hw
, sz
);
851 /* Fixup offsets for the second pass. Recall that the hardware
852 * calculates attribute addresses as:
854 * addr = base + (stride * vtx) + src_offset;
856 * However, on Mali, base must be aligned to 64-bytes, so we
859 * base' = base & ~63 = base - (base & 63)
861 * To compensate when using base' (see emit_vertex_data), we have
862 * to adjust src_offset by the masked off piece:
864 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
865 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
866 * = base + (stride * vtx) + src_offset
872 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
873 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
874 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
876 /* Adjust by the masked off bits of the offset */
877 target
[i
].src_offset
+= (addr
& 63);
880 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
884 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
886 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
888 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
889 if (!ctx
->sampler_count
[t
]) continue;
891 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
893 struct panfrost_transfer transfer
=
894 panfrost_allocate_transient(ctx
, transfer_size
);
896 struct mali_sampler_descriptor
*desc
=
897 (struct mali_sampler_descriptor
*) transfer
.cpu
;
899 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
900 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
902 if (t
== PIPE_SHADER_FRAGMENT
)
903 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
904 else if (t
== PIPE_SHADER_VERTEX
)
905 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
911 /* Computes the address to a texture at a particular slice */
914 panfrost_get_texture_address(
915 struct panfrost_resource
*rsrc
,
916 unsigned level
, unsigned face
)
918 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
919 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
921 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
927 struct panfrost_context
*ctx
,
928 struct panfrost_sampler_view
*view
)
931 return (mali_ptr
) NULL
;
933 struct pipe_resource
*tex_rsrc
= view
->base
.texture
;
934 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
936 /* Do we interleave an explicit stride with every element? */
938 bool has_manual_stride
=
939 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
941 /* Inject the addresses in, interleaving mip levels, cube faces, and
942 * strides in that order */
946 for (unsigned l
= 0; l
<= tex_rsrc
->last_level
; ++l
) {
947 for (unsigned f
= 0; f
< tex_rsrc
->array_size
; ++f
) {
948 view
->hw
.payload
[idx
++] =
949 panfrost_get_texture_address(rsrc
, l
, f
);
951 if (has_manual_stride
) {
952 view
->hw
.payload
[idx
++] =
953 rsrc
->bo
->slices
[l
].stride
;
958 return panfrost_upload_transient(ctx
, &view
->hw
,
959 sizeof(struct mali_texture_descriptor
));
963 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
965 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
967 if (!ctx
->sampler_view_count
[t
]) continue;
969 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
971 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
973 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
975 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
977 if (t
== PIPE_SHADER_FRAGMENT
)
978 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
979 else if (t
== PIPE_SHADER_VERTEX
)
980 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
986 /* Go through dirty flags and actualise them in the cmdstream. */
989 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
991 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
993 if (with_vertex_data
) {
994 panfrost_emit_vertex_data(ctx
, job
);
997 bool msaa
= ctx
->rasterizer
->base
.multisample
;
999 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1000 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1002 /* TODO: Sample size */
1003 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1004 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1007 /* Enable job requirements at draw-time */
1010 job
->requirements
|= PAN_REQ_MSAA
;
1012 if (ctx
->depth_stencil
->depth
.writemask
)
1013 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
1015 if (ctx
->occlusion_query
) {
1016 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1017 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1020 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1023 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1025 /* Late shader descriptor assignments */
1027 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1028 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1031 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1033 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1036 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1037 /* Check if we need to link the gl_PointSize varying */
1038 if (!panfrost_writes_point_size(ctx
)) {
1039 /* If the size is constant, write it out. Otherwise,
1040 * don't touch primitive_size (since we would clobber
1041 * the pointer there) */
1043 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1047 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1049 ctx
->dirty
|= PAN_DIRTY_FS
;
1051 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1053 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1055 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1058 COPY(attribute_count
);
1059 COPY(varying_count
);
1060 COPY(midgard1
.uniform_count
);
1061 COPY(midgard1
.work_count
);
1062 COPY(midgard1
.unknown2
);
1065 /* If there is a blend shader, work registers are shared */
1067 if (ctx
->blend
->has_blend_shader
)
1068 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1070 /* Set late due to depending on render state */
1071 /* The one at the end seems to mean "1 UBO" */
1072 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
1074 /* Assign texture/sample count right before upload */
1075 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1076 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1078 /* Assign the stencil refs late */
1079 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1080 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1082 /* CAN_DISCARD should be set if the fragment shader possibly
1083 * contains a 'discard' instruction. It is likely this is
1084 * related to optimizations related to forward-pixel kill, as
1085 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1086 * thing?" by Peter Harris
1089 if (variant
->can_discard
) {
1090 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1091 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1092 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1093 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1096 /* Check if we're using the default blend descriptor (fast path) */
1099 !ctx
->blend
->has_blend_shader
&&
1100 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1101 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1102 (ctx
->blend
->equation
.color_mask
== 0xf);
1104 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1105 * *also* copied to the blend_meta appended (by convention),
1106 * but this is the field actually read by the hardware. (Or
1107 * maybe both are read...?) */
1109 if (ctx
->blend
->has_blend_shader
) {
1110 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1113 if (ctx
->require_sfbd
) {
1114 /* When only a single render target platform is used, the blend
1115 * information is inside the shader meta itself. We
1116 * additionally need to signal CAN_DISCARD for nontrivial blend
1117 * modes (so we're able to read back the destination buffer) */
1119 if (!ctx
->blend
->has_blend_shader
) {
1120 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1121 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1125 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1129 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1130 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1131 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1133 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1135 if (!ctx
->require_sfbd
) {
1136 /* Additional blend descriptor tacked on for jobs using MFBD */
1138 unsigned blend_count
= 0x200;
1140 if (ctx
->blend
->has_blend_shader
) {
1141 /* For a blend shader, the bottom nibble corresponds to
1142 * the number of work registers used, which signals the
1143 * -existence- of a blend shader */
1145 assert(ctx
->blend
->blend_work_count
>= 2);
1146 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1148 /* Otherwise, the bottom bit simply specifies if
1149 * blending (anything other than REPLACE) is enabled */
1156 struct midgard_blend_rt rts
[4];
1160 for (unsigned i
= 0; i
< 1; ++i
) {
1161 rts
[i
].flags
= blend_count
;
1163 if (ctx
->blend
->has_blend_shader
) {
1164 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1166 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1167 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1171 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1175 /* We stage to transient, so always dirty.. */
1176 panfrost_stage_attributes(ctx
);
1178 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1179 panfrost_upload_sampler_descriptors(ctx
);
1181 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1182 panfrost_upload_texture_descriptors(ctx
);
1184 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1186 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1187 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1189 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1190 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1191 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1193 /* Allocate room for the sysval and the uniforms */
1194 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1195 size_t size
= sys_size
+ buf
->size
;
1196 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1198 /* Upload sysvals requested by the shader */
1199 float *uniforms
= (float *) transfer
.cpu
;
1200 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1201 int sysval
= ss
->sysval
[i
];
1203 if (sysval
== PAN_SYSVAL_VIEWPORT_SCALE
) {
1204 uniforms
[4*i
+ 0] = vp
->scale
[0];
1205 uniforms
[4*i
+ 1] = vp
->scale
[1];
1206 uniforms
[4*i
+ 2] = vp
->scale
[2];
1207 } else if (sysval
== PAN_SYSVAL_VIEWPORT_OFFSET
) {
1208 uniforms
[4*i
+ 0] = vp
->translate
[0];
1209 uniforms
[4*i
+ 1] = vp
->translate
[1];
1210 uniforms
[4*i
+ 2] = vp
->translate
[2];
1216 /* Upload uniforms */
1217 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1219 int uniform_count
= 0;
1221 struct mali_vertex_tiler_postfix
*postfix
;
1224 case PIPE_SHADER_VERTEX
:
1225 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1226 postfix
= &ctx
->payload_vertex
.postfix
;
1229 case PIPE_SHADER_FRAGMENT
:
1230 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1231 postfix
= &ctx
->payload_tiler
.postfix
;
1235 unreachable("Invalid shader stage\n");
1238 /* Also attach the same buffer as a UBO for extended access */
1240 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1242 .size
= MALI_POSITIVE((2 + uniform_count
)),
1243 .ptr
= transfer
.gpu
>> 2,
1247 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1248 postfix
->uniforms
= transfer
.gpu
;
1249 postfix
->uniform_buffers
= ubufs
;
1254 /* TODO: Upload the viewport somewhere more appropriate */
1256 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1257 * (somewhat) asymmetric ints. */
1258 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1260 struct mali_viewport view
= {
1261 /* By default, do no viewport clipping, i.e. clip to (-inf,
1262 * inf) in each direction. Clipping to the viewport in theory
1263 * should work, but in practice causes issues when we're not
1264 * explicitly trying to scissor */
1275 /* Always scissor to the viewport by default. */
1276 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1277 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1279 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1280 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1282 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1283 view
.viewport0
[0] = ss
->minx
;
1284 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1290 /* Hardware needs the min/max to be strictly ordered, so flip if we
1298 view
.viewport0
[1] = miny
;
1299 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1301 ctx
->payload_tiler
.postfix
.viewport
=
1302 panfrost_upload_transient(ctx
,
1304 sizeof(struct mali_viewport
));
1309 /* Corresponds to exactly one draw, but does not submit anything */
1312 panfrost_queue_draw(struct panfrost_context
*ctx
)
1314 /* TODO: Expand the array? */
1315 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1316 DBG("Job buffer overflow, ignoring draw\n");
1320 /* Handle dirty flags now */
1321 panfrost_emit_for_draw(ctx
, true);
1323 /* We need a set_value job before any other draw jobs */
1324 if (ctx
->draw_count
== 0)
1325 panfrost_set_value_job(ctx
);
1327 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1328 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1329 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1331 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true);
1332 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1333 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1338 /* The entire frame is in memory -- send it off to the kernel! */
1341 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1342 struct pipe_fence_handle
**fence
,
1343 struct panfrost_job
*job
)
1345 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1346 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1348 /* Edge case if screen is cleared and nothing else */
1349 bool has_draws
= ctx
->draw_count
> 0;
1351 /* Workaround a bizarre lockup (a hardware errata?) */
1353 flush_immediate
= true;
1357 bool is_scanout
= panfrost_is_scanout(ctx
);
1358 screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1360 /* If visual, we can stall a frame */
1362 if (!flush_immediate
)
1363 screen
->driver
->force_flush_fragment(ctx
, fence
);
1365 screen
->last_fragment_flushed
= false;
1366 screen
->last_job
= job
;
1368 /* If readback, flush now (hurts the pipelined performance) */
1369 if (flush_immediate
)
1370 screen
->driver
->force_flush_fragment(ctx
, fence
);
1372 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1373 screen
->driver
->dump_counters(screen
);
1376 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1377 FILE *fp
= fopen(filename
, "wb");
1378 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1386 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1388 struct panfrost_context
*ctx
= pan_context(pipe
);
1390 /* Nothing to reload? */
1391 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1394 /* Blit the wallpaper in */
1395 panfrost_blit_wallpaper(ctx
);
1397 /* We are flushing all queued draws and we know that no more jobs will
1398 * be added until the next frame.
1399 * We also know that the last jobs are the wallpaper jobs, and they
1400 * need to be linked so they execute right after the set_value job.
1403 /* set_value job to wallpaper vertex job */
1404 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[ctx
->vertex_job_count
- 1]);
1405 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1407 /* wallpaper vertex job to first vertex job */
1408 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1], ctx
->vertex_jobs
[0]);
1409 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1411 /* last vertex job to wallpaper tiler job */
1412 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 2], ctx
->tiler_jobs
[ctx
->tiler_job_count
- 1]);
1413 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_1
= ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_index
;
1414 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_2
= 0;
1416 /* wallpaper tiler job to first tiler job */
1417 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1], ctx
->tiler_jobs
[0]);
1418 ctx
->u_tiler_jobs
[0]->job_dependency_index_1
= ctx
->u_vertex_jobs
[0]->job_index
;
1419 ctx
->u_tiler_jobs
[0]->job_dependency_index_2
= ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_index
;
1421 /* last tiler job to NULL */
1422 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 2], 0);
1427 struct pipe_context
*pipe
,
1428 struct pipe_fence_handle
**fence
,
1431 struct panfrost_context
*ctx
= pan_context(pipe
);
1432 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1434 /* Nothing to do! */
1435 if (!ctx
->draw_count
&& !job
->clear
) return;
1438 panfrost_draw_wallpaper(&ctx
->base
);
1440 /* Whether to stall the pipeline for immediately correct results */
1441 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1443 /* Submit the frame itself */
1444 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1446 /* Prepare for the next frame */
1447 panfrost_invalidate_frame(ctx
);
1450 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1453 g2m_draw_mode(enum pipe_prim_type mode
)
1456 DEFINE_CASE(POINTS
);
1458 DEFINE_CASE(LINE_LOOP
);
1459 DEFINE_CASE(LINE_STRIP
);
1460 DEFINE_CASE(TRIANGLES
);
1461 DEFINE_CASE(TRIANGLE_STRIP
);
1462 DEFINE_CASE(TRIANGLE_FAN
);
1464 DEFINE_CASE(QUAD_STRIP
);
1465 DEFINE_CASE(POLYGON
);
1468 unreachable("Invalid draw mode");
1475 panfrost_translate_index_size(unsigned size
)
1479 return MALI_DRAW_INDEXED_UINT8
;
1482 return MALI_DRAW_INDEXED_UINT16
;
1485 return MALI_DRAW_INDEXED_UINT32
;
1488 unreachable("Invalid index size");
1492 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1493 * good for the duration of the draw (transient), could last longer */
1496 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1498 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1500 off_t offset
= info
->start
* info
->index_size
;
1502 if (!info
->has_user_indices
) {
1503 /* Only resources can be directly mapped */
1504 return rsrc
->bo
->gpu
+ offset
;
1506 /* Otherwise, we need to upload to transient memory */
1507 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1508 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1514 struct pipe_context
*pipe
,
1515 const struct pipe_draw_info
*info
)
1517 struct panfrost_context
*ctx
= pan_context(pipe
);
1519 ctx
->payload_vertex
.draw_start
= info
->start
;
1520 ctx
->payload_tiler
.draw_start
= info
->start
;
1522 int mode
= info
->mode
;
1524 /* Fallback for unsupported modes */
1526 if (!(ctx
->draw_modes
& (1 << mode
))) {
1527 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1528 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1530 if (info
->count
< 4) {
1531 /* Degenerate case? */
1535 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1536 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1541 /* Now that we have a guaranteed terminating path, find the job.
1542 * Assignment commented out to prevent unused warning */
1544 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1546 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1548 ctx
->vertex_count
= info
->count
;
1550 /* For non-indexed draws, they're the same */
1551 unsigned invocation_count
= ctx
->vertex_count
;
1553 unsigned draw_flags
= 0;
1555 /* The draw flags interpret how primitive size is interpreted */
1557 if (panfrost_writes_point_size(ctx
))
1558 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1560 /* For higher amounts of vertices (greater than what fits in a 16-bit
1561 * short), the other value is needed, otherwise there will be bizarre
1562 * rendering artefacts. It's not clear what these values mean yet. */
1564 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1566 if (info
->index_size
) {
1567 /* Calculate the min/max index used so we can figure out how
1568 * many times to invoke the vertex shader */
1570 /* Fetch / calculate index bounds */
1571 unsigned min_index
= 0, max_index
= 0;
1573 if (info
->max_index
== ~0u) {
1574 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1576 min_index
= info
->min_index
;
1577 max_index
= info
->max_index
;
1580 /* Use the corresponding values */
1581 invocation_count
= max_index
- min_index
+ 1;
1582 ctx
->payload_vertex
.draw_start
= min_index
;
1583 ctx
->payload_tiler
.draw_start
= min_index
;
1585 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1586 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1588 //assert(!info->restart_index); /* TODO: Research */
1589 assert(!info
->index_bias
);
1591 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1592 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1594 /* Index count == vertex count, if no indexing is applied, as
1595 * if it is internally indexed in the expected order */
1597 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1598 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1600 /* Reverse index state */
1601 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1604 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1605 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1606 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1608 /* Fire off the draw itself */
1609 panfrost_queue_draw(ctx
);
1615 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1621 panfrost_create_rasterizer_state(
1622 struct pipe_context
*pctx
,
1623 const struct pipe_rasterizer_state
*cso
)
1625 struct panfrost_context
*ctx
= pan_context(pctx
);
1626 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1630 /* Bitmask, unknown meaning of the start value */
1631 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1634 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1636 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1637 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1639 if (cso
->cull_face
& PIPE_FACE_BACK
)
1640 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1646 panfrost_bind_rasterizer_state(
1647 struct pipe_context
*pctx
,
1650 struct panfrost_context
*ctx
= pan_context(pctx
);
1652 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1656 ctx
->rasterizer
= hwcso
;
1657 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1661 panfrost_create_vertex_elements_state(
1662 struct pipe_context
*pctx
,
1663 unsigned num_elements
,
1664 const struct pipe_vertex_element
*elements
)
1666 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1668 so
->num_elements
= num_elements
;
1669 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1671 /* XXX: What the cornball? This is totally, 100%, unapologetically
1672 * nonsense. And yet it somehow fixes a regression in -bshadow
1673 * (previously, we allocated the descriptor here... a newer commit
1674 * removed that allocation, and then memory corruption led to
1675 * shader_meta getting overwritten in bad ways and then the whole test
1676 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1678 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1680 for (int i
= 0; i
< num_elements
; ++i
) {
1681 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1683 enum pipe_format fmt
= elements
[i
].src_format
;
1684 const struct util_format_description
*desc
= util_format_description(fmt
);
1685 so
->hw
[i
].unknown1
= 0x2;
1686 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1688 so
->hw
[i
].format
= panfrost_find_format(desc
);
1690 /* The field itself should probably be shifted over */
1691 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1698 panfrost_bind_vertex_elements_state(
1699 struct pipe_context
*pctx
,
1702 struct panfrost_context
*ctx
= pan_context(pctx
);
1704 ctx
->vertex
= hwcso
;
1705 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1709 panfrost_create_shader_state(
1710 struct pipe_context
*pctx
,
1711 const struct pipe_shader_state
*cso
)
1713 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1716 /* Token deep copy to prevent memory corruption */
1718 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1719 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1725 panfrost_delete_shader_state(
1726 struct pipe_context
*pctx
,
1729 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1731 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1732 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1739 panfrost_create_sampler_state(
1740 struct pipe_context
*pctx
,
1741 const struct pipe_sampler_state
*cso
)
1743 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1746 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1748 struct mali_sampler_descriptor sampler_descriptor
= {
1749 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1750 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1751 | translate_mip_filter(cso
->min_mip_filter
)
1754 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1755 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1756 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1757 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1759 cso
->border_color
.f
[0],
1760 cso
->border_color
.f
[1],
1761 cso
->border_color
.f
[2],
1762 cso
->border_color
.f
[3]
1764 .min_lod
= FIXED_16(cso
->min_lod
),
1765 .max_lod
= FIXED_16(cso
->max_lod
),
1769 so
->hw
= sampler_descriptor
;
1775 panfrost_bind_sampler_states(
1776 struct pipe_context
*pctx
,
1777 enum pipe_shader_type shader
,
1778 unsigned start_slot
, unsigned num_sampler
,
1781 assert(start_slot
== 0);
1783 struct panfrost_context
*ctx
= pan_context(pctx
);
1785 /* XXX: Should upload, not just copy? */
1786 ctx
->sampler_count
[shader
] = num_sampler
;
1787 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1789 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1793 panfrost_variant_matches(
1794 struct panfrost_context
*ctx
,
1795 struct panfrost_shader_state
*variant
,
1796 enum pipe_shader_type type
)
1798 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1800 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1802 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1803 /* Make sure enable state is at least the same */
1804 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1808 /* Check that the contents of the test are the same */
1809 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1810 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1812 if (!(same_func
&& same_ref
)) {
1816 /* Otherwise, we're good to go */
1821 panfrost_bind_shader_state(
1822 struct pipe_context
*pctx
,
1824 enum pipe_shader_type type
)
1826 struct panfrost_context
*ctx
= pan_context(pctx
);
1828 if (type
== PIPE_SHADER_FRAGMENT
) {
1830 ctx
->dirty
|= PAN_DIRTY_FS
;
1832 assert(type
== PIPE_SHADER_VERTEX
);
1834 ctx
->dirty
|= PAN_DIRTY_VS
;
1839 /* Match the appropriate variant */
1841 signed variant
= -1;
1842 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1844 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1845 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1851 if (variant
== -1) {
1852 /* No variant matched, so create a new one */
1853 variant
= variants
->variant_count
++;
1854 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1856 variants
->variants
[variant
].base
= hwcso
;
1858 if (type
== PIPE_SHADER_FRAGMENT
)
1859 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1861 /* Allocate the mapped descriptor ahead-of-time. */
1862 struct panfrost_context
*ctx
= pan_context(pctx
);
1863 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1865 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1866 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1870 /* Select this variant */
1871 variants
->active_variant
= variant
;
1873 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1874 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1876 /* We finally have a variant, so compile it */
1878 if (!shader_state
->compiled
) {
1879 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
1880 panfrost_job_type_for_pipe(type
), shader_state
);
1882 shader_state
->compiled
= true;
1887 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1889 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1893 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1895 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1899 panfrost_set_vertex_buffers(
1900 struct pipe_context
*pctx
,
1901 unsigned start_slot
,
1902 unsigned num_buffers
,
1903 const struct pipe_vertex_buffer
*buffers
)
1905 struct panfrost_context
*ctx
= pan_context(pctx
);
1907 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1911 panfrost_set_constant_buffer(
1912 struct pipe_context
*pctx
,
1913 enum pipe_shader_type shader
, uint index
,
1914 const struct pipe_constant_buffer
*buf
)
1916 struct panfrost_context
*ctx
= pan_context(pctx
);
1917 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1919 size_t sz
= buf
? buf
->buffer_size
: 0;
1921 /* Free previous buffer */
1928 pbuf
->buffer
= NULL
;
1931 /* If unbinding, we're done */
1936 /* Multiple constant buffers not yet supported */
1941 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1944 cpu
= rsrc
->bo
->cpu
;
1945 } else if (buf
->user_buffer
) {
1946 cpu
= buf
->user_buffer
;
1948 DBG("No constant buffer?\n");
1952 /* Copy the constant buffer into the driver context for later upload */
1954 pbuf
->buffer
= malloc(sz
);
1955 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1959 panfrost_set_stencil_ref(
1960 struct pipe_context
*pctx
,
1961 const struct pipe_stencil_ref
*ref
)
1963 struct panfrost_context
*ctx
= pan_context(pctx
);
1964 ctx
->stencil_ref
= *ref
;
1966 /* Shader core dirty */
1967 ctx
->dirty
|= PAN_DIRTY_FS
;
1970 static struct pipe_sampler_view
*
1971 panfrost_create_sampler_view(
1972 struct pipe_context
*pctx
,
1973 struct pipe_resource
*texture
,
1974 const struct pipe_sampler_view
*template)
1976 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1977 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1979 pipe_reference(NULL
, &texture
->reference
);
1981 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1984 so
->base
= *template;
1985 so
->base
.texture
= texture
;
1986 so
->base
.reference
.count
= 1;
1987 so
->base
.context
= pctx
;
1989 /* sampler_views correspond to texture descriptors, minus the texture
1990 * (data) itself. So, we serialise the descriptor here and cache it for
1993 /* Make sure it's something with which we're familiar */
1994 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1996 /* TODO: Detect from format better */
1997 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1999 unsigned char user_swizzle
[4] = {
2000 template->swizzle_r
,
2001 template->swizzle_g
,
2002 template->swizzle_b
,
2006 enum mali_format format
= panfrost_find_format(desc
);
2008 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2010 unsigned usage2_layout
= 0x10;
2012 switch (prsrc
->bo
->layout
) {
2014 usage2_layout
|= 0x8 | 0x4;
2017 usage2_layout
|= 0x1;
2020 usage2_layout
|= is_depth
? 0x1 : 0x2;
2027 /* Check if we need to set a custom stride by computing the "expected"
2028 * stride and comparing it to what the BO actually wants. Only applies
2029 * to linear textures, since tiled/compressed textures have strict
2030 * alignment requirements for their strides as it is */
2032 unsigned first_level
= template->u
.tex
.first_level
;
2033 unsigned last_level
= template->u
.tex
.last_level
;
2035 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
2036 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2037 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
2038 unsigned width
= u_minify(texture
->width0
, l
);
2039 unsigned comp_stride
= width
* bytes_per_pixel
;
2041 if (comp_stride
!= actual_stride
) {
2042 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2048 struct mali_texture_descriptor texture_descriptor
= {
2049 .width
= MALI_POSITIVE(texture
->width0
),
2050 .height
= MALI_POSITIVE(texture
->height0
),
2051 .depth
= MALI_POSITIVE(texture
->depth0
),
2055 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2059 .is_not_cubemap
= texture
->target
!= PIPE_TEXTURE_CUBE
,
2061 .usage2
= usage2_layout
2064 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2067 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2068 assert (template->u
.tex
.first_level
== 0);
2070 /* Disable mipmapping for now to avoid regressions while automipmapping
2071 * is being implemented. TODO: Remove me once automipmaps work */
2073 //texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2074 texture_descriptor
.nr_mipmap_levels
= 0;
2076 so
->hw
= texture_descriptor
;
2078 return (struct pipe_sampler_view
*) so
;
2082 panfrost_set_sampler_views(
2083 struct pipe_context
*pctx
,
2084 enum pipe_shader_type shader
,
2085 unsigned start_slot
, unsigned num_views
,
2086 struct pipe_sampler_view
**views
)
2088 struct panfrost_context
*ctx
= pan_context(pctx
);
2090 assert(start_slot
== 0);
2092 ctx
->sampler_view_count
[shader
] = num_views
;
2093 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2095 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2099 panfrost_sampler_view_destroy(
2100 struct pipe_context
*pctx
,
2101 struct pipe_sampler_view
*view
)
2103 pipe_resource_reference(&view
->texture
, NULL
);
2108 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2109 const struct pipe_framebuffer_state
*fb
)
2111 struct panfrost_context
*ctx
= pan_context(pctx
);
2113 /* Flush when switching away from an FBO, but not if the framebuffer
2114 * state is being restored by u_blitter
2117 if (!panfrost_is_scanout(ctx
) && !ctx
->blitter
->running
) {
2118 panfrost_flush(pctx
, NULL
, 0);
2121 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2122 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2123 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2124 ctx
->pipe_framebuffer
.width
= fb
->width
;
2125 ctx
->pipe_framebuffer
.height
= fb
->height
;
2127 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2128 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2130 /* check if changing cbuf */
2131 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2133 if (cb
&& (i
!= 0)) {
2134 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2139 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2144 if (ctx
->require_sfbd
)
2145 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2147 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2149 panfrost_attach_vt_framebuffer(ctx
);
2151 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2152 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2154 bool can_afbc
= panfrost_format_supports_afbc(format
);
2155 bool is_scanout
= panfrost_is_scanout(ctx
);
2157 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2158 panfrost_enable_afbc(ctx
, tex
, false);
2160 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2161 panfrost_enable_checksum(ctx
, tex
);
2165 struct pipe_surface
*zb
= fb
->zsbuf
;
2167 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2168 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2171 if (ctx
->require_sfbd
)
2172 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2174 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2176 panfrost_attach_vt_framebuffer(ctx
);
2178 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2179 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2180 bool is_scanout
= panfrost_is_scanout(ctx
);
2182 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2183 panfrost_enable_afbc(ctx
, tex
, true);
2190 panfrost_create_blend_state(struct pipe_context
*pipe
,
2191 const struct pipe_blend_state
*blend
)
2193 struct panfrost_context
*ctx
= pan_context(pipe
);
2194 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2197 /* TODO: The following features are not yet implemented */
2198 assert(!blend
->logicop_enable
);
2199 assert(!blend
->alpha_to_coverage
);
2200 assert(!blend
->alpha_to_one
);
2202 /* Compile the blend state, first as fixed-function if we can */
2204 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2207 /* If we can't, compile a blend shader instead */
2209 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2215 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2218 struct panfrost_context
*ctx
= pan_context(pipe
);
2219 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2220 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2221 ctx
->blend
= pblend
;
2226 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2228 /* TODO: Attach color */
2230 /* Shader itself is not dirty, but the shader core is */
2231 ctx
->dirty
|= PAN_DIRTY_FS
;
2235 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2238 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2240 if (so
->has_blend_shader
) {
2241 DBG("Deleting blend state leak blend shaders bytecode\n");
2248 panfrost_set_blend_color(struct pipe_context
*pipe
,
2249 const struct pipe_blend_color
*blend_color
)
2251 struct panfrost_context
*ctx
= pan_context(pipe
);
2253 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2256 ctx
->blend_color
= *blend_color
;
2258 /* The blend mode depends on the blend constant color, due to the
2259 * fixed/programmable split. So, we're forced to regenerate the blend
2262 /* TODO: Attach color */
2267 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2268 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2270 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2274 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2277 struct panfrost_context
*ctx
= pan_context(pipe
);
2278 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2279 ctx
->depth_stencil
= depth_stencil
;
2284 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2285 * emulated in the fragment shader */
2287 if (depth_stencil
->alpha
.enabled
) {
2288 /* We need to trigger a new shader (maybe) */
2289 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2293 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2295 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2296 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2298 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2299 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2301 /* Depth state (TODO: Refactor) */
2302 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2304 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2306 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2307 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2309 /* Bounds test not implemented */
2310 assert(!depth_stencil
->depth
.bounds_test
);
2312 ctx
->dirty
|= PAN_DIRTY_FS
;
2316 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2322 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2323 unsigned sample_mask
)
2328 panfrost_set_clip_state(struct pipe_context
*pipe
,
2329 const struct pipe_clip_state
*clip
)
2331 //struct panfrost_context *panfrost = pan_context(pipe);
2335 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2336 unsigned start_slot
,
2337 unsigned num_viewports
,
2338 const struct pipe_viewport_state
*viewports
)
2340 struct panfrost_context
*ctx
= pan_context(pipe
);
2342 assert(start_slot
== 0);
2343 assert(num_viewports
== 1);
2345 ctx
->pipe_viewport
= *viewports
;
2349 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2350 unsigned start_slot
,
2351 unsigned num_scissors
,
2352 const struct pipe_scissor_state
*scissors
)
2354 struct panfrost_context
*ctx
= pan_context(pipe
);
2356 assert(start_slot
== 0);
2357 assert(num_scissors
== 1);
2359 ctx
->scissor
= *scissors
;
2363 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2364 const struct pipe_poly_stipple
*stipple
)
2366 //struct panfrost_context *panfrost = pan_context(pipe);
2370 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2373 //struct panfrost_context *panfrost = pan_context(pipe);
2377 panfrost_destroy(struct pipe_context
*pipe
)
2379 struct panfrost_context
*panfrost
= pan_context(pipe
);
2380 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2382 if (panfrost
->blitter
)
2383 util_blitter_destroy(panfrost
->blitter
);
2385 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2386 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2387 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2388 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2389 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2392 static struct pipe_query
*
2393 panfrost_create_query(struct pipe_context
*pipe
,
2397 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2402 return (struct pipe_query
*) q
;
2406 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2412 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2414 struct panfrost_context
*ctx
= pan_context(pipe
);
2415 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2417 switch (query
->type
) {
2418 case PIPE_QUERY_OCCLUSION_COUNTER
:
2419 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2420 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2422 /* Allocate a word for the query results to be stored */
2423 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2425 ctx
->occlusion_query
= query
;
2431 DBG("Skipping query %d\n", query
->type
);
2439 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2441 struct panfrost_context
*ctx
= pan_context(pipe
);
2442 ctx
->occlusion_query
= NULL
;
2447 panfrost_get_query_result(struct pipe_context
*pipe
,
2448 struct pipe_query
*q
,
2450 union pipe_query_result
*vresult
)
2453 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2455 /* We need to flush out the jobs to actually run the counter, TODO
2456 * check wait, TODO wallpaper after if needed */
2458 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2460 switch (query
->type
) {
2461 case PIPE_QUERY_OCCLUSION_COUNTER
:
2462 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2463 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2464 /* Read back the query results */
2465 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2466 unsigned passed
= *result
;
2468 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2469 vresult
->u64
= passed
;
2471 vresult
->b
= !!passed
;
2477 DBG("Skipped query get %d\n", query
->type
);
2484 static struct pipe_stream_output_target
*
2485 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2486 struct pipe_resource
*prsc
,
2487 unsigned buffer_offset
,
2488 unsigned buffer_size
)
2490 struct pipe_stream_output_target
*target
;
2492 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2497 pipe_reference_init(&target
->reference
, 1);
2498 pipe_resource_reference(&target
->buffer
, prsc
);
2500 target
->context
= pctx
;
2501 target
->buffer_offset
= buffer_offset
;
2502 target
->buffer_size
= buffer_size
;
2508 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2509 struct pipe_stream_output_target
*target
)
2511 pipe_resource_reference(&target
->buffer
, NULL
);
2516 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2517 unsigned num_targets
,
2518 struct pipe_stream_output_target
**targets
,
2519 const unsigned *offsets
)
2525 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2527 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2528 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2530 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2531 /* Allocate the beginning of the transient pool */
2532 int entry_size
= (1 << 22); /* 4MB */
2534 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2535 ctx
->transient_pools
[i
].entry_count
= 1;
2537 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2540 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2541 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2542 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2543 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2544 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2548 /* New context creation, which also does hardware initialisation since I don't
2549 * know the better way to structure this :smirk: */
2551 struct pipe_context
*
2552 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2554 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2555 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2556 memset(ctx
, 0, sizeof(*ctx
));
2557 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2560 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2562 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2563 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2565 gallium
->screen
= screen
;
2567 gallium
->destroy
= panfrost_destroy
;
2569 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2571 gallium
->flush
= panfrost_flush
;
2572 gallium
->clear
= panfrost_clear
;
2573 gallium
->draw_vbo
= panfrost_draw_vbo
;
2575 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2576 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2578 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2580 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2581 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2582 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2584 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2585 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2586 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2588 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2589 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2590 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2592 gallium
->create_fs_state
= panfrost_create_shader_state
;
2593 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2594 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2596 gallium
->create_vs_state
= panfrost_create_shader_state
;
2597 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2598 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2600 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2601 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2602 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2604 gallium
->create_blend_state
= panfrost_create_blend_state
;
2605 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2606 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2608 gallium
->set_blend_color
= panfrost_set_blend_color
;
2610 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2611 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2612 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2614 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2616 gallium
->set_clip_state
= panfrost_set_clip_state
;
2617 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2618 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2619 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2620 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2622 gallium
->create_query
= panfrost_create_query
;
2623 gallium
->destroy_query
= panfrost_destroy_query
;
2624 gallium
->begin_query
= panfrost_begin_query
;
2625 gallium
->end_query
= panfrost_end_query
;
2626 gallium
->get_query_result
= panfrost_get_query_result
;
2628 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2629 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2630 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2632 panfrost_resource_context_init(gallium
);
2634 pscreen
->driver
->init_context(ctx
);
2636 panfrost_setup_hardware(ctx
);
2639 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2640 gallium
->const_uploader
= gallium
->stream_uploader
;
2641 assert(gallium
->stream_uploader
);
2643 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2644 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2646 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2648 ctx
->blitter
= util_blitter_create(gallium
);
2649 assert(ctx
->blitter
);
2651 /* Prepare for render! */
2653 panfrost_job_init(ctx
);
2654 panfrost_emit_vertex_payload(ctx
);
2655 panfrost_emit_tiler_payload(ctx
);
2656 panfrost_invalidate_frame(ctx
);
2657 panfrost_default_shader_backend(ctx
);
2658 panfrost_generate_space_filler_indices();