2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
50 static int performance_counter_number
= 0;
51 extern const char *pan_counters_base
;
53 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
57 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
59 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
60 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
61 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
62 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
64 /* 8 byte checksum per tile */
65 rsrc
->bo
->checksum_stride
= tile_w
* 8;
66 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
67 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
69 rsrc
->bo
->has_checksum
= true;
72 /* Framebuffer descriptor */
75 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
77 fb
->width
= MALI_POSITIVE(w
);
78 fb
->height
= MALI_POSITIVE(h
);
80 /* No idea why this is needed, but it's how resolution_check is
81 * calculated. It's not clear to us yet why the hardware wants this.
82 * The formula itself was discovered mostly by manual bruteforce and
83 * aggressive algebraic simplification. */
85 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
88 struct mali_single_framebuffer
89 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
91 struct mali_single_framebuffer framebuffer
= {
94 .clear_flags
= 0x1000,
95 .unknown_address_0
= ctx
->scratchpad
.gpu
,
96 .unknown_address_1
= ctx
->misc_0
.gpu
,
97 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
99 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
100 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
103 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
108 struct bifrost_framebuffer
109 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
111 struct bifrost_framebuffer framebuffer
= {
112 /* It is not yet clear what tiler_meta means or how it's
113 * calculated, but we can tell the lower 32-bits are a
114 * (monotonically increasing?) function of tile count and
115 * geometry complexity; I suspect it defines a memory size of
116 * some kind? for the tiler. It's really unclear at the
117 * moment... but to add to the confusion, the hardware is happy
118 * enough to accept a zero in this field, so we don't even have
119 * to worry about it right now.
121 * The byte (just after the 32-bit mark) is much more
122 * interesting. The higher nibble I've only ever seen as 0xF,
123 * but the lower one I've seen as 0x0 or 0xF, and it's not
124 * obvious what the difference is. But what -is- obvious is
125 * that when the lower nibble is zero, performance is severely
126 * degraded compared to when the lower nibble is set.
127 * Evidently, that nibble enables some sort of fast path,
128 * perhaps relating to caching or tile flush? Regardless, at
129 * this point there's no clear reason not to set it, aside from
130 * substantially increased memory requirements (of the misc_0
133 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
135 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
136 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
137 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
138 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
143 .rt_count_1
= MALI_POSITIVE(1),
148 /* Corresponds to unknown_address_X of SFBD */
149 .scratchpad
= ctx
->scratchpad
.gpu
,
150 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
152 /* The constant added here is, like the lower word of
153 * tiler_meta, (loosely) another product of framebuffer size
154 * and geometry complexity. It must be sufficiently large for
155 * the tiler_meta fast path to work; if it's too small, there
156 * will be DATA_INVALID_FAULTs. Conversely, it must be less
157 * than the total size of misc_0, or else there's no room. It's
158 * possible this constant configures a partition between two
159 * parts of misc_0? We haven't investigated the functionality,
160 * as these buffers are internally used by the hardware
161 * (presumably by the tiler) but not seemingly touched by the driver
164 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
166 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
167 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
173 /* Are we currently rendering to the screen (rather than an FBO)? */
176 panfrost_is_scanout(struct panfrost_context
*ctx
)
178 /* If there is no color buffer, it's an FBO */
179 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
182 /* If we're too early that no framebuffer was sent, it's scanout */
183 if (!ctx
->pipe_framebuffer
.cbufs
[0])
186 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
187 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
188 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
192 pan_pack_color(const union pipe_color_union
*color
, enum pipe_format format
)
194 /* Alpha magicked to 1.0 if there is no alpha */
196 bool has_alpha
= util_format_has_alpha(format
);
197 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
199 /* Packed color depends on the framebuffer format */
201 const struct util_format_description
*desc
=
202 util_format_description(format
);
204 if (util_format_is_rgba8_variant(desc
)) {
205 return (float_to_ubyte(clear_alpha
) << 24) |
206 (float_to_ubyte(color
->f
[2]) << 16) |
207 (float_to_ubyte(color
->f
[1]) << 8) |
208 (float_to_ubyte(color
->f
[0]) << 0);
209 } else if (format
== PIPE_FORMAT_B5G6R5_UNORM
) {
210 /* First, we convert the components to R5, G6, B5 separately */
211 unsigned r5
= CLAMP(color
->f
[0], 0.0, 1.0) * 31.0;
212 unsigned g6
= CLAMP(color
->f
[1], 0.0, 1.0) * 63.0;
213 unsigned b5
= CLAMP(color
->f
[2], 0.0, 1.0) * 31.0;
215 /* Then we pack into a sparse u32. TODO: Why these shifts? */
216 return (b5
<< 25) | (g6
<< 14) | (r5
<< 5);
227 struct pipe_context
*pipe
,
229 const union pipe_color_union
*color
,
230 double depth
, unsigned stencil
)
232 struct panfrost_context
*ctx
= pan_context(pipe
);
233 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
235 if (buffers
& PIPE_CLEAR_COLOR
) {
236 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[0]->format
;
237 job
->clear_color
= pan_pack_color(color
, format
);
240 if (buffers
& PIPE_CLEAR_DEPTH
) {
241 job
->clear_depth
= depth
;
244 if (buffers
& PIPE_CLEAR_STENCIL
) {
245 job
->clear_stencil
= stencil
;
248 job
->clear
|= buffers
;
252 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
254 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
258 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
260 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
264 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
266 mali_ptr framebuffer
= ctx
->require_sfbd
?
267 panfrost_attach_vt_sfbd(ctx
) :
268 panfrost_attach_vt_mfbd(ctx
);
270 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
271 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
274 /* Reset per-frame context, called on context initialisation as well as after
275 * flushing a frame */
278 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
280 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
281 DBG("Uploaded transient %d bytes\n", transient_count
);
283 /* Rotate cmdstream */
284 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
285 ctx
->cmdstream_i
= 0;
287 if (ctx
->require_sfbd
)
288 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
290 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
292 /* Reset varyings allocated */
293 ctx
->varying_height
= 0;
295 /* The transient cmdstream is dirty every frame; the only bits worth preserving
296 * (textures, shaders, etc) are in other buffers anyways */
298 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
299 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
301 /* Regenerate payloads */
302 panfrost_attach_vt_framebuffer(ctx
);
305 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
308 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
310 /* Reset job counters */
312 ctx
->vertex_job_count
= 0;
313 ctx
->tiler_job_count
= 0;
316 /* In practice, every field of these payloads should be configurable
317 * arbitrarily, which means these functions are basically catch-all's for
318 * as-of-yet unwavering unknowns */
321 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
323 struct midgard_payload_vertex_tiler payload
= {
325 .workgroups_z_shift
= 32,
326 .workgroups_x_shift_2
= 0x2,
327 .workgroups_x_shift_3
= 0x5,
329 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
332 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
336 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
338 struct midgard_payload_vertex_tiler payload
= {
340 .workgroups_z_shift
= 32,
341 .workgroups_x_shift_2
= 0x2,
342 .workgroups_x_shift_3
= 0x6,
344 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
348 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
352 translate_tex_wrap(enum pipe_tex_wrap w
)
355 case PIPE_TEX_WRAP_REPEAT
:
356 return MALI_WRAP_REPEAT
;
358 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
359 return MALI_WRAP_CLAMP_TO_EDGE
;
361 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
362 return MALI_WRAP_CLAMP_TO_BORDER
;
364 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
365 return MALI_WRAP_MIRRORED_REPEAT
;
368 unreachable("Invalid wrap");
373 translate_tex_filter(enum pipe_tex_filter f
)
376 case PIPE_TEX_FILTER_NEAREST
:
379 case PIPE_TEX_FILTER_LINEAR
:
383 unreachable("Invalid filter");
388 translate_mip_filter(enum pipe_tex_mipfilter f
)
390 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
394 panfrost_translate_compare_func(enum pipe_compare_func in
)
397 case PIPE_FUNC_NEVER
:
398 return MALI_FUNC_NEVER
;
401 return MALI_FUNC_LESS
;
403 case PIPE_FUNC_EQUAL
:
404 return MALI_FUNC_EQUAL
;
406 case PIPE_FUNC_LEQUAL
:
407 return MALI_FUNC_LEQUAL
;
409 case PIPE_FUNC_GREATER
:
410 return MALI_FUNC_GREATER
;
412 case PIPE_FUNC_NOTEQUAL
:
413 return MALI_FUNC_NOTEQUAL
;
415 case PIPE_FUNC_GEQUAL
:
416 return MALI_FUNC_GEQUAL
;
418 case PIPE_FUNC_ALWAYS
:
419 return MALI_FUNC_ALWAYS
;
422 unreachable("Invalid func");
427 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
430 case PIPE_FUNC_NEVER
:
431 return MALI_ALT_FUNC_NEVER
;
434 return MALI_ALT_FUNC_LESS
;
436 case PIPE_FUNC_EQUAL
:
437 return MALI_ALT_FUNC_EQUAL
;
439 case PIPE_FUNC_LEQUAL
:
440 return MALI_ALT_FUNC_LEQUAL
;
442 case PIPE_FUNC_GREATER
:
443 return MALI_ALT_FUNC_GREATER
;
445 case PIPE_FUNC_NOTEQUAL
:
446 return MALI_ALT_FUNC_NOTEQUAL
;
448 case PIPE_FUNC_GEQUAL
:
449 return MALI_ALT_FUNC_GEQUAL
;
451 case PIPE_FUNC_ALWAYS
:
452 return MALI_ALT_FUNC_ALWAYS
;
455 unreachable("Invalid alt func");
460 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
463 case PIPE_STENCIL_OP_KEEP
:
464 return MALI_STENCIL_KEEP
;
466 case PIPE_STENCIL_OP_ZERO
:
467 return MALI_STENCIL_ZERO
;
469 case PIPE_STENCIL_OP_REPLACE
:
470 return MALI_STENCIL_REPLACE
;
472 case PIPE_STENCIL_OP_INCR
:
473 return MALI_STENCIL_INCR
;
475 case PIPE_STENCIL_OP_DECR
:
476 return MALI_STENCIL_DECR
;
478 case PIPE_STENCIL_OP_INCR_WRAP
:
479 return MALI_STENCIL_INCR_WRAP
;
481 case PIPE_STENCIL_OP_DECR_WRAP
:
482 return MALI_STENCIL_DECR_WRAP
;
484 case PIPE_STENCIL_OP_INVERT
:
485 return MALI_STENCIL_INVERT
;
488 unreachable("Invalid stencil op");
493 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
495 out
->ref
= 0; /* Gallium gets it from elsewhere */
497 out
->mask
= in
->valuemask
;
498 out
->func
= panfrost_translate_compare_func(in
->func
);
499 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
500 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
501 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
505 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
507 struct mali_shader_meta shader
= {
508 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
510 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
511 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
515 shader
.unknown2_4
|= 0x10;
518 struct pipe_stencil_state default_stencil
= {
520 .func
= PIPE_FUNC_ALWAYS
,
521 .fail_op
= MALI_STENCIL_KEEP
,
522 .zfail_op
= MALI_STENCIL_KEEP
,
523 .zpass_op
= MALI_STENCIL_KEEP
,
528 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
529 shader
.stencil_mask_front
= default_stencil
.writemask
;
531 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
532 shader
.stencil_mask_back
= default_stencil
.writemask
;
534 if (default_stencil
.enabled
)
535 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
537 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
541 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
543 if (first
->job_descriptor_size
)
544 first
->next_job_64
= (u64
) (uintptr_t) next
;
546 first
->next_job_32
= (u32
) (uintptr_t) next
;
549 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
550 * graphics command stream. It should be called once per draw, accordding to
551 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
552 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
555 struct panfrost_transfer
556 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
558 /* Each draw call corresponds to two jobs, and the set-value job is first */
559 int draw_job_index
= 1 + (2 * ctx
->draw_count
) + 1;
561 struct mali_job_descriptor_header job
= {
562 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
563 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
565 .job_descriptor_size
= 1,
569 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
571 /* There's some padding hacks on 32-bit */
578 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
581 /* Tiler jobs depend on vertex jobs */
583 job
.job_dependency_index_1
= draw_job_index
;
585 /* Tiler jobs also depend on the previous tiler job */
587 if (ctx
->draw_count
) {
588 job
.job_dependency_index_2
= draw_job_index
- 1;
589 /* Previous tiler job points to this tiler job */
590 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
592 /* The only vertex job so far points to first tiler job */
593 panfrost_link_job_pair(ctx
->u_vertex_jobs
[0], transfer
.gpu
);
596 if (ctx
->draw_count
) {
597 /* Previous vertex job points to this vertex job */
598 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
600 /* Last vertex job points to first tiler job */
601 panfrost_link_job_pair(&job
, ctx
->tiler_jobs
[0]);
603 /* Have the first vertex job depend on the set value job */
604 job
.job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
605 panfrost_link_job_pair(ctx
->u_set_value_job
, transfer
.gpu
);
609 memcpy(transfer
.cpu
, &job
, sizeof(job
));
610 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
614 /* Generates a set value job. It's unclear what exactly this does, why it's
615 * necessary, and when to call it. */
618 panfrost_set_value_job(struct panfrost_context
*ctx
)
620 struct mali_job_descriptor_header job
= {
621 .job_type
= JOB_TYPE_SET_VALUE
,
622 .job_descriptor_size
= 1,
626 struct mali_payload_set_value payload
= {
627 .out
= ctx
->misc_0
.gpu
,
631 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
632 memcpy(transfer
.cpu
, &job
, sizeof(job
));
633 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
635 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
636 ctx
->set_value_job
= transfer
.gpu
;
640 panfrost_emit_varyings(
641 struct panfrost_context
*ctx
,
642 union mali_attr
*slot
,
646 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
648 /* Fill out the descriptor */
649 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
650 slot
->stride
= stride
;
651 slot
->size
= stride
* count
;
653 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
654 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
656 return varying_address
;
660 panfrost_emit_point_coord(union mali_attr
*slot
)
662 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
663 slot
->stride
= slot
->size
= 0;
667 panfrost_emit_varying_descriptor(
668 struct panfrost_context
*ctx
,
669 unsigned invocation_count
)
671 /* Load the shaders */
673 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
674 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
676 /* Allocate the varying descriptor */
678 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
679 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
681 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
684 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
685 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
687 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
688 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
690 /* Buffer indices must be in this order per our convention */
691 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
694 /* General varyings -- use the VS's, since those are more likely to be
695 * accurate on desktop */
697 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
698 vs
->general_varying_stride
, invocation_count
);
700 /* fp32 vec4 gl_Position */
701 ctx
->payload_tiler
.postfix
.position_varying
=
702 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
703 sizeof(float) * 4, invocation_count
);
706 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
707 /* fp16 vec1 gl_PointSize */
708 ctx
->payload_tiler
.primitive_size
.pointer
=
709 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
710 2, invocation_count
);
713 if (fs
->reads_point_coord
) {
714 /* Special descriptor */
715 panfrost_emit_point_coord(&varyings
[idx
++]);
718 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
719 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
720 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
724 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
726 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
727 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
729 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
732 /* Emits attributes and varying descriptors, which should be called every draw,
733 * excepting some obscure circumstances */
736 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
738 /* Staged mali_attr, and index into them. i =/= k, depending on the
739 * vertex buffer mask */
740 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
743 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
745 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
746 if (!(ctx
->vb_mask
& (1 << i
))) continue;
748 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
749 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
753 /* Align to 64 bytes by masking off the lower bits. This
754 * will be adjusted back when we fixup the src_offset in
757 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
759 /* Offset vertex count by draw_start to make sure we upload enough */
760 attrs
[k
].stride
= buf
->stride
;
761 attrs
[k
].size
= rsrc
->base
.width0
;
763 panfrost_job_add_bo(job
, rsrc
->bo
);
764 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
769 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
771 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
775 panfrost_writes_point_size(struct panfrost_context
*ctx
)
778 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
780 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
783 /* Stage the attribute descriptors so we can adjust src_offset
784 * to let BOs align nicely */
787 panfrost_stage_attributes(struct panfrost_context
*ctx
)
789 struct panfrost_vertex_state
*so
= ctx
->vertex
;
791 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
792 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
793 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
795 /* Copy as-is for the first pass */
796 memcpy(target
, so
->hw
, sz
);
798 /* Fixup offsets for the second pass. Recall that the hardware
799 * calculates attribute addresses as:
801 * addr = base + (stride * vtx) + src_offset;
803 * However, on Mali, base must be aligned to 64-bytes, so we
806 * base' = base & ~63 = base - (base & 63)
808 * To compensate when using base' (see emit_vertex_data), we have
809 * to adjust src_offset by the masked off piece:
811 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
812 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
813 * = base + (stride * vtx) + src_offset
819 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
820 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
821 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
823 /* Adjust by the masked off bits of the offset */
824 target
[i
].src_offset
+= (addr
& 63);
827 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
831 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
833 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
835 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
836 if (!ctx
->sampler_count
[t
]) continue;
838 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
840 struct panfrost_transfer transfer
=
841 panfrost_allocate_transient(ctx
, transfer_size
);
843 struct mali_sampler_descriptor
*desc
=
844 (struct mali_sampler_descriptor
*) transfer
.cpu
;
846 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
847 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
849 if (t
== PIPE_SHADER_FRAGMENT
)
850 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
851 else if (t
== PIPE_SHADER_VERTEX
)
852 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
858 /* Computes the address to a texture at a particular slice */
861 panfrost_get_texture_address(
862 struct panfrost_resource
*rsrc
,
863 unsigned level
, unsigned face
)
865 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
866 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
868 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
874 struct panfrost_context
*ctx
,
875 struct panfrost_sampler_view
*view
)
878 return (mali_ptr
) NULL
;
880 struct pipe_resource
*tex_rsrc
= view
->base
.texture
;
881 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
883 /* Do we interleave an explicit stride with every element? */
885 bool has_manual_stride
=
886 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
888 /* Inject the addresses in, interleaving mip levels, cube faces, and
889 * strides in that order */
893 for (unsigned l
= 0; l
<= tex_rsrc
->last_level
; ++l
) {
894 for (unsigned f
= 0; f
< tex_rsrc
->array_size
; ++f
) {
895 view
->hw
.payload
[idx
++] =
896 panfrost_get_texture_address(rsrc
, l
, f
);
898 if (has_manual_stride
) {
899 view
->hw
.payload
[idx
++] =
900 rsrc
->bo
->slices
[l
].stride
;
905 return panfrost_upload_transient(ctx
, &view
->hw
,
906 sizeof(struct mali_texture_descriptor
));
910 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
912 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
914 if (!ctx
->sampler_view_count
[t
]) continue;
916 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
918 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
920 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
922 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
924 if (t
== PIPE_SHADER_FRAGMENT
)
925 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
926 else if (t
== PIPE_SHADER_VERTEX
)
927 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
933 /* Go through dirty flags and actualise them in the cmdstream. */
936 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
938 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
940 if (with_vertex_data
) {
941 panfrost_emit_vertex_data(ctx
, job
);
944 bool msaa
= ctx
->rasterizer
->base
.multisample
;
946 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
947 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
949 /* TODO: Sample size */
950 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
951 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
954 /* Enable job requirements at draw-time */
957 job
->requirements
|= PAN_REQ_MSAA
;
959 if (ctx
->depth_stencil
->depth
.writemask
)
960 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
962 if (ctx
->occlusion_query
) {
963 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
964 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
967 if (ctx
->dirty
& PAN_DIRTY_VS
) {
970 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
972 /* Late shader descriptor assignments */
974 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
975 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
978 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
980 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
983 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
984 /* Check if we need to link the gl_PointSize varying */
985 if (!panfrost_writes_point_size(ctx
)) {
986 /* If the size is constant, write it out. Otherwise,
987 * don't touch primitive_size (since we would clobber
988 * the pointer there) */
990 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
994 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
996 ctx
->dirty
|= PAN_DIRTY_FS
;
998 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1000 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1002 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1005 COPY(attribute_count
);
1006 COPY(varying_count
);
1007 COPY(midgard1
.uniform_count
);
1008 COPY(midgard1
.work_count
);
1009 COPY(midgard1
.unknown2
);
1012 /* If there is a blend shader, work registers are shared */
1014 if (ctx
->blend
->has_blend_shader
)
1015 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1017 /* Set late due to depending on render state */
1018 /* The one at the end seems to mean "1 UBO" */
1019 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
1021 /* Assign texture/sample count right before upload */
1022 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1023 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1025 /* Assign the stencil refs late */
1026 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1027 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1029 /* CAN_DISCARD should be set if the fragment shader possibly
1030 * contains a 'discard' instruction. It is likely this is
1031 * related to optimizations related to forward-pixel kill, as
1032 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1033 * thing?" by Peter Harris
1036 if (variant
->can_discard
) {
1037 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1038 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1039 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1040 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1043 /* Check if we're using the default blend descriptor (fast path) */
1046 !ctx
->blend
->has_blend_shader
&&
1047 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1048 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1049 (ctx
->blend
->equation
.color_mask
== 0xf);
1051 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1052 * *also* copied to the blend_meta appended (by convention),
1053 * but this is the field actually read by the hardware. (Or
1054 * maybe both are read...?) */
1056 if (ctx
->blend
->has_blend_shader
) {
1057 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1060 if (ctx
->require_sfbd
) {
1061 /* When only a single render target platform is used, the blend
1062 * information is inside the shader meta itself. We
1063 * additionally need to signal CAN_DISCARD for nontrivial blend
1064 * modes (so we're able to read back the destination buffer) */
1066 if (!ctx
->blend
->has_blend_shader
) {
1067 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1068 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1072 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1076 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1077 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1078 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1080 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1082 if (!ctx
->require_sfbd
) {
1083 /* Additional blend descriptor tacked on for jobs using MFBD */
1085 unsigned blend_count
= 0x200;
1087 if (ctx
->blend
->has_blend_shader
) {
1088 /* For a blend shader, the bottom nibble corresponds to
1089 * the number of work registers used, which signals the
1090 * -existence- of a blend shader */
1092 assert(ctx
->blend
->blend_work_count
>= 2);
1093 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1095 /* Otherwise, the bottom bit simply specifies if
1096 * blending (anything other than REPLACE) is enabled */
1103 struct midgard_blend_rt rts
[4];
1107 for (unsigned i
= 0; i
< 1; ++i
) {
1108 rts
[i
].flags
= blend_count
;
1110 if (ctx
->blend
->has_blend_shader
) {
1111 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1113 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1114 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1118 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1122 /* We stage to transient, so always dirty.. */
1123 panfrost_stage_attributes(ctx
);
1125 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1126 panfrost_upload_sampler_descriptors(ctx
);
1128 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1129 panfrost_upload_texture_descriptors(ctx
);
1131 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1133 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1134 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1136 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1137 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1138 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1140 /* Allocate room for the sysval and the uniforms */
1141 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1142 size_t size
= sys_size
+ buf
->size
;
1143 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1145 /* Upload sysvals requested by the shader */
1146 float *uniforms
= (float *) transfer
.cpu
;
1147 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1148 int sysval
= ss
->sysval
[i
];
1150 if (sysval
== PAN_SYSVAL_VIEWPORT_SCALE
) {
1151 uniforms
[4*i
+ 0] = vp
->scale
[0];
1152 uniforms
[4*i
+ 1] = vp
->scale
[1];
1153 uniforms
[4*i
+ 2] = vp
->scale
[2];
1154 } else if (sysval
== PAN_SYSVAL_VIEWPORT_OFFSET
) {
1155 uniforms
[4*i
+ 0] = vp
->translate
[0];
1156 uniforms
[4*i
+ 1] = vp
->translate
[1];
1157 uniforms
[4*i
+ 2] = vp
->translate
[2];
1163 /* Upload uniforms */
1164 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1166 int uniform_count
= 0;
1168 struct mali_vertex_tiler_postfix
*postfix
;
1171 case PIPE_SHADER_VERTEX
:
1172 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1173 postfix
= &ctx
->payload_vertex
.postfix
;
1176 case PIPE_SHADER_FRAGMENT
:
1177 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1178 postfix
= &ctx
->payload_tiler
.postfix
;
1182 unreachable("Invalid shader stage\n");
1185 /* Also attach the same buffer as a UBO for extended access */
1187 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1189 .size
= MALI_POSITIVE((2 + uniform_count
)),
1190 .ptr
= transfer
.gpu
>> 2,
1194 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1195 postfix
->uniforms
= transfer
.gpu
;
1196 postfix
->uniform_buffers
= ubufs
;
1201 /* TODO: Upload the viewport somewhere more appropriate */
1203 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1204 * (somewhat) asymmetric ints. */
1205 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1207 struct mali_viewport view
= {
1208 /* By default, do no viewport clipping, i.e. clip to (-inf,
1209 * inf) in each direction. Clipping to the viewport in theory
1210 * should work, but in practice causes issues when we're not
1211 * explicitly trying to scissor */
1222 /* Always scissor to the viewport by default. */
1223 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1224 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1226 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1227 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1229 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1230 view
.viewport0
[0] = ss
->minx
;
1231 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1237 /* Hardware needs the min/max to be strictly ordered, so flip if we
1245 view
.viewport0
[1] = miny
;
1246 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1248 ctx
->payload_tiler
.postfix
.viewport
=
1249 panfrost_upload_transient(ctx
,
1251 sizeof(struct mali_viewport
));
1256 /* Corresponds to exactly one draw, but does not submit anything */
1259 panfrost_queue_draw(struct panfrost_context
*ctx
)
1261 /* TODO: Expand the array? */
1262 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1263 DBG("Job buffer overflow, ignoring draw\n");
1267 /* Handle dirty flags now */
1268 panfrost_emit_for_draw(ctx
, true);
1270 /* We need a set_value job before any other draw jobs */
1271 if (ctx
->draw_count
== 0)
1272 panfrost_set_value_job(ctx
);
1274 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1275 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1276 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1278 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true);
1279 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1280 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1285 /* The entire frame is in memory -- send it off to the kernel! */
1288 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1289 struct pipe_fence_handle
**fence
,
1290 struct panfrost_job
*job
)
1292 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1293 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1295 /* Edge case if screen is cleared and nothing else */
1296 bool has_draws
= ctx
->draw_count
> 0;
1298 /* Workaround a bizarre lockup (a hardware errata?) */
1300 flush_immediate
= true;
1304 bool is_scanout
= panfrost_is_scanout(ctx
);
1305 screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1307 /* If visual, we can stall a frame */
1309 if (!flush_immediate
)
1310 screen
->driver
->force_flush_fragment(ctx
, fence
);
1312 screen
->last_fragment_flushed
= false;
1313 screen
->last_job
= job
;
1315 /* If readback, flush now (hurts the pipelined performance) */
1316 if (flush_immediate
)
1317 screen
->driver
->force_flush_fragment(ctx
, fence
);
1319 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1320 screen
->driver
->dump_counters(screen
);
1323 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1324 FILE *fp
= fopen(filename
, "wb");
1325 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1333 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1335 struct panfrost_context
*ctx
= pan_context(pipe
);
1337 /* Nothing to reload? */
1338 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1341 /* Blit the wallpaper in */
1342 panfrost_blit_wallpaper(ctx
);
1344 /* We are flushing all queued draws and we know that no more jobs will
1345 * be added until the next frame.
1346 * We also know that the last jobs are the wallpaper jobs, and they
1347 * need to be linked so they execute right after the set_value job.
1350 /* set_value job to wallpaper vertex job */
1351 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[ctx
->vertex_job_count
- 1]);
1352 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1354 /* wallpaper vertex job to first vertex job */
1355 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1], ctx
->vertex_jobs
[0]);
1356 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1358 /* last vertex job to wallpaper tiler job */
1359 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 2], ctx
->tiler_jobs
[ctx
->tiler_job_count
- 1]);
1360 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_1
= ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_index
;
1361 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_2
= 0;
1363 /* wallpaper tiler job to first tiler job */
1364 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1], ctx
->tiler_jobs
[0]);
1365 ctx
->u_tiler_jobs
[0]->job_dependency_index_1
= ctx
->u_vertex_jobs
[0]->job_index
;
1366 ctx
->u_tiler_jobs
[0]->job_dependency_index_2
= ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_index
;
1368 /* last tiler job to NULL */
1369 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 2], 0);
1374 struct pipe_context
*pipe
,
1375 struct pipe_fence_handle
**fence
,
1378 struct panfrost_context
*ctx
= pan_context(pipe
);
1379 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1381 /* Nothing to do! */
1382 if (!ctx
->draw_count
&& !job
->clear
) return;
1385 panfrost_draw_wallpaper(&ctx
->base
);
1387 /* Whether to stall the pipeline for immediately correct results */
1388 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1390 /* Submit the frame itself */
1391 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1393 /* Prepare for the next frame */
1394 panfrost_invalidate_frame(ctx
);
1397 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1400 g2m_draw_mode(enum pipe_prim_type mode
)
1403 DEFINE_CASE(POINTS
);
1405 DEFINE_CASE(LINE_LOOP
);
1406 DEFINE_CASE(LINE_STRIP
);
1407 DEFINE_CASE(TRIANGLES
);
1408 DEFINE_CASE(TRIANGLE_STRIP
);
1409 DEFINE_CASE(TRIANGLE_FAN
);
1411 DEFINE_CASE(QUAD_STRIP
);
1412 DEFINE_CASE(POLYGON
);
1415 unreachable("Invalid draw mode");
1422 panfrost_translate_index_size(unsigned size
)
1426 return MALI_DRAW_INDEXED_UINT8
;
1429 return MALI_DRAW_INDEXED_UINT16
;
1432 return MALI_DRAW_INDEXED_UINT32
;
1435 unreachable("Invalid index size");
1439 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1440 * good for the duration of the draw (transient), could last longer */
1443 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1445 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1447 off_t offset
= info
->start
* info
->index_size
;
1449 if (!info
->has_user_indices
) {
1450 /* Only resources can be directly mapped */
1451 return rsrc
->bo
->gpu
+ offset
;
1453 /* Otherwise, we need to upload to transient memory */
1454 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1455 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1461 struct pipe_context
*pipe
,
1462 const struct pipe_draw_info
*info
)
1464 struct panfrost_context
*ctx
= pan_context(pipe
);
1466 ctx
->payload_vertex
.draw_start
= info
->start
;
1467 ctx
->payload_tiler
.draw_start
= info
->start
;
1469 int mode
= info
->mode
;
1471 /* Fallback for unsupported modes */
1473 if (!(ctx
->draw_modes
& (1 << mode
))) {
1474 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1475 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1477 if (info
->count
< 4) {
1478 /* Degenerate case? */
1482 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1483 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1488 /* Now that we have a guaranteed terminating path, find the job.
1489 * Assignment commented out to prevent unused warning */
1491 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1493 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1495 ctx
->vertex_count
= info
->count
;
1497 /* For non-indexed draws, they're the same */
1498 unsigned invocation_count
= ctx
->vertex_count
;
1500 unsigned draw_flags
= 0;
1502 /* The draw flags interpret how primitive size is interpreted */
1504 if (panfrost_writes_point_size(ctx
))
1505 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1507 /* For higher amounts of vertices (greater than what fits in a 16-bit
1508 * short), the other value is needed, otherwise there will be bizarre
1509 * rendering artefacts. It's not clear what these values mean yet. */
1511 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1513 if (info
->index_size
) {
1514 /* Calculate the min/max index used so we can figure out how
1515 * many times to invoke the vertex shader */
1517 /* Fetch / calculate index bounds */
1518 unsigned min_index
= 0, max_index
= 0;
1520 if (info
->max_index
== ~0u) {
1521 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1523 min_index
= info
->min_index
;
1524 max_index
= info
->max_index
;
1527 /* Use the corresponding values */
1528 invocation_count
= max_index
- min_index
+ 1;
1529 ctx
->payload_vertex
.draw_start
= min_index
;
1530 ctx
->payload_tiler
.draw_start
= min_index
;
1532 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1533 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1535 //assert(!info->restart_index); /* TODO: Research */
1536 assert(!info
->index_bias
);
1538 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1539 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1541 /* Index count == vertex count, if no indexing is applied, as
1542 * if it is internally indexed in the expected order */
1544 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1545 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1547 /* Reverse index state */
1548 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1551 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1552 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1553 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1555 /* Fire off the draw itself */
1556 panfrost_queue_draw(ctx
);
1562 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1568 panfrost_create_rasterizer_state(
1569 struct pipe_context
*pctx
,
1570 const struct pipe_rasterizer_state
*cso
)
1572 struct panfrost_context
*ctx
= pan_context(pctx
);
1573 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1577 /* Bitmask, unknown meaning of the start value */
1578 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1581 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1583 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1584 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1586 if (cso
->cull_face
& PIPE_FACE_BACK
)
1587 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1593 panfrost_bind_rasterizer_state(
1594 struct pipe_context
*pctx
,
1597 struct panfrost_context
*ctx
= pan_context(pctx
);
1599 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1603 ctx
->rasterizer
= hwcso
;
1604 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1608 panfrost_create_vertex_elements_state(
1609 struct pipe_context
*pctx
,
1610 unsigned num_elements
,
1611 const struct pipe_vertex_element
*elements
)
1613 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1615 so
->num_elements
= num_elements
;
1616 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1618 /* XXX: What the cornball? This is totally, 100%, unapologetically
1619 * nonsense. And yet it somehow fixes a regression in -bshadow
1620 * (previously, we allocated the descriptor here... a newer commit
1621 * removed that allocation, and then memory corruption led to
1622 * shader_meta getting overwritten in bad ways and then the whole test
1623 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1625 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1627 for (int i
= 0; i
< num_elements
; ++i
) {
1628 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1630 enum pipe_format fmt
= elements
[i
].src_format
;
1631 const struct util_format_description
*desc
= util_format_description(fmt
);
1632 so
->hw
[i
].unknown1
= 0x2;
1633 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1635 so
->hw
[i
].format
= panfrost_find_format(desc
);
1637 /* The field itself should probably be shifted over */
1638 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1645 panfrost_bind_vertex_elements_state(
1646 struct pipe_context
*pctx
,
1649 struct panfrost_context
*ctx
= pan_context(pctx
);
1651 ctx
->vertex
= hwcso
;
1652 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1656 panfrost_create_shader_state(
1657 struct pipe_context
*pctx
,
1658 const struct pipe_shader_state
*cso
)
1660 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1663 /* Token deep copy to prevent memory corruption */
1665 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1666 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1672 panfrost_delete_shader_state(
1673 struct pipe_context
*pctx
,
1676 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1678 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1679 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1686 panfrost_create_sampler_state(
1687 struct pipe_context
*pctx
,
1688 const struct pipe_sampler_state
*cso
)
1690 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1693 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1695 struct mali_sampler_descriptor sampler_descriptor
= {
1696 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1697 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1698 | translate_mip_filter(cso
->min_mip_filter
)
1701 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1702 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1703 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1704 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1706 cso
->border_color
.f
[0],
1707 cso
->border_color
.f
[1],
1708 cso
->border_color
.f
[2],
1709 cso
->border_color
.f
[3]
1711 .min_lod
= FIXED_16(cso
->min_lod
),
1712 .max_lod
= FIXED_16(cso
->max_lod
),
1716 so
->hw
= sampler_descriptor
;
1722 panfrost_bind_sampler_states(
1723 struct pipe_context
*pctx
,
1724 enum pipe_shader_type shader
,
1725 unsigned start_slot
, unsigned num_sampler
,
1728 assert(start_slot
== 0);
1730 struct panfrost_context
*ctx
= pan_context(pctx
);
1732 /* XXX: Should upload, not just copy? */
1733 ctx
->sampler_count
[shader
] = num_sampler
;
1734 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1736 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1740 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
1742 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1744 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
1745 /* Make sure enable state is at least the same */
1746 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1750 /* Check that the contents of the test are the same */
1751 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1752 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1754 if (!(same_func
&& same_ref
)) {
1758 /* Otherwise, we're good to go */
1763 panfrost_bind_fs_state(
1764 struct pipe_context
*pctx
,
1767 struct panfrost_context
*ctx
= pan_context(pctx
);
1772 /* Match the appropriate variant */
1774 signed variant
= -1;
1776 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1778 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1779 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
1785 if (variant
== -1) {
1786 /* No variant matched, so create a new one */
1787 variant
= variants
->variant_count
++;
1788 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1790 variants
->variants
[variant
].base
= hwcso
;
1791 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1793 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
1794 struct panfrost_context
*ctx
= pan_context(pctx
);
1795 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1797 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1798 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1802 /* Select this variant */
1803 variants
->active_variant
= variant
;
1805 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1806 assert(panfrost_variant_matches(ctx
, shader_state
));
1808 /* Now we have a variant selected, so compile and go */
1810 if (!shader_state
->compiled
) {
1811 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
1812 shader_state
->compiled
= true;
1816 ctx
->dirty
|= PAN_DIRTY_FS
;
1820 panfrost_bind_vs_state(
1821 struct pipe_context
*pctx
,
1824 struct panfrost_context
*ctx
= pan_context(pctx
);
1829 if (!ctx
->vs
->variants
[0].compiled
) {
1830 ctx
->vs
->variants
[0].base
= hwcso
;
1832 /* TODO DRY from above */
1833 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1834 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1835 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
1837 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
1838 ctx
->vs
->variants
[0].compiled
= true;
1842 ctx
->dirty
|= PAN_DIRTY_VS
;
1846 panfrost_set_vertex_buffers(
1847 struct pipe_context
*pctx
,
1848 unsigned start_slot
,
1849 unsigned num_buffers
,
1850 const struct pipe_vertex_buffer
*buffers
)
1852 struct panfrost_context
*ctx
= pan_context(pctx
);
1854 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1858 panfrost_set_constant_buffer(
1859 struct pipe_context
*pctx
,
1860 enum pipe_shader_type shader
, uint index
,
1861 const struct pipe_constant_buffer
*buf
)
1863 struct panfrost_context
*ctx
= pan_context(pctx
);
1864 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1866 size_t sz
= buf
? buf
->buffer_size
: 0;
1868 /* Free previous buffer */
1875 pbuf
->buffer
= NULL
;
1878 /* If unbinding, we're done */
1883 /* Multiple constant buffers not yet supported */
1888 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1891 cpu
= rsrc
->bo
->cpu
;
1892 } else if (buf
->user_buffer
) {
1893 cpu
= buf
->user_buffer
;
1895 DBG("No constant buffer?\n");
1899 /* Copy the constant buffer into the driver context for later upload */
1901 pbuf
->buffer
= malloc(sz
);
1902 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1906 panfrost_set_stencil_ref(
1907 struct pipe_context
*pctx
,
1908 const struct pipe_stencil_ref
*ref
)
1910 struct panfrost_context
*ctx
= pan_context(pctx
);
1911 ctx
->stencil_ref
= *ref
;
1913 /* Shader core dirty */
1914 ctx
->dirty
|= PAN_DIRTY_FS
;
1917 static struct pipe_sampler_view
*
1918 panfrost_create_sampler_view(
1919 struct pipe_context
*pctx
,
1920 struct pipe_resource
*texture
,
1921 const struct pipe_sampler_view
*template)
1923 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1924 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1926 pipe_reference(NULL
, &texture
->reference
);
1928 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1931 so
->base
= *template;
1932 so
->base
.texture
= texture
;
1933 so
->base
.reference
.count
= 1;
1934 so
->base
.context
= pctx
;
1936 /* sampler_views correspond to texture descriptors, minus the texture
1937 * (data) itself. So, we serialise the descriptor here and cache it for
1940 /* Make sure it's something with which we're familiar */
1941 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1943 /* TODO: Detect from format better */
1944 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1946 unsigned char user_swizzle
[4] = {
1947 template->swizzle_r
,
1948 template->swizzle_g
,
1949 template->swizzle_b
,
1953 enum mali_format format
= panfrost_find_format(desc
);
1955 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
1957 unsigned usage2_layout
= 0x10;
1959 switch (prsrc
->bo
->layout
) {
1961 usage2_layout
|= 0x8 | 0x4;
1964 usage2_layout
|= 0x1;
1967 usage2_layout
|= is_depth
? 0x1 : 0x2;
1974 /* Check if we need to set a custom stride by computing the "expected"
1975 * stride and comparing it to what the BO actually wants. Only applies
1976 * to linear textures, since tiled/compressed textures have strict
1977 * alignment requirements for their strides as it is */
1979 unsigned first_level
= template->u
.tex
.first_level
;
1980 unsigned last_level
= template->u
.tex
.last_level
;
1982 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
1983 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
1984 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
1985 unsigned width
= u_minify(texture
->width0
, l
);
1986 unsigned comp_stride
= width
* bytes_per_pixel
;
1988 if (comp_stride
!= actual_stride
) {
1989 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
1995 struct mali_texture_descriptor texture_descriptor
= {
1996 .width
= MALI_POSITIVE(texture
->width0
),
1997 .height
= MALI_POSITIVE(texture
->height0
),
1998 .depth
= MALI_POSITIVE(texture
->depth0
),
2002 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2006 .is_not_cubemap
= texture
->target
!= PIPE_TEXTURE_CUBE
,
2008 .usage2
= usage2_layout
2011 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2014 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2015 assert (template->u
.tex
.first_level
== 0);
2017 /* Disable mipmapping for now to avoid regressions while automipmapping
2018 * is being implemented. TODO: Remove me once automipmaps work */
2020 //texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2021 texture_descriptor
.nr_mipmap_levels
= 0;
2023 so
->hw
= texture_descriptor
;
2025 return (struct pipe_sampler_view
*) so
;
2029 panfrost_set_sampler_views(
2030 struct pipe_context
*pctx
,
2031 enum pipe_shader_type shader
,
2032 unsigned start_slot
, unsigned num_views
,
2033 struct pipe_sampler_view
**views
)
2035 struct panfrost_context
*ctx
= pan_context(pctx
);
2037 assert(start_slot
== 0);
2039 ctx
->sampler_view_count
[shader
] = num_views
;
2040 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2042 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2046 panfrost_sampler_view_destroy(
2047 struct pipe_context
*pctx
,
2048 struct pipe_sampler_view
*view
)
2050 pipe_resource_reference(&view
->texture
, NULL
);
2055 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2056 const struct pipe_framebuffer_state
*fb
)
2058 struct panfrost_context
*ctx
= pan_context(pctx
);
2060 /* Flush when switching away from an FBO, but not if the framebuffer
2061 * state is being restored by u_blitter
2064 if (!panfrost_is_scanout(ctx
) && !ctx
->blitter
->running
) {
2065 panfrost_flush(pctx
, NULL
, 0);
2068 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2069 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2070 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2071 ctx
->pipe_framebuffer
.width
= fb
->width
;
2072 ctx
->pipe_framebuffer
.height
= fb
->height
;
2074 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2075 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2077 /* check if changing cbuf */
2078 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2080 if (cb
&& (i
!= 0)) {
2081 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2086 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2091 if (ctx
->require_sfbd
)
2092 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2094 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2096 panfrost_attach_vt_framebuffer(ctx
);
2098 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2099 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2101 bool can_afbc
= panfrost_format_supports_afbc(format
);
2102 bool is_scanout
= panfrost_is_scanout(ctx
);
2104 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2105 panfrost_enable_afbc(ctx
, tex
, false);
2107 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2108 panfrost_enable_checksum(ctx
, tex
);
2112 struct pipe_surface
*zb
= fb
->zsbuf
;
2114 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2115 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2118 if (ctx
->require_sfbd
)
2119 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2121 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2123 panfrost_attach_vt_framebuffer(ctx
);
2125 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2126 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2127 bool is_scanout
= panfrost_is_scanout(ctx
);
2129 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2130 panfrost_enable_afbc(ctx
, tex
, true);
2137 panfrost_create_blend_state(struct pipe_context
*pipe
,
2138 const struct pipe_blend_state
*blend
)
2140 struct panfrost_context
*ctx
= pan_context(pipe
);
2141 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2144 /* TODO: The following features are not yet implemented */
2145 assert(!blend
->logicop_enable
);
2146 assert(!blend
->alpha_to_coverage
);
2147 assert(!blend
->alpha_to_one
);
2149 /* Compile the blend state, first as fixed-function if we can */
2151 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2154 /* If we can't, compile a blend shader instead */
2156 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2162 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2165 struct panfrost_context
*ctx
= pan_context(pipe
);
2166 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2167 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2168 ctx
->blend
= pblend
;
2173 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2175 /* TODO: Attach color */
2177 /* Shader itself is not dirty, but the shader core is */
2178 ctx
->dirty
|= PAN_DIRTY_FS
;
2182 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2185 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2187 if (so
->has_blend_shader
) {
2188 DBG("Deleting blend state leak blend shaders bytecode\n");
2195 panfrost_set_blend_color(struct pipe_context
*pipe
,
2196 const struct pipe_blend_color
*blend_color
)
2198 struct panfrost_context
*ctx
= pan_context(pipe
);
2200 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2203 ctx
->blend_color
= *blend_color
;
2205 /* The blend mode depends on the blend constant color, due to the
2206 * fixed/programmable split. So, we're forced to regenerate the blend
2209 /* TODO: Attach color */
2214 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2215 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2217 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2221 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2224 struct panfrost_context
*ctx
= pan_context(pipe
);
2225 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2226 ctx
->depth_stencil
= depth_stencil
;
2231 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2232 * emulated in the fragment shader */
2234 if (depth_stencil
->alpha
.enabled
) {
2235 /* We need to trigger a new shader (maybe) */
2236 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2240 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2242 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2243 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2245 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2246 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2248 /* Depth state (TODO: Refactor) */
2249 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2251 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2253 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2254 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2256 /* Bounds test not implemented */
2257 assert(!depth_stencil
->depth
.bounds_test
);
2259 ctx
->dirty
|= PAN_DIRTY_FS
;
2263 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2269 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2270 unsigned sample_mask
)
2275 panfrost_set_clip_state(struct pipe_context
*pipe
,
2276 const struct pipe_clip_state
*clip
)
2278 //struct panfrost_context *panfrost = pan_context(pipe);
2282 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2283 unsigned start_slot
,
2284 unsigned num_viewports
,
2285 const struct pipe_viewport_state
*viewports
)
2287 struct panfrost_context
*ctx
= pan_context(pipe
);
2289 assert(start_slot
== 0);
2290 assert(num_viewports
== 1);
2292 ctx
->pipe_viewport
= *viewports
;
2296 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2297 unsigned start_slot
,
2298 unsigned num_scissors
,
2299 const struct pipe_scissor_state
*scissors
)
2301 struct panfrost_context
*ctx
= pan_context(pipe
);
2303 assert(start_slot
== 0);
2304 assert(num_scissors
== 1);
2306 ctx
->scissor
= *scissors
;
2310 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2311 const struct pipe_poly_stipple
*stipple
)
2313 //struct panfrost_context *panfrost = pan_context(pipe);
2317 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2320 //struct panfrost_context *panfrost = pan_context(pipe);
2324 panfrost_destroy(struct pipe_context
*pipe
)
2326 struct panfrost_context
*panfrost
= pan_context(pipe
);
2327 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2329 if (panfrost
->blitter
)
2330 util_blitter_destroy(panfrost
->blitter
);
2332 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2333 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2334 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2335 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2336 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2339 static struct pipe_query
*
2340 panfrost_create_query(struct pipe_context
*pipe
,
2344 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2349 return (struct pipe_query
*) q
;
2353 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2359 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2361 struct panfrost_context
*ctx
= pan_context(pipe
);
2362 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2364 switch (query
->type
) {
2365 case PIPE_QUERY_OCCLUSION_COUNTER
:
2366 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2367 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2369 /* Allocate a word for the query results to be stored */
2370 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2372 ctx
->occlusion_query
= query
;
2378 DBG("Skipping query %d\n", query
->type
);
2386 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2388 struct panfrost_context
*ctx
= pan_context(pipe
);
2389 ctx
->occlusion_query
= NULL
;
2394 panfrost_get_query_result(struct pipe_context
*pipe
,
2395 struct pipe_query
*q
,
2397 union pipe_query_result
*vresult
)
2400 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2402 /* We need to flush out the jobs to actually run the counter, TODO
2403 * check wait, TODO wallpaper after if needed */
2405 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2407 switch (query
->type
) {
2408 case PIPE_QUERY_OCCLUSION_COUNTER
:
2409 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2410 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2411 /* Read back the query results */
2412 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2413 unsigned passed
= *result
;
2415 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2416 vresult
->u64
= passed
;
2418 vresult
->b
= !!passed
;
2424 DBG("Skipped query get %d\n", query
->type
);
2431 static struct pipe_stream_output_target
*
2432 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2433 struct pipe_resource
*prsc
,
2434 unsigned buffer_offset
,
2435 unsigned buffer_size
)
2437 struct pipe_stream_output_target
*target
;
2439 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2444 pipe_reference_init(&target
->reference
, 1);
2445 pipe_resource_reference(&target
->buffer
, prsc
);
2447 target
->context
= pctx
;
2448 target
->buffer_offset
= buffer_offset
;
2449 target
->buffer_size
= buffer_size
;
2455 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2456 struct pipe_stream_output_target
*target
)
2458 pipe_resource_reference(&target
->buffer
, NULL
);
2463 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2464 unsigned num_targets
,
2465 struct pipe_stream_output_target
**targets
,
2466 const unsigned *offsets
)
2472 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2474 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2475 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2477 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2478 /* Allocate the beginning of the transient pool */
2479 int entry_size
= (1 << 22); /* 4MB */
2481 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2482 ctx
->transient_pools
[i
].entry_count
= 1;
2484 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2487 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2488 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2489 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2490 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2491 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2495 /* New context creation, which also does hardware initialisation since I don't
2496 * know the better way to structure this :smirk: */
2498 struct pipe_context
*
2499 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2501 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2502 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2503 memset(ctx
, 0, sizeof(*ctx
));
2504 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2507 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2509 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2510 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2512 gallium
->screen
= screen
;
2514 gallium
->destroy
= panfrost_destroy
;
2516 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2518 gallium
->flush
= panfrost_flush
;
2519 gallium
->clear
= panfrost_clear
;
2520 gallium
->draw_vbo
= panfrost_draw_vbo
;
2522 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2523 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2525 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2527 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2528 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2529 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2531 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2532 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2533 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2535 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2536 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2537 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2539 gallium
->create_fs_state
= panfrost_create_shader_state
;
2540 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2541 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2543 gallium
->create_vs_state
= panfrost_create_shader_state
;
2544 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2545 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2547 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2548 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2549 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2551 gallium
->create_blend_state
= panfrost_create_blend_state
;
2552 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2553 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2555 gallium
->set_blend_color
= panfrost_set_blend_color
;
2557 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2558 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2559 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2561 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2563 gallium
->set_clip_state
= panfrost_set_clip_state
;
2564 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2565 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2566 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2567 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2569 gallium
->create_query
= panfrost_create_query
;
2570 gallium
->destroy_query
= panfrost_destroy_query
;
2571 gallium
->begin_query
= panfrost_begin_query
;
2572 gallium
->end_query
= panfrost_end_query
;
2573 gallium
->get_query_result
= panfrost_get_query_result
;
2575 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2576 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2577 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2579 panfrost_resource_context_init(gallium
);
2581 pscreen
->driver
->init_context(ctx
);
2583 panfrost_setup_hardware(ctx
);
2586 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2587 gallium
->const_uploader
= gallium
->stream_uploader
;
2588 assert(gallium
->stream_uploader
);
2590 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2591 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2593 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2595 ctx
->blitter
= util_blitter_create(gallium
);
2596 assert(ctx
->blitter
);
2598 /* Prepare for render! */
2600 panfrost_job_init(ctx
);
2601 panfrost_emit_vertex_payload(ctx
);
2602 panfrost_emit_tiler_payload(ctx
);
2603 panfrost_invalidate_frame(ctx
);
2604 panfrost_default_shader_backend(ctx
);
2605 panfrost_generate_space_filler_indices();