2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
34 #include "util/macros.h"
35 #include "util/u_format.h"
36 #include "util/u_inlines.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_memory.h"
39 #include "util/u_vbuf.h"
40 #include "util/half_float.h"
41 #include "util/u_helpers.h"
42 #include "util/u_format.h"
43 #include "util/u_prim.h"
44 #include "util/u_prim_restart.h"
45 #include "indices/u_primconvert.h"
46 #include "tgsi/tgsi_parse.h"
47 #include "tgsi/tgsi_from_mesa.h"
48 #include "util/u_math.h"
50 #include "pan_screen.h"
51 #include "pan_blending.h"
52 #include "pan_blend_shaders.h"
55 /* Framebuffer descriptor */
57 static struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
61 struct midgard_tiler_descriptor t
= {};
62 unsigned height
= batch
->key
.height
;
63 unsigned width
= batch
->key
.width
;
66 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
68 /* Compute the polygon header size and use that to offset the body */
70 unsigned header_size
= panfrost_tiler_header_size(
71 width
, height
, t
.hierarchy_mask
);
73 t
.polygon_list_size
= panfrost_tiler_full_size(
74 width
, height
, t
.hierarchy_mask
);
78 if (t
.hierarchy_mask
) {
79 struct panfrost_bo
*tiler_heap
;
81 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
82 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
87 /* Allow the entire tiler heap */
88 t
.heap_start
= tiler_heap
->gpu
;
89 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
91 struct panfrost_bo
*tiler_dummy
;
93 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
95 /* The tiler is disabled, so don't allow the tiler heap */
96 t
.heap_start
= tiler_dummy
->gpu
;
97 t
.heap_end
= t
.heap_start
;
99 /* Use a dummy polygon list */
100 t
.polygon_list
= tiler_dummy
->gpu
;
102 /* Disable the tiler */
103 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
105 if (screen
->require_sfbd
) {
106 t
.hierarchy_mask
= 0xFFF; /* TODO: What's this? */
107 t
.polygon_list_size
= 0x200;
109 /* We don't have a SET_VALUE job, so write the polygon list manually */
110 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
111 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
115 t
.polygon_list_body
=
116 t
.polygon_list
+ header_size
;
121 struct mali_single_framebuffer
122 panfrost_emit_sfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
124 unsigned width
= batch
->key
.width
;
125 unsigned height
= batch
->key
.height
;
127 struct mali_single_framebuffer framebuffer
= {
128 .width
= MALI_POSITIVE(width
),
129 .height
= MALI_POSITIVE(height
),
134 .clear_flags
= 0x1000,
135 .unknown_address_0
= panfrost_batch_get_scratchpad(batch
)->gpu
,
136 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
),
142 struct bifrost_framebuffer
143 panfrost_emit_mfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
145 unsigned width
= batch
->key
.width
;
146 unsigned height
= batch
->key
.height
;
148 struct bifrost_framebuffer framebuffer
= {
149 .unk0
= 0x1e5, /* 1e4 if no spill */
150 .width1
= MALI_POSITIVE(width
),
151 .height1
= MALI_POSITIVE(height
),
152 .width2
= MALI_POSITIVE(width
),
153 .height2
= MALI_POSITIVE(height
),
157 .rt_count_1
= MALI_POSITIVE(batch
->key
.nr_cbufs
),
162 .scratchpad
= panfrost_batch_get_scratchpad(batch
)->gpu
,
163 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
)
171 struct pipe_context
*pipe
,
173 const union pipe_color_union
*color
,
174 double depth
, unsigned stencil
)
176 struct panfrost_context
*ctx
= pan_context(pipe
);
178 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
179 * the existing batch targeting this FBO has draws. We could probably
180 * avoid that by replacing plain clears by quad-draws with a specific
181 * color/depth/stencil value, thus avoiding the generation of extra
182 * fragment/set_value jobs.
184 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
186 panfrost_batch_add_fbo_bos(batch
);
187 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
191 panfrost_attach_vt_mfbd(struct panfrost_batch
*batch
)
193 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(batch
, ~0);
195 return panfrost_upload_transient(batch
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
199 panfrost_attach_vt_sfbd(struct panfrost_batch
*batch
)
201 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(batch
, ~0);
203 return panfrost_upload_transient(batch
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
207 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
209 /* Skip the attach if we can */
211 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
212 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
216 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
217 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
219 if (!batch
->framebuffer
)
220 batch
->framebuffer
= screen
->require_sfbd
?
221 panfrost_attach_vt_sfbd(batch
) :
222 panfrost_attach_vt_mfbd(batch
);
224 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
225 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
;
228 /* Reset per-frame context, called on context initialisation as well as after
229 * flushing a frame */
232 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
234 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
235 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
238 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
241 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
243 /* TODO: When does this need to be handled? */
244 ctx
->active_queries
= true;
247 /* In practice, every field of these payloads should be configurable
248 * arbitrarily, which means these functions are basically catch-all's for
249 * as-of-yet unwavering unknowns */
252 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
254 /* 0x2 bit clear on 32-bit T6XX */
256 struct midgard_payload_vertex_tiler payload
= {
257 .gl_enables
= 0x4 | 0x2,
260 /* Vertex and compute are closely coupled, so share a payload */
262 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
263 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
267 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
269 struct midgard_payload_vertex_tiler payload
= {
271 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
275 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
279 translate_tex_wrap(enum pipe_tex_wrap w
)
282 case PIPE_TEX_WRAP_REPEAT
:
283 return MALI_WRAP_REPEAT
;
285 /* TODO: lower GL_CLAMP? */
286 case PIPE_TEX_WRAP_CLAMP
:
287 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
288 return MALI_WRAP_CLAMP_TO_EDGE
;
290 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
291 return MALI_WRAP_CLAMP_TO_BORDER
;
293 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
294 return MALI_WRAP_MIRRORED_REPEAT
;
297 unreachable("Invalid wrap");
302 panfrost_translate_compare_func(enum pipe_compare_func in
)
305 case PIPE_FUNC_NEVER
:
306 return MALI_FUNC_NEVER
;
309 return MALI_FUNC_LESS
;
311 case PIPE_FUNC_EQUAL
:
312 return MALI_FUNC_EQUAL
;
314 case PIPE_FUNC_LEQUAL
:
315 return MALI_FUNC_LEQUAL
;
317 case PIPE_FUNC_GREATER
:
318 return MALI_FUNC_GREATER
;
320 case PIPE_FUNC_NOTEQUAL
:
321 return MALI_FUNC_NOTEQUAL
;
323 case PIPE_FUNC_GEQUAL
:
324 return MALI_FUNC_GEQUAL
;
326 case PIPE_FUNC_ALWAYS
:
327 return MALI_FUNC_ALWAYS
;
330 unreachable("Invalid func");
335 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
338 case PIPE_FUNC_NEVER
:
339 return MALI_ALT_FUNC_NEVER
;
342 return MALI_ALT_FUNC_LESS
;
344 case PIPE_FUNC_EQUAL
:
345 return MALI_ALT_FUNC_EQUAL
;
347 case PIPE_FUNC_LEQUAL
:
348 return MALI_ALT_FUNC_LEQUAL
;
350 case PIPE_FUNC_GREATER
:
351 return MALI_ALT_FUNC_GREATER
;
353 case PIPE_FUNC_NOTEQUAL
:
354 return MALI_ALT_FUNC_NOTEQUAL
;
356 case PIPE_FUNC_GEQUAL
:
357 return MALI_ALT_FUNC_GEQUAL
;
359 case PIPE_FUNC_ALWAYS
:
360 return MALI_ALT_FUNC_ALWAYS
;
363 unreachable("Invalid alt func");
368 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
371 case PIPE_STENCIL_OP_KEEP
:
372 return MALI_STENCIL_KEEP
;
374 case PIPE_STENCIL_OP_ZERO
:
375 return MALI_STENCIL_ZERO
;
377 case PIPE_STENCIL_OP_REPLACE
:
378 return MALI_STENCIL_REPLACE
;
380 case PIPE_STENCIL_OP_INCR
:
381 return MALI_STENCIL_INCR
;
383 case PIPE_STENCIL_OP_DECR
:
384 return MALI_STENCIL_DECR
;
386 case PIPE_STENCIL_OP_INCR_WRAP
:
387 return MALI_STENCIL_INCR_WRAP
;
389 case PIPE_STENCIL_OP_DECR_WRAP
:
390 return MALI_STENCIL_DECR_WRAP
;
392 case PIPE_STENCIL_OP_INVERT
:
393 return MALI_STENCIL_INVERT
;
396 unreachable("Invalid stencil op");
401 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
403 out
->ref
= 0; /* Gallium gets it from elsewhere */
405 out
->mask
= in
->valuemask
;
406 out
->func
= panfrost_translate_compare_func(in
->func
);
407 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
408 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
409 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
413 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
415 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
416 struct mali_shader_meta shader
= {
417 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
419 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
420 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
423 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
424 * required (independent of 32-bit/64-bit descriptors), or why it's not
425 * used on later GPU revisions. Otherwise, all shader jobs fault on
426 * these earlier chips (perhaps this is a chicken bit of some kind).
427 * More investigation is needed. */
429 if (screen
->require_sfbd
) {
430 shader
.unknown2_4
|= 0x10;
433 struct pipe_stencil_state default_stencil
= {
435 .func
= PIPE_FUNC_ALWAYS
,
436 .fail_op
= MALI_STENCIL_KEEP
,
437 .zfail_op
= MALI_STENCIL_KEEP
,
438 .zpass_op
= MALI_STENCIL_KEEP
,
443 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
444 shader
.stencil_mask_front
= default_stencil
.writemask
;
446 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
447 shader
.stencil_mask_back
= default_stencil
.writemask
;
449 if (default_stencil
.enabled
)
450 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
452 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
455 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
456 * graphics command stream. It should be called once per draw, accordding to
457 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
458 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
461 struct panfrost_transfer
462 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
464 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
465 struct mali_job_descriptor_header job
= {
466 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
467 .job_descriptor_size
= 1,
470 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
472 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
473 memcpy(transfer
.cpu
, &job
, sizeof(job
));
474 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
479 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
481 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
482 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
484 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
488 panfrost_writes_point_size(struct panfrost_context
*ctx
)
490 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
491 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
493 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
496 /* Stage the attribute descriptors so we can adjust src_offset
497 * to let BOs align nicely */
500 panfrost_stage_attributes(struct panfrost_context
*ctx
)
502 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
503 struct panfrost_vertex_state
*so
= ctx
->vertex
;
505 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
506 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
507 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
509 /* Copy as-is for the first pass */
510 memcpy(target
, so
->hw
, sz
);
512 /* Fixup offsets for the second pass. Recall that the hardware
513 * calculates attribute addresses as:
515 * addr = base + (stride * vtx) + src_offset;
517 * However, on Mali, base must be aligned to 64-bytes, so we
520 * base' = base & ~63 = base - (base & 63)
522 * To compensate when using base' (see emit_vertex_data), we have
523 * to adjust src_offset by the masked off piece:
525 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
526 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
527 * = base + (stride * vtx) + src_offset
533 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
535 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
536 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
537 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
538 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
540 /* Adjust by the masked off bits of the offset */
541 target
[i
].src_offset
+= (addr
& 63);
543 /* Also, somewhat obscurely per-instance data needs to be
544 * offset in response to a delayed start in an indexed draw */
546 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
547 target
[i
].src_offset
-= buf
->stride
* start
;
553 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
557 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
559 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
560 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
562 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
565 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
566 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
568 struct panfrost_transfer transfer
=
569 panfrost_allocate_transient(batch
, transfer_size
);
571 struct mali_sampler_descriptor
*desc
=
572 (struct mali_sampler_descriptor
*) transfer
.cpu
;
574 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
575 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
577 upload
= transfer
.gpu
;
580 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
584 static enum mali_texture_layout
585 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
587 /* TODO: other linear depth textures */
588 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
590 switch (rsrc
->layout
) {
592 return MALI_TEXTURE_AFBC
;
595 return MALI_TEXTURE_TILED
;
597 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
599 unreachable("Invalid texture layout");
605 struct panfrost_context
*ctx
,
606 enum pipe_shader_type st
,
607 struct panfrost_sampler_view
*view
)
612 struct pipe_sampler_view
*pview
= &view
->base
;
613 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
615 /* Do we interleave an explicit stride with every element? */
617 bool has_manual_stride
= view
->manual_stride
;
619 /* For easy access */
621 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
622 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
623 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
624 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
625 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
627 /* Lower-bit is set when sampling from colour AFBC */
628 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
629 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
630 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
632 /* Add the BO to the job so it's retained until the job is done. */
633 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
634 panfrost_batch_add_bo(batch
, rsrc
->bo
,
635 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
636 panfrost_bo_access_for_stage(st
));
638 /* Add the usage flags in, since they can change across the CSO
639 * lifetime due to layout switches */
641 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
642 view
->hw
.format
.manual_stride
= has_manual_stride
;
644 /* Inject the addresses in, interleaving mip levels, cube faces, and
645 * strides in that order */
649 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
650 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
652 view
->hw
.payload
[idx
++] =
653 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
655 if (has_manual_stride
) {
656 view
->hw
.payload
[idx
++] =
657 rsrc
->slices
[l
].stride
;
662 return panfrost_upload_transient(batch
, &view
->hw
,
663 sizeof(struct mali_texture_descriptor
));
667 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
669 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
671 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
672 mali_ptr trampoline
= 0;
674 if (ctx
->sampler_view_count
[t
]) {
675 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
677 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
679 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
681 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
684 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
688 struct sysval_uniform
{
697 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
698 struct sysval_uniform
*uniform
)
700 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
702 uniform
->f
[0] = vp
->scale
[0];
703 uniform
->f
[1] = vp
->scale
[1];
704 uniform
->f
[2] = vp
->scale
[2];
707 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
708 struct sysval_uniform
*uniform
)
710 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
712 uniform
->f
[0] = vp
->translate
[0];
713 uniform
->f
[1] = vp
->translate
[1];
714 uniform
->f
[2] = vp
->translate
[2];
717 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
718 enum pipe_shader_type st
,
719 unsigned int sysvalid
,
720 struct sysval_uniform
*uniform
)
722 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
723 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
724 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
725 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
728 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
731 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
732 tex
->u
.tex
.first_level
);
735 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
736 tex
->u
.tex
.first_level
);
739 uniform
->i
[dim
] = tex
->texture
->array_size
;
742 static void panfrost_upload_ssbo_sysval(
743 struct panfrost_context
*ctx
,
744 enum pipe_shader_type st
,
746 struct sysval_uniform
*uniform
)
748 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
749 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
751 /* Compute address */
752 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
753 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
755 panfrost_batch_add_bo(batch
, bo
,
756 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
757 panfrost_bo_access_for_stage(st
));
759 /* Upload address and size as sysval */
760 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
761 uniform
->u
[2] = sb
.buffer_size
;
764 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
765 struct sysval_uniform
*uniform
)
767 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
768 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
769 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
772 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
773 struct panfrost_shader_state
*ss
,
774 enum pipe_shader_type st
)
776 struct sysval_uniform
*uniforms
= (void *)buf
;
778 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
779 int sysval
= ss
->sysval
[i
];
781 switch (PAN_SYSVAL_TYPE(sysval
)) {
782 case PAN_SYSVAL_VIEWPORT_SCALE
:
783 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
785 case PAN_SYSVAL_VIEWPORT_OFFSET
:
786 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
788 case PAN_SYSVAL_TEXTURE_SIZE
:
789 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
792 case PAN_SYSVAL_SSBO
:
793 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
796 case PAN_SYSVAL_NUM_WORK_GROUPS
:
797 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
807 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
809 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
810 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
813 return rsrc
->bo
->cpu
;
814 else if (cb
->user_buffer
)
815 return cb
->user_buffer
;
817 unreachable("No constant buffer");
821 panfrost_map_constant_buffer_gpu(
822 struct panfrost_context
*ctx
,
823 enum pipe_shader_type st
,
824 struct panfrost_constant_buffer
*buf
,
827 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
828 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
829 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
832 panfrost_batch_add_bo(batch
, rsrc
->bo
,
833 PAN_BO_ACCESS_SHARED
|
835 panfrost_bo_access_for_stage(st
));
836 return rsrc
->bo
->gpu
;
837 } else if (cb
->user_buffer
) {
838 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
840 unreachable("No constant buffer");
844 /* Compute number of UBOs active (more specifically, compute the highest UBO
845 * number addressable -- if there are gaps, include them in the count anyway).
846 * We always include UBO #0 in the count, since we *need* uniforms enabled for
850 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
852 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
853 return 32 - __builtin_clz(mask
);
856 /* Fixes up a shader state with current state, returning a GPU address to the
860 panfrost_patch_shader_state(
861 struct panfrost_context
*ctx
,
862 struct panfrost_shader_state
*ss
,
863 enum pipe_shader_type stage
,
866 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
867 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
869 ss
->tripipe
->midgard1
.flags
= 0x220;
871 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
872 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
874 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
876 /* Add the shader BO to the batch. */
877 panfrost_batch_add_bo(batch
, ss
->bo
,
878 PAN_BO_ACCESS_PRIVATE
|
880 panfrost_bo_access_for_stage(stage
));
882 /* We can't reuse over frames; that's not safe. The descriptor must be
883 * transient uploaded */
886 return panfrost_upload_transient(batch
, ss
->tripipe
,
887 sizeof(struct mali_shader_meta
));
890 /* If we don't need an upload, don't bother */
896 panfrost_patch_shader_state_compute(
897 struct panfrost_context
*ctx
,
898 enum pipe_shader_type stage
,
901 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
904 ctx
->payloads
[stage
].postfix
.shader
= 0;
908 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
910 ctx
->payloads
[stage
].postfix
.shader
=
911 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
);
914 /* Go through dirty flags and actualise them in the cmdstream. */
917 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
919 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
920 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
922 panfrost_batch_add_fbo_bos(batch
);
923 panfrost_attach_vt_framebuffer(ctx
);
925 if (with_vertex_data
) {
926 panfrost_emit_vertex_data(batch
);
928 /* Varyings emitted for -all- geometry */
929 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
930 panfrost_emit_varying_descriptor(ctx
, total_count
);
933 bool msaa
= ctx
->rasterizer
->base
.multisample
;
935 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
936 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
938 /* TODO: Sample size */
939 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
940 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
943 panfrost_batch_set_requirements(batch
);
945 if (ctx
->occlusion_query
) {
946 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
947 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
950 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
951 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
953 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
954 /* Check if we need to link the gl_PointSize varying */
955 if (!panfrost_writes_point_size(ctx
)) {
956 /* If the size is constant, write it out. Otherwise,
957 * don't touch primitive_size (since we would clobber
958 * the pointer there) */
960 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
964 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
965 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
966 ctx
->dirty
|= PAN_DIRTY_FS
;
968 if (ctx
->dirty
& PAN_DIRTY_FS
) {
969 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
970 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
972 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
974 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
977 COPY(attribute_count
);
981 COPY(midgard1
.uniform_count
);
982 COPY(midgard1
.uniform_buffer_count
);
983 COPY(midgard1
.work_count
);
984 COPY(midgard1
.flags
);
985 COPY(midgard1
.unknown2
);
989 /* Get blending setup */
990 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
992 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
994 for (unsigned c
= 0; c
< rt_count
; ++c
)
995 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
997 /* If there is a blend shader, work registers are shared. XXX: opt */
999 for (unsigned c
= 0; c
< rt_count
; ++c
) {
1000 if (blend
[c
].is_shader
)
1001 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
1004 /* Set late due to depending on render state */
1005 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
1007 /* Depending on whether it's legal to in the given shader, we
1008 * try to enable early-z testing (or forward-pixel kill?) */
1010 if (!variant
->can_discard
)
1011 flags
|= MALI_EARLY_Z
;
1013 /* Any time texturing is used, derivatives are implicitly
1014 * calculated, so we need to enable helper invocations */
1016 if (variant
->helper_invocations
)
1017 flags
|= MALI_HELPER_INVOCATIONS
;
1019 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
1021 /* Assign the stencil refs late */
1023 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
1024 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
1025 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
1027 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
1028 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
1030 /* CAN_DISCARD should be set if the fragment shader possibly
1031 * contains a 'discard' instruction. It is likely this is
1032 * related to optimizations related to forward-pixel kill, as
1033 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1034 * thing?" by Peter Harris
1037 if (variant
->can_discard
) {
1038 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1039 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1042 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1043 * *also* copied to the blend_meta appended (by convention),
1044 * but this is the field actually read by the hardware. (Or
1045 * maybe both are read...?) */
1047 if (blend
[0].is_shader
) {
1048 ctx
->fragment_shader_core
.blend
.shader
=
1049 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1051 ctx
->fragment_shader_core
.blend
.shader
= 0;
1054 if (screen
->require_sfbd
) {
1055 /* When only a single render target platform is used, the blend
1056 * information is inside the shader meta itself. We
1057 * additionally need to signal CAN_DISCARD for nontrivial blend
1058 * modes (so we're able to read back the destination buffer) */
1060 if (blend
[0].is_shader
) {
1061 ctx
->fragment_shader_core
.unknown2_3
|= MALI_HAS_BLEND_SHADER
;
1063 ctx
->fragment_shader_core
.blend
.equation
=
1064 *blend
[0].equation
.equation
;
1065 ctx
->fragment_shader_core
.blend
.constant
=
1066 blend
[0].equation
.constant
;
1069 if (!blend
[0].no_blending
) {
1070 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1074 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1075 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1076 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1078 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
1080 if (!screen
->require_sfbd
) {
1081 /* Additional blend descriptor tacked on for jobs using MFBD */
1083 struct midgard_blend_rt rts
[4];
1085 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1086 unsigned blend_count
= 0x200;
1088 if (blend
[i
].is_shader
) {
1089 /* For a blend shader, the bottom nibble corresponds to
1090 * the number of work registers used, which signals the
1091 * -existence- of a blend shader */
1093 assert(blend
[i
].shader
.work_count
>= 2);
1094 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1096 /* Otherwise, the bottom bit simply specifies if
1097 * blending (anything other than REPLACE) is enabled */
1099 if (!blend
[i
].no_blending
)
1105 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1106 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1107 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1109 rts
[i
].flags
= blend_count
;
1112 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1114 if (!ctx
->blend
->base
.dither
)
1115 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1117 /* TODO: sRGB in blend shaders is currently
1118 * unimplemented. Contact me (Alyssa) if you're
1119 * interested in working on this. We have
1120 * native Midgard ops for helping here, but
1121 * they're not well-understood yet. */
1123 assert(!(is_srgb
&& blend
[i
].is_shader
));
1125 if (blend
[i
].is_shader
) {
1126 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1128 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1129 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1133 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1137 /* We stage to transient, so always dirty.. */
1139 panfrost_stage_attributes(ctx
);
1141 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1142 panfrost_upload_sampler_descriptors(ctx
);
1144 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1145 panfrost_upload_texture_descriptors(ctx
);
1147 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1149 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1150 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1155 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1157 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1159 /* Uniforms are implicitly UBO #0 */
1160 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1162 /* Allocate room for the sysval and the uniforms */
1163 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1164 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1165 size_t size
= sys_size
+ uniform_size
;
1166 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1168 /* Upload sysvals requested by the shader */
1169 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1171 /* Upload uniforms */
1173 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1174 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1178 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1180 struct mali_vertex_tiler_postfix
*postfix
=
1181 &ctx
->payloads
[i
].postfix
;
1183 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1186 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1187 assert(ubo_count
>= 1);
1189 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1190 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1192 /* Upload uniforms as a UBO */
1193 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1194 ubos
[0].ptr
= transfer
.gpu
>> 2;
1196 /* The rest are honest-to-goodness UBOs */
1198 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1199 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1201 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1202 bool empty
= usz
== 0;
1204 if (!enabled
|| empty
) {
1205 /* Stub out disabled UBOs to catch accesses */
1208 ubos
[ubo
].ptr
= 0xDEAD0000;
1212 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1214 unsigned bytes_per_field
= 16;
1215 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1216 unsigned fields
= aligned
/ bytes_per_field
;
1218 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1219 ubos
[ubo
].ptr
= gpu
>> 2;
1222 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1223 postfix
->uniforms
= transfer
.gpu
;
1224 postfix
->uniform_buffers
= ubufs
;
1226 buf
->dirty_mask
= 0;
1229 /* TODO: Upload the viewport somewhere more appropriate */
1231 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1232 * (somewhat) asymmetric ints. */
1233 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1235 struct mali_viewport view
= {
1236 /* By default, do no viewport clipping, i.e. clip to (-inf,
1237 * inf) in each direction. Clipping to the viewport in theory
1238 * should work, but in practice causes issues when we're not
1239 * explicitly trying to scissor */
1241 .clip_minx
= -INFINITY
,
1242 .clip_miny
= -INFINITY
,
1243 .clip_maxx
= INFINITY
,
1244 .clip_maxy
= INFINITY
,
1247 /* Always scissor to the viewport by default. */
1248 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1249 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1251 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1252 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1254 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1255 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1257 /* Apply the scissor test */
1259 unsigned minx
, miny
, maxx
, maxy
;
1261 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1262 minx
= MAX2(ss
->minx
, vp_minx
);
1263 miny
= MAX2(ss
->miny
, vp_miny
);
1264 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1265 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1273 /* Hardware needs the min/max to be strictly ordered, so flip if we
1274 * need to. The viewport transformation in the vertex shader will
1275 * handle the negatives if we don't */
1278 unsigned temp
= miny
;
1284 unsigned temp
= minx
;
1295 /* Clamp to the framebuffer size as a last check */
1297 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1298 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1300 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1301 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1303 /* Update the job, unless we're doing wallpapering (whose lack of
1304 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1305 * just... be faster :) */
1307 if (!ctx
->wallpaper_batch
)
1308 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1312 view
.viewport0
[0] = minx
;
1313 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1315 view
.viewport0
[1] = miny
;
1316 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1318 view
.clip_minz
= minz
;
1319 view
.clip_maxz
= maxz
;
1321 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1322 panfrost_upload_transient(batch
,
1324 sizeof(struct mali_viewport
));
1329 /* Corresponds to exactly one draw, but does not submit anything */
1332 panfrost_queue_draw(struct panfrost_context
*ctx
)
1334 /* Handle dirty flags now */
1335 panfrost_emit_for_draw(ctx
, true);
1337 /* If rasterizer discard is enable, only submit the vertex */
1339 bool rasterizer_discard
= ctx
->rasterizer
1340 && ctx
->rasterizer
->base
.rasterizer_discard
;
1342 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1343 struct panfrost_transfer tiler
;
1345 if (!rasterizer_discard
)
1346 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1348 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1350 if (rasterizer_discard
)
1351 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1352 else if (ctx
->wallpaper_batch
&& batch
->first_tiler
.gpu
)
1353 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1355 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1358 /* The entire frame is in memory -- send it off to the kernel! */
1362 struct pipe_context
*pipe
,
1363 struct pipe_fence_handle
**fence
,
1366 struct panfrost_context
*ctx
= pan_context(pipe
);
1367 struct util_dynarray fences
;
1369 /* We must collect the fences before the flush is done, otherwise we'll
1370 * lose track of them.
1373 util_dynarray_init(&fences
, NULL
);
1374 hash_table_foreach(ctx
->batches
, hentry
) {
1375 struct panfrost_batch
*batch
= hentry
->data
;
1377 panfrost_batch_fence_reference(batch
->out_sync
);
1378 util_dynarray_append(&fences
,
1379 struct panfrost_batch_fence
*,
1384 /* Submit all pending jobs */
1385 panfrost_flush_all_batches(ctx
, false);
1388 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1389 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1390 *fence
= (struct pipe_fence_handle
*)f
;
1392 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1393 panfrost_batch_fence_unreference(*fence
);
1395 util_dynarray_fini(&fences
);
1399 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1402 g2m_draw_mode(enum pipe_prim_type mode
)
1405 DEFINE_CASE(POINTS
);
1407 DEFINE_CASE(LINE_LOOP
);
1408 DEFINE_CASE(LINE_STRIP
);
1409 DEFINE_CASE(TRIANGLES
);
1410 DEFINE_CASE(TRIANGLE_STRIP
);
1411 DEFINE_CASE(TRIANGLE_FAN
);
1413 DEFINE_CASE(QUAD_STRIP
);
1414 DEFINE_CASE(POLYGON
);
1417 unreachable("Invalid draw mode");
1424 panfrost_translate_index_size(unsigned size
)
1428 return MALI_DRAW_INDEXED_UINT8
;
1431 return MALI_DRAW_INDEXED_UINT16
;
1434 return MALI_DRAW_INDEXED_UINT32
;
1437 unreachable("Invalid index size");
1441 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1442 * good for the duration of the draw (transient), could last longer */
1445 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1447 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1449 off_t offset
= info
->start
* info
->index_size
;
1450 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1452 if (!info
->has_user_indices
) {
1453 /* Only resources can be directly mapped */
1454 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1455 PAN_BO_ACCESS_SHARED
|
1456 PAN_BO_ACCESS_READ
|
1457 PAN_BO_ACCESS_VERTEX_TILER
);
1458 return rsrc
->bo
->gpu
+ offset
;
1460 /* Otherwise, we need to upload to transient memory */
1461 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1462 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1467 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1469 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1471 /* Check if we're scissoring at all */
1473 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1476 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1479 /* Count generated primitives (when there is no geom/tess shaders) for
1480 * transform feedback */
1483 panfrost_statistics_record(
1484 struct panfrost_context
*ctx
,
1485 const struct pipe_draw_info
*info
)
1487 if (!ctx
->active_queries
)
1490 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1491 ctx
->prims_generated
+= prims
;
1493 if (!ctx
->streamout
.num_targets
)
1496 ctx
->tf_prims_generated
+= prims
;
1501 struct pipe_context
*pipe
,
1502 const struct pipe_draw_info
*info
)
1504 struct panfrost_context
*ctx
= pan_context(pipe
);
1506 /* First of all, check the scissor to see if anything is drawn at all.
1507 * If it's not, we drop the draw (mostly a conformance issue;
1508 * well-behaved apps shouldn't hit this) */
1510 if (panfrost_scissor_culls_everything(ctx
))
1513 int mode
= info
->mode
;
1515 /* Fallback unsupported restart index */
1516 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1518 if (info
->primitive_restart
&& info
->index_size
1519 && info
->restart_index
!= primitive_index
) {
1520 util_draw_vbo_without_prim_restart(pipe
, info
);
1524 /* Fallback for unsupported modes */
1526 assert(ctx
->rasterizer
!= NULL
);
1528 if (!(ctx
->draw_modes
& (1 << mode
))) {
1529 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1530 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1532 if (info
->count
< 4) {
1533 /* Degenerate case? */
1537 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1538 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1543 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1544 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1546 /* Now that we have a guaranteed terminating path, find the job.
1547 * Assignment commented out to prevent unused warning */
1549 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1551 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1553 /* Take into account a negative bias */
1554 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1555 ctx
->instance_count
= info
->instance_count
;
1556 ctx
->active_prim
= info
->mode
;
1558 /* For non-indexed draws, they're the same */
1559 unsigned vertex_count
= ctx
->vertex_count
;
1561 unsigned draw_flags
= 0;
1563 /* The draw flags interpret how primitive size is interpreted */
1565 if (panfrost_writes_point_size(ctx
))
1566 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1568 if (info
->primitive_restart
)
1569 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1571 /* For higher amounts of vertices (greater than what fits in a 16-bit
1572 * short), the other value is needed, otherwise there will be bizarre
1573 * rendering artefacts. It's not clear what these values mean yet. This
1574 * change is also needed for instancing and sometimes points (perhaps
1575 * related to dynamically setting gl_PointSize) */
1577 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1578 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1579 bool instanced
= ctx
->instance_count
> 1;
1581 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1583 /* This doesn't make much sense */
1584 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1585 draw_flags
|= 0x800;
1588 panfrost_statistics_record(ctx
, info
);
1590 if (info
->index_size
) {
1591 /* Calculate the min/max index used so we can figure out how
1592 * many times to invoke the vertex shader */
1594 /* Fetch / calculate index bounds */
1595 unsigned min_index
= 0, max_index
= 0;
1597 if (info
->max_index
== ~0u) {
1598 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1600 min_index
= info
->min_index
;
1601 max_index
= info
->max_index
;
1604 /* Use the corresponding values */
1605 vertex_count
= max_index
- min_index
+ 1;
1606 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1607 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1609 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1610 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1612 //assert(!info->restart_index); /* TODO: Research */
1614 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1615 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1617 /* Index count == vertex count, if no indexing is applied, as
1618 * if it is internally indexed in the expected order */
1620 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1621 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1623 /* Reverse index state */
1624 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1627 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1628 * vertex_count, 1) */
1630 panfrost_pack_work_groups_fused(
1631 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1632 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1633 1, vertex_count
, info
->instance_count
,
1636 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1638 /* Encode the padded vertex count */
1640 if (info
->instance_count
> 1) {
1641 /* Triangles have non-even vertex counts so they change how
1642 * padding works internally */
1645 mode
== PIPE_PRIM_TRIANGLES
||
1646 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1647 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1649 struct pan_shift_odd so
=
1650 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1652 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1653 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1655 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1656 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1658 ctx
->padded_count
= pan_expand_shift_odd(so
);
1660 ctx
->padded_count
= vertex_count
;
1662 /* Reset instancing state */
1663 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1664 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1665 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1666 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1669 /* Fire off the draw itself */
1670 panfrost_queue_draw(ctx
);
1672 /* Increment transform feedback offsets */
1674 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1675 unsigned output_count
= u_stream_outputs_for_vertices(
1676 ctx
->active_prim
, ctx
->vertex_count
);
1678 ctx
->streamout
.offsets
[i
] += output_count
;
1685 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1691 panfrost_create_rasterizer_state(
1692 struct pipe_context
*pctx
,
1693 const struct pipe_rasterizer_state
*cso
)
1695 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1699 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1700 so
->tiler_gl_enables
= 0x7;
1703 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1705 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1706 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1708 if (cso
->cull_face
& PIPE_FACE_BACK
)
1709 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1715 panfrost_bind_rasterizer_state(
1716 struct pipe_context
*pctx
,
1719 struct panfrost_context
*ctx
= pan_context(pctx
);
1721 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1725 ctx
->rasterizer
= hwcso
;
1726 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1728 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1729 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1731 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1732 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1734 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1736 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1737 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1739 /* Point sprites are emulated */
1741 struct panfrost_shader_state
*variant
=
1742 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1744 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1745 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1749 panfrost_create_vertex_elements_state(
1750 struct pipe_context
*pctx
,
1751 unsigned num_elements
,
1752 const struct pipe_vertex_element
*elements
)
1754 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1756 so
->num_elements
= num_elements
;
1757 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1759 for (int i
= 0; i
< num_elements
; ++i
) {
1760 so
->hw
[i
].index
= i
;
1762 enum pipe_format fmt
= elements
[i
].src_format
;
1763 const struct util_format_description
*desc
= util_format_description(fmt
);
1764 so
->hw
[i
].unknown1
= 0x2;
1765 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1767 so
->hw
[i
].format
= panfrost_find_format(desc
);
1769 /* The field itself should probably be shifted over */
1770 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1777 panfrost_bind_vertex_elements_state(
1778 struct pipe_context
*pctx
,
1781 struct panfrost_context
*ctx
= pan_context(pctx
);
1783 ctx
->vertex
= hwcso
;
1784 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1788 panfrost_create_shader_state(
1789 struct pipe_context
*pctx
,
1790 const struct pipe_shader_state
*cso
)
1792 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1795 /* Token deep copy to prevent memory corruption */
1797 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1798 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1804 panfrost_delete_shader_state(
1805 struct pipe_context
*pctx
,
1808 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1810 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1811 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1814 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1815 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1816 panfrost_bo_unreference(shader_state
->bo
);
1817 shader_state
->bo
= NULL
;
1824 panfrost_create_sampler_state(
1825 struct pipe_context
*pctx
,
1826 const struct pipe_sampler_state
*cso
)
1828 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1831 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1833 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1834 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1835 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1837 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1838 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1839 unsigned mip_filter
= mip_linear
?
1840 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1841 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1843 struct mali_sampler_descriptor sampler_descriptor
= {
1844 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1845 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1846 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1847 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1848 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1850 cso
->border_color
.f
[0],
1851 cso
->border_color
.f
[1],
1852 cso
->border_color
.f
[2],
1853 cso
->border_color
.f
[3]
1855 .min_lod
= FIXED_16(cso
->min_lod
),
1856 .max_lod
= FIXED_16(cso
->max_lod
),
1857 .seamless_cube_map
= cso
->seamless_cube_map
,
1860 /* If necessary, we disable mipmapping in the sampler descriptor by
1861 * clamping the LOD as tight as possible (from 0 to epsilon,
1862 * essentially -- remember these are fixed point numbers, so
1865 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1866 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1868 /* Enforce that there is something in the middle by adding epsilon*/
1870 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1871 sampler_descriptor
.max_lod
++;
1874 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1876 so
->hw
= sampler_descriptor
;
1882 panfrost_bind_sampler_states(
1883 struct pipe_context
*pctx
,
1884 enum pipe_shader_type shader
,
1885 unsigned start_slot
, unsigned num_sampler
,
1888 assert(start_slot
== 0);
1890 struct panfrost_context
*ctx
= pan_context(pctx
);
1892 /* XXX: Should upload, not just copy? */
1893 ctx
->sampler_count
[shader
] = num_sampler
;
1894 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1896 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1900 panfrost_variant_matches(
1901 struct panfrost_context
*ctx
,
1902 struct panfrost_shader_state
*variant
,
1903 enum pipe_shader_type type
)
1905 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1906 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1908 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1910 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1911 /* Make sure enable state is at least the same */
1912 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1916 /* Check that the contents of the test are the same */
1917 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1918 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1920 if (!(same_func
&& same_ref
)) {
1925 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1926 variant
->point_sprite_mask
)) {
1927 /* Ensure the same varyings are turned to point sprites */
1928 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1931 /* Ensure the orientation is correct */
1933 rasterizer
->sprite_coord_mode
==
1934 PIPE_SPRITE_COORD_UPPER_LEFT
;
1936 if (variant
->point_sprite_upper_left
!= upper_left
)
1940 /* Otherwise, we're good to go */
1945 * Fix an uncompiled shader's stream output info, and produce a bitmask
1946 * of which VARYING_SLOT_* are captured for stream output.
1948 * Core Gallium stores output->register_index as a "slot" number, where
1949 * slots are assigned consecutively to all outputs in info->outputs_written.
1950 * This naive packing of outputs doesn't work for us - we too have slots,
1951 * but the layout is defined by the VUE map, which we won't have until we
1952 * compile a specific shader variant. So, we remap these and simply store
1953 * VARYING_SLOT_* in our copy's output->register_index fields.
1955 * We then produce a bitmask of outputs which are used for SO.
1957 * Implementation from iris.
1961 update_so_info(struct pipe_stream_output_info
*so_info
,
1962 uint64_t outputs_written
)
1964 uint64_t so_outputs
= 0;
1965 uint8_t reverse_map
[64] = {};
1968 while (outputs_written
)
1969 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1971 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1972 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1974 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1975 output
->register_index
= reverse_map
[output
->register_index
];
1977 so_outputs
|= 1ull << output
->register_index
;
1984 panfrost_bind_shader_state(
1985 struct pipe_context
*pctx
,
1987 enum pipe_shader_type type
)
1989 struct panfrost_context
*ctx
= pan_context(pctx
);
1991 ctx
->shader
[type
] = hwcso
;
1993 if (type
== PIPE_SHADER_FRAGMENT
)
1994 ctx
->dirty
|= PAN_DIRTY_FS
;
1996 ctx
->dirty
|= PAN_DIRTY_VS
;
2000 /* Match the appropriate variant */
2002 signed variant
= -1;
2003 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2005 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2006 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2012 if (variant
== -1) {
2013 /* No variant matched, so create a new one */
2014 variant
= variants
->variant_count
++;
2015 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2017 struct panfrost_shader_state
*v
=
2018 &variants
->variants
[variant
];
2020 if (type
== PIPE_SHADER_FRAGMENT
) {
2021 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2023 if (ctx
->rasterizer
) {
2024 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2025 v
->point_sprite_upper_left
=
2026 ctx
->rasterizer
->base
.sprite_coord_mode
==
2027 PIPE_SPRITE_COORD_UPPER_LEFT
;
2031 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
2035 /* Select this variant */
2036 variants
->active_variant
= variant
;
2038 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2039 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2041 /* We finally have a variant, so compile it */
2043 if (!shader_state
->compiled
) {
2044 uint64_t outputs_written
= 0;
2046 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2047 variants
->base
.type
,
2048 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2049 variants
->base
.ir
.nir
:
2050 variants
->base
.tokens
,
2051 tgsi_processor_to_shader_stage(type
), shader_state
,
2054 shader_state
->compiled
= true;
2056 /* Fixup the stream out information, since what Gallium returns
2057 * normally is mildly insane */
2059 shader_state
->stream_output
= variants
->base
.stream_output
;
2060 shader_state
->so_mask
=
2061 update_so_info(&shader_state
->stream_output
, outputs_written
);
2066 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2068 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2072 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2074 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2078 panfrost_set_vertex_buffers(
2079 struct pipe_context
*pctx
,
2080 unsigned start_slot
,
2081 unsigned num_buffers
,
2082 const struct pipe_vertex_buffer
*buffers
)
2084 struct panfrost_context
*ctx
= pan_context(pctx
);
2086 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2090 panfrost_set_constant_buffer(
2091 struct pipe_context
*pctx
,
2092 enum pipe_shader_type shader
, uint index
,
2093 const struct pipe_constant_buffer
*buf
)
2095 struct panfrost_context
*ctx
= pan_context(pctx
);
2096 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2098 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2100 unsigned mask
= (1 << index
);
2102 if (unlikely(!buf
)) {
2103 pbuf
->enabled_mask
&= ~mask
;
2104 pbuf
->dirty_mask
&= ~mask
;
2108 pbuf
->enabled_mask
|= mask
;
2109 pbuf
->dirty_mask
|= mask
;
2113 panfrost_set_stencil_ref(
2114 struct pipe_context
*pctx
,
2115 const struct pipe_stencil_ref
*ref
)
2117 struct panfrost_context
*ctx
= pan_context(pctx
);
2118 ctx
->stencil_ref
= *ref
;
2120 /* Shader core dirty */
2121 ctx
->dirty
|= PAN_DIRTY_FS
;
2124 static enum mali_texture_type
2125 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2129 case PIPE_TEXTURE_1D
:
2130 case PIPE_TEXTURE_1D_ARRAY
:
2133 case PIPE_TEXTURE_2D
:
2134 case PIPE_TEXTURE_2D_ARRAY
:
2135 case PIPE_TEXTURE_RECT
:
2138 case PIPE_TEXTURE_3D
:
2141 case PIPE_TEXTURE_CUBE
:
2142 case PIPE_TEXTURE_CUBE_ARRAY
:
2143 return MALI_TEX_CUBE
;
2146 unreachable("Unknown target");
2150 static struct pipe_sampler_view
*
2151 panfrost_create_sampler_view(
2152 struct pipe_context
*pctx
,
2153 struct pipe_resource
*texture
,
2154 const struct pipe_sampler_view
*template)
2156 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2157 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2159 pipe_reference(NULL
, &texture
->reference
);
2161 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2164 so
->base
= *template;
2165 so
->base
.texture
= texture
;
2166 so
->base
.reference
.count
= 1;
2167 so
->base
.context
= pctx
;
2169 /* sampler_views correspond to texture descriptors, minus the texture
2170 * (data) itself. So, we serialise the descriptor here and cache it for
2173 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2175 unsigned char user_swizzle
[4] = {
2176 template->swizzle_r
,
2177 template->swizzle_g
,
2178 template->swizzle_b
,
2182 enum mali_format format
= panfrost_find_format(desc
);
2184 /* Check if we need to set a custom stride by computing the "expected"
2185 * stride and comparing it to what the BO actually wants. Only applies
2186 * to linear textures, since tiled/compressed textures have strict
2187 * alignment requirements for their strides as it is */
2189 unsigned first_level
= template->u
.tex
.first_level
;
2190 unsigned last_level
= template->u
.tex
.last_level
;
2192 if (prsrc
->layout
== PAN_LINEAR
) {
2193 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2194 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2195 unsigned width
= u_minify(texture
->width0
, l
);
2196 unsigned comp_stride
= width
* bytes_per_pixel
;
2198 if (comp_stride
!= actual_stride
) {
2199 so
->manual_stride
= true;
2205 /* In the hardware, array_size refers specifically to array textures,
2206 * whereas in Gallium, it also covers cubemaps */
2208 unsigned array_size
= texture
->array_size
;
2210 if (template->target
== PIPE_TEXTURE_CUBE
) {
2211 /* TODO: Cubemap arrays */
2212 assert(array_size
== 6);
2216 struct mali_texture_descriptor texture_descriptor
= {
2217 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2218 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2219 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2220 .array_size
= MALI_POSITIVE(array_size
),
2223 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2225 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2226 .type
= panfrost_translate_texture_type(template->target
),
2230 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2233 texture_descriptor
.levels
= last_level
- first_level
;
2235 so
->hw
= texture_descriptor
;
2237 return (struct pipe_sampler_view
*) so
;
2241 panfrost_set_sampler_views(
2242 struct pipe_context
*pctx
,
2243 enum pipe_shader_type shader
,
2244 unsigned start_slot
, unsigned num_views
,
2245 struct pipe_sampler_view
**views
)
2247 struct panfrost_context
*ctx
= pan_context(pctx
);
2249 assert(start_slot
== 0);
2251 unsigned new_nr
= 0;
2252 for (unsigned i
= 0; i
< num_views
; ++i
) {
2257 ctx
->sampler_view_count
[shader
] = new_nr
;
2258 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2260 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2264 panfrost_sampler_view_destroy(
2265 struct pipe_context
*pctx
,
2266 struct pipe_sampler_view
*view
)
2268 pipe_resource_reference(&view
->texture
, NULL
);
2273 panfrost_set_shader_buffers(
2274 struct pipe_context
*pctx
,
2275 enum pipe_shader_type shader
,
2276 unsigned start
, unsigned count
,
2277 const struct pipe_shader_buffer
*buffers
,
2278 unsigned writable_bitmask
)
2280 struct panfrost_context
*ctx
= pan_context(pctx
);
2282 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2283 buffers
, start
, count
);
2286 /* Hints that a framebuffer should use AFBC where possible */
2290 struct panfrost_screen
*screen
,
2291 const struct pipe_framebuffer_state
*fb
)
2293 /* AFBC implemenation incomplete; hide it */
2294 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2296 /* Hint AFBC to the resources bound to each color buffer */
2298 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2299 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2300 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2301 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2304 /* Also hint it to the depth buffer */
2307 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2308 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2313 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2314 const struct pipe_framebuffer_state
*fb
)
2316 struct panfrost_context
*ctx
= pan_context(pctx
);
2318 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2319 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2321 panfrost_invalidate_frame(ctx
);
2325 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2326 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2328 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2332 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2335 struct panfrost_context
*ctx
= pan_context(pipe
);
2336 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2337 ctx
->depth_stencil
= depth_stencil
;
2342 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2343 * emulated in the fragment shader */
2345 if (depth_stencil
->alpha
.enabled
) {
2346 /* We need to trigger a new shader (maybe) */
2347 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2351 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2353 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2354 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2356 /* If back-stencil is not enabled, use the front values */
2357 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2358 unsigned back_index
= back_enab
? 1 : 0;
2360 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2361 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2363 /* Depth state (TODO: Refactor) */
2364 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2365 depth_stencil
->depth
.writemask
);
2367 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2369 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2370 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2372 /* Bounds test not implemented */
2373 assert(!depth_stencil
->depth
.bounds_test
);
2375 ctx
->dirty
|= PAN_DIRTY_FS
;
2379 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2385 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2386 unsigned sample_mask
)
2391 panfrost_set_clip_state(struct pipe_context
*pipe
,
2392 const struct pipe_clip_state
*clip
)
2394 //struct panfrost_context *panfrost = pan_context(pipe);
2398 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2399 unsigned start_slot
,
2400 unsigned num_viewports
,
2401 const struct pipe_viewport_state
*viewports
)
2403 struct panfrost_context
*ctx
= pan_context(pipe
);
2405 assert(start_slot
== 0);
2406 assert(num_viewports
== 1);
2408 ctx
->pipe_viewport
= *viewports
;
2412 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2413 unsigned start_slot
,
2414 unsigned num_scissors
,
2415 const struct pipe_scissor_state
*scissors
)
2417 struct panfrost_context
*ctx
= pan_context(pipe
);
2419 assert(start_slot
== 0);
2420 assert(num_scissors
== 1);
2422 ctx
->scissor
= *scissors
;
2426 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2427 const struct pipe_poly_stipple
*stipple
)
2429 //struct panfrost_context *panfrost = pan_context(pipe);
2433 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2436 struct panfrost_context
*ctx
= pan_context(pipe
);
2437 ctx
->active_queries
= enable
;
2441 panfrost_destroy(struct pipe_context
*pipe
)
2443 struct panfrost_context
*panfrost
= pan_context(pipe
);
2445 if (panfrost
->blitter
)
2446 util_blitter_destroy(panfrost
->blitter
);
2448 if (panfrost
->blitter_wallpaper
)
2449 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2451 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
2452 u_upload_destroy(pipe
->stream_uploader
);
2457 static struct pipe_query
*
2458 panfrost_create_query(struct pipe_context
*pipe
,
2462 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2467 return (struct pipe_query
*) q
;
2471 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2473 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2476 panfrost_bo_unreference(query
->bo
);
2484 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2486 struct panfrost_context
*ctx
= pan_context(pipe
);
2487 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2489 switch (query
->type
) {
2490 case PIPE_QUERY_OCCLUSION_COUNTER
:
2491 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2492 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2493 /* Allocate a bo for the query results to be stored */
2495 query
->bo
= panfrost_bo_create(
2496 pan_screen(ctx
->base
.screen
),
2497 sizeof(unsigned), 0);
2500 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2501 *result
= 0; /* Default to 0 if nothing at all drawn. */
2502 ctx
->occlusion_query
= query
;
2505 /* Geometry statistics are computed in the driver. XXX: geom/tess
2508 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2509 query
->start
= ctx
->prims_generated
;
2511 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2512 query
->start
= ctx
->tf_prims_generated
;
2516 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2524 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2526 struct panfrost_context
*ctx
= pan_context(pipe
);
2527 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2529 switch (query
->type
) {
2530 case PIPE_QUERY_OCCLUSION_COUNTER
:
2531 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2532 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2533 ctx
->occlusion_query
= NULL
;
2535 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2536 query
->end
= ctx
->prims_generated
;
2538 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2539 query
->end
= ctx
->tf_prims_generated
;
2547 panfrost_get_query_result(struct pipe_context
*pipe
,
2548 struct pipe_query
*q
,
2550 union pipe_query_result
*vresult
)
2552 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2553 struct panfrost_context
*ctx
= pan_context(pipe
);
2556 switch (query
->type
) {
2557 case PIPE_QUERY_OCCLUSION_COUNTER
:
2558 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2559 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2561 panfrost_flush_all_batches(ctx
, true);
2563 /* Read back the query results */
2564 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2565 unsigned passed
= *result
;
2567 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2568 vresult
->u64
= passed
;
2570 vresult
->b
= !!passed
;
2575 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2576 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2577 panfrost_flush_all_batches(ctx
, true);
2578 vresult
->u64
= query
->end
- query
->start
;
2582 DBG("Skipped query get %u\n", query
->type
);
2589 static struct pipe_stream_output_target
*
2590 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2591 struct pipe_resource
*prsc
,
2592 unsigned buffer_offset
,
2593 unsigned buffer_size
)
2595 struct pipe_stream_output_target
*target
;
2597 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2602 pipe_reference_init(&target
->reference
, 1);
2603 pipe_resource_reference(&target
->buffer
, prsc
);
2605 target
->context
= pctx
;
2606 target
->buffer_offset
= buffer_offset
;
2607 target
->buffer_size
= buffer_size
;
2613 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2614 struct pipe_stream_output_target
*target
)
2616 pipe_resource_reference(&target
->buffer
, NULL
);
2617 ralloc_free(target
);
2621 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2622 unsigned num_targets
,
2623 struct pipe_stream_output_target
**targets
,
2624 const unsigned *offsets
)
2626 struct panfrost_context
*ctx
= pan_context(pctx
);
2627 struct panfrost_streamout
*so
= &ctx
->streamout
;
2629 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2631 for (unsigned i
= 0; i
< num_targets
; i
++) {
2632 if (offsets
[i
] != -1)
2633 so
->offsets
[i
] = offsets
[i
];
2635 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2638 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2639 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2641 so
->num_targets
= num_targets
;
2644 struct pipe_context
*
2645 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2647 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2648 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2649 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2651 gallium
->screen
= screen
;
2653 gallium
->destroy
= panfrost_destroy
;
2655 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2657 gallium
->flush
= panfrost_flush
;
2658 gallium
->clear
= panfrost_clear
;
2659 gallium
->draw_vbo
= panfrost_draw_vbo
;
2661 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2662 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2663 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2665 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2667 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2668 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2669 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2671 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2672 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2673 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2675 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2676 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2677 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2679 gallium
->create_fs_state
= panfrost_create_shader_state
;
2680 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2681 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2683 gallium
->create_vs_state
= panfrost_create_shader_state
;
2684 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2685 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2687 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2688 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2689 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2691 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2692 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2693 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2695 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2697 gallium
->set_clip_state
= panfrost_set_clip_state
;
2698 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2699 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2700 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2701 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2703 gallium
->create_query
= panfrost_create_query
;
2704 gallium
->destroy_query
= panfrost_destroy_query
;
2705 gallium
->begin_query
= panfrost_begin_query
;
2706 gallium
->end_query
= panfrost_end_query
;
2707 gallium
->get_query_result
= panfrost_get_query_result
;
2709 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2710 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2711 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2713 panfrost_resource_context_init(gallium
);
2714 panfrost_blend_context_init(gallium
);
2715 panfrost_compute_context_init(gallium
);
2718 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2719 gallium
->const_uploader
= gallium
->stream_uploader
;
2720 assert(gallium
->stream_uploader
);
2722 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2723 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2725 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2727 ctx
->blitter
= util_blitter_create(gallium
);
2728 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2730 assert(ctx
->blitter
);
2731 assert(ctx
->blitter_wallpaper
);
2733 /* Prepare for render! */
2735 panfrost_batch_init(ctx
);
2736 panfrost_emit_vertex_payload(ctx
);
2737 panfrost_emit_tiler_payload(ctx
);
2738 panfrost_invalidate_frame(ctx
);
2739 panfrost_default_shader_backend(ctx
);