2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
49 #include "pan_tiler.h"
51 static int performance_counter_number
= 0;
52 extern const char *pan_counters_base
;
54 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
57 static enum mali_job_type
58 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
61 case PIPE_SHADER_VERTEX
:
62 return JOB_TYPE_VERTEX
;
64 case PIPE_SHADER_FRAGMENT
:
65 /* Note: JOB_TYPE_FRAGMENT is different.
66 * JOB_TYPE_FRAGMENT actually executes the
67 * fragment shader, but JOB_TYPE_TILER is how you
69 return JOB_TYPE_TILER
;
71 case PIPE_SHADER_GEOMETRY
:
72 return JOB_TYPE_GEOMETRY
;
74 case PIPE_SHADER_COMPUTE
:
75 return JOB_TYPE_COMPUTE
;
78 unreachable("Unsupported shader stage");
83 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
85 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
86 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
87 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
88 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
90 /* 8 byte checksum per tile */
91 rsrc
->bo
->checksum_stride
= tile_w
* 8;
92 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
93 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
95 rsrc
->bo
->has_checksum
= true;
98 /* Framebuffer descriptor */
101 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
103 fb
->width
= MALI_POSITIVE(w
);
104 fb
->height
= MALI_POSITIVE(h
);
106 /* No idea why this is needed, but it's how resolution_check is
107 * calculated. It's not clear to us yet why the hardware wants this.
108 * The formula itself was discovered mostly by manual bruteforce and
109 * aggressive algebraic simplification. */
111 fb
->tiler_resolution_check
= ((w
+ h
) / 3) << 4;
114 struct mali_single_framebuffer
115 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
117 struct mali_single_framebuffer framebuffer
= {
119 .format
= 0x30000000,
120 .clear_flags
= 0x1000,
121 .unknown_address_0
= ctx
->scratchpad
.gpu
,
122 .tiler_polygon_list
= ctx
->misc_0
.gpu
,
123 .tiler_polygon_list_body
= ctx
->misc_0
.gpu
+ 40960,
124 .tiler_hierarchy_mask
= 0xF0,
126 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
127 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
130 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
135 struct bifrost_framebuffer
136 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
138 unsigned width
= ctx
->pipe_framebuffer
.width
;
139 unsigned height
= ctx
->pipe_framebuffer
.height
;
141 struct bifrost_framebuffer framebuffer
= {
142 /* The lower 0x1ff controls the hierarchy mask. Set more bits
143 * on for more tile granularity (which can be a performance win
144 * on some scenes, at memory bandwidth costs). For now, be lazy
145 * and enable everything. This might be a terrible idea. */
147 .tiler_hierarchy_mask
= 0xff,
150 /* The hardware deals with suballocation; we don't care */
151 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
152 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
154 /* See pan_tiler.c */
155 .tiler_polygon_list
= ctx
->misc_0
.gpu
,
156 .tiler_polygon_list_size
= 0x0,
158 .width1
= MALI_POSITIVE(width
),
159 .height1
= MALI_POSITIVE(height
),
160 .width2
= MALI_POSITIVE(width
),
161 .height2
= MALI_POSITIVE(height
),
166 .rt_count_1
= MALI_POSITIVE(1),
171 .scratchpad
= ctx
->scratchpad
.gpu
,
174 /* Compute the polygon header size and use that to offset the body */
176 unsigned header_size
= panfrost_tiler_header_size(
177 width
, height
, framebuffer
.tiler_hierarchy_mask
);
179 framebuffer
.tiler_polygon_list_body
=
180 framebuffer
.tiler_polygon_list
+ header_size
;
185 /* Are we currently rendering to the screen (rather than an FBO)? */
188 panfrost_is_scanout(struct panfrost_context
*ctx
)
190 /* If there is no color buffer, it's an FBO */
191 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
194 /* If we're too early that no framebuffer was sent, it's scanout */
195 if (!ctx
->pipe_framebuffer
.cbufs
[0])
198 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
199 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
200 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
204 pan_pack_color(const union pipe_color_union
*color
, enum pipe_format format
)
206 /* Alpha magicked to 1.0 if there is no alpha */
208 bool has_alpha
= util_format_has_alpha(format
);
209 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
211 /* Packed color depends on the framebuffer format */
213 const struct util_format_description
*desc
=
214 util_format_description(format
);
216 if (util_format_is_rgba8_variant(desc
)) {
217 return (float_to_ubyte(clear_alpha
) << 24) |
218 (float_to_ubyte(color
->f
[2]) << 16) |
219 (float_to_ubyte(color
->f
[1]) << 8) |
220 (float_to_ubyte(color
->f
[0]) << 0);
221 } else if (format
== PIPE_FORMAT_B5G6R5_UNORM
) {
222 /* First, we convert the components to R5, G6, B5 separately */
223 unsigned r5
= CLAMP(color
->f
[0], 0.0, 1.0) * 31.0;
224 unsigned g6
= CLAMP(color
->f
[1], 0.0, 1.0) * 63.0;
225 unsigned b5
= CLAMP(color
->f
[2], 0.0, 1.0) * 31.0;
227 /* Then we pack into a sparse u32. TODO: Why these shifts? */
228 return (b5
<< 25) | (g6
<< 14) | (r5
<< 5);
239 struct pipe_context
*pipe
,
241 const union pipe_color_union
*color
,
242 double depth
, unsigned stencil
)
244 struct panfrost_context
*ctx
= pan_context(pipe
);
245 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
247 if (buffers
& PIPE_CLEAR_COLOR
) {
248 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[0]->format
;
249 job
->clear_color
= pan_pack_color(color
, format
);
252 if (buffers
& PIPE_CLEAR_DEPTH
) {
253 job
->clear_depth
= depth
;
256 if (buffers
& PIPE_CLEAR_STENCIL
) {
257 job
->clear_stencil
= stencil
;
260 job
->clear
|= buffers
;
264 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
266 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
270 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
272 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
276 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
278 mali_ptr framebuffer
= ctx
->require_sfbd
?
279 panfrost_attach_vt_sfbd(ctx
) :
280 panfrost_attach_vt_mfbd(ctx
);
282 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
283 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
286 /* Reset per-frame context, called on context initialisation as well as after
287 * flushing a frame */
290 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
292 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
293 DBG("Uploaded transient %d bytes\n", transient_count
);
295 /* Rotate cmdstream */
296 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
297 ctx
->cmdstream_i
= 0;
299 if (ctx
->require_sfbd
)
300 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
302 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
304 /* Reset varyings allocated */
305 ctx
->varying_height
= 0;
307 /* The transient cmdstream is dirty every frame; the only bits worth preserving
308 * (textures, shaders, etc) are in other buffers anyways */
310 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
311 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
313 /* Regenerate payloads */
314 panfrost_attach_vt_framebuffer(ctx
);
317 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
320 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
322 /* Reset job counters */
324 ctx
->vertex_job_count
= 0;
325 ctx
->tiler_job_count
= 0;
328 /* In practice, every field of these payloads should be configurable
329 * arbitrarily, which means these functions are basically catch-all's for
330 * as-of-yet unwavering unknowns */
333 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
335 struct midgard_payload_vertex_tiler payload
= {
337 .workgroups_z_shift
= 32,
338 .workgroups_x_shift_2
= 0x2,
339 .workgroups_x_shift_3
= 0x5,
341 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
344 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
348 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
350 struct midgard_payload_vertex_tiler payload
= {
352 .workgroups_z_shift
= 32,
353 .workgroups_x_shift_2
= 0x2,
354 .workgroups_x_shift_3
= 0x6,
356 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
360 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
364 translate_tex_wrap(enum pipe_tex_wrap w
)
367 case PIPE_TEX_WRAP_REPEAT
:
368 return MALI_WRAP_REPEAT
;
370 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
371 return MALI_WRAP_CLAMP_TO_EDGE
;
373 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
374 return MALI_WRAP_CLAMP_TO_BORDER
;
376 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
377 return MALI_WRAP_MIRRORED_REPEAT
;
380 unreachable("Invalid wrap");
385 translate_tex_filter(enum pipe_tex_filter f
)
388 case PIPE_TEX_FILTER_NEAREST
:
391 case PIPE_TEX_FILTER_LINEAR
:
395 unreachable("Invalid filter");
400 translate_mip_filter(enum pipe_tex_mipfilter f
)
402 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
406 panfrost_translate_compare_func(enum pipe_compare_func in
)
409 case PIPE_FUNC_NEVER
:
410 return MALI_FUNC_NEVER
;
413 return MALI_FUNC_LESS
;
415 case PIPE_FUNC_EQUAL
:
416 return MALI_FUNC_EQUAL
;
418 case PIPE_FUNC_LEQUAL
:
419 return MALI_FUNC_LEQUAL
;
421 case PIPE_FUNC_GREATER
:
422 return MALI_FUNC_GREATER
;
424 case PIPE_FUNC_NOTEQUAL
:
425 return MALI_FUNC_NOTEQUAL
;
427 case PIPE_FUNC_GEQUAL
:
428 return MALI_FUNC_GEQUAL
;
430 case PIPE_FUNC_ALWAYS
:
431 return MALI_FUNC_ALWAYS
;
434 unreachable("Invalid func");
439 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
442 case PIPE_FUNC_NEVER
:
443 return MALI_ALT_FUNC_NEVER
;
446 return MALI_ALT_FUNC_LESS
;
448 case PIPE_FUNC_EQUAL
:
449 return MALI_ALT_FUNC_EQUAL
;
451 case PIPE_FUNC_LEQUAL
:
452 return MALI_ALT_FUNC_LEQUAL
;
454 case PIPE_FUNC_GREATER
:
455 return MALI_ALT_FUNC_GREATER
;
457 case PIPE_FUNC_NOTEQUAL
:
458 return MALI_ALT_FUNC_NOTEQUAL
;
460 case PIPE_FUNC_GEQUAL
:
461 return MALI_ALT_FUNC_GEQUAL
;
463 case PIPE_FUNC_ALWAYS
:
464 return MALI_ALT_FUNC_ALWAYS
;
467 unreachable("Invalid alt func");
472 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
475 case PIPE_STENCIL_OP_KEEP
:
476 return MALI_STENCIL_KEEP
;
478 case PIPE_STENCIL_OP_ZERO
:
479 return MALI_STENCIL_ZERO
;
481 case PIPE_STENCIL_OP_REPLACE
:
482 return MALI_STENCIL_REPLACE
;
484 case PIPE_STENCIL_OP_INCR
:
485 return MALI_STENCIL_INCR
;
487 case PIPE_STENCIL_OP_DECR
:
488 return MALI_STENCIL_DECR
;
490 case PIPE_STENCIL_OP_INCR_WRAP
:
491 return MALI_STENCIL_INCR_WRAP
;
493 case PIPE_STENCIL_OP_DECR_WRAP
:
494 return MALI_STENCIL_DECR_WRAP
;
496 case PIPE_STENCIL_OP_INVERT
:
497 return MALI_STENCIL_INVERT
;
500 unreachable("Invalid stencil op");
505 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
507 out
->ref
= 0; /* Gallium gets it from elsewhere */
509 out
->mask
= in
->valuemask
;
510 out
->func
= panfrost_translate_compare_func(in
->func
);
511 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
512 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
513 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
517 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
519 struct mali_shader_meta shader
= {
520 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
522 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
523 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
527 shader
.unknown2_4
|= 0x10;
530 struct pipe_stencil_state default_stencil
= {
532 .func
= PIPE_FUNC_ALWAYS
,
533 .fail_op
= MALI_STENCIL_KEEP
,
534 .zfail_op
= MALI_STENCIL_KEEP
,
535 .zpass_op
= MALI_STENCIL_KEEP
,
540 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
541 shader
.stencil_mask_front
= default_stencil
.writemask
;
543 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
544 shader
.stencil_mask_back
= default_stencil
.writemask
;
546 if (default_stencil
.enabled
)
547 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
549 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
553 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
555 if (first
->job_descriptor_size
)
556 first
->next_job_64
= (u64
) (uintptr_t) next
;
558 first
->next_job_32
= (u32
) (uintptr_t) next
;
561 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
562 * graphics command stream. It should be called once per draw, accordding to
563 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
564 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
567 struct panfrost_transfer
568 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
570 /* Each draw call corresponds to two jobs, and the set-value job is first */
571 int draw_job_index
= 1 + (2 * ctx
->draw_count
) + 1;
573 struct mali_job_descriptor_header job
= {
574 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
575 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
577 .job_descriptor_size
= 1,
581 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
583 /* There's some padding hacks on 32-bit */
590 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
593 /* Tiler jobs depend on vertex jobs */
595 job
.job_dependency_index_1
= draw_job_index
;
597 /* Tiler jobs also depend on the previous tiler job */
599 if (ctx
->draw_count
) {
600 job
.job_dependency_index_2
= draw_job_index
- 1;
601 /* Previous tiler job points to this tiler job */
602 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
604 /* The only vertex job so far points to first tiler job */
605 panfrost_link_job_pair(ctx
->u_vertex_jobs
[0], transfer
.gpu
);
608 if (ctx
->draw_count
) {
609 /* Previous vertex job points to this vertex job */
610 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
612 /* Last vertex job points to first tiler job */
613 panfrost_link_job_pair(&job
, ctx
->tiler_jobs
[0]);
615 /* Have the first vertex job depend on the set value job */
616 job
.job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
617 panfrost_link_job_pair(ctx
->u_set_value_job
, transfer
.gpu
);
621 memcpy(transfer
.cpu
, &job
, sizeof(job
));
622 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
626 /* Generates a set value job. It's unclear what exactly this does, why it's
627 * necessary, and when to call it. */
630 panfrost_set_value_job(struct panfrost_context
*ctx
)
632 struct mali_job_descriptor_header job
= {
633 .job_type
= JOB_TYPE_SET_VALUE
,
634 .job_descriptor_size
= 1,
638 struct mali_payload_set_value payload
= {
639 .out
= ctx
->misc_0
.gpu
,
643 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
644 memcpy(transfer
.cpu
, &job
, sizeof(job
));
645 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
647 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
648 ctx
->set_value_job
= transfer
.gpu
;
652 panfrost_emit_varyings(
653 struct panfrost_context
*ctx
,
654 union mali_attr
*slot
,
658 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
660 /* Fill out the descriptor */
661 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
662 slot
->stride
= stride
;
663 slot
->size
= stride
* count
;
665 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
666 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
668 return varying_address
;
672 panfrost_emit_point_coord(union mali_attr
*slot
)
674 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
675 slot
->stride
= slot
->size
= 0;
679 panfrost_emit_varying_descriptor(
680 struct panfrost_context
*ctx
,
681 unsigned invocation_count
)
683 /* Load the shaders */
685 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
686 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
687 unsigned int num_gen_varyings
= 0;
689 /* Allocate the varying descriptor */
691 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
692 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
694 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
698 * Assign ->src_offset now that we know about all the general purpose
699 * varyings that will be used by the fragment and vertex shaders.
701 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
703 * General purpose varyings have ->index set to 0, skip other
706 if (vs
->varyings
[i
].index
)
709 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
712 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
715 if (fs
->varyings
[i
].index
)
719 * Re-use the VS general purpose varying pos if it exists,
720 * create a new one otherwise.
722 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
723 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
727 if (j
< vs
->tripipe
->varying_count
)
728 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
730 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
733 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
734 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
736 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
737 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
739 /* Buffer indices must be in this order per our convention */
740 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
743 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
746 /* fp32 vec4 gl_Position */
747 ctx
->payload_tiler
.postfix
.position_varying
=
748 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
749 sizeof(float) * 4, invocation_count
);
752 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
753 /* fp16 vec1 gl_PointSize */
754 ctx
->payload_tiler
.primitive_size
.pointer
=
755 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
756 2, invocation_count
);
759 if (fs
->reads_point_coord
) {
760 /* Special descriptor */
761 panfrost_emit_point_coord(&varyings
[idx
++]);
764 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
765 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
766 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
770 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
772 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
773 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
775 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
778 /* Emits attributes and varying descriptors, which should be called every draw,
779 * excepting some obscure circumstances */
782 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
784 /* Staged mali_attr, and index into them. i =/= k, depending on the
785 * vertex buffer mask */
786 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
789 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
791 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
792 if (!(ctx
->vb_mask
& (1 << i
))) continue;
794 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
795 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
799 /* Align to 64 bytes by masking off the lower bits. This
800 * will be adjusted back when we fixup the src_offset in
803 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
805 /* Offset vertex count by draw_start to make sure we upload enough */
806 attrs
[k
].stride
= buf
->stride
;
807 attrs
[k
].size
= rsrc
->base
.width0
;
809 panfrost_job_add_bo(job
, rsrc
->bo
);
810 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
815 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
817 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
821 panfrost_writes_point_size(struct panfrost_context
*ctx
)
824 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
826 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
829 /* Stage the attribute descriptors so we can adjust src_offset
830 * to let BOs align nicely */
833 panfrost_stage_attributes(struct panfrost_context
*ctx
)
835 struct panfrost_vertex_state
*so
= ctx
->vertex
;
837 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
838 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
839 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
841 /* Copy as-is for the first pass */
842 memcpy(target
, so
->hw
, sz
);
844 /* Fixup offsets for the second pass. Recall that the hardware
845 * calculates attribute addresses as:
847 * addr = base + (stride * vtx) + src_offset;
849 * However, on Mali, base must be aligned to 64-bytes, so we
852 * base' = base & ~63 = base - (base & 63)
854 * To compensate when using base' (see emit_vertex_data), we have
855 * to adjust src_offset by the masked off piece:
857 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
858 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
859 * = base + (stride * vtx) + src_offset
865 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
866 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
867 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
869 /* Adjust by the masked off bits of the offset */
870 target
[i
].src_offset
+= (addr
& 63);
873 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
877 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
879 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
881 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
882 if (!ctx
->sampler_count
[t
]) continue;
884 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
886 struct panfrost_transfer transfer
=
887 panfrost_allocate_transient(ctx
, transfer_size
);
889 struct mali_sampler_descriptor
*desc
=
890 (struct mali_sampler_descriptor
*) transfer
.cpu
;
892 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
893 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
895 if (t
== PIPE_SHADER_FRAGMENT
)
896 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
897 else if (t
== PIPE_SHADER_VERTEX
)
898 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
904 /* Computes the address to a texture at a particular slice */
907 panfrost_get_texture_address(
908 struct panfrost_resource
*rsrc
,
909 unsigned level
, unsigned face
)
911 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
912 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
914 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
920 struct panfrost_context
*ctx
,
921 struct panfrost_sampler_view
*view
)
924 return (mali_ptr
) NULL
;
926 struct pipe_resource
*tex_rsrc
= view
->base
.texture
;
927 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
929 /* Do we interleave an explicit stride with every element? */
931 bool has_manual_stride
=
932 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
934 /* Inject the addresses in, interleaving mip levels, cube faces, and
935 * strides in that order */
939 for (unsigned l
= 0; l
<= tex_rsrc
->last_level
; ++l
) {
940 for (unsigned f
= 0; f
< tex_rsrc
->array_size
; ++f
) {
941 view
->hw
.payload
[idx
++] =
942 panfrost_get_texture_address(rsrc
, l
, f
);
944 if (has_manual_stride
) {
945 view
->hw
.payload
[idx
++] =
946 rsrc
->bo
->slices
[l
].stride
;
951 return panfrost_upload_transient(ctx
, &view
->hw
,
952 sizeof(struct mali_texture_descriptor
));
956 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
958 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
960 if (!ctx
->sampler_view_count
[t
]) continue;
962 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
964 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
966 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
968 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
970 if (t
== PIPE_SHADER_FRAGMENT
)
971 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
972 else if (t
== PIPE_SHADER_VERTEX
)
973 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
979 /* Go through dirty flags and actualise them in the cmdstream. */
982 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
984 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
986 if (with_vertex_data
) {
987 panfrost_emit_vertex_data(ctx
, job
);
990 bool msaa
= ctx
->rasterizer
->base
.multisample
;
992 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
993 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
995 /* TODO: Sample size */
996 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
997 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1000 /* Enable job requirements at draw-time */
1003 job
->requirements
|= PAN_REQ_MSAA
;
1005 if (ctx
->depth_stencil
->depth
.writemask
)
1006 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
1008 if (ctx
->occlusion_query
) {
1009 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1010 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1013 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1016 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1018 /* Late shader descriptor assignments */
1020 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1021 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1024 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1026 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1029 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1030 /* Check if we need to link the gl_PointSize varying */
1031 if (!panfrost_writes_point_size(ctx
)) {
1032 /* If the size is constant, write it out. Otherwise,
1033 * don't touch primitive_size (since we would clobber
1034 * the pointer there) */
1036 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1040 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1042 ctx
->dirty
|= PAN_DIRTY_FS
;
1044 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1046 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1048 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1051 COPY(attribute_count
);
1052 COPY(varying_count
);
1053 COPY(midgard1
.uniform_count
);
1054 COPY(midgard1
.work_count
);
1055 COPY(midgard1
.unknown2
);
1058 /* If there is a blend shader, work registers are shared */
1060 if (ctx
->blend
->has_blend_shader
)
1061 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1063 /* Set late due to depending on render state */
1064 /* The one at the end seems to mean "1 UBO" */
1065 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
1067 /* Assign texture/sample count right before upload */
1068 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1069 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1071 /* Assign the stencil refs late */
1072 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1073 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1075 /* CAN_DISCARD should be set if the fragment shader possibly
1076 * contains a 'discard' instruction. It is likely this is
1077 * related to optimizations related to forward-pixel kill, as
1078 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1079 * thing?" by Peter Harris
1082 if (variant
->can_discard
) {
1083 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1084 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1085 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1086 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1089 /* Check if we're using the default blend descriptor (fast path) */
1092 !ctx
->blend
->has_blend_shader
&&
1093 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1094 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1095 (ctx
->blend
->equation
.color_mask
== 0xf);
1097 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1098 * *also* copied to the blend_meta appended (by convention),
1099 * but this is the field actually read by the hardware. (Or
1100 * maybe both are read...?) */
1102 if (ctx
->blend
->has_blend_shader
) {
1103 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1106 if (ctx
->require_sfbd
) {
1107 /* When only a single render target platform is used, the blend
1108 * information is inside the shader meta itself. We
1109 * additionally need to signal CAN_DISCARD for nontrivial blend
1110 * modes (so we're able to read back the destination buffer) */
1112 if (!ctx
->blend
->has_blend_shader
) {
1113 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1114 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1118 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1122 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1123 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1124 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1126 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1128 if (!ctx
->require_sfbd
) {
1129 /* Additional blend descriptor tacked on for jobs using MFBD */
1131 unsigned blend_count
= 0x200;
1133 if (ctx
->blend
->has_blend_shader
) {
1134 /* For a blend shader, the bottom nibble corresponds to
1135 * the number of work registers used, which signals the
1136 * -existence- of a blend shader */
1138 assert(ctx
->blend
->blend_work_count
>= 2);
1139 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1141 /* Otherwise, the bottom bit simply specifies if
1142 * blending (anything other than REPLACE) is enabled */
1149 struct midgard_blend_rt rts
[4];
1153 for (unsigned i
= 0; i
< 1; ++i
) {
1154 rts
[i
].flags
= blend_count
;
1156 if (ctx
->blend
->has_blend_shader
) {
1157 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1159 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1160 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1164 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1168 /* We stage to transient, so always dirty.. */
1169 panfrost_stage_attributes(ctx
);
1171 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1172 panfrost_upload_sampler_descriptors(ctx
);
1174 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1175 panfrost_upload_texture_descriptors(ctx
);
1177 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1179 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1180 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1182 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1183 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1184 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1186 /* Allocate room for the sysval and the uniforms */
1187 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1188 size_t size
= sys_size
+ buf
->size
;
1189 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1191 /* Upload sysvals requested by the shader */
1192 float *uniforms
= (float *) transfer
.cpu
;
1193 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1194 int sysval
= ss
->sysval
[i
];
1196 if (sysval
== PAN_SYSVAL_VIEWPORT_SCALE
) {
1197 uniforms
[4*i
+ 0] = vp
->scale
[0];
1198 uniforms
[4*i
+ 1] = vp
->scale
[1];
1199 uniforms
[4*i
+ 2] = vp
->scale
[2];
1200 } else if (sysval
== PAN_SYSVAL_VIEWPORT_OFFSET
) {
1201 uniforms
[4*i
+ 0] = vp
->translate
[0];
1202 uniforms
[4*i
+ 1] = vp
->translate
[1];
1203 uniforms
[4*i
+ 2] = vp
->translate
[2];
1209 /* Upload uniforms */
1210 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1212 int uniform_count
= 0;
1214 struct mali_vertex_tiler_postfix
*postfix
;
1217 case PIPE_SHADER_VERTEX
:
1218 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1219 postfix
= &ctx
->payload_vertex
.postfix
;
1222 case PIPE_SHADER_FRAGMENT
:
1223 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1224 postfix
= &ctx
->payload_tiler
.postfix
;
1228 unreachable("Invalid shader stage\n");
1231 /* Also attach the same buffer as a UBO for extended access */
1233 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1235 .size
= MALI_POSITIVE((2 + uniform_count
)),
1236 .ptr
= transfer
.gpu
>> 2,
1240 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1241 postfix
->uniforms
= transfer
.gpu
;
1242 postfix
->uniform_buffers
= ubufs
;
1247 /* TODO: Upload the viewport somewhere more appropriate */
1249 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1250 * (somewhat) asymmetric ints. */
1251 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1253 struct mali_viewport view
= {
1254 /* By default, do no viewport clipping, i.e. clip to (-inf,
1255 * inf) in each direction. Clipping to the viewport in theory
1256 * should work, but in practice causes issues when we're not
1257 * explicitly trying to scissor */
1268 /* Always scissor to the viewport by default. */
1269 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1270 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1272 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1273 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1275 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1276 view
.viewport0
[0] = ss
->minx
;
1277 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1283 /* Hardware needs the min/max to be strictly ordered, so flip if we
1291 view
.viewport0
[1] = miny
;
1292 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1294 ctx
->payload_tiler
.postfix
.viewport
=
1295 panfrost_upload_transient(ctx
,
1297 sizeof(struct mali_viewport
));
1302 /* Corresponds to exactly one draw, but does not submit anything */
1305 panfrost_queue_draw(struct panfrost_context
*ctx
)
1307 /* TODO: Expand the array? */
1308 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1309 DBG("Job buffer overflow, ignoring draw\n");
1313 /* Handle dirty flags now */
1314 panfrost_emit_for_draw(ctx
, true);
1316 /* We need a set_value job before any other draw jobs */
1317 if (ctx
->draw_count
== 0)
1318 panfrost_set_value_job(ctx
);
1320 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1321 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1322 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1324 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true);
1325 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1326 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1331 /* The entire frame is in memory -- send it off to the kernel! */
1334 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1335 struct pipe_fence_handle
**fence
,
1336 struct panfrost_job
*job
)
1338 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1339 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1341 /* Edge case if screen is cleared and nothing else */
1342 bool has_draws
= ctx
->draw_count
> 0;
1344 /* Workaround a bizarre lockup (a hardware errata?) */
1346 flush_immediate
= true;
1350 bool is_scanout
= panfrost_is_scanout(ctx
);
1351 screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1353 /* If visual, we can stall a frame */
1355 if (!flush_immediate
)
1356 screen
->driver
->force_flush_fragment(ctx
, fence
);
1358 screen
->last_fragment_flushed
= false;
1359 screen
->last_job
= job
;
1361 /* If readback, flush now (hurts the pipelined performance) */
1362 if (flush_immediate
)
1363 screen
->driver
->force_flush_fragment(ctx
, fence
);
1365 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1366 screen
->driver
->dump_counters(screen
);
1369 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1370 FILE *fp
= fopen(filename
, "wb");
1371 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1379 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1381 struct panfrost_context
*ctx
= pan_context(pipe
);
1383 /* Nothing to reload? */
1384 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1387 /* Blit the wallpaper in */
1388 panfrost_blit_wallpaper(ctx
);
1390 /* We are flushing all queued draws and we know that no more jobs will
1391 * be added until the next frame.
1392 * We also know that the last jobs are the wallpaper jobs, and they
1393 * need to be linked so they execute right after the set_value job.
1396 /* set_value job to wallpaper vertex job */
1397 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[ctx
->vertex_job_count
- 1]);
1398 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1400 /* wallpaper vertex job to first vertex job */
1401 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1], ctx
->vertex_jobs
[0]);
1402 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1404 /* last vertex job to wallpaper tiler job */
1405 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 2], ctx
->tiler_jobs
[ctx
->tiler_job_count
- 1]);
1406 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_1
= ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_index
;
1407 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_2
= 0;
1409 /* wallpaper tiler job to first tiler job */
1410 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1], ctx
->tiler_jobs
[0]);
1411 ctx
->u_tiler_jobs
[0]->job_dependency_index_1
= ctx
->u_vertex_jobs
[0]->job_index
;
1412 ctx
->u_tiler_jobs
[0]->job_dependency_index_2
= ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_index
;
1414 /* last tiler job to NULL */
1415 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 2], 0);
1420 struct pipe_context
*pipe
,
1421 struct pipe_fence_handle
**fence
,
1424 struct panfrost_context
*ctx
= pan_context(pipe
);
1425 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1427 /* Nothing to do! */
1428 if (!ctx
->draw_count
&& !job
->clear
) return;
1431 panfrost_draw_wallpaper(&ctx
->base
);
1433 /* Whether to stall the pipeline for immediately correct results */
1434 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1436 /* Submit the frame itself */
1437 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1439 /* Prepare for the next frame */
1440 panfrost_invalidate_frame(ctx
);
1443 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1446 g2m_draw_mode(enum pipe_prim_type mode
)
1449 DEFINE_CASE(POINTS
);
1451 DEFINE_CASE(LINE_LOOP
);
1452 DEFINE_CASE(LINE_STRIP
);
1453 DEFINE_CASE(TRIANGLES
);
1454 DEFINE_CASE(TRIANGLE_STRIP
);
1455 DEFINE_CASE(TRIANGLE_FAN
);
1457 DEFINE_CASE(QUAD_STRIP
);
1458 DEFINE_CASE(POLYGON
);
1461 unreachable("Invalid draw mode");
1468 panfrost_translate_index_size(unsigned size
)
1472 return MALI_DRAW_INDEXED_UINT8
;
1475 return MALI_DRAW_INDEXED_UINT16
;
1478 return MALI_DRAW_INDEXED_UINT32
;
1481 unreachable("Invalid index size");
1485 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1486 * good for the duration of the draw (transient), could last longer */
1489 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1491 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1493 off_t offset
= info
->start
* info
->index_size
;
1495 if (!info
->has_user_indices
) {
1496 /* Only resources can be directly mapped */
1497 return rsrc
->bo
->gpu
+ offset
;
1499 /* Otherwise, we need to upload to transient memory */
1500 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1501 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1507 struct pipe_context
*pipe
,
1508 const struct pipe_draw_info
*info
)
1510 struct panfrost_context
*ctx
= pan_context(pipe
);
1512 ctx
->payload_vertex
.draw_start
= info
->start
;
1513 ctx
->payload_tiler
.draw_start
= info
->start
;
1515 int mode
= info
->mode
;
1517 /* Fallback for unsupported modes */
1519 if (!(ctx
->draw_modes
& (1 << mode
))) {
1520 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1521 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1523 if (info
->count
< 4) {
1524 /* Degenerate case? */
1528 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1529 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1534 /* Now that we have a guaranteed terminating path, find the job.
1535 * Assignment commented out to prevent unused warning */
1537 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1539 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1541 ctx
->vertex_count
= info
->count
;
1543 /* For non-indexed draws, they're the same */
1544 unsigned invocation_count
= ctx
->vertex_count
;
1546 unsigned draw_flags
= 0;
1548 /* The draw flags interpret how primitive size is interpreted */
1550 if (panfrost_writes_point_size(ctx
))
1551 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1553 /* For higher amounts of vertices (greater than what fits in a 16-bit
1554 * short), the other value is needed, otherwise there will be bizarre
1555 * rendering artefacts. It's not clear what these values mean yet. */
1557 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1559 if (info
->index_size
) {
1560 /* Calculate the min/max index used so we can figure out how
1561 * many times to invoke the vertex shader */
1563 /* Fetch / calculate index bounds */
1564 unsigned min_index
= 0, max_index
= 0;
1566 if (info
->max_index
== ~0u) {
1567 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1569 min_index
= info
->min_index
;
1570 max_index
= info
->max_index
;
1573 /* Use the corresponding values */
1574 invocation_count
= max_index
- min_index
+ 1;
1575 ctx
->payload_vertex
.draw_start
= min_index
;
1576 ctx
->payload_tiler
.draw_start
= min_index
;
1578 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1579 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1581 //assert(!info->restart_index); /* TODO: Research */
1582 assert(!info
->index_bias
);
1584 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1585 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1587 /* Index count == vertex count, if no indexing is applied, as
1588 * if it is internally indexed in the expected order */
1590 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1591 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1593 /* Reverse index state */
1594 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1597 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1598 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1599 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1601 /* Fire off the draw itself */
1602 panfrost_queue_draw(ctx
);
1608 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1614 panfrost_create_rasterizer_state(
1615 struct pipe_context
*pctx
,
1616 const struct pipe_rasterizer_state
*cso
)
1618 struct panfrost_context
*ctx
= pan_context(pctx
);
1619 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1623 /* Bitmask, unknown meaning of the start value */
1624 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1627 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1629 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1630 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1632 if (cso
->cull_face
& PIPE_FACE_BACK
)
1633 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1639 panfrost_bind_rasterizer_state(
1640 struct pipe_context
*pctx
,
1643 struct panfrost_context
*ctx
= pan_context(pctx
);
1645 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1649 ctx
->rasterizer
= hwcso
;
1650 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1654 panfrost_create_vertex_elements_state(
1655 struct pipe_context
*pctx
,
1656 unsigned num_elements
,
1657 const struct pipe_vertex_element
*elements
)
1659 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1661 so
->num_elements
= num_elements
;
1662 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1664 /* XXX: What the cornball? This is totally, 100%, unapologetically
1665 * nonsense. And yet it somehow fixes a regression in -bshadow
1666 * (previously, we allocated the descriptor here... a newer commit
1667 * removed that allocation, and then memory corruption led to
1668 * shader_meta getting overwritten in bad ways and then the whole test
1669 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1671 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1673 for (int i
= 0; i
< num_elements
; ++i
) {
1674 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1676 enum pipe_format fmt
= elements
[i
].src_format
;
1677 const struct util_format_description
*desc
= util_format_description(fmt
);
1678 so
->hw
[i
].unknown1
= 0x2;
1679 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1681 so
->hw
[i
].format
= panfrost_find_format(desc
);
1683 /* The field itself should probably be shifted over */
1684 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1691 panfrost_bind_vertex_elements_state(
1692 struct pipe_context
*pctx
,
1695 struct panfrost_context
*ctx
= pan_context(pctx
);
1697 ctx
->vertex
= hwcso
;
1698 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1702 panfrost_create_shader_state(
1703 struct pipe_context
*pctx
,
1704 const struct pipe_shader_state
*cso
)
1706 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1709 /* Token deep copy to prevent memory corruption */
1711 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1712 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1718 panfrost_delete_shader_state(
1719 struct pipe_context
*pctx
,
1722 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1724 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1725 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1732 panfrost_create_sampler_state(
1733 struct pipe_context
*pctx
,
1734 const struct pipe_sampler_state
*cso
)
1736 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1739 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1741 struct mali_sampler_descriptor sampler_descriptor
= {
1742 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1743 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1744 | translate_mip_filter(cso
->min_mip_filter
)
1747 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1748 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1749 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1750 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1752 cso
->border_color
.f
[0],
1753 cso
->border_color
.f
[1],
1754 cso
->border_color
.f
[2],
1755 cso
->border_color
.f
[3]
1757 .min_lod
= FIXED_16(cso
->min_lod
),
1758 .max_lod
= FIXED_16(cso
->max_lod
),
1762 so
->hw
= sampler_descriptor
;
1768 panfrost_bind_sampler_states(
1769 struct pipe_context
*pctx
,
1770 enum pipe_shader_type shader
,
1771 unsigned start_slot
, unsigned num_sampler
,
1774 assert(start_slot
== 0);
1776 struct panfrost_context
*ctx
= pan_context(pctx
);
1778 /* XXX: Should upload, not just copy? */
1779 ctx
->sampler_count
[shader
] = num_sampler
;
1780 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1782 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1786 panfrost_variant_matches(
1787 struct panfrost_context
*ctx
,
1788 struct panfrost_shader_state
*variant
,
1789 enum pipe_shader_type type
)
1791 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1793 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1795 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1796 /* Make sure enable state is at least the same */
1797 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1801 /* Check that the contents of the test are the same */
1802 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1803 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1805 if (!(same_func
&& same_ref
)) {
1809 /* Otherwise, we're good to go */
1814 panfrost_bind_shader_state(
1815 struct pipe_context
*pctx
,
1817 enum pipe_shader_type type
)
1819 struct panfrost_context
*ctx
= pan_context(pctx
);
1821 if (type
== PIPE_SHADER_FRAGMENT
) {
1823 ctx
->dirty
|= PAN_DIRTY_FS
;
1825 assert(type
== PIPE_SHADER_VERTEX
);
1827 ctx
->dirty
|= PAN_DIRTY_VS
;
1832 /* Match the appropriate variant */
1834 signed variant
= -1;
1835 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1837 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1838 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1844 if (variant
== -1) {
1845 /* No variant matched, so create a new one */
1846 variant
= variants
->variant_count
++;
1847 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1849 variants
->variants
[variant
].base
= hwcso
;
1851 if (type
== PIPE_SHADER_FRAGMENT
)
1852 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1854 /* Allocate the mapped descriptor ahead-of-time. */
1855 struct panfrost_context
*ctx
= pan_context(pctx
);
1856 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1858 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1859 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1863 /* Select this variant */
1864 variants
->active_variant
= variant
;
1866 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1867 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1869 /* We finally have a variant, so compile it */
1871 if (!shader_state
->compiled
) {
1872 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
1873 panfrost_job_type_for_pipe(type
), shader_state
);
1875 shader_state
->compiled
= true;
1880 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1882 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1886 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1888 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1892 panfrost_set_vertex_buffers(
1893 struct pipe_context
*pctx
,
1894 unsigned start_slot
,
1895 unsigned num_buffers
,
1896 const struct pipe_vertex_buffer
*buffers
)
1898 struct panfrost_context
*ctx
= pan_context(pctx
);
1900 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1904 panfrost_set_constant_buffer(
1905 struct pipe_context
*pctx
,
1906 enum pipe_shader_type shader
, uint index
,
1907 const struct pipe_constant_buffer
*buf
)
1909 struct panfrost_context
*ctx
= pan_context(pctx
);
1910 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1912 size_t sz
= buf
? buf
->buffer_size
: 0;
1914 /* Free previous buffer */
1921 pbuf
->buffer
= NULL
;
1924 /* If unbinding, we're done */
1929 /* Multiple constant buffers not yet supported */
1934 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1937 cpu
= rsrc
->bo
->cpu
;
1938 } else if (buf
->user_buffer
) {
1939 cpu
= buf
->user_buffer
;
1941 DBG("No constant buffer?\n");
1945 /* Copy the constant buffer into the driver context for later upload */
1947 pbuf
->buffer
= malloc(sz
);
1948 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1952 panfrost_set_stencil_ref(
1953 struct pipe_context
*pctx
,
1954 const struct pipe_stencil_ref
*ref
)
1956 struct panfrost_context
*ctx
= pan_context(pctx
);
1957 ctx
->stencil_ref
= *ref
;
1959 /* Shader core dirty */
1960 ctx
->dirty
|= PAN_DIRTY_FS
;
1963 static struct pipe_sampler_view
*
1964 panfrost_create_sampler_view(
1965 struct pipe_context
*pctx
,
1966 struct pipe_resource
*texture
,
1967 const struct pipe_sampler_view
*template)
1969 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1970 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1972 pipe_reference(NULL
, &texture
->reference
);
1974 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1977 so
->base
= *template;
1978 so
->base
.texture
= texture
;
1979 so
->base
.reference
.count
= 1;
1980 so
->base
.context
= pctx
;
1982 /* sampler_views correspond to texture descriptors, minus the texture
1983 * (data) itself. So, we serialise the descriptor here and cache it for
1986 /* Make sure it's something with which we're familiar */
1987 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1989 /* TODO: Detect from format better */
1990 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1992 unsigned char user_swizzle
[4] = {
1993 template->swizzle_r
,
1994 template->swizzle_g
,
1995 template->swizzle_b
,
1999 enum mali_format format
= panfrost_find_format(desc
);
2001 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2003 unsigned usage2_layout
= 0x10;
2005 switch (prsrc
->bo
->layout
) {
2007 usage2_layout
|= 0x8 | 0x4;
2010 usage2_layout
|= 0x1;
2013 usage2_layout
|= is_depth
? 0x1 : 0x2;
2020 /* Check if we need to set a custom stride by computing the "expected"
2021 * stride and comparing it to what the BO actually wants. Only applies
2022 * to linear textures, since tiled/compressed textures have strict
2023 * alignment requirements for their strides as it is */
2025 unsigned first_level
= template->u
.tex
.first_level
;
2026 unsigned last_level
= template->u
.tex
.last_level
;
2028 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
2029 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2030 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
2031 unsigned width
= u_minify(texture
->width0
, l
);
2032 unsigned comp_stride
= width
* bytes_per_pixel
;
2034 if (comp_stride
!= actual_stride
) {
2035 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2041 struct mali_texture_descriptor texture_descriptor
= {
2042 .width
= MALI_POSITIVE(texture
->width0
),
2043 .height
= MALI_POSITIVE(texture
->height0
),
2044 .depth
= MALI_POSITIVE(texture
->depth0
),
2048 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2052 .is_not_cubemap
= texture
->target
!= PIPE_TEXTURE_CUBE
,
2054 .usage2
= usage2_layout
2057 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2060 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2061 assert (template->u
.tex
.first_level
== 0);
2063 /* Disable mipmapping for now to avoid regressions while automipmapping
2064 * is being implemented. TODO: Remove me once automipmaps work */
2066 //texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2067 texture_descriptor
.nr_mipmap_levels
= 0;
2069 so
->hw
= texture_descriptor
;
2071 return (struct pipe_sampler_view
*) so
;
2075 panfrost_set_sampler_views(
2076 struct pipe_context
*pctx
,
2077 enum pipe_shader_type shader
,
2078 unsigned start_slot
, unsigned num_views
,
2079 struct pipe_sampler_view
**views
)
2081 struct panfrost_context
*ctx
= pan_context(pctx
);
2083 assert(start_slot
== 0);
2085 ctx
->sampler_view_count
[shader
] = num_views
;
2086 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2088 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2092 panfrost_sampler_view_destroy(
2093 struct pipe_context
*pctx
,
2094 struct pipe_sampler_view
*view
)
2096 pipe_resource_reference(&view
->texture
, NULL
);
2101 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2102 const struct pipe_framebuffer_state
*fb
)
2104 struct panfrost_context
*ctx
= pan_context(pctx
);
2106 /* Flush when switching away from an FBO, but not if the framebuffer
2107 * state is being restored by u_blitter
2110 if (!panfrost_is_scanout(ctx
) && !ctx
->blitter
->running
) {
2111 panfrost_flush(pctx
, NULL
, 0);
2114 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2115 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2116 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2117 ctx
->pipe_framebuffer
.width
= fb
->width
;
2118 ctx
->pipe_framebuffer
.height
= fb
->height
;
2120 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2121 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2123 /* check if changing cbuf */
2124 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2126 if (cb
&& (i
!= 0)) {
2127 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2132 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2137 if (ctx
->require_sfbd
)
2138 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2140 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2142 panfrost_attach_vt_framebuffer(ctx
);
2144 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2145 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2147 bool can_afbc
= panfrost_format_supports_afbc(format
);
2148 bool is_scanout
= panfrost_is_scanout(ctx
);
2150 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2151 panfrost_enable_afbc(ctx
, tex
, false);
2153 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2154 panfrost_enable_checksum(ctx
, tex
);
2158 struct pipe_surface
*zb
= fb
->zsbuf
;
2160 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2161 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2164 if (ctx
->require_sfbd
)
2165 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2167 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2169 panfrost_attach_vt_framebuffer(ctx
);
2171 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2172 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2173 bool is_scanout
= panfrost_is_scanout(ctx
);
2175 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2176 panfrost_enable_afbc(ctx
, tex
, true);
2183 panfrost_create_blend_state(struct pipe_context
*pipe
,
2184 const struct pipe_blend_state
*blend
)
2186 struct panfrost_context
*ctx
= pan_context(pipe
);
2187 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2190 /* TODO: The following features are not yet implemented */
2191 assert(!blend
->logicop_enable
);
2192 assert(!blend
->alpha_to_coverage
);
2193 assert(!blend
->alpha_to_one
);
2195 /* Compile the blend state, first as fixed-function if we can */
2197 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2200 /* If we can't, compile a blend shader instead */
2202 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2208 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2211 struct panfrost_context
*ctx
= pan_context(pipe
);
2212 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2213 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2214 ctx
->blend
= pblend
;
2219 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2221 /* TODO: Attach color */
2223 /* Shader itself is not dirty, but the shader core is */
2224 ctx
->dirty
|= PAN_DIRTY_FS
;
2228 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2231 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2233 if (so
->has_blend_shader
) {
2234 DBG("Deleting blend state leak blend shaders bytecode\n");
2241 panfrost_set_blend_color(struct pipe_context
*pipe
,
2242 const struct pipe_blend_color
*blend_color
)
2244 struct panfrost_context
*ctx
= pan_context(pipe
);
2246 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2249 ctx
->blend_color
= *blend_color
;
2251 /* The blend mode depends on the blend constant color, due to the
2252 * fixed/programmable split. So, we're forced to regenerate the blend
2255 /* TODO: Attach color */
2260 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2261 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2263 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2267 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2270 struct panfrost_context
*ctx
= pan_context(pipe
);
2271 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2272 ctx
->depth_stencil
= depth_stencil
;
2277 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2278 * emulated in the fragment shader */
2280 if (depth_stencil
->alpha
.enabled
) {
2281 /* We need to trigger a new shader (maybe) */
2282 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2286 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2288 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2289 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2291 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2292 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2294 /* Depth state (TODO: Refactor) */
2295 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2297 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2299 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2300 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2302 /* Bounds test not implemented */
2303 assert(!depth_stencil
->depth
.bounds_test
);
2305 ctx
->dirty
|= PAN_DIRTY_FS
;
2309 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2315 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2316 unsigned sample_mask
)
2321 panfrost_set_clip_state(struct pipe_context
*pipe
,
2322 const struct pipe_clip_state
*clip
)
2324 //struct panfrost_context *panfrost = pan_context(pipe);
2328 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2329 unsigned start_slot
,
2330 unsigned num_viewports
,
2331 const struct pipe_viewport_state
*viewports
)
2333 struct panfrost_context
*ctx
= pan_context(pipe
);
2335 assert(start_slot
== 0);
2336 assert(num_viewports
== 1);
2338 ctx
->pipe_viewport
= *viewports
;
2342 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2343 unsigned start_slot
,
2344 unsigned num_scissors
,
2345 const struct pipe_scissor_state
*scissors
)
2347 struct panfrost_context
*ctx
= pan_context(pipe
);
2349 assert(start_slot
== 0);
2350 assert(num_scissors
== 1);
2352 ctx
->scissor
= *scissors
;
2356 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2357 const struct pipe_poly_stipple
*stipple
)
2359 //struct panfrost_context *panfrost = pan_context(pipe);
2363 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2366 //struct panfrost_context *panfrost = pan_context(pipe);
2370 panfrost_destroy(struct pipe_context
*pipe
)
2372 struct panfrost_context
*panfrost
= pan_context(pipe
);
2373 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2375 if (panfrost
->blitter
)
2376 util_blitter_destroy(panfrost
->blitter
);
2378 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2379 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2380 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2381 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2382 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2385 static struct pipe_query
*
2386 panfrost_create_query(struct pipe_context
*pipe
,
2390 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2395 return (struct pipe_query
*) q
;
2399 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2405 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2407 struct panfrost_context
*ctx
= pan_context(pipe
);
2408 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2410 switch (query
->type
) {
2411 case PIPE_QUERY_OCCLUSION_COUNTER
:
2412 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2413 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2415 /* Allocate a word for the query results to be stored */
2416 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2418 ctx
->occlusion_query
= query
;
2424 DBG("Skipping query %d\n", query
->type
);
2432 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2434 struct panfrost_context
*ctx
= pan_context(pipe
);
2435 ctx
->occlusion_query
= NULL
;
2440 panfrost_get_query_result(struct pipe_context
*pipe
,
2441 struct pipe_query
*q
,
2443 union pipe_query_result
*vresult
)
2446 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2448 /* We need to flush out the jobs to actually run the counter, TODO
2449 * check wait, TODO wallpaper after if needed */
2451 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2453 switch (query
->type
) {
2454 case PIPE_QUERY_OCCLUSION_COUNTER
:
2455 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2456 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2457 /* Read back the query results */
2458 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2459 unsigned passed
= *result
;
2461 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2462 vresult
->u64
= passed
;
2464 vresult
->b
= !!passed
;
2470 DBG("Skipped query get %d\n", query
->type
);
2477 static struct pipe_stream_output_target
*
2478 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2479 struct pipe_resource
*prsc
,
2480 unsigned buffer_offset
,
2481 unsigned buffer_size
)
2483 struct pipe_stream_output_target
*target
;
2485 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2490 pipe_reference_init(&target
->reference
, 1);
2491 pipe_resource_reference(&target
->buffer
, prsc
);
2493 target
->context
= pctx
;
2494 target
->buffer_offset
= buffer_offset
;
2495 target
->buffer_size
= buffer_size
;
2501 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2502 struct pipe_stream_output_target
*target
)
2504 pipe_resource_reference(&target
->buffer
, NULL
);
2509 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2510 unsigned num_targets
,
2511 struct pipe_stream_output_target
**targets
,
2512 const unsigned *offsets
)
2518 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2520 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2521 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2523 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2524 /* Allocate the beginning of the transient pool */
2525 int entry_size
= (1 << 22); /* 4MB */
2527 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2528 ctx
->transient_pools
[i
].entry_count
= 1;
2530 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2533 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2534 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2535 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2536 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2537 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2541 /* New context creation, which also does hardware initialisation since I don't
2542 * know the better way to structure this :smirk: */
2544 struct pipe_context
*
2545 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2547 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2548 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2549 memset(ctx
, 0, sizeof(*ctx
));
2550 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2553 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2555 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2556 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2558 gallium
->screen
= screen
;
2560 gallium
->destroy
= panfrost_destroy
;
2562 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2564 gallium
->flush
= panfrost_flush
;
2565 gallium
->clear
= panfrost_clear
;
2566 gallium
->draw_vbo
= panfrost_draw_vbo
;
2568 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2569 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2571 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2573 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2574 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2575 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2577 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2578 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2579 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2581 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2582 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2583 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2585 gallium
->create_fs_state
= panfrost_create_shader_state
;
2586 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2587 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2589 gallium
->create_vs_state
= panfrost_create_shader_state
;
2590 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2591 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2593 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2594 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2595 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2597 gallium
->create_blend_state
= panfrost_create_blend_state
;
2598 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2599 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2601 gallium
->set_blend_color
= panfrost_set_blend_color
;
2603 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2604 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2605 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2607 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2609 gallium
->set_clip_state
= panfrost_set_clip_state
;
2610 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2611 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2612 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2613 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2615 gallium
->create_query
= panfrost_create_query
;
2616 gallium
->destroy_query
= panfrost_destroy_query
;
2617 gallium
->begin_query
= panfrost_begin_query
;
2618 gallium
->end_query
= panfrost_end_query
;
2619 gallium
->get_query_result
= panfrost_get_query_result
;
2621 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2622 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2623 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2625 panfrost_resource_context_init(gallium
);
2627 pscreen
->driver
->init_context(ctx
);
2629 panfrost_setup_hardware(ctx
);
2632 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2633 gallium
->const_uploader
= gallium
->stream_uploader
;
2634 assert(gallium
->stream_uploader
);
2636 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2637 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2639 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2641 ctx
->blitter
= util_blitter_create(gallium
);
2642 assert(ctx
->blitter
);
2644 /* Prepare for render! */
2646 panfrost_job_init(ctx
);
2647 panfrost_emit_vertex_payload(ctx
);
2648 panfrost_emit_tiler_payload(ctx
);
2649 panfrost_invalidate_frame(ctx
);
2650 panfrost_default_shader_backend(ctx
);
2651 panfrost_generate_space_filler_indices();