2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
33 #include "panfrost-quirks.h"
35 #include "util/macros.h"
36 #include "util/format/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_memory.h"
40 #include "util/u_vbuf.h"
41 #include "util/half_float.h"
42 #include "util/u_helpers.h"
43 #include "util/format/u_format.h"
44 #include "util/u_prim.h"
45 #include "util/u_prim_restart.h"
46 #include "indices/u_primconvert.h"
47 #include "tgsi/tgsi_parse.h"
48 #include "tgsi/tgsi_from_mesa.h"
49 #include "util/u_math.h"
51 #include "pan_screen.h"
52 #include "pan_blending.h"
53 #include "pan_blend_shaders.h"
56 struct midgard_tiler_descriptor
57 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
59 struct panfrost_screen
*screen
= pan_screen(batch
->ctx
->base
.screen
);
60 bool hierarchy
= !(screen
->quirks
& MIDGARD_NO_HIER_TILING
);
61 struct midgard_tiler_descriptor t
= {0};
62 unsigned height
= batch
->key
.height
;
63 unsigned width
= batch
->key
.width
;
66 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
, hierarchy
);
68 /* Compute the polygon header size and use that to offset the body */
70 unsigned header_size
= panfrost_tiler_header_size(
71 width
, height
, t
.hierarchy_mask
, hierarchy
);
73 t
.polygon_list_size
= panfrost_tiler_full_size(
74 width
, height
, t
.hierarchy_mask
, hierarchy
);
79 struct panfrost_bo
*tiler_heap
;
81 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
82 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
87 /* Allow the entire tiler heap */
88 t
.heap_start
= tiler_heap
->gpu
;
89 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
91 struct panfrost_bo
*tiler_dummy
;
93 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
94 header_size
= MALI_TILER_MINIMUM_HEADER_SIZE
;
96 /* The tiler is disabled, so don't allow the tiler heap */
97 t
.heap_start
= tiler_dummy
->gpu
;
98 t
.heap_end
= t
.heap_start
;
100 /* Use a dummy polygon list */
101 t
.polygon_list
= tiler_dummy
->gpu
;
103 /* Disable the tiler */
105 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
107 t
.hierarchy_mask
= MALI_TILER_USER
;
108 t
.polygon_list_size
= MALI_TILER_MINIMUM_HEADER_SIZE
+ 4;
110 /* We don't have a WRITE_VALUE job, so write the polygon list manually */
111 uint32_t *polygon_list_body
= (uint32_t *) (tiler_dummy
->cpu
+ header_size
);
112 polygon_list_body
[0] = 0xa0000000; /* TODO: Just that? */
116 t
.polygon_list_body
=
117 t
.polygon_list
+ header_size
;
124 struct pipe_context
*pipe
,
126 const union pipe_color_union
*color
,
127 double depth
, unsigned stencil
)
129 struct panfrost_context
*ctx
= pan_context(pipe
);
131 /* TODO: panfrost_get_fresh_batch_for_fbo() instantiates a new batch if
132 * the existing batch targeting this FBO has draws. We could probably
133 * avoid that by replacing plain clears by quad-draws with a specific
134 * color/depth/stencil value, thus avoiding the generation of extra
137 struct panfrost_batch
*batch
= panfrost_get_fresh_batch_for_fbo(ctx
);
139 panfrost_batch_add_fbo_bos(batch
);
140 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
144 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
146 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
147 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
149 /* If we haven't, reserve space for the framebuffer */
151 if (!batch
->framebuffer
.gpu
) {
152 unsigned size
= (screen
->quirks
& MIDGARD_SFBD
) ?
153 sizeof(struct mali_single_framebuffer
) :
154 sizeof(struct bifrost_framebuffer
);
156 batch
->framebuffer
= panfrost_allocate_transient(batch
, size
);
158 /* Tag the pointer */
159 if (!(screen
->quirks
& MIDGARD_SFBD
))
160 batch
->framebuffer
.gpu
|= MALI_MFBD
;
163 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
164 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
.gpu
;
167 /* Reset per-frame context, called on context initialisation as well as after
168 * flushing a frame */
171 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
173 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
174 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
177 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
180 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
182 /* TODO: When does this need to be handled? */
183 ctx
->active_queries
= true;
186 /* In practice, every field of these payloads should be configurable
187 * arbitrarily, which means these functions are basically catch-all's for
188 * as-of-yet unwavering unknowns */
191 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
193 /* 0x2 bit clear on 32-bit T6XX */
195 struct midgard_payload_vertex_tiler payload
= {
196 .gl_enables
= 0x4 | 0x2,
199 /* Vertex and compute are closely coupled, so share a payload */
201 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
202 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
206 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
208 struct midgard_payload_vertex_tiler payload
= {
210 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
214 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
218 translate_tex_wrap(enum pipe_tex_wrap w
)
221 case PIPE_TEX_WRAP_REPEAT
:
222 return MALI_WRAP_REPEAT
;
224 /* TODO: lower GL_CLAMP? */
225 case PIPE_TEX_WRAP_CLAMP
:
226 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
227 return MALI_WRAP_CLAMP_TO_EDGE
;
229 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
230 return MALI_WRAP_CLAMP_TO_BORDER
;
232 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
233 return MALI_WRAP_MIRRORED_REPEAT
;
236 unreachable("Invalid wrap");
241 panfrost_translate_compare_func(enum pipe_compare_func in
)
244 case PIPE_FUNC_NEVER
:
245 return MALI_FUNC_NEVER
;
248 return MALI_FUNC_LESS
;
250 case PIPE_FUNC_EQUAL
:
251 return MALI_FUNC_EQUAL
;
253 case PIPE_FUNC_LEQUAL
:
254 return MALI_FUNC_LEQUAL
;
256 case PIPE_FUNC_GREATER
:
257 return MALI_FUNC_GREATER
;
259 case PIPE_FUNC_NOTEQUAL
:
260 return MALI_FUNC_NOTEQUAL
;
262 case PIPE_FUNC_GEQUAL
:
263 return MALI_FUNC_GEQUAL
;
265 case PIPE_FUNC_ALWAYS
:
266 return MALI_FUNC_ALWAYS
;
269 unreachable("Invalid func");
274 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
277 case PIPE_FUNC_NEVER
:
278 return MALI_ALT_FUNC_NEVER
;
281 return MALI_ALT_FUNC_LESS
;
283 case PIPE_FUNC_EQUAL
:
284 return MALI_ALT_FUNC_EQUAL
;
286 case PIPE_FUNC_LEQUAL
:
287 return MALI_ALT_FUNC_LEQUAL
;
289 case PIPE_FUNC_GREATER
:
290 return MALI_ALT_FUNC_GREATER
;
292 case PIPE_FUNC_NOTEQUAL
:
293 return MALI_ALT_FUNC_NOTEQUAL
;
295 case PIPE_FUNC_GEQUAL
:
296 return MALI_ALT_FUNC_GEQUAL
;
298 case PIPE_FUNC_ALWAYS
:
299 return MALI_ALT_FUNC_ALWAYS
;
302 unreachable("Invalid alt func");
307 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
310 case PIPE_STENCIL_OP_KEEP
:
311 return MALI_STENCIL_KEEP
;
313 case PIPE_STENCIL_OP_ZERO
:
314 return MALI_STENCIL_ZERO
;
316 case PIPE_STENCIL_OP_REPLACE
:
317 return MALI_STENCIL_REPLACE
;
319 case PIPE_STENCIL_OP_INCR
:
320 return MALI_STENCIL_INCR
;
322 case PIPE_STENCIL_OP_DECR
:
323 return MALI_STENCIL_DECR
;
325 case PIPE_STENCIL_OP_INCR_WRAP
:
326 return MALI_STENCIL_INCR_WRAP
;
328 case PIPE_STENCIL_OP_DECR_WRAP
:
329 return MALI_STENCIL_DECR_WRAP
;
331 case PIPE_STENCIL_OP_INVERT
:
332 return MALI_STENCIL_INVERT
;
335 unreachable("Invalid stencil op");
340 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
342 out
->ref
= 0; /* Gallium gets it from elsewhere */
344 out
->mask
= in
->valuemask
;
345 out
->func
= panfrost_translate_compare_func(in
->func
);
346 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
347 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
348 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
352 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
354 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
355 struct mali_shader_meta shader
= {
356 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
358 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
359 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
362 /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this is
363 * required (independent of 32-bit/64-bit descriptors), or why it's not
364 * used on later GPU revisions. Otherwise, all shader jobs fault on
365 * these earlier chips (perhaps this is a chicken bit of some kind).
366 * More investigation is needed. */
368 if (screen
->quirks
& MIDGARD_SFBD
)
369 shader
.unknown2_4
|= 0x10;
371 struct pipe_stencil_state default_stencil
= {
373 .func
= PIPE_FUNC_ALWAYS
,
374 .fail_op
= MALI_STENCIL_KEEP
,
375 .zfail_op
= MALI_STENCIL_KEEP
,
376 .zpass_op
= MALI_STENCIL_KEEP
,
381 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
382 shader
.stencil_mask_front
= default_stencil
.writemask
;
384 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
385 shader
.stencil_mask_back
= default_stencil
.writemask
;
387 if (default_stencil
.enabled
)
388 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
390 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
393 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
394 * graphics command stream. It should be called once per draw, accordding to
395 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
396 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
399 struct panfrost_transfer
400 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
402 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
403 struct mali_job_descriptor_header job
= {
404 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
405 .job_descriptor_size
= 1,
408 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
410 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
411 memcpy(transfer
.cpu
, &job
, sizeof(job
));
412 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
417 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
419 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
420 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
422 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
426 panfrost_writes_point_size(struct panfrost_context
*ctx
)
428 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
429 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
431 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
434 /* Stage the attribute descriptors so we can adjust src_offset
435 * to let BOs align nicely */
438 panfrost_stage_attributes(struct panfrost_context
*ctx
)
440 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
441 struct panfrost_vertex_state
*so
= ctx
->vertex
;
443 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
444 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
445 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
447 /* Copy as-is for the first pass */
448 memcpy(target
, so
->hw
, sz
);
450 /* Fixup offsets for the second pass. Recall that the hardware
451 * calculates attribute addresses as:
453 * addr = base + (stride * vtx) + src_offset;
455 * However, on Mali, base must be aligned to 64-bytes, so we
458 * base' = base & ~63 = base - (base & 63)
460 * To compensate when using base' (see emit_vertex_data), we have
461 * to adjust src_offset by the masked off piece:
463 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
464 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
465 * = base + (stride * vtx) + src_offset
471 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
473 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
474 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
475 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
476 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
478 /* Adjust by the masked off bits of the offset */
479 target
[i
].src_offset
+= (addr
& 63);
481 /* Also, somewhat obscurely per-instance data needs to be
482 * offset in response to a delayed start in an indexed draw */
484 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
485 target
[i
].src_offset
-= buf
->stride
* start
;
491 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
495 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
497 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
498 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
500 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
503 if (ctx
->sampler_count
[t
]) {
504 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
506 struct panfrost_transfer transfer
=
507 panfrost_allocate_transient(batch
, transfer_size
);
509 struct mali_sampler_descriptor
*desc
=
510 (struct mali_sampler_descriptor
*) transfer
.cpu
;
512 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
513 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
515 upload
= transfer
.gpu
;
518 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
522 static enum mali_texture_layout
523 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
525 /* TODO: other linear depth textures */
526 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
528 switch (rsrc
->layout
) {
530 return MALI_TEXTURE_AFBC
;
533 return MALI_TEXTURE_TILED
;
535 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
537 unreachable("Invalid texture layout");
543 struct panfrost_context
*ctx
,
544 enum pipe_shader_type st
,
545 struct panfrost_sampler_view
*view
)
550 struct pipe_sampler_view
*pview
= &view
->base
;
551 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
553 /* Do we interleave an explicit stride with every element? */
555 bool has_manual_stride
= view
->manual_stride
;
557 /* For easy access */
559 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
560 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
561 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
562 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
563 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
565 /* Lower-bit is set when sampling from colour AFBC */
566 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
567 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
568 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
570 /* Add the BO to the job so it's retained until the job is done. */
571 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
572 panfrost_batch_add_bo(batch
, rsrc
->bo
,
573 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_READ
|
574 panfrost_bo_access_for_stage(st
));
576 /* Add the usage flags in, since they can change across the CSO
577 * lifetime due to layout switches */
579 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
580 view
->hw
.format
.manual_stride
= has_manual_stride
;
582 /* Inject the addresses in, interleaving mip levels, cube faces, and
583 * strides in that order */
587 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
588 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
590 view
->hw
.payload
[idx
++] =
591 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
593 if (has_manual_stride
) {
594 view
->hw
.payload
[idx
++] =
595 rsrc
->slices
[l
].stride
;
600 return panfrost_upload_transient(batch
, &view
->hw
,
601 sizeof(struct mali_texture_descriptor
));
605 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
607 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
609 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
610 mali_ptr trampoline
= 0;
612 if (ctx
->sampler_view_count
[t
]) {
613 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
615 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
617 panfrost_upload_tex(ctx
, t
, ctx
->sampler_views
[t
][i
]);
619 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
622 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
626 struct sysval_uniform
{
635 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
636 struct sysval_uniform
*uniform
)
638 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
640 uniform
->f
[0] = vp
->scale
[0];
641 uniform
->f
[1] = vp
->scale
[1];
642 uniform
->f
[2] = vp
->scale
[2];
645 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
646 struct sysval_uniform
*uniform
)
648 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
650 uniform
->f
[0] = vp
->translate
[0];
651 uniform
->f
[1] = vp
->translate
[1];
652 uniform
->f
[2] = vp
->translate
[2];
655 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
656 enum pipe_shader_type st
,
657 unsigned int sysvalid
,
658 struct sysval_uniform
*uniform
)
660 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
661 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
662 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
663 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
666 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
669 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
670 tex
->u
.tex
.first_level
);
673 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
674 tex
->u
.tex
.first_level
);
677 uniform
->i
[dim
] = tex
->texture
->array_size
;
680 static void panfrost_upload_ssbo_sysval(
681 struct panfrost_context
*ctx
,
682 enum pipe_shader_type st
,
684 struct sysval_uniform
*uniform
)
686 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
687 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
689 /* Compute address */
690 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
691 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
693 panfrost_batch_add_bo(batch
, bo
,
694 PAN_BO_ACCESS_SHARED
| PAN_BO_ACCESS_RW
|
695 panfrost_bo_access_for_stage(st
));
697 /* Upload address and size as sysval */
698 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
699 uniform
->u
[2] = sb
.buffer_size
;
703 panfrost_upload_sampler_sysval(
704 struct panfrost_context
*ctx
,
705 enum pipe_shader_type st
,
706 unsigned sampler_index
,
707 struct sysval_uniform
*uniform
)
709 struct pipe_sampler_state
*sampl
=
710 &ctx
->samplers
[st
][sampler_index
]->base
;
712 uniform
->f
[0] = sampl
->min_lod
;
713 uniform
->f
[1] = sampl
->max_lod
;
714 uniform
->f
[2] = sampl
->lod_bias
;
716 /* Even without any errata, Midgard represents "no mipmapping" as
717 * fixing the LOD with the clamps; keep behaviour consistent. c.f.
718 * panfrost_create_sampler_state which also explains our choice of
719 * epsilon value (again to keep behaviour consistent) */
721 if (sampl
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
722 uniform
->f
[1] = uniform
->f
[0] + (1.0/256.0);
725 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
726 struct sysval_uniform
*uniform
)
728 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
729 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
730 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
733 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
734 struct panfrost_shader_state
*ss
,
735 enum pipe_shader_type st
)
737 struct sysval_uniform
*uniforms
= (void *)buf
;
739 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
740 int sysval
= ss
->sysval
[i
];
742 switch (PAN_SYSVAL_TYPE(sysval
)) {
743 case PAN_SYSVAL_VIEWPORT_SCALE
:
744 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
746 case PAN_SYSVAL_VIEWPORT_OFFSET
:
747 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
749 case PAN_SYSVAL_TEXTURE_SIZE
:
750 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
753 case PAN_SYSVAL_SSBO
:
754 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
757 case PAN_SYSVAL_NUM_WORK_GROUPS
:
758 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
760 case PAN_SYSVAL_SAMPLER
:
761 panfrost_upload_sampler_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
771 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
773 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
774 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
777 return rsrc
->bo
->cpu
;
778 else if (cb
->user_buffer
)
779 return cb
->user_buffer
;
781 unreachable("No constant buffer");
785 panfrost_map_constant_buffer_gpu(
786 struct panfrost_context
*ctx
,
787 enum pipe_shader_type st
,
788 struct panfrost_constant_buffer
*buf
,
791 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
792 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
793 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
796 panfrost_batch_add_bo(batch
, rsrc
->bo
,
797 PAN_BO_ACCESS_SHARED
|
799 panfrost_bo_access_for_stage(st
));
800 return rsrc
->bo
->gpu
;
801 } else if (cb
->user_buffer
) {
802 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
804 unreachable("No constant buffer");
808 /* Compute number of UBOs active (more specifically, compute the highest UBO
809 * number addressable -- if there are gaps, include them in the count anyway).
810 * We always include UBO #0 in the count, since we *need* uniforms enabled for
814 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
816 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
817 return 32 - __builtin_clz(mask
);
820 /* Fixes up a shader state with current state */
823 panfrost_patch_shader_state(struct panfrost_context
*ctx
,
824 enum pipe_shader_type stage
)
826 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
829 ctx
->payloads
[stage
].postfix
.shader
= 0;
833 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
835 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
836 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
838 ss
->tripipe
->midgard1
.flags
= 0x220;
840 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
841 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
843 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
845 /* Add the shader BO to the batch. */
846 panfrost_batch_add_bo(batch
, ss
->bo
,
847 PAN_BO_ACCESS_PRIVATE
|
849 panfrost_bo_access_for_stage(stage
));
851 ctx
->payloads
[stage
].postfix
.shader
= panfrost_upload_transient(batch
,
853 sizeof(struct mali_shader_meta
));
856 /* Go through dirty flags and actualise them in the cmdstream. */
859 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
861 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
862 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
864 panfrost_batch_add_fbo_bos(batch
);
865 panfrost_attach_vt_framebuffer(ctx
);
867 if (with_vertex_data
) {
868 panfrost_emit_vertex_data(batch
);
870 /* Varyings emitted for -all- geometry */
871 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
872 panfrost_emit_varying_descriptor(ctx
, total_count
);
875 bool msaa
= ctx
->rasterizer
->base
.multisample
;
877 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
878 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
880 /* TODO: Sample size */
881 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
882 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
885 panfrost_batch_set_requirements(batch
);
887 if (ctx
->occlusion_query
) {
888 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
;
889 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->bo
->gpu
;
892 panfrost_patch_shader_state(ctx
, PIPE_SHADER_VERTEX
);
893 panfrost_patch_shader_state(ctx
, PIPE_SHADER_COMPUTE
);
895 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
896 /* Check if we need to link the gl_PointSize varying */
897 if (!panfrost_writes_point_size(ctx
)) {
898 /* If the size is constant, write it out. Otherwise,
899 * don't touch primitive_size (since we would clobber
900 * the pointer there) */
902 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
906 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
907 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
908 ctx
->dirty
|= PAN_DIRTY_FS
;
910 if (ctx
->dirty
& PAN_DIRTY_FS
) {
911 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
912 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
914 panfrost_patch_shader_state(ctx
, PIPE_SHADER_FRAGMENT
);
916 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
919 COPY(attribute_count
);
923 COPY(midgard1
.uniform_count
);
924 COPY(midgard1
.uniform_buffer_count
);
925 COPY(midgard1
.work_count
);
926 COPY(midgard1
.flags
);
927 COPY(midgard1
.unknown2
);
931 /* Get blending setup */
932 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
934 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
936 for (unsigned c
= 0; c
< rt_count
; ++c
)
937 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
939 /* If there is a blend shader, work registers are shared. XXX: opt */
941 for (unsigned c
= 0; c
< rt_count
; ++c
) {
942 if (blend
[c
].is_shader
)
943 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
946 /* Depending on whether it's legal to in the given shader, we
947 * try to enable early-z testing (or forward-pixel kill?) */
949 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags
, MALI_EARLY_Z
, !variant
->can_discard
);
951 /* Any time texturing is used, derivatives are implicitly
952 * calculated, so we need to enable helper invocations */
954 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags
, MALI_HELPER_INVOCATIONS
, variant
->helper_invocations
);
956 /* Assign the stencil refs late */
958 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
959 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
960 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
962 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
963 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
965 /* CAN_DISCARD should be set if the fragment shader possibly
966 * contains a 'discard' instruction. It is likely this is
967 * related to optimizations related to forward-pixel kill, as
968 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
969 * thing?" by Peter Harris
972 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, variant
->can_discard
);
973 SET_BIT(ctx
->fragment_shader_core
.midgard1
.flags
, 0x400, variant
->can_discard
);
975 /* Even on MFBD, the shader descriptor gets blend shaders. It's
976 * *also* copied to the blend_meta appended (by convention),
977 * but this is the field actually read by the hardware. (Or
978 * maybe both are read...?) */
980 if (blend
[0].is_shader
) {
981 ctx
->fragment_shader_core
.blend
.shader
=
982 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
984 ctx
->fragment_shader_core
.blend
.shader
= 0;
987 if (screen
->quirks
& MIDGARD_SFBD
) {
988 /* When only a single render target platform is used, the blend
989 * information is inside the shader meta itself. We
990 * additionally need to signal CAN_DISCARD for nontrivial blend
991 * modes (so we're able to read back the destination buffer) */
993 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_BLEND_SHADER
, blend
[0].is_shader
);
995 if (!blend
[0].is_shader
) {
996 ctx
->fragment_shader_core
.blend
.equation
=
997 *blend
[0].equation
.equation
;
998 ctx
->fragment_shader_core
.blend
.constant
=
999 blend
[0].equation
.constant
;
1002 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_CAN_DISCARD
, !blend
[0].no_blending
);
1005 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1006 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1007 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1009 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.shader
= transfer
.gpu
;
1011 if (!(screen
->quirks
& MIDGARD_SFBD
)) {
1012 /* Additional blend descriptor tacked on for jobs using MFBD */
1014 struct midgard_blend_rt rts
[4];
1016 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1017 rts
[i
].flags
= 0x200;
1020 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1021 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1022 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1024 SET_BIT(rts
[i
].flags
, MALI_BLEND_MRT_SHADER
, blend
[i
].is_shader
);
1025 SET_BIT(rts
[i
].flags
, MALI_BLEND_LOAD_TIB
, !blend
[i
].no_blending
);
1026 SET_BIT(rts
[i
].flags
, MALI_BLEND_SRGB
, is_srgb
);
1027 SET_BIT(rts
[i
].flags
, MALI_BLEND_NO_DITHER
, !ctx
->blend
->base
.dither
);
1029 /* TODO: sRGB in blend shaders is currently
1030 * unimplemented. Contact me (Alyssa) if you're
1031 * interested in working on this. We have
1032 * native Midgard ops for helping here, but
1033 * they're not well-understood yet. */
1035 assert(!(is_srgb
&& blend
[i
].is_shader
));
1037 if (blend
[i
].is_shader
) {
1038 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1040 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1041 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1045 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1049 /* We stage to transient, so always dirty.. */
1051 panfrost_stage_attributes(ctx
);
1053 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1054 panfrost_upload_sampler_descriptors(ctx
);
1056 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1057 panfrost_upload_texture_descriptors(ctx
);
1059 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1061 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1062 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1067 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1069 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1071 /* Uniforms are implicitly UBO #0 */
1072 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1074 /* Allocate room for the sysval and the uniforms */
1075 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1076 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1077 size_t size
= sys_size
+ uniform_size
;
1078 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1080 /* Upload sysvals requested by the shader */
1081 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1083 /* Upload uniforms */
1085 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1086 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1090 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1092 struct mali_vertex_tiler_postfix
*postfix
=
1093 &ctx
->payloads
[i
].postfix
;
1095 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1098 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1099 assert(ubo_count
>= 1);
1101 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1102 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1104 /* Upload uniforms as a UBO */
1105 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1106 ubos
[0].ptr
= transfer
.gpu
>> 2;
1108 /* The rest are honest-to-goodness UBOs */
1110 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1111 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1113 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1114 bool empty
= usz
== 0;
1116 if (!enabled
|| empty
) {
1117 /* Stub out disabled UBOs to catch accesses */
1120 ubos
[ubo
].ptr
= 0xDEAD0000;
1124 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, i
, buf
, ubo
);
1126 unsigned bytes_per_field
= 16;
1127 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1128 unsigned fields
= aligned
/ bytes_per_field
;
1130 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1131 ubos
[ubo
].ptr
= gpu
>> 2;
1134 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1135 postfix
->uniforms
= transfer
.gpu
;
1136 postfix
->uniform_buffers
= ubufs
;
1138 buf
->dirty_mask
= 0;
1141 /* TODO: Upload the viewport somewhere more appropriate */
1143 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1144 * (somewhat) asymmetric ints. */
1145 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1147 struct mali_viewport view
= {
1148 /* By default, do no viewport clipping, i.e. clip to (-inf,
1149 * inf) in each direction. Clipping to the viewport in theory
1150 * should work, but in practice causes issues when we're not
1151 * explicitly trying to scissor */
1153 .clip_minx
= -INFINITY
,
1154 .clip_miny
= -INFINITY
,
1155 .clip_maxx
= INFINITY
,
1156 .clip_maxy
= INFINITY
,
1159 /* Always scissor to the viewport by default. */
1160 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1161 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1163 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1164 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1166 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1167 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1169 /* Apply the scissor test */
1171 unsigned minx
, miny
, maxx
, maxy
;
1173 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1174 minx
= MAX2(ss
->minx
, vp_minx
);
1175 miny
= MAX2(ss
->miny
, vp_miny
);
1176 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1177 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1185 /* Hardware needs the min/max to be strictly ordered, so flip if we
1186 * need to. The viewport transformation in the vertex shader will
1187 * handle the negatives if we don't */
1190 unsigned temp
= miny
;
1196 unsigned temp
= minx
;
1207 /* Clamp to the framebuffer size as a last check */
1209 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1210 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1212 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1213 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1215 /* Update the job, unless we're doing wallpapering (whose lack of
1216 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1217 * just... be faster :) */
1219 if (!ctx
->wallpaper_batch
)
1220 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1224 view
.viewport0
[0] = minx
;
1225 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1227 view
.viewport0
[1] = miny
;
1228 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1230 view
.clip_minz
= minz
;
1231 view
.clip_maxz
= maxz
;
1233 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1234 panfrost_upload_transient(batch
,
1236 sizeof(struct mali_viewport
));
1241 /* Corresponds to exactly one draw, but does not submit anything */
1244 panfrost_queue_draw(struct panfrost_context
*ctx
)
1246 /* Handle dirty flags now */
1247 panfrost_emit_for_draw(ctx
, true);
1249 /* If rasterizer discard is enable, only submit the vertex */
1251 bool rasterizer_discard
= ctx
->rasterizer
1252 && ctx
->rasterizer
->base
.rasterizer_discard
;
1254 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1255 struct panfrost_transfer tiler
;
1257 if (!rasterizer_discard
)
1258 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1260 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1262 if (rasterizer_discard
)
1263 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1264 else if (ctx
->wallpaper_batch
&& batch
->first_tiler
.gpu
)
1265 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1267 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1269 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1270 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1275 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1276 batch
->stack_size
= MAX2(batch
->stack_size
, ss
->stack_size
);
1280 /* The entire frame is in memory -- send it off to the kernel! */
1284 struct pipe_context
*pipe
,
1285 struct pipe_fence_handle
**fence
,
1288 struct panfrost_context
*ctx
= pan_context(pipe
);
1289 struct util_dynarray fences
;
1291 /* We must collect the fences before the flush is done, otherwise we'll
1292 * lose track of them.
1295 util_dynarray_init(&fences
, NULL
);
1296 hash_table_foreach(ctx
->batches
, hentry
) {
1297 struct panfrost_batch
*batch
= hentry
->data
;
1299 panfrost_batch_fence_reference(batch
->out_sync
);
1300 util_dynarray_append(&fences
,
1301 struct panfrost_batch_fence
*,
1306 /* Submit all pending jobs */
1307 panfrost_flush_all_batches(ctx
, false);
1310 struct panfrost_fence
*f
= panfrost_fence_create(ctx
, &fences
);
1311 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1312 *fence
= (struct pipe_fence_handle
*)f
;
1314 util_dynarray_foreach(&fences
, struct panfrost_batch_fence
*, fence
)
1315 panfrost_batch_fence_unreference(*fence
);
1317 util_dynarray_fini(&fences
);
1321 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1324 g2m_draw_mode(enum pipe_prim_type mode
)
1327 DEFINE_CASE(POINTS
);
1329 DEFINE_CASE(LINE_LOOP
);
1330 DEFINE_CASE(LINE_STRIP
);
1331 DEFINE_CASE(TRIANGLES
);
1332 DEFINE_CASE(TRIANGLE_STRIP
);
1333 DEFINE_CASE(TRIANGLE_FAN
);
1335 DEFINE_CASE(QUAD_STRIP
);
1336 DEFINE_CASE(POLYGON
);
1339 unreachable("Invalid draw mode");
1346 panfrost_translate_index_size(unsigned size
)
1350 return MALI_DRAW_INDEXED_UINT8
;
1353 return MALI_DRAW_INDEXED_UINT16
;
1356 return MALI_DRAW_INDEXED_UINT32
;
1359 unreachable("Invalid index size");
1363 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1364 * good for the duration of the draw (transient), could last longer */
1367 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1369 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1371 off_t offset
= info
->start
* info
->index_size
;
1372 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1374 if (!info
->has_user_indices
) {
1375 /* Only resources can be directly mapped */
1376 panfrost_batch_add_bo(batch
, rsrc
->bo
,
1377 PAN_BO_ACCESS_SHARED
|
1378 PAN_BO_ACCESS_READ
|
1379 PAN_BO_ACCESS_VERTEX_TILER
);
1380 return rsrc
->bo
->gpu
+ offset
;
1382 /* Otherwise, we need to upload to transient memory */
1383 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1384 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1389 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1391 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1393 /* Check if we're scissoring at all */
1395 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1398 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1401 /* Count generated primitives (when there is no geom/tess shaders) for
1402 * transform feedback */
1405 panfrost_statistics_record(
1406 struct panfrost_context
*ctx
,
1407 const struct pipe_draw_info
*info
)
1409 if (!ctx
->active_queries
)
1412 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1413 ctx
->prims_generated
+= prims
;
1415 if (!ctx
->streamout
.num_targets
)
1418 ctx
->tf_prims_generated
+= prims
;
1423 struct pipe_context
*pipe
,
1424 const struct pipe_draw_info
*info
)
1426 struct panfrost_context
*ctx
= pan_context(pipe
);
1428 /* First of all, check the scissor to see if anything is drawn at all.
1429 * If it's not, we drop the draw (mostly a conformance issue;
1430 * well-behaved apps shouldn't hit this) */
1432 if (panfrost_scissor_culls_everything(ctx
))
1435 int mode
= info
->mode
;
1437 /* Fallback unsupported restart index */
1438 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1440 if (info
->primitive_restart
&& info
->index_size
1441 && info
->restart_index
!= primitive_index
) {
1442 util_draw_vbo_without_prim_restart(pipe
, info
);
1446 /* Fallback for unsupported modes */
1448 assert(ctx
->rasterizer
!= NULL
);
1450 if (!(ctx
->draw_modes
& (1 << mode
))) {
1451 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1452 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1454 if (info
->count
< 4) {
1455 /* Degenerate case? */
1459 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1460 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1465 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1466 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1468 /* Now that we have a guaranteed terminating path, find the job.
1469 * Assignment commented out to prevent unused warning */
1471 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1473 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1475 /* Take into account a negative bias */
1476 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1477 ctx
->instance_count
= info
->instance_count
;
1478 ctx
->active_prim
= info
->mode
;
1480 /* For non-indexed draws, they're the same */
1481 unsigned vertex_count
= ctx
->vertex_count
;
1483 unsigned draw_flags
= 0;
1485 /* The draw flags interpret how primitive size is interpreted */
1487 if (panfrost_writes_point_size(ctx
))
1488 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1490 if (info
->primitive_restart
)
1491 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1493 /* These doesn't make much sense */
1495 draw_flags
|= 0x3000;
1497 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1498 draw_flags
|= 0x800;
1501 panfrost_statistics_record(ctx
, info
);
1503 if (info
->index_size
) {
1504 /* Calculate the min/max index used so we can figure out how
1505 * many times to invoke the vertex shader */
1507 /* Fetch / calculate index bounds */
1508 unsigned min_index
= 0, max_index
= 0;
1510 if (info
->max_index
== ~0u) {
1511 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1513 min_index
= info
->min_index
;
1514 max_index
= info
->max_index
;
1517 /* Use the corresponding values */
1518 vertex_count
= max_index
- min_index
+ 1;
1519 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1520 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1522 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1523 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1525 //assert(!info->restart_index); /* TODO: Research */
1527 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1528 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1530 /* Index count == vertex count, if no indexing is applied, as
1531 * if it is internally indexed in the expected order */
1533 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1534 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1536 /* Reverse index state */
1537 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1540 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1541 * vertex_count, 1) */
1543 panfrost_pack_work_groups_fused(
1544 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1545 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1546 1, vertex_count
, info
->instance_count
,
1549 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1551 /* Encode the padded vertex count */
1553 if (info
->instance_count
> 1) {
1554 ctx
->padded_count
= panfrost_padded_vertex_count(vertex_count
);
1556 unsigned shift
= __builtin_ctz(ctx
->padded_count
);
1557 unsigned k
= ctx
->padded_count
>> (shift
+ 1);
1559 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= shift
;
1560 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= shift
;
1562 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= k
;
1563 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= k
;
1565 ctx
->padded_count
= vertex_count
;
1567 /* Reset instancing state */
1568 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1569 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1570 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1571 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1574 /* Fire off the draw itself */
1575 panfrost_queue_draw(ctx
);
1577 /* Increment transform feedback offsets */
1579 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1580 unsigned output_count
= u_stream_outputs_for_vertices(
1581 ctx
->active_prim
, ctx
->vertex_count
);
1583 ctx
->streamout
.offsets
[i
] += output_count
;
1590 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1596 panfrost_create_rasterizer_state(
1597 struct pipe_context
*pctx
,
1598 const struct pipe_rasterizer_state
*cso
)
1600 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1604 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1605 so
->tiler_gl_enables
= 0x7;
1608 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1610 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1611 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1613 if (cso
->cull_face
& PIPE_FACE_BACK
)
1614 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1620 panfrost_bind_rasterizer_state(
1621 struct pipe_context
*pctx
,
1624 struct panfrost_context
*ctx
= pan_context(pctx
);
1626 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1630 ctx
->rasterizer
= hwcso
;
1631 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1633 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
* 2.0f
;
1634 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1636 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1637 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1639 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1641 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1642 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1644 /* Point sprites are emulated */
1646 struct panfrost_shader_state
*variant
=
1647 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1649 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1650 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1654 panfrost_create_vertex_elements_state(
1655 struct pipe_context
*pctx
,
1656 unsigned num_elements
,
1657 const struct pipe_vertex_element
*elements
)
1659 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1661 so
->num_elements
= num_elements
;
1662 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1664 for (int i
= 0; i
< num_elements
; ++i
) {
1665 so
->hw
[i
].index
= i
;
1667 enum pipe_format fmt
= elements
[i
].src_format
;
1668 const struct util_format_description
*desc
= util_format_description(fmt
);
1669 so
->hw
[i
].unknown1
= 0x2;
1670 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1672 so
->hw
[i
].format
= panfrost_find_format(desc
);
1674 /* The field itself should probably be shifted over */
1675 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1682 panfrost_bind_vertex_elements_state(
1683 struct pipe_context
*pctx
,
1686 struct panfrost_context
*ctx
= pan_context(pctx
);
1688 ctx
->vertex
= hwcso
;
1689 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1693 panfrost_create_shader_state(
1694 struct pipe_context
*pctx
,
1695 const struct pipe_shader_state
*cso
,
1696 enum pipe_shader_type stage
)
1698 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1701 /* Token deep copy to prevent memory corruption */
1703 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1704 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1706 /* Precompile for shader-db if we need to */
1707 if (unlikely((pan_debug
& PAN_DBG_PRECOMPILE
) && cso
->type
== PIPE_SHADER_IR_NIR
)) {
1708 struct panfrost_context
*ctx
= pan_context(pctx
);
1710 struct mali_shader_meta meta
;
1711 struct panfrost_shader_state state
;
1712 uint64_t outputs_written
;
1714 panfrost_shader_compile(ctx
, &meta
,
1717 tgsi_processor_to_shader_stage(stage
), &state
,
1725 panfrost_delete_shader_state(
1726 struct pipe_context
*pctx
,
1729 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1731 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1732 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1735 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1736 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1737 panfrost_bo_unreference(shader_state
->bo
);
1738 shader_state
->bo
= NULL
;
1745 panfrost_create_sampler_state(
1746 struct pipe_context
*pctx
,
1747 const struct pipe_sampler_state
*cso
)
1749 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1752 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1754 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1755 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1756 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1758 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1759 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1760 unsigned mip_filter
= mip_linear
?
1761 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1762 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1764 struct mali_sampler_descriptor sampler_descriptor
= {
1765 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1766 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1767 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1768 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1769 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1771 cso
->border_color
.f
[0],
1772 cso
->border_color
.f
[1],
1773 cso
->border_color
.f
[2],
1774 cso
->border_color
.f
[3]
1776 .min_lod
= FIXED_16(cso
->min_lod
),
1777 .max_lod
= FIXED_16(cso
->max_lod
),
1778 .lod_bias
= FIXED_16(cso
->lod_bias
),
1779 .seamless_cube_map
= cso
->seamless_cube_map
,
1782 /* If necessary, we disable mipmapping in the sampler descriptor by
1783 * clamping the LOD as tight as possible (from 0 to epsilon,
1784 * essentially -- remember these are fixed point numbers, so
1787 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1788 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1790 /* Enforce that there is something in the middle by adding epsilon*/
1792 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1793 sampler_descriptor
.max_lod
++;
1796 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1798 so
->hw
= sampler_descriptor
;
1804 panfrost_bind_sampler_states(
1805 struct pipe_context
*pctx
,
1806 enum pipe_shader_type shader
,
1807 unsigned start_slot
, unsigned num_sampler
,
1810 assert(start_slot
== 0);
1812 struct panfrost_context
*ctx
= pan_context(pctx
);
1814 /* XXX: Should upload, not just copy? */
1815 ctx
->sampler_count
[shader
] = num_sampler
;
1816 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1818 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1822 panfrost_variant_matches(
1823 struct panfrost_context
*ctx
,
1824 struct panfrost_shader_state
*variant
,
1825 enum pipe_shader_type type
)
1827 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1828 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1830 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1832 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1833 /* Make sure enable state is at least the same */
1834 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1838 /* Check that the contents of the test are the same */
1839 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1840 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1842 if (!(same_func
&& same_ref
)) {
1847 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1848 variant
->point_sprite_mask
)) {
1849 /* Ensure the same varyings are turned to point sprites */
1850 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1853 /* Ensure the orientation is correct */
1855 rasterizer
->sprite_coord_mode
==
1856 PIPE_SPRITE_COORD_UPPER_LEFT
;
1858 if (variant
->point_sprite_upper_left
!= upper_left
)
1862 /* Otherwise, we're good to go */
1867 * Fix an uncompiled shader's stream output info, and produce a bitmask
1868 * of which VARYING_SLOT_* are captured for stream output.
1870 * Core Gallium stores output->register_index as a "slot" number, where
1871 * slots are assigned consecutively to all outputs in info->outputs_written.
1872 * This naive packing of outputs doesn't work for us - we too have slots,
1873 * but the layout is defined by the VUE map, which we won't have until we
1874 * compile a specific shader variant. So, we remap these and simply store
1875 * VARYING_SLOT_* in our copy's output->register_index fields.
1877 * We then produce a bitmask of outputs which are used for SO.
1879 * Implementation from iris.
1883 update_so_info(struct pipe_stream_output_info
*so_info
,
1884 uint64_t outputs_written
)
1886 uint64_t so_outputs
= 0;
1887 uint8_t reverse_map
[64] = {0};
1890 while (outputs_written
)
1891 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1893 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1894 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1896 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1897 output
->register_index
= reverse_map
[output
->register_index
];
1899 so_outputs
|= 1ull << output
->register_index
;
1906 panfrost_bind_shader_state(
1907 struct pipe_context
*pctx
,
1909 enum pipe_shader_type type
)
1911 struct panfrost_context
*ctx
= pan_context(pctx
);
1913 ctx
->shader
[type
] = hwcso
;
1915 if (type
== PIPE_SHADER_FRAGMENT
)
1916 ctx
->dirty
|= PAN_DIRTY_FS
;
1918 ctx
->dirty
|= PAN_DIRTY_VS
;
1922 /* Match the appropriate variant */
1924 signed variant
= -1;
1925 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1927 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1928 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1934 if (variant
== -1) {
1935 /* No variant matched, so create a new one */
1936 variant
= variants
->variant_count
++;
1937 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1939 struct panfrost_shader_state
*v
=
1940 &variants
->variants
[variant
];
1942 if (type
== PIPE_SHADER_FRAGMENT
) {
1943 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1945 if (ctx
->rasterizer
) {
1946 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1947 v
->point_sprite_upper_left
=
1948 ctx
->rasterizer
->base
.sprite_coord_mode
==
1949 PIPE_SPRITE_COORD_UPPER_LEFT
;
1953 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1957 /* Select this variant */
1958 variants
->active_variant
= variant
;
1960 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1961 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1963 /* We finally have a variant, so compile it */
1965 if (!shader_state
->compiled
) {
1966 uint64_t outputs_written
= 0;
1968 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1969 variants
->base
.type
,
1970 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1971 variants
->base
.ir
.nir
:
1972 variants
->base
.tokens
,
1973 tgsi_processor_to_shader_stage(type
), shader_state
,
1976 shader_state
->compiled
= true;
1978 /* Fixup the stream out information, since what Gallium returns
1979 * normally is mildly insane */
1981 shader_state
->stream_output
= variants
->base
.stream_output
;
1982 shader_state
->so_mask
=
1983 update_so_info(&shader_state
->stream_output
, outputs_written
);
1988 panfrost_create_vs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1990 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1994 panfrost_create_fs_state(struct pipe_context
*pctx
, const struct pipe_shader_state
*hwcso
)
1996 return panfrost_create_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2000 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2002 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2006 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2008 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2012 panfrost_set_vertex_buffers(
2013 struct pipe_context
*pctx
,
2014 unsigned start_slot
,
2015 unsigned num_buffers
,
2016 const struct pipe_vertex_buffer
*buffers
)
2018 struct panfrost_context
*ctx
= pan_context(pctx
);
2020 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2024 panfrost_set_constant_buffer(
2025 struct pipe_context
*pctx
,
2026 enum pipe_shader_type shader
, uint index
,
2027 const struct pipe_constant_buffer
*buf
)
2029 struct panfrost_context
*ctx
= pan_context(pctx
);
2030 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2032 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2034 unsigned mask
= (1 << index
);
2036 if (unlikely(!buf
)) {
2037 pbuf
->enabled_mask
&= ~mask
;
2038 pbuf
->dirty_mask
&= ~mask
;
2042 pbuf
->enabled_mask
|= mask
;
2043 pbuf
->dirty_mask
|= mask
;
2047 panfrost_set_stencil_ref(
2048 struct pipe_context
*pctx
,
2049 const struct pipe_stencil_ref
*ref
)
2051 struct panfrost_context
*ctx
= pan_context(pctx
);
2052 ctx
->stencil_ref
= *ref
;
2054 /* Shader core dirty */
2055 ctx
->dirty
|= PAN_DIRTY_FS
;
2058 static enum mali_texture_type
2059 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2063 case PIPE_TEXTURE_1D
:
2064 case PIPE_TEXTURE_1D_ARRAY
:
2067 case PIPE_TEXTURE_2D
:
2068 case PIPE_TEXTURE_2D_ARRAY
:
2069 case PIPE_TEXTURE_RECT
:
2072 case PIPE_TEXTURE_3D
:
2075 case PIPE_TEXTURE_CUBE
:
2076 case PIPE_TEXTURE_CUBE_ARRAY
:
2077 return MALI_TEX_CUBE
;
2080 unreachable("Unknown target");
2084 static struct pipe_sampler_view
*
2085 panfrost_create_sampler_view(
2086 struct pipe_context
*pctx
,
2087 struct pipe_resource
*texture
,
2088 const struct pipe_sampler_view
*template)
2090 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2091 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2093 pipe_reference(NULL
, &texture
->reference
);
2095 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2098 so
->base
= *template;
2099 so
->base
.texture
= texture
;
2100 so
->base
.reference
.count
= 1;
2101 so
->base
.context
= pctx
;
2103 /* sampler_views correspond to texture descriptors, minus the texture
2104 * (data) itself. So, we serialise the descriptor here and cache it for
2107 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2109 unsigned char user_swizzle
[4] = {
2110 template->swizzle_r
,
2111 template->swizzle_g
,
2112 template->swizzle_b
,
2116 enum mali_format format
= panfrost_find_format(desc
);
2118 /* Check if we need to set a custom stride by computing the "expected"
2119 * stride and comparing it to what the BO actually wants. Only applies
2120 * to linear textures, since tiled/compressed textures have strict
2121 * alignment requirements for their strides as it is */
2123 unsigned first_level
= template->u
.tex
.first_level
;
2124 unsigned last_level
= template->u
.tex
.last_level
;
2126 if (prsrc
->layout
== PAN_LINEAR
) {
2127 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2128 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2129 unsigned width
= u_minify(texture
->width0
, l
);
2130 unsigned comp_stride
= width
* bytes_per_pixel
;
2132 if (comp_stride
!= actual_stride
) {
2133 so
->manual_stride
= true;
2139 /* In the hardware, array_size refers specifically to array textures,
2140 * whereas in Gallium, it also covers cubemaps */
2142 unsigned array_size
= texture
->array_size
;
2144 if (template->target
== PIPE_TEXTURE_CUBE
) {
2145 /* TODO: Cubemap arrays */
2146 assert(array_size
== 6);
2150 struct mali_texture_descriptor texture_descriptor
= {
2151 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2152 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2153 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2154 .array_size
= MALI_POSITIVE(array_size
),
2157 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2159 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2160 .type
= panfrost_translate_texture_type(template->target
),
2164 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2167 texture_descriptor
.levels
= last_level
- first_level
;
2169 so
->hw
= texture_descriptor
;
2171 return (struct pipe_sampler_view
*) so
;
2175 panfrost_set_sampler_views(
2176 struct pipe_context
*pctx
,
2177 enum pipe_shader_type shader
,
2178 unsigned start_slot
, unsigned num_views
,
2179 struct pipe_sampler_view
**views
)
2181 struct panfrost_context
*ctx
= pan_context(pctx
);
2182 unsigned new_nr
= 0;
2185 assert(start_slot
== 0);
2187 for (i
= 0; i
< num_views
; ++i
) {
2190 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2194 for (; i
< ctx
->sampler_view_count
[shader
]; i
++) {
2195 pipe_sampler_view_reference((struct pipe_sampler_view
**)&ctx
->sampler_views
[shader
][i
],
2198 ctx
->sampler_view_count
[shader
] = new_nr
;
2200 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2204 panfrost_sampler_view_destroy(
2205 struct pipe_context
*pctx
,
2206 struct pipe_sampler_view
*view
)
2208 pipe_resource_reference(&view
->texture
, NULL
);
2213 panfrost_set_shader_buffers(
2214 struct pipe_context
*pctx
,
2215 enum pipe_shader_type shader
,
2216 unsigned start
, unsigned count
,
2217 const struct pipe_shader_buffer
*buffers
,
2218 unsigned writable_bitmask
)
2220 struct panfrost_context
*ctx
= pan_context(pctx
);
2222 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2223 buffers
, start
, count
);
2226 /* Hints that a framebuffer should use AFBC where possible */
2230 struct panfrost_screen
*screen
,
2231 const struct pipe_framebuffer_state
*fb
)
2233 /* AFBC implemenation incomplete; hide it */
2234 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2236 /* Hint AFBC to the resources bound to each color buffer */
2238 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2239 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2240 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2241 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2244 /* Also hint it to the depth buffer */
2247 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2248 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2253 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2254 const struct pipe_framebuffer_state
*fb
)
2256 struct panfrost_context
*ctx
= pan_context(pctx
);
2258 panfrost_hint_afbc(pan_screen(pctx
->screen
), fb
);
2259 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2261 panfrost_invalidate_frame(ctx
);
2265 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2266 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2268 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2272 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2275 struct panfrost_context
*ctx
= pan_context(pipe
);
2276 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2277 ctx
->depth_stencil
= depth_stencil
;
2282 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2283 * emulated in the fragment shader */
2285 if (depth_stencil
->alpha
.enabled
) {
2286 /* We need to trigger a new shader (maybe) */
2287 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2291 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2293 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2294 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2296 /* If back-stencil is not enabled, use the front values */
2297 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2298 unsigned back_index
= back_enab
? 1 : 0;
2300 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2301 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2303 /* Depth state (TODO: Refactor) */
2304 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_WRITEMASK
,
2305 depth_stencil
->depth
.writemask
);
2307 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2309 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2310 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2312 /* Bounds test not implemented */
2313 assert(!depth_stencil
->depth
.bounds_test
);
2315 ctx
->dirty
|= PAN_DIRTY_FS
;
2319 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2325 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2326 unsigned sample_mask
)
2331 panfrost_set_clip_state(struct pipe_context
*pipe
,
2332 const struct pipe_clip_state
*clip
)
2334 //struct panfrost_context *panfrost = pan_context(pipe);
2338 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2339 unsigned start_slot
,
2340 unsigned num_viewports
,
2341 const struct pipe_viewport_state
*viewports
)
2343 struct panfrost_context
*ctx
= pan_context(pipe
);
2345 assert(start_slot
== 0);
2346 assert(num_viewports
== 1);
2348 ctx
->pipe_viewport
= *viewports
;
2352 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2353 unsigned start_slot
,
2354 unsigned num_scissors
,
2355 const struct pipe_scissor_state
*scissors
)
2357 struct panfrost_context
*ctx
= pan_context(pipe
);
2359 assert(start_slot
== 0);
2360 assert(num_scissors
== 1);
2362 ctx
->scissor
= *scissors
;
2366 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2367 const struct pipe_poly_stipple
*stipple
)
2369 //struct panfrost_context *panfrost = pan_context(pipe);
2373 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2376 struct panfrost_context
*ctx
= pan_context(pipe
);
2377 ctx
->active_queries
= enable
;
2381 panfrost_destroy(struct pipe_context
*pipe
)
2383 struct panfrost_context
*panfrost
= pan_context(pipe
);
2385 if (panfrost
->blitter
)
2386 util_blitter_destroy(panfrost
->blitter
);
2388 if (panfrost
->blitter_wallpaper
)
2389 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2391 util_unreference_framebuffer_state(&panfrost
->pipe_framebuffer
);
2392 u_upload_destroy(pipe
->stream_uploader
);
2397 static struct pipe_query
*
2398 panfrost_create_query(struct pipe_context
*pipe
,
2402 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2407 return (struct pipe_query
*) q
;
2411 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2413 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2416 panfrost_bo_unreference(query
->bo
);
2424 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2426 struct panfrost_context
*ctx
= pan_context(pipe
);
2427 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2429 switch (query
->type
) {
2430 case PIPE_QUERY_OCCLUSION_COUNTER
:
2431 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2432 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2433 /* Allocate a bo for the query results to be stored */
2435 query
->bo
= panfrost_bo_create(
2436 pan_screen(ctx
->base
.screen
),
2437 sizeof(unsigned), 0);
2440 unsigned *result
= (unsigned *)query
->bo
->cpu
;
2441 *result
= 0; /* Default to 0 if nothing at all drawn. */
2442 ctx
->occlusion_query
= query
;
2445 /* Geometry statistics are computed in the driver. XXX: geom/tess
2448 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2449 query
->start
= ctx
->prims_generated
;
2451 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2452 query
->start
= ctx
->tf_prims_generated
;
2456 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2464 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2466 struct panfrost_context
*ctx
= pan_context(pipe
);
2467 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2469 switch (query
->type
) {
2470 case PIPE_QUERY_OCCLUSION_COUNTER
:
2471 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2472 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2473 ctx
->occlusion_query
= NULL
;
2475 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2476 query
->end
= ctx
->prims_generated
;
2478 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2479 query
->end
= ctx
->tf_prims_generated
;
2487 panfrost_get_query_result(struct pipe_context
*pipe
,
2488 struct pipe_query
*q
,
2490 union pipe_query_result
*vresult
)
2492 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2493 struct panfrost_context
*ctx
= pan_context(pipe
);
2496 switch (query
->type
) {
2497 case PIPE_QUERY_OCCLUSION_COUNTER
:
2498 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2499 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2501 panfrost_flush_all_batches(ctx
, true);
2503 /* Read back the query results */
2504 unsigned *result
= (unsigned *) query
->bo
->cpu
;
2505 unsigned passed
= *result
;
2507 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2508 vresult
->u64
= passed
;
2510 vresult
->b
= !!passed
;
2515 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2516 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2517 panfrost_flush_all_batches(ctx
, true);
2518 vresult
->u64
= query
->end
- query
->start
;
2522 DBG("Skipped query get %u\n", query
->type
);
2529 static struct pipe_stream_output_target
*
2530 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2531 struct pipe_resource
*prsc
,
2532 unsigned buffer_offset
,
2533 unsigned buffer_size
)
2535 struct pipe_stream_output_target
*target
;
2537 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2542 pipe_reference_init(&target
->reference
, 1);
2543 pipe_resource_reference(&target
->buffer
, prsc
);
2545 target
->context
= pctx
;
2546 target
->buffer_offset
= buffer_offset
;
2547 target
->buffer_size
= buffer_size
;
2553 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2554 struct pipe_stream_output_target
*target
)
2556 pipe_resource_reference(&target
->buffer
, NULL
);
2557 ralloc_free(target
);
2561 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2562 unsigned num_targets
,
2563 struct pipe_stream_output_target
**targets
,
2564 const unsigned *offsets
)
2566 struct panfrost_context
*ctx
= pan_context(pctx
);
2567 struct panfrost_streamout
*so
= &ctx
->streamout
;
2569 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2571 for (unsigned i
= 0; i
< num_targets
; i
++) {
2572 if (offsets
[i
] != -1)
2573 so
->offsets
[i
] = offsets
[i
];
2575 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2578 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2579 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2581 so
->num_targets
= num_targets
;
2584 struct pipe_context
*
2585 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2587 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2588 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2590 gallium
->screen
= screen
;
2592 gallium
->destroy
= panfrost_destroy
;
2594 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2596 gallium
->flush
= panfrost_flush
;
2597 gallium
->clear
= panfrost_clear
;
2598 gallium
->draw_vbo
= panfrost_draw_vbo
;
2600 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2601 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2602 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2604 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2606 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2607 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2608 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2610 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2611 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2612 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2614 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2615 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2616 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2618 gallium
->create_fs_state
= panfrost_create_fs_state
;
2619 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2620 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2622 gallium
->create_vs_state
= panfrost_create_vs_state
;
2623 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2624 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2626 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2627 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2628 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2630 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2631 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2632 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2634 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2636 gallium
->set_clip_state
= panfrost_set_clip_state
;
2637 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2638 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2639 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2640 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2642 gallium
->create_query
= panfrost_create_query
;
2643 gallium
->destroy_query
= panfrost_destroy_query
;
2644 gallium
->begin_query
= panfrost_begin_query
;
2645 gallium
->end_query
= panfrost_end_query
;
2646 gallium
->get_query_result
= panfrost_get_query_result
;
2648 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2649 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2650 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2652 panfrost_resource_context_init(gallium
);
2653 panfrost_blend_context_init(gallium
);
2654 panfrost_compute_context_init(gallium
);
2657 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2658 gallium
->const_uploader
= gallium
->stream_uploader
;
2659 assert(gallium
->stream_uploader
);
2661 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2662 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2664 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2666 ctx
->blitter
= util_blitter_create(gallium
);
2667 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2669 assert(ctx
->blitter
);
2670 assert(ctx
->blitter_wallpaper
);
2672 /* Prepare for render! */
2674 panfrost_batch_init(ctx
);
2675 panfrost_emit_vertex_payload(ctx
);
2676 panfrost_emit_tiler_payload(ctx
);
2677 panfrost_invalidate_frame(ctx
);
2678 panfrost_default_shader_backend(ctx
);