2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
34 #include "util/macros.h"
35 #include "util/u_format.h"
36 #include "util/u_inlines.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_memory.h"
39 #include "util/u_vbuf.h"
40 #include "util/half_float.h"
41 #include "util/u_helpers.h"
42 #include "util/u_format.h"
43 #include "util/u_prim.h"
44 #include "util/u_prim_restart.h"
45 #include "indices/u_primconvert.h"
46 #include "tgsi/tgsi_parse.h"
47 #include "tgsi/tgsi_from_mesa.h"
48 #include "util/u_math.h"
50 #include "pan_screen.h"
51 #include "pan_blending.h"
52 #include "pan_blend_shaders.h"
55 /* Framebuffer descriptor */
57 static struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct panfrost_context
*ctx
= batch
->ctx
;
61 struct midgard_tiler_descriptor t
= {};
62 unsigned height
= batch
->key
.height
;
63 unsigned width
= batch
->key
.width
;
66 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
68 /* Compute the polygon header size and use that to offset the body */
70 unsigned header_size
= panfrost_tiler_header_size(
71 width
, height
, t
.hierarchy_mask
);
73 t
.polygon_list_size
= panfrost_tiler_full_size(
74 width
, height
, t
.hierarchy_mask
);
78 if (t
.hierarchy_mask
) {
79 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
84 /* Allow the entire tiler heap */
85 t
.heap_start
= ctx
->tiler_heap
->gpu
;
86 t
.heap_end
= ctx
->tiler_heap
->gpu
+ ctx
->tiler_heap
->size
;
88 /* The tiler is disabled, so don't allow the tiler heap */
89 t
.heap_start
= ctx
->tiler_heap
->gpu
;
90 t
.heap_end
= t
.heap_start
;
92 /* Use a dummy polygon list */
93 t
.polygon_list
= ctx
->tiler_dummy
->gpu
;
95 /* Disable the tiler */
96 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
100 t
.polygon_list
+ header_size
;
105 struct mali_single_framebuffer
106 panfrost_emit_sfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
108 struct panfrost_context
*ctx
= batch
->ctx
;
109 unsigned width
= batch
->key
.width
;
110 unsigned height
= batch
->key
.height
;
112 struct mali_single_framebuffer framebuffer
= {
113 .width
= MALI_POSITIVE(width
),
114 .height
= MALI_POSITIVE(height
),
116 .format
= 0x30000000,
117 .clear_flags
= 0x1000,
118 .unknown_address_0
= ctx
->scratchpad
->gpu
,
119 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
),
125 struct bifrost_framebuffer
126 panfrost_emit_mfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
128 struct panfrost_context
*ctx
= batch
->ctx
;
129 unsigned width
= batch
->key
.width
;
130 unsigned height
= batch
->key
.height
;
132 struct bifrost_framebuffer framebuffer
= {
133 .unk0
= 0x1e5, /* 1e4 if no spill */
134 .width1
= MALI_POSITIVE(width
),
135 .height1
= MALI_POSITIVE(height
),
136 .width2
= MALI_POSITIVE(width
),
137 .height2
= MALI_POSITIVE(height
),
141 .rt_count_1
= MALI_POSITIVE(batch
->key
.nr_cbufs
),
146 .scratchpad
= ctx
->scratchpad
->gpu
,
147 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
)
155 struct pipe_context
*pipe
,
157 const union pipe_color_union
*color
,
158 double depth
, unsigned stencil
)
160 struct panfrost_context
*ctx
= pan_context(pipe
);
161 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
163 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
167 panfrost_attach_vt_mfbd(struct panfrost_batch
*batch
)
169 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(batch
, ~0);
171 return panfrost_upload_transient(batch
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
175 panfrost_attach_vt_sfbd(struct panfrost_batch
*batch
)
177 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(batch
, ~0);
179 return panfrost_upload_transient(batch
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
183 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
185 /* Skip the attach if we can */
187 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
188 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
192 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
193 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
195 if (!batch
->framebuffer
)
196 batch
->framebuffer
= screen
->require_sfbd
?
197 panfrost_attach_vt_sfbd(batch
) :
198 panfrost_attach_vt_mfbd(batch
);
200 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
201 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
;
204 /* Reset per-frame context, called on context initialisation as well as after
205 * flushing a frame */
208 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
210 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
211 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
214 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
217 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
219 /* TODO: When does this need to be handled? */
220 ctx
->active_queries
= true;
223 /* In practice, every field of these payloads should be configurable
224 * arbitrarily, which means these functions are basically catch-all's for
225 * as-of-yet unwavering unknowns */
228 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
230 /* 0x2 bit clear on 32-bit T6XX */
232 struct midgard_payload_vertex_tiler payload
= {
233 .gl_enables
= 0x4 | 0x2,
236 /* Vertex and compute are closely coupled, so share a payload */
238 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
239 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
243 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
245 struct midgard_payload_vertex_tiler payload
= {
247 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
251 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
255 translate_tex_wrap(enum pipe_tex_wrap w
)
258 case PIPE_TEX_WRAP_REPEAT
:
259 return MALI_WRAP_REPEAT
;
261 /* TODO: lower GL_CLAMP? */
262 case PIPE_TEX_WRAP_CLAMP
:
263 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
264 return MALI_WRAP_CLAMP_TO_EDGE
;
266 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
267 return MALI_WRAP_CLAMP_TO_BORDER
;
269 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
270 return MALI_WRAP_MIRRORED_REPEAT
;
273 unreachable("Invalid wrap");
278 panfrost_translate_compare_func(enum pipe_compare_func in
)
281 case PIPE_FUNC_NEVER
:
282 return MALI_FUNC_NEVER
;
285 return MALI_FUNC_LESS
;
287 case PIPE_FUNC_EQUAL
:
288 return MALI_FUNC_EQUAL
;
290 case PIPE_FUNC_LEQUAL
:
291 return MALI_FUNC_LEQUAL
;
293 case PIPE_FUNC_GREATER
:
294 return MALI_FUNC_GREATER
;
296 case PIPE_FUNC_NOTEQUAL
:
297 return MALI_FUNC_NOTEQUAL
;
299 case PIPE_FUNC_GEQUAL
:
300 return MALI_FUNC_GEQUAL
;
302 case PIPE_FUNC_ALWAYS
:
303 return MALI_FUNC_ALWAYS
;
306 unreachable("Invalid func");
311 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
314 case PIPE_FUNC_NEVER
:
315 return MALI_ALT_FUNC_NEVER
;
318 return MALI_ALT_FUNC_LESS
;
320 case PIPE_FUNC_EQUAL
:
321 return MALI_ALT_FUNC_EQUAL
;
323 case PIPE_FUNC_LEQUAL
:
324 return MALI_ALT_FUNC_LEQUAL
;
326 case PIPE_FUNC_GREATER
:
327 return MALI_ALT_FUNC_GREATER
;
329 case PIPE_FUNC_NOTEQUAL
:
330 return MALI_ALT_FUNC_NOTEQUAL
;
332 case PIPE_FUNC_GEQUAL
:
333 return MALI_ALT_FUNC_GEQUAL
;
335 case PIPE_FUNC_ALWAYS
:
336 return MALI_ALT_FUNC_ALWAYS
;
339 unreachable("Invalid alt func");
344 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
347 case PIPE_STENCIL_OP_KEEP
:
348 return MALI_STENCIL_KEEP
;
350 case PIPE_STENCIL_OP_ZERO
:
351 return MALI_STENCIL_ZERO
;
353 case PIPE_STENCIL_OP_REPLACE
:
354 return MALI_STENCIL_REPLACE
;
356 case PIPE_STENCIL_OP_INCR
:
357 return MALI_STENCIL_INCR
;
359 case PIPE_STENCIL_OP_DECR
:
360 return MALI_STENCIL_DECR
;
362 case PIPE_STENCIL_OP_INCR_WRAP
:
363 return MALI_STENCIL_INCR_WRAP
;
365 case PIPE_STENCIL_OP_DECR_WRAP
:
366 return MALI_STENCIL_DECR_WRAP
;
368 case PIPE_STENCIL_OP_INVERT
:
369 return MALI_STENCIL_INVERT
;
372 unreachable("Invalid stencil op");
377 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
379 out
->ref
= 0; /* Gallium gets it from elsewhere */
381 out
->mask
= in
->valuemask
;
382 out
->func
= panfrost_translate_compare_func(in
->func
);
383 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
384 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
385 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
389 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
391 struct mali_shader_meta shader
= {
392 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
394 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
395 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
398 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
399 * required (independent of 32-bit/64-bit descriptors), or why it's not
400 * used on later GPU revisions. Otherwise, all shader jobs fault on
401 * these earlier chips (perhaps this is a chicken bit of some kind).
402 * More investigation is needed. */
405 shader
.unknown2_4
|= 0x10;
408 struct pipe_stencil_state default_stencil
= {
410 .func
= PIPE_FUNC_ALWAYS
,
411 .fail_op
= MALI_STENCIL_KEEP
,
412 .zfail_op
= MALI_STENCIL_KEEP
,
413 .zpass_op
= MALI_STENCIL_KEEP
,
418 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
419 shader
.stencil_mask_front
= default_stencil
.writemask
;
421 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
422 shader
.stencil_mask_back
= default_stencil
.writemask
;
424 if (default_stencil
.enabled
)
425 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
427 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
430 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
431 * graphics command stream. It should be called once per draw, accordding to
432 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
433 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
436 struct panfrost_transfer
437 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
439 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
440 struct mali_job_descriptor_header job
= {
441 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
442 .job_descriptor_size
= 1,
445 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
447 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
448 memcpy(transfer
.cpu
, &job
, sizeof(job
));
449 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
454 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
456 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
457 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
459 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
463 panfrost_writes_point_size(struct panfrost_context
*ctx
)
465 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
466 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
468 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
471 /* Stage the attribute descriptors so we can adjust src_offset
472 * to let BOs align nicely */
475 panfrost_stage_attributes(struct panfrost_context
*ctx
)
477 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
478 struct panfrost_vertex_state
*so
= ctx
->vertex
;
480 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
481 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
482 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
484 /* Copy as-is for the first pass */
485 memcpy(target
, so
->hw
, sz
);
487 /* Fixup offsets for the second pass. Recall that the hardware
488 * calculates attribute addresses as:
490 * addr = base + (stride * vtx) + src_offset;
492 * However, on Mali, base must be aligned to 64-bytes, so we
495 * base' = base & ~63 = base - (base & 63)
497 * To compensate when using base' (see emit_vertex_data), we have
498 * to adjust src_offset by the masked off piece:
500 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
501 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
502 * = base + (stride * vtx) + src_offset
508 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
510 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
511 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
512 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
513 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
515 /* Adjust by the masked off bits of the offset */
516 target
[i
].src_offset
+= (addr
& 63);
518 /* Also, somewhat obscurely per-instance data needs to be
519 * offset in response to a delayed start in an indexed draw */
521 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
522 target
[i
].src_offset
-= buf
->stride
* start
;
528 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
532 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
534 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
535 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
537 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
540 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
541 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
543 struct panfrost_transfer transfer
=
544 panfrost_allocate_transient(batch
, transfer_size
);
546 struct mali_sampler_descriptor
*desc
=
547 (struct mali_sampler_descriptor
*) transfer
.cpu
;
549 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
550 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
552 upload
= transfer
.gpu
;
555 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
559 static enum mali_texture_layout
560 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
562 /* TODO: other linear depth textures */
563 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
565 switch (rsrc
->layout
) {
567 return MALI_TEXTURE_AFBC
;
570 return MALI_TEXTURE_TILED
;
572 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
574 unreachable("Invalid texture layout");
580 struct panfrost_context
*ctx
,
581 struct panfrost_sampler_view
*view
)
586 struct pipe_sampler_view
*pview
= &view
->base
;
587 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
589 /* Do we interleave an explicit stride with every element? */
591 bool has_manual_stride
= view
->manual_stride
;
593 /* For easy access */
595 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
596 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
597 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
598 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
599 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
601 /* Lower-bit is set when sampling from colour AFBC */
602 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
603 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
604 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
606 /* Add the BO to the job so it's retained until the job is done. */
607 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
608 panfrost_batch_add_bo(batch
, rsrc
->bo
);
610 /* Add the usage flags in, since they can change across the CSO
611 * lifetime due to layout switches */
613 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
614 view
->hw
.format
.manual_stride
= has_manual_stride
;
616 /* Inject the addresses in, interleaving mip levels, cube faces, and
617 * strides in that order */
621 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
622 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
624 view
->hw
.payload
[idx
++] =
625 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
627 if (has_manual_stride
) {
628 view
->hw
.payload
[idx
++] =
629 rsrc
->slices
[l
].stride
;
634 return panfrost_upload_transient(batch
, &view
->hw
,
635 sizeof(struct mali_texture_descriptor
));
639 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
641 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
643 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
644 mali_ptr trampoline
= 0;
646 if (ctx
->sampler_view_count
[t
]) {
647 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
649 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
651 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
653 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
656 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
660 struct sysval_uniform
{
669 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
670 struct sysval_uniform
*uniform
)
672 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
674 uniform
->f
[0] = vp
->scale
[0];
675 uniform
->f
[1] = vp
->scale
[1];
676 uniform
->f
[2] = vp
->scale
[2];
679 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
680 struct sysval_uniform
*uniform
)
682 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
684 uniform
->f
[0] = vp
->translate
[0];
685 uniform
->f
[1] = vp
->translate
[1];
686 uniform
->f
[2] = vp
->translate
[2];
689 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
690 enum pipe_shader_type st
,
691 unsigned int sysvalid
,
692 struct sysval_uniform
*uniform
)
694 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
695 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
696 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
697 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
700 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
703 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
704 tex
->u
.tex
.first_level
);
707 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
708 tex
->u
.tex
.first_level
);
711 uniform
->i
[dim
] = tex
->texture
->array_size
;
714 static void panfrost_upload_ssbo_sysval(
715 struct panfrost_context
*ctx
,
716 enum pipe_shader_type st
,
718 struct sysval_uniform
*uniform
)
720 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
721 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
723 /* Compute address */
724 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
725 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
727 panfrost_batch_add_bo(batch
, bo
);
729 /* Upload address and size as sysval */
730 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
731 uniform
->u
[2] = sb
.buffer_size
;
734 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
735 struct sysval_uniform
*uniform
)
737 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
738 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
739 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
742 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
743 struct panfrost_shader_state
*ss
,
744 enum pipe_shader_type st
)
746 struct sysval_uniform
*uniforms
= (void *)buf
;
748 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
749 int sysval
= ss
->sysval
[i
];
751 switch (PAN_SYSVAL_TYPE(sysval
)) {
752 case PAN_SYSVAL_VIEWPORT_SCALE
:
753 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
755 case PAN_SYSVAL_VIEWPORT_OFFSET
:
756 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
758 case PAN_SYSVAL_TEXTURE_SIZE
:
759 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
762 case PAN_SYSVAL_SSBO
:
763 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
766 case PAN_SYSVAL_NUM_WORK_GROUPS
:
767 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
777 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
779 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
780 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
783 return rsrc
->bo
->cpu
;
784 else if (cb
->user_buffer
)
785 return cb
->user_buffer
;
787 unreachable("No constant buffer");
791 panfrost_map_constant_buffer_gpu(
792 struct panfrost_context
*ctx
,
793 struct panfrost_constant_buffer
*buf
,
796 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
797 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
798 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
801 panfrost_batch_add_bo(batch
, rsrc
->bo
);
802 return rsrc
->bo
->gpu
;
803 } else if (cb
->user_buffer
) {
804 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
806 unreachable("No constant buffer");
810 /* Compute number of UBOs active (more specifically, compute the highest UBO
811 * number addressable -- if there are gaps, include them in the count anyway).
812 * We always include UBO #0 in the count, since we *need* uniforms enabled for
816 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
818 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
819 return 32 - __builtin_clz(mask
);
822 /* Fixes up a shader state with current state, returning a GPU address to the
826 panfrost_patch_shader_state(
827 struct panfrost_context
*ctx
,
828 struct panfrost_shader_state
*ss
,
829 enum pipe_shader_type stage
,
832 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
833 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
835 ss
->tripipe
->midgard1
.flags
= 0x220;
837 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
838 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
840 /* We can't reuse over frames; that's not safe. The descriptor must be
841 * transient uploaded */
844 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
846 return panfrost_upload_transient(batch
, ss
->tripipe
,
847 sizeof(struct mali_shader_meta
));
850 /* If we don't need an upload, don't bother */
856 panfrost_patch_shader_state_compute(
857 struct panfrost_context
*ctx
,
858 enum pipe_shader_type stage
,
861 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
864 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
868 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
870 ctx
->payloads
[stage
].postfix
._shader_upper
=
871 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
874 /* Go through dirty flags and actualise them in the cmdstream. */
877 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
879 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
880 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
882 panfrost_attach_vt_framebuffer(ctx
);
884 if (with_vertex_data
) {
885 panfrost_emit_vertex_data(batch
);
887 /* Varyings emitted for -all- geometry */
888 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
889 panfrost_emit_varying_descriptor(ctx
, total_count
);
892 bool msaa
= ctx
->rasterizer
->base
.multisample
;
894 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
895 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
897 /* TODO: Sample size */
898 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
899 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
902 panfrost_batch_set_requirements(batch
);
904 if (ctx
->occlusion_query
) {
905 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
906 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
909 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
910 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
912 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
913 /* Check if we need to link the gl_PointSize varying */
914 if (!panfrost_writes_point_size(ctx
)) {
915 /* If the size is constant, write it out. Otherwise,
916 * don't touch primitive_size (since we would clobber
917 * the pointer there) */
919 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
923 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
924 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
925 ctx
->dirty
|= PAN_DIRTY_FS
;
927 if (ctx
->dirty
& PAN_DIRTY_FS
) {
928 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
929 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
931 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
933 panfrost_batch_add_bo(batch
, variant
->bo
);
935 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
938 COPY(attribute_count
);
942 COPY(midgard1
.uniform_count
);
943 COPY(midgard1
.uniform_buffer_count
);
944 COPY(midgard1
.work_count
);
945 COPY(midgard1
.flags
);
946 COPY(midgard1
.unknown2
);
950 /* Get blending setup */
951 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
953 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
955 for (unsigned c
= 0; c
< rt_count
; ++c
)
956 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
958 /* If there is a blend shader, work registers are shared. XXX: opt */
960 for (unsigned c
= 0; c
< rt_count
; ++c
) {
961 if (blend
[c
].is_shader
)
962 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
965 /* Set late due to depending on render state */
966 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
968 /* Depending on whether it's legal to in the given shader, we
969 * try to enable early-z testing (or forward-pixel kill?) */
971 if (!variant
->can_discard
)
972 flags
|= MALI_EARLY_Z
;
974 /* Any time texturing is used, derivatives are implicitly
975 * calculated, so we need to enable helper invocations */
977 if (variant
->helper_invocations
)
978 flags
|= MALI_HELPER_INVOCATIONS
;
980 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
982 /* Assign the stencil refs late */
984 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
985 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
986 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
988 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
989 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
991 /* CAN_DISCARD should be set if the fragment shader possibly
992 * contains a 'discard' instruction. It is likely this is
993 * related to optimizations related to forward-pixel kill, as
994 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
995 * thing?" by Peter Harris
998 if (variant
->can_discard
) {
999 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1000 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1003 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1004 * *also* copied to the blend_meta appended (by convention),
1005 * but this is the field actually read by the hardware. (Or
1006 * maybe both are read...?) */
1008 if (blend
[0].is_shader
) {
1009 ctx
->fragment_shader_core
.blend
.shader
=
1010 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1012 ctx
->fragment_shader_core
.blend
.shader
= 0;
1015 if (screen
->require_sfbd
) {
1016 /* When only a single render target platform is used, the blend
1017 * information is inside the shader meta itself. We
1018 * additionally need to signal CAN_DISCARD for nontrivial blend
1019 * modes (so we're able to read back the destination buffer) */
1021 if (!blend
[0].is_shader
) {
1022 ctx
->fragment_shader_core
.blend
.equation
=
1023 *blend
[0].equation
.equation
;
1024 ctx
->fragment_shader_core
.blend
.constant
=
1025 blend
[0].equation
.constant
;
1028 if (!blend
[0].no_blending
) {
1029 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1033 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1034 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1035 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1037 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1039 if (!screen
->require_sfbd
) {
1040 /* Additional blend descriptor tacked on for jobs using MFBD */
1042 struct midgard_blend_rt rts
[4];
1044 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1045 unsigned blend_count
= 0x200;
1047 if (blend
[i
].is_shader
) {
1048 /* For a blend shader, the bottom nibble corresponds to
1049 * the number of work registers used, which signals the
1050 * -existence- of a blend shader */
1052 assert(blend
[i
].shader
.work_count
>= 2);
1053 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1055 /* Otherwise, the bottom bit simply specifies if
1056 * blending (anything other than REPLACE) is enabled */
1058 if (!blend
[i
].no_blending
)
1064 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1065 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1066 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1068 rts
[i
].flags
= blend_count
;
1071 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1073 if (!ctx
->blend
->base
.dither
)
1074 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1076 /* TODO: sRGB in blend shaders is currently
1077 * unimplemented. Contact me (Alyssa) if you're
1078 * interested in working on this. We have
1079 * native Midgard ops for helping here, but
1080 * they're not well-understood yet. */
1082 assert(!(is_srgb
&& blend
[i
].is_shader
));
1084 if (blend
[i
].is_shader
) {
1085 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1087 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1088 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1092 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1096 /* We stage to transient, so always dirty.. */
1098 panfrost_stage_attributes(ctx
);
1100 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1101 panfrost_upload_sampler_descriptors(ctx
);
1103 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1104 panfrost_upload_texture_descriptors(ctx
);
1106 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1108 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1109 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1114 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1116 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1118 panfrost_batch_add_bo(batch
, ss
->bo
);
1120 /* Uniforms are implicitly UBO #0 */
1121 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1123 /* Allocate room for the sysval and the uniforms */
1124 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1125 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1126 size_t size
= sys_size
+ uniform_size
;
1127 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1129 /* Upload sysvals requested by the shader */
1130 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1132 /* Upload uniforms */
1134 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1135 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1139 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1141 struct mali_vertex_tiler_postfix
*postfix
=
1142 &ctx
->payloads
[i
].postfix
;
1144 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1147 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1148 assert(ubo_count
>= 1);
1150 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1151 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1153 /* Upload uniforms as a UBO */
1154 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1155 ubos
[0].ptr
= transfer
.gpu
>> 2;
1157 /* The rest are honest-to-goodness UBOs */
1159 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1160 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1162 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1163 bool empty
= usz
== 0;
1165 if (!enabled
|| empty
) {
1166 /* Stub out disabled UBOs to catch accesses */
1169 ubos
[ubo
].ptr
= 0xDEAD0000;
1173 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1175 unsigned bytes_per_field
= 16;
1176 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1177 unsigned fields
= aligned
/ bytes_per_field
;
1179 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1180 ubos
[ubo
].ptr
= gpu
>> 2;
1183 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1184 postfix
->uniforms
= transfer
.gpu
;
1185 postfix
->uniform_buffers
= ubufs
;
1187 buf
->dirty_mask
= 0;
1190 /* TODO: Upload the viewport somewhere more appropriate */
1192 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1193 * (somewhat) asymmetric ints. */
1194 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1196 struct mali_viewport view
= {
1197 /* By default, do no viewport clipping, i.e. clip to (-inf,
1198 * inf) in each direction. Clipping to the viewport in theory
1199 * should work, but in practice causes issues when we're not
1200 * explicitly trying to scissor */
1202 .clip_minx
= -INFINITY
,
1203 .clip_miny
= -INFINITY
,
1204 .clip_maxx
= INFINITY
,
1205 .clip_maxy
= INFINITY
,
1208 /* Always scissor to the viewport by default. */
1209 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1210 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1212 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1213 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1215 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1216 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1218 /* Apply the scissor test */
1220 unsigned minx
, miny
, maxx
, maxy
;
1222 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1223 minx
= MAX2(ss
->minx
, vp_minx
);
1224 miny
= MAX2(ss
->miny
, vp_miny
);
1225 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1226 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1234 /* Hardware needs the min/max to be strictly ordered, so flip if we
1235 * need to. The viewport transformation in the vertex shader will
1236 * handle the negatives if we don't */
1239 unsigned temp
= miny
;
1245 unsigned temp
= minx
;
1256 /* Clamp to the framebuffer size as a last check */
1258 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1259 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1261 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1262 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1264 /* Update the job, unless we're doing wallpapering (whose lack of
1265 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1266 * just... be faster :) */
1268 if (!ctx
->wallpaper_batch
)
1269 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1273 view
.viewport0
[0] = minx
;
1274 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1276 view
.viewport0
[1] = miny
;
1277 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1279 view
.clip_minz
= minz
;
1280 view
.clip_maxz
= maxz
;
1282 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1283 panfrost_upload_transient(batch
,
1285 sizeof(struct mali_viewport
));
1290 /* Corresponds to exactly one draw, but does not submit anything */
1293 panfrost_queue_draw(struct panfrost_context
*ctx
)
1295 /* Handle dirty flags now */
1296 panfrost_emit_for_draw(ctx
, true);
1298 /* If rasterizer discard is enable, only submit the vertex */
1300 bool rasterizer_discard
= ctx
->rasterizer
1301 && ctx
->rasterizer
->base
.rasterizer_discard
;
1303 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1304 struct panfrost_transfer tiler
;
1306 if (!rasterizer_discard
)
1307 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1309 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1311 if (rasterizer_discard
)
1312 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1313 else if (ctx
->wallpaper_batch
)
1314 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1316 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1319 /* The entire frame is in memory -- send it off to the kernel! */
1323 struct pipe_context
*pipe
,
1324 struct pipe_fence_handle
**fence
,
1327 struct panfrost_context
*ctx
= pan_context(pipe
);
1328 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1330 /* Submit the frame itself */
1331 panfrost_batch_submit(batch
);
1334 struct panfrost_fence
*f
= panfrost_fence_create(ctx
);
1335 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1336 *fence
= (struct pipe_fence_handle
*)f
;
1340 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1343 g2m_draw_mode(enum pipe_prim_type mode
)
1346 DEFINE_CASE(POINTS
);
1348 DEFINE_CASE(LINE_LOOP
);
1349 DEFINE_CASE(LINE_STRIP
);
1350 DEFINE_CASE(TRIANGLES
);
1351 DEFINE_CASE(TRIANGLE_STRIP
);
1352 DEFINE_CASE(TRIANGLE_FAN
);
1354 DEFINE_CASE(QUAD_STRIP
);
1355 DEFINE_CASE(POLYGON
);
1358 unreachable("Invalid draw mode");
1365 panfrost_translate_index_size(unsigned size
)
1369 return MALI_DRAW_INDEXED_UINT8
;
1372 return MALI_DRAW_INDEXED_UINT16
;
1375 return MALI_DRAW_INDEXED_UINT32
;
1378 unreachable("Invalid index size");
1382 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1383 * good for the duration of the draw (transient), could last longer */
1386 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1388 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1390 off_t offset
= info
->start
* info
->index_size
;
1391 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1393 if (!info
->has_user_indices
) {
1394 /* Only resources can be directly mapped */
1395 panfrost_batch_add_bo(batch
, rsrc
->bo
);
1396 return rsrc
->bo
->gpu
+ offset
;
1398 /* Otherwise, we need to upload to transient memory */
1399 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1400 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1405 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1407 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1409 /* Check if we're scissoring at all */
1411 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1414 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1417 /* Count generated primitives (when there is no geom/tess shaders) for
1418 * transform feedback */
1421 panfrost_statistics_record(
1422 struct panfrost_context
*ctx
,
1423 const struct pipe_draw_info
*info
)
1425 if (!ctx
->active_queries
)
1428 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1429 ctx
->prims_generated
+= prims
;
1431 if (!ctx
->streamout
.num_targets
)
1434 ctx
->tf_prims_generated
+= prims
;
1439 struct pipe_context
*pipe
,
1440 const struct pipe_draw_info
*info
)
1442 struct panfrost_context
*ctx
= pan_context(pipe
);
1444 /* First of all, check the scissor to see if anything is drawn at all.
1445 * If it's not, we drop the draw (mostly a conformance issue;
1446 * well-behaved apps shouldn't hit this) */
1448 if (panfrost_scissor_culls_everything(ctx
))
1451 int mode
= info
->mode
;
1453 /* Fallback unsupported restart index */
1454 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1456 if (info
->primitive_restart
&& info
->index_size
1457 && info
->restart_index
!= primitive_index
) {
1458 util_draw_vbo_without_prim_restart(pipe
, info
);
1462 /* Fallback for unsupported modes */
1464 assert(ctx
->rasterizer
!= NULL
);
1466 if (!(ctx
->draw_modes
& (1 << mode
))) {
1467 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1468 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1470 if (info
->count
< 4) {
1471 /* Degenerate case? */
1475 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1476 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1481 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1482 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1484 /* Now that we have a guaranteed terminating path, find the job.
1485 * Assignment commented out to prevent unused warning */
1487 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1489 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1491 /* Take into account a negative bias */
1492 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1493 ctx
->instance_count
= info
->instance_count
;
1494 ctx
->active_prim
= info
->mode
;
1496 /* For non-indexed draws, they're the same */
1497 unsigned vertex_count
= ctx
->vertex_count
;
1499 unsigned draw_flags
= 0;
1501 /* The draw flags interpret how primitive size is interpreted */
1503 if (panfrost_writes_point_size(ctx
))
1504 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1506 if (info
->primitive_restart
)
1507 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1509 /* For higher amounts of vertices (greater than what fits in a 16-bit
1510 * short), the other value is needed, otherwise there will be bizarre
1511 * rendering artefacts. It's not clear what these values mean yet. This
1512 * change is also needed for instancing and sometimes points (perhaps
1513 * related to dynamically setting gl_PointSize) */
1515 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1516 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1517 bool instanced
= ctx
->instance_count
> 1;
1519 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1521 /* This doesn't make much sense */
1522 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1523 draw_flags
|= 0x800;
1526 panfrost_statistics_record(ctx
, info
);
1528 if (info
->index_size
) {
1529 /* Calculate the min/max index used so we can figure out how
1530 * many times to invoke the vertex shader */
1532 /* Fetch / calculate index bounds */
1533 unsigned min_index
= 0, max_index
= 0;
1535 if (info
->max_index
== ~0u) {
1536 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1538 min_index
= info
->min_index
;
1539 max_index
= info
->max_index
;
1542 /* Use the corresponding values */
1543 vertex_count
= max_index
- min_index
+ 1;
1544 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1545 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1547 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1548 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1550 //assert(!info->restart_index); /* TODO: Research */
1552 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1553 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1555 /* Index count == vertex count, if no indexing is applied, as
1556 * if it is internally indexed in the expected order */
1558 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1559 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1561 /* Reverse index state */
1562 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1565 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1566 * vertex_count, 1) */
1568 panfrost_pack_work_groups_fused(
1569 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1570 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1571 1, vertex_count
, info
->instance_count
,
1574 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1576 /* Encode the padded vertex count */
1578 if (info
->instance_count
> 1) {
1579 /* Triangles have non-even vertex counts so they change how
1580 * padding works internally */
1583 mode
== PIPE_PRIM_TRIANGLES
||
1584 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1585 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1587 struct pan_shift_odd so
=
1588 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1590 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1591 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1593 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1594 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1596 ctx
->padded_count
= pan_expand_shift_odd(so
);
1598 ctx
->padded_count
= ctx
->vertex_count
;
1600 /* Reset instancing state */
1601 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1602 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1603 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1604 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1607 /* Fire off the draw itself */
1608 panfrost_queue_draw(ctx
);
1610 /* Increment transform feedback offsets */
1612 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1613 unsigned output_count
= u_stream_outputs_for_vertices(
1614 ctx
->active_prim
, ctx
->vertex_count
);
1616 ctx
->streamout
.offsets
[i
] += output_count
;
1623 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1629 panfrost_create_rasterizer_state(
1630 struct pipe_context
*pctx
,
1631 const struct pipe_rasterizer_state
*cso
)
1633 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1637 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1638 so
->tiler_gl_enables
= 0x7;
1641 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1643 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1644 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1646 if (cso
->cull_face
& PIPE_FACE_BACK
)
1647 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1653 panfrost_bind_rasterizer_state(
1654 struct pipe_context
*pctx
,
1657 struct panfrost_context
*ctx
= pan_context(pctx
);
1659 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1663 ctx
->rasterizer
= hwcso
;
1664 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1666 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1667 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1669 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1670 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1672 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1674 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1675 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1677 /* Point sprites are emulated */
1679 struct panfrost_shader_state
*variant
=
1680 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1682 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1683 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1687 panfrost_create_vertex_elements_state(
1688 struct pipe_context
*pctx
,
1689 unsigned num_elements
,
1690 const struct pipe_vertex_element
*elements
)
1692 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1694 so
->num_elements
= num_elements
;
1695 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1697 for (int i
= 0; i
< num_elements
; ++i
) {
1698 so
->hw
[i
].index
= i
;
1700 enum pipe_format fmt
= elements
[i
].src_format
;
1701 const struct util_format_description
*desc
= util_format_description(fmt
);
1702 so
->hw
[i
].unknown1
= 0x2;
1703 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1705 so
->hw
[i
].format
= panfrost_find_format(desc
);
1707 /* The field itself should probably be shifted over */
1708 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1715 panfrost_bind_vertex_elements_state(
1716 struct pipe_context
*pctx
,
1719 struct panfrost_context
*ctx
= pan_context(pctx
);
1721 ctx
->vertex
= hwcso
;
1722 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1726 panfrost_create_shader_state(
1727 struct pipe_context
*pctx
,
1728 const struct pipe_shader_state
*cso
)
1730 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1733 /* Token deep copy to prevent memory corruption */
1735 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1736 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1742 panfrost_delete_shader_state(
1743 struct pipe_context
*pctx
,
1746 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1748 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1749 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1752 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1753 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1754 panfrost_bo_unreference(shader_state
->bo
);
1755 shader_state
->bo
= NULL
;
1762 panfrost_create_sampler_state(
1763 struct pipe_context
*pctx
,
1764 const struct pipe_sampler_state
*cso
)
1766 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1769 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1771 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1772 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1773 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1775 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1776 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1777 unsigned mip_filter
= mip_linear
?
1778 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1779 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1781 struct mali_sampler_descriptor sampler_descriptor
= {
1782 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1783 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1784 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1785 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1786 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1788 cso
->border_color
.f
[0],
1789 cso
->border_color
.f
[1],
1790 cso
->border_color
.f
[2],
1791 cso
->border_color
.f
[3]
1793 .min_lod
= FIXED_16(cso
->min_lod
),
1794 .max_lod
= FIXED_16(cso
->max_lod
),
1795 .seamless_cube_map
= cso
->seamless_cube_map
,
1798 /* If necessary, we disable mipmapping in the sampler descriptor by
1799 * clamping the LOD as tight as possible (from 0 to epsilon,
1800 * essentially -- remember these are fixed point numbers, so
1803 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1804 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1806 /* Enforce that there is something in the middle by adding epsilon*/
1808 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1809 sampler_descriptor
.max_lod
++;
1812 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1814 so
->hw
= sampler_descriptor
;
1820 panfrost_bind_sampler_states(
1821 struct pipe_context
*pctx
,
1822 enum pipe_shader_type shader
,
1823 unsigned start_slot
, unsigned num_sampler
,
1826 assert(start_slot
== 0);
1828 struct panfrost_context
*ctx
= pan_context(pctx
);
1830 /* XXX: Should upload, not just copy? */
1831 ctx
->sampler_count
[shader
] = num_sampler
;
1832 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1834 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1838 panfrost_variant_matches(
1839 struct panfrost_context
*ctx
,
1840 struct panfrost_shader_state
*variant
,
1841 enum pipe_shader_type type
)
1843 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1844 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1846 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1848 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1849 /* Make sure enable state is at least the same */
1850 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1854 /* Check that the contents of the test are the same */
1855 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1856 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1858 if (!(same_func
&& same_ref
)) {
1863 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1864 variant
->point_sprite_mask
)) {
1865 /* Ensure the same varyings are turned to point sprites */
1866 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1869 /* Ensure the orientation is correct */
1871 rasterizer
->sprite_coord_mode
==
1872 PIPE_SPRITE_COORD_UPPER_LEFT
;
1874 if (variant
->point_sprite_upper_left
!= upper_left
)
1878 /* Otherwise, we're good to go */
1883 * Fix an uncompiled shader's stream output info, and produce a bitmask
1884 * of which VARYING_SLOT_* are captured for stream output.
1886 * Core Gallium stores output->register_index as a "slot" number, where
1887 * slots are assigned consecutively to all outputs in info->outputs_written.
1888 * This naive packing of outputs doesn't work for us - we too have slots,
1889 * but the layout is defined by the VUE map, which we won't have until we
1890 * compile a specific shader variant. So, we remap these and simply store
1891 * VARYING_SLOT_* in our copy's output->register_index fields.
1893 * We then produce a bitmask of outputs which are used for SO.
1895 * Implementation from iris.
1899 update_so_info(struct pipe_stream_output_info
*so_info
,
1900 uint64_t outputs_written
)
1902 uint64_t so_outputs
= 0;
1903 uint8_t reverse_map
[64] = {};
1906 while (outputs_written
)
1907 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1909 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1910 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1912 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1913 output
->register_index
= reverse_map
[output
->register_index
];
1915 so_outputs
|= 1ull << output
->register_index
;
1922 panfrost_bind_shader_state(
1923 struct pipe_context
*pctx
,
1925 enum pipe_shader_type type
)
1927 struct panfrost_context
*ctx
= pan_context(pctx
);
1929 ctx
->shader
[type
] = hwcso
;
1931 if (type
== PIPE_SHADER_FRAGMENT
)
1932 ctx
->dirty
|= PAN_DIRTY_FS
;
1934 ctx
->dirty
|= PAN_DIRTY_VS
;
1938 /* Match the appropriate variant */
1940 signed variant
= -1;
1941 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1943 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1944 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1950 if (variant
== -1) {
1951 /* No variant matched, so create a new one */
1952 variant
= variants
->variant_count
++;
1953 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1955 struct panfrost_shader_state
*v
=
1956 &variants
->variants
[variant
];
1958 if (type
== PIPE_SHADER_FRAGMENT
) {
1959 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1961 if (ctx
->rasterizer
) {
1962 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1963 v
->point_sprite_upper_left
=
1964 ctx
->rasterizer
->base
.sprite_coord_mode
==
1965 PIPE_SPRITE_COORD_UPPER_LEFT
;
1969 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1973 /* Select this variant */
1974 variants
->active_variant
= variant
;
1976 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1977 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1979 /* We finally have a variant, so compile it */
1981 if (!shader_state
->compiled
) {
1982 uint64_t outputs_written
= 0;
1984 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1985 variants
->base
.type
,
1986 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1987 variants
->base
.ir
.nir
:
1988 variants
->base
.tokens
,
1989 tgsi_processor_to_shader_stage(type
), shader_state
,
1992 shader_state
->compiled
= true;
1994 /* Fixup the stream out information, since what Gallium returns
1995 * normally is mildly insane */
1997 shader_state
->stream_output
= variants
->base
.stream_output
;
1998 shader_state
->so_mask
=
1999 update_so_info(&shader_state
->stream_output
, outputs_written
);
2004 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2006 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2010 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2012 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2016 panfrost_set_vertex_buffers(
2017 struct pipe_context
*pctx
,
2018 unsigned start_slot
,
2019 unsigned num_buffers
,
2020 const struct pipe_vertex_buffer
*buffers
)
2022 struct panfrost_context
*ctx
= pan_context(pctx
);
2024 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2028 panfrost_set_constant_buffer(
2029 struct pipe_context
*pctx
,
2030 enum pipe_shader_type shader
, uint index
,
2031 const struct pipe_constant_buffer
*buf
)
2033 struct panfrost_context
*ctx
= pan_context(pctx
);
2034 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2036 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2038 unsigned mask
= (1 << index
);
2040 if (unlikely(!buf
)) {
2041 pbuf
->enabled_mask
&= ~mask
;
2042 pbuf
->dirty_mask
&= ~mask
;
2046 pbuf
->enabled_mask
|= mask
;
2047 pbuf
->dirty_mask
|= mask
;
2051 panfrost_set_stencil_ref(
2052 struct pipe_context
*pctx
,
2053 const struct pipe_stencil_ref
*ref
)
2055 struct panfrost_context
*ctx
= pan_context(pctx
);
2056 ctx
->stencil_ref
= *ref
;
2058 /* Shader core dirty */
2059 ctx
->dirty
|= PAN_DIRTY_FS
;
2062 static enum mali_texture_type
2063 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2067 case PIPE_TEXTURE_1D
:
2068 case PIPE_TEXTURE_1D_ARRAY
:
2071 case PIPE_TEXTURE_2D
:
2072 case PIPE_TEXTURE_2D_ARRAY
:
2073 case PIPE_TEXTURE_RECT
:
2076 case PIPE_TEXTURE_3D
:
2079 case PIPE_TEXTURE_CUBE
:
2080 case PIPE_TEXTURE_CUBE_ARRAY
:
2081 return MALI_TEX_CUBE
;
2084 unreachable("Unknown target");
2088 static struct pipe_sampler_view
*
2089 panfrost_create_sampler_view(
2090 struct pipe_context
*pctx
,
2091 struct pipe_resource
*texture
,
2092 const struct pipe_sampler_view
*template)
2094 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2095 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2097 pipe_reference(NULL
, &texture
->reference
);
2099 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2102 so
->base
= *template;
2103 so
->base
.texture
= texture
;
2104 so
->base
.reference
.count
= 1;
2105 so
->base
.context
= pctx
;
2107 /* sampler_views correspond to texture descriptors, minus the texture
2108 * (data) itself. So, we serialise the descriptor here and cache it for
2111 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2113 unsigned char user_swizzle
[4] = {
2114 template->swizzle_r
,
2115 template->swizzle_g
,
2116 template->swizzle_b
,
2120 enum mali_format format
= panfrost_find_format(desc
);
2122 /* Check if we need to set a custom stride by computing the "expected"
2123 * stride and comparing it to what the BO actually wants. Only applies
2124 * to linear textures, since tiled/compressed textures have strict
2125 * alignment requirements for their strides as it is */
2127 unsigned first_level
= template->u
.tex
.first_level
;
2128 unsigned last_level
= template->u
.tex
.last_level
;
2130 if (prsrc
->layout
== PAN_LINEAR
) {
2131 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2132 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2133 unsigned width
= u_minify(texture
->width0
, l
);
2134 unsigned comp_stride
= width
* bytes_per_pixel
;
2136 if (comp_stride
!= actual_stride
) {
2137 so
->manual_stride
= true;
2143 /* In the hardware, array_size refers specifically to array textures,
2144 * whereas in Gallium, it also covers cubemaps */
2146 unsigned array_size
= texture
->array_size
;
2148 if (template->target
== PIPE_TEXTURE_CUBE
) {
2149 /* TODO: Cubemap arrays */
2150 assert(array_size
== 6);
2154 struct mali_texture_descriptor texture_descriptor
= {
2155 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2156 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2157 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2158 .array_size
= MALI_POSITIVE(array_size
),
2161 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2163 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2164 .type
= panfrost_translate_texture_type(template->target
),
2168 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2171 texture_descriptor
.levels
= last_level
- first_level
;
2173 so
->hw
= texture_descriptor
;
2175 return (struct pipe_sampler_view
*) so
;
2179 panfrost_set_sampler_views(
2180 struct pipe_context
*pctx
,
2181 enum pipe_shader_type shader
,
2182 unsigned start_slot
, unsigned num_views
,
2183 struct pipe_sampler_view
**views
)
2185 struct panfrost_context
*ctx
= pan_context(pctx
);
2187 assert(start_slot
== 0);
2189 unsigned new_nr
= 0;
2190 for (unsigned i
= 0; i
< num_views
; ++i
) {
2195 ctx
->sampler_view_count
[shader
] = new_nr
;
2196 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2198 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2202 panfrost_sampler_view_destroy(
2203 struct pipe_context
*pctx
,
2204 struct pipe_sampler_view
*view
)
2206 pipe_resource_reference(&view
->texture
, NULL
);
2211 panfrost_set_shader_buffers(
2212 struct pipe_context
*pctx
,
2213 enum pipe_shader_type shader
,
2214 unsigned start
, unsigned count
,
2215 const struct pipe_shader_buffer
*buffers
,
2216 unsigned writable_bitmask
)
2218 struct panfrost_context
*ctx
= pan_context(pctx
);
2220 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2221 buffers
, start
, count
);
2224 /* Hints that a framebuffer should use AFBC where possible */
2228 struct panfrost_screen
*screen
,
2229 const struct pipe_framebuffer_state
*fb
)
2231 /* AFBC implemenation incomplete; hide it */
2232 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2234 /* Hint AFBC to the resources bound to each color buffer */
2236 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2237 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2238 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2239 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2242 /* Also hint it to the depth buffer */
2245 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2246 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2251 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2252 const struct pipe_framebuffer_state
*fb
)
2254 struct panfrost_context
*ctx
= pan_context(pctx
);
2256 /* Flush when switching framebuffers, but not if the framebuffer
2257 * state is being restored by u_blitter
2260 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2261 bool is_scanout
= panfrost_batch_is_scanout(batch
);
2262 bool has_draws
= batch
->last_job
.gpu
;
2264 /* Bail out early when the current and new states are the same. */
2265 if (util_framebuffer_state_equal(&ctx
->pipe_framebuffer
, fb
))
2268 /* The wallpaper logic sets a new FB state before doing the blit and
2269 * restore the old one when it's done. Those FB states are reported to
2270 * be different because the surface they are pointing to are different,
2271 * but those surfaces actually point to the same cbufs/zbufs. In that
2272 * case we definitely don't want new FB descs to be emitted/attached
2273 * since the job is expected to be flushed just after the blit is done,
2274 * so let's just copy the new state and return here.
2276 if (ctx
->wallpaper_batch
) {
2277 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2281 if (!is_scanout
|| has_draws
)
2282 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2284 assert(!ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
&&
2285 !ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
2287 /* Invalidate the FBO job cache since we've just been assigned a new
2292 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2294 /* Given that we're rendering, we'd love to have compression */
2295 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2297 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2298 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
2299 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
2303 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2304 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2306 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2310 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2313 struct panfrost_context
*ctx
= pan_context(pipe
);
2314 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2315 ctx
->depth_stencil
= depth_stencil
;
2320 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2321 * emulated in the fragment shader */
2323 if (depth_stencil
->alpha
.enabled
) {
2324 /* We need to trigger a new shader (maybe) */
2325 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2329 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2331 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2332 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2334 /* If back-stencil is not enabled, use the front values */
2335 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2336 unsigned back_index
= back_enab
? 1 : 0;
2338 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2339 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2341 /* Depth state (TODO: Refactor) */
2342 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2344 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2346 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2347 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2349 /* Bounds test not implemented */
2350 assert(!depth_stencil
->depth
.bounds_test
);
2352 ctx
->dirty
|= PAN_DIRTY_FS
;
2356 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2362 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2363 unsigned sample_mask
)
2368 panfrost_set_clip_state(struct pipe_context
*pipe
,
2369 const struct pipe_clip_state
*clip
)
2371 //struct panfrost_context *panfrost = pan_context(pipe);
2375 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2376 unsigned start_slot
,
2377 unsigned num_viewports
,
2378 const struct pipe_viewport_state
*viewports
)
2380 struct panfrost_context
*ctx
= pan_context(pipe
);
2382 assert(start_slot
== 0);
2383 assert(num_viewports
== 1);
2385 ctx
->pipe_viewport
= *viewports
;
2389 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2390 unsigned start_slot
,
2391 unsigned num_scissors
,
2392 const struct pipe_scissor_state
*scissors
)
2394 struct panfrost_context
*ctx
= pan_context(pipe
);
2396 assert(start_slot
== 0);
2397 assert(num_scissors
== 1);
2399 ctx
->scissor
= *scissors
;
2403 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2404 const struct pipe_poly_stipple
*stipple
)
2406 //struct panfrost_context *panfrost = pan_context(pipe);
2410 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2413 struct panfrost_context
*ctx
= pan_context(pipe
);
2414 ctx
->active_queries
= enable
;
2418 panfrost_destroy(struct pipe_context
*pipe
)
2420 struct panfrost_context
*panfrost
= pan_context(pipe
);
2422 if (panfrost
->blitter
)
2423 util_blitter_destroy(panfrost
->blitter
);
2425 if (panfrost
->blitter_wallpaper
)
2426 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2428 panfrost_bo_release(panfrost
->scratchpad
, false);
2429 panfrost_bo_release(panfrost
->tiler_heap
, false);
2430 panfrost_bo_release(panfrost
->tiler_dummy
, false);
2435 static struct pipe_query
*
2436 panfrost_create_query(struct pipe_context
*pipe
,
2440 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2445 return (struct pipe_query
*) q
;
2449 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2455 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2457 struct panfrost_context
*ctx
= pan_context(pipe
);
2458 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2459 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2461 switch (query
->type
) {
2462 case PIPE_QUERY_OCCLUSION_COUNTER
:
2463 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2464 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2465 /* Allocate a word for the query results to be stored */
2466 query
->transfer
= panfrost_allocate_transient(batch
, sizeof(unsigned));
2467 ctx
->occlusion_query
= query
;
2470 /* Geometry statistics are computed in the driver. XXX: geom/tess
2473 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2474 query
->start
= ctx
->prims_generated
;
2476 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2477 query
->start
= ctx
->tf_prims_generated
;
2481 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2489 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2491 struct panfrost_context
*ctx
= pan_context(pipe
);
2492 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2494 switch (query
->type
) {
2495 case PIPE_QUERY_OCCLUSION_COUNTER
:
2496 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2497 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2498 ctx
->occlusion_query
= NULL
;
2500 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2501 query
->end
= ctx
->prims_generated
;
2503 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2504 query
->end
= ctx
->tf_prims_generated
;
2512 panfrost_get_query_result(struct pipe_context
*pipe
,
2513 struct pipe_query
*q
,
2515 union pipe_query_result
*vresult
)
2517 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2520 switch (query
->type
) {
2521 case PIPE_QUERY_OCCLUSION_COUNTER
:
2522 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2523 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2525 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2527 /* Read back the query results */
2528 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2529 unsigned passed
= *result
;
2531 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2532 vresult
->u64
= passed
;
2534 vresult
->b
= !!passed
;
2539 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2540 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2541 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2542 vresult
->u64
= query
->end
- query
->start
;
2546 DBG("Skipped query get %u\n", query
->type
);
2553 static struct pipe_stream_output_target
*
2554 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2555 struct pipe_resource
*prsc
,
2556 unsigned buffer_offset
,
2557 unsigned buffer_size
)
2559 struct pipe_stream_output_target
*target
;
2561 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2566 pipe_reference_init(&target
->reference
, 1);
2567 pipe_resource_reference(&target
->buffer
, prsc
);
2569 target
->context
= pctx
;
2570 target
->buffer_offset
= buffer_offset
;
2571 target
->buffer_size
= buffer_size
;
2577 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2578 struct pipe_stream_output_target
*target
)
2580 pipe_resource_reference(&target
->buffer
, NULL
);
2581 ralloc_free(target
);
2585 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2586 unsigned num_targets
,
2587 struct pipe_stream_output_target
**targets
,
2588 const unsigned *offsets
)
2590 struct panfrost_context
*ctx
= pan_context(pctx
);
2591 struct panfrost_streamout
*so
= &ctx
->streamout
;
2593 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2595 for (unsigned i
= 0; i
< num_targets
; i
++) {
2596 if (offsets
[i
] != -1)
2597 so
->offsets
[i
] = offsets
[i
];
2599 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2602 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2603 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2605 so
->num_targets
= num_targets
;
2609 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2611 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2612 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2614 ctx
->scratchpad
= panfrost_bo_create(screen
, 64 * 4 * 4096, 0);
2615 ctx
->tiler_heap
= panfrost_bo_create(screen
, 4096 * 4096,
2618 ctx
->tiler_dummy
= panfrost_bo_create(screen
, 4096,
2620 assert(ctx
->scratchpad
&& ctx
->tiler_heap
&& ctx
->tiler_dummy
);
2623 /* New context creation, which also does hardware initialisation since I don't
2624 * know the better way to structure this :smirk: */
2626 struct pipe_context
*
2627 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2629 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2630 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2631 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2633 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2635 gallium
->screen
= screen
;
2637 gallium
->destroy
= panfrost_destroy
;
2639 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2641 gallium
->flush
= panfrost_flush
;
2642 gallium
->clear
= panfrost_clear
;
2643 gallium
->draw_vbo
= panfrost_draw_vbo
;
2645 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2646 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2647 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2649 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2651 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2652 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2653 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2655 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2656 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2657 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2659 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2660 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2661 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2663 gallium
->create_fs_state
= panfrost_create_shader_state
;
2664 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2665 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2667 gallium
->create_vs_state
= panfrost_create_shader_state
;
2668 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2669 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2671 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2672 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2673 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2675 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2676 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2677 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2679 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2681 gallium
->set_clip_state
= panfrost_set_clip_state
;
2682 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2683 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2684 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2685 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2687 gallium
->create_query
= panfrost_create_query
;
2688 gallium
->destroy_query
= panfrost_destroy_query
;
2689 gallium
->begin_query
= panfrost_begin_query
;
2690 gallium
->end_query
= panfrost_end_query
;
2691 gallium
->get_query_result
= panfrost_get_query_result
;
2693 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2694 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2695 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2697 panfrost_resource_context_init(gallium
);
2698 panfrost_blend_context_init(gallium
);
2699 panfrost_compute_context_init(gallium
);
2703 ret
= drmSyncobjCreate(pscreen
->fd
, DRM_SYNCOBJ_CREATE_SIGNALED
,
2707 panfrost_setup_hardware(ctx
);
2710 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2711 gallium
->const_uploader
= gallium
->stream_uploader
;
2712 assert(gallium
->stream_uploader
);
2714 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2715 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2717 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2719 ctx
->blitter
= util_blitter_create(gallium
);
2720 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2722 assert(ctx
->blitter
);
2723 assert(ctx
->blitter_wallpaper
);
2725 /* Prepare for render! */
2727 panfrost_batch_init(ctx
);
2728 panfrost_emit_vertex_payload(ctx
);
2729 panfrost_emit_tiler_payload(ctx
);
2730 panfrost_invalidate_frame(ctx
);
2731 panfrost_default_shader_backend(ctx
);