2 * Copyright (C) 2008 VMware, Inc.
3 * Copyright (C) 2014 Broadcom
4 * Copyright (C) 2018 Alyssa Rosenzweig
5 * Copyright (C) 2019 Collabora, Ltd.
6 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 #include "util/u_debug.h"
30 #include "util/u_memory.h"
31 #include "util/format/u_format.h"
32 #include "util/format/u_format_s3tc.h"
33 #include "util/u_video.h"
34 #include "util/u_screen.h"
35 #include "util/os_time.h"
36 #include "util/u_process.h"
37 #include "pipe/p_defines.h"
38 #include "pipe/p_screen.h"
39 #include "draw/draw_context.h"
43 #include "drm-uapi/drm_fourcc.h"
44 #include "drm-uapi/panfrost_drm.h"
47 #include "pan_screen.h"
48 #include "pan_resource.h"
49 #include "pan_public.h"
51 #include "pandecode/decode.h"
53 #include "pan_context.h"
54 #include "midgard/midgard_compile.h"
55 #include "bifrost/bifrost_compile.h"
56 #include "panfrost-quirks.h"
58 static const struct debug_named_value debug_options
[] = {
59 {"msgs", PAN_DBG_MSGS
, "Print debug messages"},
60 {"trace", PAN_DBG_TRACE
, "Trace the command stream"},
61 {"deqp", PAN_DBG_DEQP
, "Hacks for dEQP"},
62 {"afbc", PAN_DBG_AFBC
, "Enable non-conformant AFBC impl"},
63 {"sync", PAN_DBG_SYNC
, "Wait for each job's completion and check for any GPU fault"},
64 {"precompile", PAN_DBG_PRECOMPILE
, "Precompile shaders for shader-db"},
65 {"gles3", PAN_DBG_GLES3
, "Enable experimental GLES3 implementation"},
66 {"fp16", PAN_DBG_FP16
, "Enable buggy experimental (don't use!) fp16"},
67 {"bifrost", PAN_DBG_BIFROST
, "Enable experimental Mali G31 and G52 support"},
71 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug
, "PAN_MESA_DEBUG", debug_options
, 0)
76 panfrost_get_name(struct pipe_screen
*screen
)
78 return panfrost_model_name(pan_device(screen
)->gpu_id
);
82 panfrost_get_vendor(struct pipe_screen
*screen
)
88 panfrost_get_device_vendor(struct pipe_screen
*screen
)
94 panfrost_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
96 /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
97 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
98 struct panfrost_device
*dev
= pan_device(screen
);
100 /* Our GLES3 implementation is WIP */
101 bool is_gles3
= pan_debug
& PAN_DBG_GLES3
;
105 case PIPE_CAP_NPOT_TEXTURES
:
106 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
107 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
108 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
109 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
110 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
111 case PIPE_CAP_POINT_SPRITE
:
114 case PIPE_CAP_MAX_RENDER_TARGETS
:
115 return is_gles3
? 4 : 1;
117 /* Throttling frames breaks pipelining */
118 case PIPE_CAP_THROTTLE
:
121 case PIPE_CAP_OCCLUSION_QUERY
:
123 case PIPE_CAP_QUERY_TIME_ELAPSED
:
124 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
125 case PIPE_CAP_QUERY_TIMESTAMP
:
126 case PIPE_CAP_QUERY_SO_OVERFLOW
:
129 case PIPE_CAP_TEXTURE_SWIZZLE
:
132 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
133 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
136 case PIPE_CAP_TGSI_INSTANCEID
:
137 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
138 case PIPE_CAP_PRIMITIVE_RESTART
:
141 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
142 return is_gles3
? 4 : 0;
143 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
144 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
145 return is_gles3
? 64 : 0;
146 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
149 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
152 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
153 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
154 return is_gles3
? 140 : 120;
155 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
156 return is_gles3
? 300 : 120;
158 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
161 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
164 /* For faking GLES 3.1 for dEQP-GLES31 */
165 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
:
166 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
:
167 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
168 case PIPE_CAP_CUBE_MAP_ARRAY
:
171 /* For faking compute shaders */
172 case PIPE_CAP_COMPUTE
:
175 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
177 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
178 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
181 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
182 case PIPE_CAP_INDEP_BLEND_ENABLE
:
183 case PIPE_CAP_INDEP_BLEND_FUNC
:
186 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
187 /* Hardware is natively upper left */
190 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
191 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
192 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
193 case PIPE_CAP_GENERATE_MIPMAP
:
196 /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
197 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
198 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
199 return dev
->quirks
& IS_BIFROST
;
201 /* I really don't want to set this CAP but let's not swim against the
203 case PIPE_CAP_TGSI_TEXCOORD
:
206 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
207 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
210 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
:
213 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
216 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
219 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
222 case PIPE_CAP_ENDIANNESS
:
223 return PIPE_ENDIAN_NATIVE
;
225 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
228 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
231 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
234 case PIPE_CAP_VENDOR_ID
:
235 case PIPE_CAP_DEVICE_ID
:
238 case PIPE_CAP_ACCELERATED
:
240 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
241 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
242 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
243 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
246 case PIPE_CAP_VIDEO_MEMORY
: {
247 uint64_t system_memory
;
249 if (!os_get_total_physical_memory(&system_memory
))
252 return (int)(system_memory
>> 20);
255 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
258 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
261 case PIPE_CAP_MAX_VARYINGS
:
264 case PIPE_CAP_ALPHA_TEST
:
265 case PIPE_CAP_FLATSHADE
:
266 case PIPE_CAP_TWO_SIDED_COLOR
:
267 case PIPE_CAP_CLIP_PLANES
:
270 case PIPE_CAP_PACKED_STREAM_OUTPUT
:
273 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED
:
274 case PIPE_CAP_PSIZ_CLAMPED
:
278 return u_pipe_screen_get_param_defaults(screen
, param
);
283 panfrost_get_shader_param(struct pipe_screen
*screen
,
284 enum pipe_shader_type shader
,
285 enum pipe_shader_cap param
)
287 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
288 bool is_fp16
= pan_debug
& PAN_DBG_FP16
;
289 struct panfrost_device
*dev
= pan_device(screen
);
291 if (shader
!= PIPE_SHADER_VERTEX
&&
292 shader
!= PIPE_SHADER_FRAGMENT
&&
293 !(shader
== PIPE_SHADER_COMPUTE
&& is_deqp
))
296 /* this is probably not totally correct.. but it's a start: */
298 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
299 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
300 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
301 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
304 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
307 case PIPE_SHADER_CAP_MAX_INPUTS
:
310 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
311 return shader
== PIPE_SHADER_FRAGMENT
? 4 : 16;
313 case PIPE_SHADER_CAP_MAX_TEMPS
:
314 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
316 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
317 return 16 * 1024 * sizeof(float);
319 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
320 return PAN_MAX_CONST_BUFFERS
;
322 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
325 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
327 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
330 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
333 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
336 case PIPE_SHADER_CAP_SUBROUTINES
:
339 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
342 case PIPE_SHADER_CAP_INTEGERS
:
345 case PIPE_SHADER_CAP_FP16
:
346 return !(dev
->quirks
& MIDGARD_BROKEN_FP16
) || is_fp16
;
348 case PIPE_SHADER_CAP_INT64_ATOMICS
:
349 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
350 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
351 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
352 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
353 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
356 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
357 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
358 return 16; /* XXX: How many? */
360 case PIPE_SHADER_CAP_PREFERRED_IR
:
361 return PIPE_SHADER_IR_NIR
;
363 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
364 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED
);
366 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
369 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
370 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
371 return is_deqp
? 8 : 0;
372 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
373 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
376 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
377 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
381 DBG("unknown shader param %d\n", param
);
389 panfrost_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
392 case PIPE_CAPF_MAX_LINE_WIDTH
:
395 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
396 return 255.0; /* arbitrary */
398 case PIPE_CAPF_MAX_POINT_WIDTH
:
401 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
404 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
407 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
408 return 16.0; /* arbitrary */
410 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
411 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
412 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
416 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
422 * Query format support for creating a texture, drawing surface, etc.
423 * \param format the format to test
424 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
427 panfrost_is_format_supported( struct pipe_screen
*screen
,
428 enum pipe_format format
,
429 enum pipe_texture_target target
,
430 unsigned sample_count
,
431 unsigned storage_sample_count
,
434 const struct util_format_description
*format_desc
;
436 assert(target
== PIPE_BUFFER
||
437 target
== PIPE_TEXTURE_1D
||
438 target
== PIPE_TEXTURE_1D_ARRAY
||
439 target
== PIPE_TEXTURE_2D
||
440 target
== PIPE_TEXTURE_2D_ARRAY
||
441 target
== PIPE_TEXTURE_RECT
||
442 target
== PIPE_TEXTURE_3D
||
443 target
== PIPE_TEXTURE_CUBE
||
444 target
== PIPE_TEXTURE_CUBE_ARRAY
);
446 format_desc
= util_format_description(format
);
451 /* MSAA 4x supported, but no more. Technically some revisions of the
452 * hardware can go up to 16x but we don't support higher modes yet. */
454 if (sample_count
> 1 && !(pan_debug
& PAN_DBG_DEQP
))
457 if (sample_count
> 4)
460 if (MAX2(sample_count
, 1) != MAX2(storage_sample_count
, 1))
463 /* Don't confuse poorly written apps (workaround dEQP bug) that expect
464 * more alpha than they ask for */
466 bool scanout
= bind
& (PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
| PIPE_BIND_DISPLAY_TARGET
);
467 bool renderable
= bind
& PIPE_BIND_RENDER_TARGET
;
469 if (scanout
&& renderable
&& !util_format_is_rgba8_variant(format_desc
))
472 /* Check we support the format with the given bind */
474 unsigned relevant_bind
= bind
&
475 ( PIPE_BIND_DEPTH_STENCIL
| PIPE_BIND_RENDER_TARGET
476 | PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_SAMPLER_VIEW
);
478 struct panfrost_format fmt
= panfrost_pipe_format_table
[format
];
479 return fmt
.hw
&& ((relevant_bind
& ~fmt
.bind
) == 0);
483 panfrost_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
484 enum pipe_compute_cap param
, void *ret
)
486 const char * const ir
= "panfrost";
488 if (!(pan_debug
& PAN_DBG_DEQP
))
491 #define RET(x) do { \
493 memcpy(ret, x, sizeof(x)); \
498 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
499 RET((uint32_t []){ 64 });
501 case PIPE_COMPUTE_CAP_IR_TARGET
:
503 sprintf(ret
, "%s", ir
);
504 return strlen(ir
) * sizeof(char);
506 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
507 RET((uint64_t []) { 3 });
509 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
510 RET(((uint64_t []) { 65535, 65535, 65535 }));
512 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
513 RET(((uint64_t []) { 1024, 1024, 64 }));
515 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
516 RET((uint64_t []) { 1024 });
518 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
519 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
521 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
522 RET((uint64_t []) { 32768 });
524 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
525 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
526 RET((uint64_t []) { 4096 });
528 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
529 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
531 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
532 RET((uint32_t []) { 800 /* MHz -- TODO */ });
534 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
535 RET((uint32_t []) { 9999 }); // TODO
537 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
538 RET((uint32_t []) { 1 }); // TODO
540 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
541 RET((uint32_t []) { 32 }); // TODO
543 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
544 RET((uint64_t []) { 1024 }); // TODO
551 panfrost_destroy_screen(struct pipe_screen
*pscreen
)
553 panfrost_close_device(pan_device(pscreen
));
554 ralloc_free(pscreen
);
558 panfrost_get_timestamp(struct pipe_screen
*_screen
)
560 return os_time_get_nano();
564 panfrost_fence_reference(struct pipe_screen
*pscreen
,
565 struct pipe_fence_handle
**ptr
,
566 struct pipe_fence_handle
*fence
)
568 struct panfrost_fence
**p
= (struct panfrost_fence
**)ptr
;
569 struct panfrost_fence
*f
= (struct panfrost_fence
*)fence
;
570 struct panfrost_fence
*old
= *p
;
572 if (pipe_reference(&(*p
)->reference
, &f
->reference
)) {
573 util_dynarray_foreach(&old
->syncfds
, int, fd
)
575 util_dynarray_fini(&old
->syncfds
);
582 panfrost_fence_finish(struct pipe_screen
*pscreen
,
583 struct pipe_context
*ctx
,
584 struct pipe_fence_handle
*fence
,
587 struct panfrost_device
*dev
= pan_device(pscreen
);
588 struct panfrost_fence
*f
= (struct panfrost_fence
*)fence
;
589 struct util_dynarray syncobjs
;
592 /* All fences were already signaled */
593 if (!util_dynarray_num_elements(&f
->syncfds
, int))
596 util_dynarray_init(&syncobjs
, NULL
);
597 util_dynarray_foreach(&f
->syncfds
, int, fd
) {
600 ret
= drmSyncobjCreate(dev
->fd
, 0, &syncobj
);
603 ret
= drmSyncobjImportSyncFile(dev
->fd
, syncobj
, *fd
);
605 util_dynarray_append(&syncobjs
, uint32_t, syncobj
);
608 uint64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
609 if (abs_timeout
== OS_TIMEOUT_INFINITE
)
610 abs_timeout
= INT64_MAX
;
612 ret
= drmSyncobjWait(dev
->fd
, util_dynarray_begin(&syncobjs
),
613 util_dynarray_num_elements(&syncobjs
, uint32_t),
614 abs_timeout
, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL
,
617 util_dynarray_foreach(&syncobjs
, uint32_t, syncobj
)
618 drmSyncobjDestroy(dev
->fd
, *syncobj
);
623 struct panfrost_fence
*
624 panfrost_fence_create(struct panfrost_context
*ctx
,
625 struct util_dynarray
*fences
)
627 struct panfrost_device
*device
= pan_device(ctx
->base
.screen
);
628 struct panfrost_fence
*f
= calloc(1, sizeof(*f
));
632 util_dynarray_init(&f
->syncfds
, NULL
);
634 /* Export fences from all pending batches. */
635 util_dynarray_foreach(fences
, struct panfrost_batch_fence
*, fence
) {
638 /* The fence is already signaled, no need to export it. */
639 if ((*fence
)->signaled
)
642 drmSyncobjExportSyncFile(device
->fd
, (*fence
)->syncobj
, &fd
);
644 fprintf(stderr
, "export failed: %m\n");
647 util_dynarray_append(&f
->syncfds
, int, fd
);
650 pipe_reference_init(&f
->reference
, 1);
656 panfrost_screen_get_compiler_options(struct pipe_screen
*pscreen
,
657 enum pipe_shader_ir ir
,
658 enum pipe_shader_type shader
)
660 if (pan_device(pscreen
)->quirks
& IS_BIFROST
)
661 return &bifrost_nir_options
;
663 return &midgard_nir_options
;
667 panfrost_create_screen(int fd
, struct renderonly
*ro
)
669 pan_debug
= debug_get_option_pan_debug();
671 /* Blacklist apps known to be buggy under Panfrost */
672 const char *proc
= util_get_process_name();
673 const char *blacklist
[] = {
678 for (unsigned i
= 0; i
< ARRAY_SIZE(blacklist
); ++i
) {
679 if ((strcmp(blacklist
[i
], proc
) == 0))
683 /* Create the screen */
684 struct panfrost_screen
*screen
= rzalloc(NULL
, struct panfrost_screen
);
689 struct panfrost_device
*dev
= pan_device(&screen
->base
);
690 panfrost_open_device(screen
, fd
, dev
);
693 dev
->ro
= renderonly_dup(ro
);
695 DBG("Failed to dup renderonly object\n");
701 /* Check if we're loading against a supported GPU model. */
703 switch (dev
->gpu_id
) {
704 case 0x720: /* T720 */
705 case 0x750: /* T760 */
706 case 0x820: /* T820 */
707 case 0x860: /* T860 */
709 case 0x7093: /* G31 */
710 case 0x7212: /* G52 */
711 if (pan_debug
& PAN_DBG_BIFROST
)
716 /* Fail to load against untested models */
717 debug_printf("panfrost: Unsupported model %X", dev
->gpu_id
);
718 panfrost_destroy_screen(&(screen
->base
));
722 if (pan_debug
& (PAN_DBG_TRACE
| PAN_DBG_SYNC
))
723 pandecode_initialize(!(pan_debug
& PAN_DBG_TRACE
));
725 screen
->base
.destroy
= panfrost_destroy_screen
;
727 screen
->base
.get_name
= panfrost_get_name
;
728 screen
->base
.get_vendor
= panfrost_get_vendor
;
729 screen
->base
.get_device_vendor
= panfrost_get_device_vendor
;
730 screen
->base
.get_param
= panfrost_get_param
;
731 screen
->base
.get_shader_param
= panfrost_get_shader_param
;
732 screen
->base
.get_compute_param
= panfrost_get_compute_param
;
733 screen
->base
.get_paramf
= panfrost_get_paramf
;
734 screen
->base
.get_timestamp
= panfrost_get_timestamp
;
735 screen
->base
.is_format_supported
= panfrost_is_format_supported
;
736 screen
->base
.context_create
= panfrost_create_context
;
737 screen
->base
.get_compiler_options
= panfrost_screen_get_compiler_options
;
738 screen
->base
.fence_reference
= panfrost_fence_reference
;
739 screen
->base
.fence_finish
= panfrost_fence_finish
;
740 screen
->base
.set_damage_region
= panfrost_resource_set_damage_region
;
742 panfrost_resource_screen_init(&screen
->base
);
744 return &screen
->base
;