src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "bifrost/bifrost_compile.h"
  56 #include "panfrost-quirks.h"
  57
  58 static const struct debug_named_value debug_options[] = {
  59         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  60         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  61         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  62         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  63         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  64         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  65         {"gles3",     PAN_DBG_GLES3,    "Enable experimental GLES3 implementation"},
  66         DEBUG_NAMED_VALUE_END
  67 };
  68
  69 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  70
  71 int pan_debug = 0;
  72
  73 static const char *
  74 panfrost_get_name(struct pipe_screen *screen)
  75 {
  76         return panfrost_model_name(pan_device(screen)->gpu_id);
  77 }
  78
  79 static const char *
  80 panfrost_get_vendor(struct pipe_screen *screen)
  81 {
  82         return "Panfrost";
  83 }
  84
  85 static const char *
  86 panfrost_get_device_vendor(struct pipe_screen *screen)
  87 {
  88         return "Arm";
  89 }
  90
  91 static int
  92 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  93 {
  94         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  95         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  96         struct panfrost_device *dev = pan_device(screen);
  97
  98         /* Our GLES3 implementation is WIP */
  99         bool is_gles3 = pan_debug & PAN_DBG_GLES3;
 100         is_gles3 |= is_deqp;
 101
 102         switch (param) {
 103         case PIPE_CAP_NPOT_TEXTURES:
 104         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 105         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 106         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 107         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 108         case PIPE_CAP_POINT_SPRITE:
 109                 return 1;
 110
 111         case PIPE_CAP_MAX_RENDER_TARGETS:
 112                 return is_gles3 ? 4 : 1;
 113
 114         /* Throttling frames breaks pipelining */
 115         case PIPE_CAP_THROTTLE:
 116                 return 0;
 117
 118         case PIPE_CAP_OCCLUSION_QUERY:
 119                 return 1;
 120         case PIPE_CAP_QUERY_TIME_ELAPSED:
 121         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 122         case PIPE_CAP_QUERY_TIMESTAMP:
 123         case PIPE_CAP_QUERY_SO_OVERFLOW:
 124                 return 0;
 125
 126         case PIPE_CAP_TEXTURE_SWIZZLE:
 127                 return 1;
 128
 129         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 130         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 131                 return 1;
 132
 133         case PIPE_CAP_TGSI_INSTANCEID:
 134         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 135         case PIPE_CAP_PRIMITIVE_RESTART:
 136                 return 1;
 137
 138         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 139                 return is_gles3 ? 4 : 0;
 140         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 141         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 142                 return is_gles3 ? 64 : 0;
 143         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 144                 return 1;
 145
 146         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 147                 return 256;
 148
 149         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 150         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 151                 return is_gles3 ? 140 : 120;
 152         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 153                 return is_gles3 ? 300 : 120;
 154
 155         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 156                 return 16;
 157
 158                 return is_deqp;
 159
 160         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 161                 return is_gles3;
 162
 163         /* For faking GLES 3.1 for dEQP-GLES31 */
 164         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 165         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 166         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 167         case PIPE_CAP_CUBE_MAP_ARRAY:
 168                 return is_deqp;
 169
 170         /* For faking compute shaders */
 171         case PIPE_CAP_COMPUTE:
 172                 return is_deqp;
 173
 174         /* TODO: Where does this req come from in practice? */
 175         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 176                 return 1;
 177
 178         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 179                 return 4096;
 180         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 181         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 182                 return 13;
 183
 184         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 185         case PIPE_CAP_INDEP_BLEND_ENABLE:
 186         case PIPE_CAP_INDEP_BLEND_FUNC:
 187                 return 1;
 188
 189         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 190                 /* Hardware is natively upper left */
 191                 return 0;
 192
 193         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 194         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 195         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 196         case PIPE_CAP_GENERATE_MIPMAP:
 197                 return 1;
 198
 199         /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
 200         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 201         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 202                 return dev->quirks & IS_BIFROST;
 203
 204         /* I really don't want to set this CAP but let's not swim against the
 205          * tide.. */
 206         case PIPE_CAP_TGSI_TEXCOORD:
 207                 return 1;
 208
 209         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 210         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 211                 return 1;
 212
 213         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 214                 return 0xffff;
 215
 216         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 217                 return 1;
 218
 219         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 220                 return 65536;
 221
 222         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 223                 return 0;
 224
 225         case PIPE_CAP_ENDIANNESS:
 226                 return PIPE_ENDIAN_NATIVE;
 227
 228         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 229                 return 1;
 230
 231         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 232                 return -8;
 233
 234         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 235                 return 7;
 236
 237         case PIPE_CAP_VENDOR_ID:
 238         case PIPE_CAP_DEVICE_ID:
 239                 return 0xFFFFFFFF;
 240
 241         case PIPE_CAP_ACCELERATED:
 242         case PIPE_CAP_UMA:
 243         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 244         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 245         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 246         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 247                 return 1;
 248
 249         case PIPE_CAP_VIDEO_MEMORY: {
 250                 uint64_t system_memory;
 251
 252                 if (!os_get_total_physical_memory(&system_memory))
 253                         return 0;
 254
 255                 return (int)(system_memory >> 20);
 256         }
 257
 258         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 259                 return 1;
 260
 261         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 262                 return 4;
 263
 264         case PIPE_CAP_MAX_VARYINGS:
 265                 return 16;
 266
 267         case PIPE_CAP_ALPHA_TEST:
 268         case PIPE_CAP_FLATSHADE:
 269         case PIPE_CAP_TWO_SIDED_COLOR:
 270         case PIPE_CAP_CLIP_PLANES:
 271                 return 0;
 272
 273         case PIPE_CAP_PACKED_STREAM_OUTPUT:
 274                 return 0;
 275
 276         case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
 277         case PIPE_CAP_PSIZ_CLAMPED:
 278                 return 1;
 279
 280         default:
 281                 return u_pipe_screen_get_param_defaults(screen, param);
 282         }
 283 }
 284
 285 static int
 286 panfrost_get_shader_param(struct pipe_screen *screen,
 287                           enum pipe_shader_type shader,
 288                           enum pipe_shader_cap param)
 289 {
 290         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 291         struct panfrost_device *dev = pan_device(screen);
 292
 293         if (shader != PIPE_SHADER_VERTEX &&
 294             shader != PIPE_SHADER_FRAGMENT &&
 295             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 296                 return 0;
 297
 298         /* this is probably not totally correct.. but it's a start: */
 299         switch (param) {
 300         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 301         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 302         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 303         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 304                 return 16384;
 305
 306         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 307                 return 1024;
 308
 309         case PIPE_SHADER_CAP_MAX_INPUTS:
 310                 return 16;
 311
 312         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 313                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
 314
 315         case PIPE_SHADER_CAP_MAX_TEMPS:
 316                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 317
 318         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 319                 return 16 * 1024 * sizeof(float);
 320
 321         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 322                 return PAN_MAX_CONST_BUFFERS;
 323
 324         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 325                 return 0;
 326
 327         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 328                 return 1;
 329         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 330                 return 0;
 331
 332         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 333                 return 0;
 334
 335         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 336                 return 1;
 337
 338         case PIPE_SHADER_CAP_SUBROUTINES:
 339                 return 0;
 340
 341         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 342                 return 0;
 343
 344         case PIPE_SHADER_CAP_INTEGERS:
 345                 return 1;
 346
 347         case PIPE_SHADER_CAP_FP16:
 348                 return !(dev->quirks & MIDGARD_BROKEN_FP16);
 349
 350         case PIPE_SHADER_CAP_INT64_ATOMICS:
 351         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 352         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 353         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 354         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 355         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 356                 return 0;
 357
 358         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 359         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 360                 return 16; /* XXX: How many? */
 361
 362         case PIPE_SHADER_CAP_PREFERRED_IR:
 363                 return PIPE_SHADER_IR_NIR;
 364
 365         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 366                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 367
 368         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 369                 return 32;
 370
 371         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 372         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 373                 return is_deqp ? 8 : 0;
 374         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 375         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 376                 return 0;
 377
 378         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 379         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 380                 return 0;
 381
 382         default:
 383                 DBG("unknown shader param %d\n", param);
 384                 return 0;
 385         }
 386
 387         return 0;
 388 }
 389
 390 static float
 391 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 392 {
 393         switch (param) {
 394         case PIPE_CAPF_MAX_LINE_WIDTH:
 395
 396         /* fall-through */
 397         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 398                 return 255.0; /* arbitrary */
 399
 400         case PIPE_CAPF_MAX_POINT_WIDTH:
 401
 402         /* fall-through */
 403         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 404                 return 1024.0;
 405
 406         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 407                 return 16.0;
 408
 409         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 410                 return 16.0; /* arbitrary */
 411
 412         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 413         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 414         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 415                 return 0.0f;
 416
 417         default:
 418                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 419                 return 0.0;
 420         }
 421 }
 422
 423 /**
 424  * Query format support for creating a texture, drawing surface, etc.
 425  * \param format  the format to test
 426  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 427  */
 428 static bool
 429 panfrost_is_format_supported( struct pipe_screen *screen,
 430                               enum pipe_format format,
 431                               enum pipe_texture_target target,
 432                               unsigned sample_count,
 433                               unsigned storage_sample_count,
 434                               unsigned bind)
 435 {
 436         const struct util_format_description *format_desc;
 437
 438         assert(target == PIPE_BUFFER ||
 439                target == PIPE_TEXTURE_1D ||
 440                target == PIPE_TEXTURE_1D_ARRAY ||
 441                target == PIPE_TEXTURE_2D ||
 442                target == PIPE_TEXTURE_2D_ARRAY ||
 443                target == PIPE_TEXTURE_RECT ||
 444                target == PIPE_TEXTURE_3D ||
 445                target == PIPE_TEXTURE_CUBE ||
 446                target == PIPE_TEXTURE_CUBE_ARRAY);
 447
 448         format_desc = util_format_description(format);
 449
 450         if (!format_desc)
 451                 return false;
 452
 453         /* MSAA 4x supported, but no more. Technically some revisions of the
 454          * hardware can go up to 16x but we don't support higher modes yet. */
 455
 456         if (sample_count > 1 && !(pan_debug & PAN_DBG_DEQP))
 457                 return false;
 458
 459         if (sample_count > 4)
 460                 return false;
 461
 462         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 463                 return false;
 464
 465         /* Format wishlist */
 466         if (format == PIPE_FORMAT_X8Z24_UNORM)
 467                 return false;
 468
 469         if (format == PIPE_FORMAT_A1B5G5R5_UNORM ||
 470             format == PIPE_FORMAT_X1B5G5R5_UNORM ||
 471             format == PIPE_FORMAT_B2G3R3_UNORM)
 472                 return false;
 473
 474         /* TODO */
 475         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 476                 return FALSE;
 477
 478         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 479          * more alpha than they ask for */
 480
 481         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 482         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 483
 484         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 485                 return false;
 486
 487         switch (format_desc->layout) {
 488                 case UTIL_FORMAT_LAYOUT_PLAIN:
 489                 case UTIL_FORMAT_LAYOUT_OTHER:
 490                         break;
 491                 case UTIL_FORMAT_LAYOUT_ETC:
 492                 case UTIL_FORMAT_LAYOUT_ASTC:
 493                         return true;
 494                 default:
 495                         return false;
 496         }
 497
 498         if (format_desc->channel[0].size > 32)
 499             return false;
 500
 501         /* Internally, formats that are depth/stencil renderable are limited.
 502          *
 503          * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
 504          * rendering perspective. That is, we render to Z24S8 (which we can
 505          * AFBC compress), ignore the different when texturing (who cares?),
 506          * and then in the off-chance there's a CPU read we blit back to
 507          * staging.
 508          *
 509          * ...alternatively, we can make the gallium frontend deal with that. */
 510
 511         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 512                 switch (format) {
 513                         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 514                         case PIPE_FORMAT_Z24X8_UNORM:
 515                         case PIPE_FORMAT_Z32_UNORM:
 516                         case PIPE_FORMAT_Z32_FLOAT:
 517                         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 518                                 return true;
 519
 520                         default:
 521                                 return false;
 522                 }
 523         }
 524
 525         return true;
 526 }
 527
 528 static int
 529 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 530                 enum pipe_compute_cap param, void *ret)
 531 {
 532         const char * const ir = "panfrost";
 533
 534         if (!(pan_debug & PAN_DBG_DEQP))
 535                 return 0;
 536
 537 #define RET(x) do {                  \
 538    if (ret)                          \
 539       memcpy(ret, x, sizeof(x));     \
 540    return sizeof(x);                 \
 541 } while (0)
 542
 543         switch (param) {
 544         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 545                 RET((uint32_t []){ 64 });
 546
 547         case PIPE_COMPUTE_CAP_IR_TARGET:
 548                 if (ret)
 549                         sprintf(ret, "%s", ir);
 550                 return strlen(ir) * sizeof(char);
 551
 552         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 553                 RET((uint64_t []) { 3 });
 554
 555         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 556                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 557
 558         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 559                 RET(((uint64_t []) { 1024, 1024, 64 }));
 560
 561         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 562                 RET((uint64_t []) { 1024 });
 563
 564         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 565                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 566
 567         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 568                 RET((uint64_t []) { 32768 });
 569
 570         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 571         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 572                 RET((uint64_t []) { 4096 });
 573
 574         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 575                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 576
 577         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 578                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 579
 580         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 581                 RET((uint32_t []) { 9999 });  // TODO
 582
 583         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 584                 RET((uint32_t []) { 1 }); // TODO
 585
 586         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 587                 RET((uint32_t []) { 32 });  // TODO
 588
 589         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 590                 RET((uint64_t []) { 1024 }); // TODO
 591         }
 592
 593         return 0;
 594 }
 595
 596 static void
 597 panfrost_destroy_screen(struct pipe_screen *pscreen)
 598 {
 599         panfrost_close_device(pan_device(pscreen));
 600         ralloc_free(pscreen);
 601 }
 602
 603 static uint64_t
 604 panfrost_get_timestamp(struct pipe_screen *_screen)
 605 {
 606         return os_time_get_nano();
 607 }
 608
 609 static void
 610 panfrost_fence_reference(struct pipe_screen *pscreen,
 611                          struct pipe_fence_handle **ptr,
 612                          struct pipe_fence_handle *fence)
 613 {
 614         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 615         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 616         struct panfrost_fence *old = *p;
 617
 618         if (pipe_reference(&(*p)->reference, &f->reference)) {
 619                 util_dynarray_foreach(&old->syncfds, int, fd)
 620                         close(*fd);
 621                 util_dynarray_fini(&old->syncfds);
 622                 free(old);
 623         }
 624         *p = f;
 625 }
 626
 627 static bool
 628 panfrost_fence_finish(struct pipe_screen *pscreen,
 629                       struct pipe_context *ctx,
 630                       struct pipe_fence_handle *fence,
 631                       uint64_t timeout)
 632 {
 633         struct panfrost_device *dev = pan_device(pscreen);
 634         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 635         struct util_dynarray syncobjs;
 636         int ret;
 637
 638         /* All fences were already signaled */
 639         if (!util_dynarray_num_elements(&f->syncfds, int))
 640                 return true;
 641
 642         util_dynarray_init(&syncobjs, NULL);
 643         util_dynarray_foreach(&f->syncfds, int, fd) {
 644                 uint32_t syncobj;
 645
 646                 ret = drmSyncobjCreate(dev->fd, 0, &syncobj);
 647                 assert(!ret);
 648
 649                 ret = drmSyncobjImportSyncFile(dev->fd, syncobj, *fd);
 650                 assert(!ret);
 651                 util_dynarray_append(&syncobjs, uint32_t, syncobj);
 652         }
 653
 654         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 655         if (abs_timeout == OS_TIMEOUT_INFINITE)
 656                 abs_timeout = INT64_MAX;
 657
 658         ret = drmSyncobjWait(dev->fd, util_dynarray_begin(&syncobjs),
 659                              util_dynarray_num_elements(&syncobjs, uint32_t),
 660                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 661                              NULL);
 662
 663         util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
 664                 drmSyncobjDestroy(dev->fd, *syncobj);
 665
 666         return ret >= 0;
 667 }
 668
 669 struct panfrost_fence *
 670 panfrost_fence_create(struct panfrost_context *ctx,
 671                       struct util_dynarray *fences)
 672 {
 673         struct panfrost_device *device = pan_device(ctx->base.screen);
 674         struct panfrost_fence *f = calloc(1, sizeof(*f));
 675         if (!f)
 676                 return NULL;
 677
 678         util_dynarray_init(&f->syncfds, NULL);
 679
 680         /* Export fences from all pending batches. */
 681         util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
 682                 int fd = -1;
 683
 684                 /* The fence is already signaled, no need to export it. */
 685                 if ((*fence)->signaled)
 686                         continue;
 687
 688                 drmSyncobjExportSyncFile(device->fd, (*fence)->syncobj, &fd);
 689                 if (fd == -1)
 690                         fprintf(stderr, "export failed: %m\n");
 691
 692                 assert(fd != -1);
 693                 util_dynarray_append(&f->syncfds, int, fd);
 694         }
 695
 696         pipe_reference_init(&f->reference, 1);
 697
 698         return f;
 699 }
 700
 701 static const void *
 702 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 703                                      enum pipe_shader_ir ir,
 704                                      enum pipe_shader_type shader)
 705 {
 706         if (pan_device(pscreen)->quirks & IS_BIFROST)
 707                 return &bifrost_nir_options;
 708         else
 709                 return &midgard_nir_options;
 710 }
 711
 712 struct pipe_screen *
 713 panfrost_create_screen(int fd, struct renderonly *ro)
 714 {
 715         pan_debug = debug_get_option_pan_debug();
 716
 717         /* Blacklist apps known to be buggy under Panfrost */
 718         const char *proc = util_get_process_name();
 719         const char *blacklist[] = {
 720                 "chromium",
 721                 "chrome",
 722         };
 723
 724         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 725                 if ((strcmp(blacklist[i], proc) == 0))
 726                         return NULL;
 727         }
 728
 729         /* Create the screen */
 730         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 731
 732         if (!screen)
 733                 return NULL;
 734
 735         struct panfrost_device *dev = pan_device(&screen->base);
 736         panfrost_open_device(screen, fd, dev);
 737
 738         if (ro) {
 739                 dev->ro = renderonly_dup(ro);
 740                 if (!dev->ro) {
 741                         DBG("Failed to dup renderonly object\n");
 742                         free(screen);
 743                         return NULL;
 744                 }
 745         }
 746
 747         /* Check if we're loading against a supported GPU model. */
 748
 749         switch (dev->gpu_id) {
 750         case 0x720: /* T720 */
 751         case 0x750: /* T760 */
 752         case 0x820: /* T820 */
 753         case 0x860: /* T860 */
 754                 break;
 755         default:
 756                 /* Fail to load against untested models */
 757                 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
 758                 panfrost_destroy_screen(&(screen->base));
 759                 return NULL;
 760         }
 761
 762         if (pan_debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 763                 pandecode_initialize(!(pan_debug & PAN_DBG_TRACE));
 764
 765         screen->base.destroy = panfrost_destroy_screen;
 766
 767         screen->base.get_name = panfrost_get_name;
 768         screen->base.get_vendor = panfrost_get_vendor;
 769         screen->base.get_device_vendor = panfrost_get_device_vendor;
 770         screen->base.get_param = panfrost_get_param;
 771         screen->base.get_shader_param = panfrost_get_shader_param;
 772         screen->base.get_compute_param = panfrost_get_compute_param;
 773         screen->base.get_paramf = panfrost_get_paramf;
 774         screen->base.get_timestamp = panfrost_get_timestamp;
 775         screen->base.is_format_supported = panfrost_is_format_supported;
 776         screen->base.context_create = panfrost_create_context;
 777         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 778         screen->base.fence_reference = panfrost_fence_reference;
 779         screen->base.fence_finish = panfrost_fence_finish;
 780         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 781
 782         panfrost_resource_screen_init(&screen->base);
 783
 784         return &screen->base;
 785 }