r300g/swtcl: simplify vertex uploading
[mesa.git] / src / gallium / drivers / r300 / r300_context.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "draw/draw_context.h"
24
25 #include "util/u_memory.h"
26 #include "util/u_sampler.h"
27 #include "util/u_simple_list.h"
28 #include "util/u_upload_mgr.h"
29 #include "os/os_time.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "r300_cb.h"
34 #include "r300_context.h"
35 #include "r300_emit.h"
36 #include "r300_screen.h"
37 #include "r300_screen_buffer.h"
38 #include "compiler/radeon_regalloc.h"
39
40 static void r300_release_referenced_objects(struct r300_context *r300)
41 {
42 struct pipe_framebuffer_state *fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 struct r300_textures_state *textures =
45 (struct r300_textures_state*)r300->textures_state.state;
46 unsigned i;
47
48 /* Framebuffer state. */
49 util_unreference_framebuffer_state(fb);
50
51 /* Textures. */
52 for (i = 0; i < textures->sampler_view_count; i++)
53 pipe_sampler_view_reference(
54 (struct pipe_sampler_view**)&textures->sampler_views[i], NULL);
55
56 /* The special dummy texture for texkill. */
57 if (r300->texkill_sampler) {
58 pipe_sampler_view_reference(
59 (struct pipe_sampler_view**)&r300->texkill_sampler,
60 NULL);
61 }
62
63 /* Manually-created vertex buffers. */
64 pipe_resource_reference(&r300->dummy_vb.buffer, NULL);
65 pb_reference(&r300->vbo, NULL);
66
67 r300->context.delete_depth_stencil_alpha_state(&r300->context,
68 r300->dsa_decompress_zmask);
69 }
70
71 static void r300_destroy_context(struct pipe_context* context)
72 {
73 struct r300_context* r300 = r300_context(context);
74
75 if (r300->cs && r300->hyperz_enabled) {
76 r300->rws->cs_request_feature(r300->cs, RADEON_FID_R300_HYPERZ_ACCESS, FALSE);
77 }
78
79 if (r300->blitter)
80 util_blitter_destroy(r300->blitter);
81 if (r300->draw)
82 draw_destroy(r300->draw);
83
84 if (r300->uploader)
85 u_upload_destroy(r300->uploader);
86
87 /* XXX: This function assumes r300->query_list was initialized */
88 r300_release_referenced_objects(r300);
89
90 if (r300->cs)
91 r300->rws->cs_destroy(r300->cs);
92
93 rc_destroy_regalloc_state(&r300->fs_regalloc_state);
94
95 /* XXX: No way to tell if this was initialized or not? */
96 util_slab_destroy(&r300->pool_transfers);
97
98 /* Free the structs allocated in r300_setup_atoms() */
99 if (r300->aa_state.state) {
100 FREE(r300->aa_state.state);
101 FREE(r300->blend_color_state.state);
102 FREE(r300->clip_state.state);
103 FREE(r300->fb_state.state);
104 FREE(r300->gpu_flush.state);
105 FREE(r300->hyperz_state.state);
106 FREE(r300->invariant_state.state);
107 FREE(r300->rs_block_state.state);
108 FREE(r300->scissor_state.state);
109 FREE(r300->textures_state.state);
110 FREE(r300->vap_invariant_state.state);
111 FREE(r300->viewport_state.state);
112 FREE(r300->ztop_state.state);
113 FREE(r300->fs_constants.state);
114 FREE(r300->vs_constants.state);
115 if (!r300->screen->caps.has_tcl) {
116 FREE(r300->vertex_stream_state.state);
117 }
118 }
119 FREE(r300);
120 }
121
122 static void r300_flush_callback(void *data, unsigned flags)
123 {
124 struct r300_context* const cs_context_copy = data;
125
126 r300_flush(&cs_context_copy->context, flags, NULL);
127 }
128
129 #define R300_INIT_ATOM(atomname, atomsize) \
130 do { \
131 r300->atomname.name = #atomname; \
132 r300->atomname.state = NULL; \
133 r300->atomname.size = atomsize; \
134 r300->atomname.emit = r300_emit_##atomname; \
135 r300->atomname.dirty = FALSE; \
136 } while (0)
137
138 #define R300_ALLOC_ATOM(atomname, statetype) \
139 do { \
140 r300->atomname.state = CALLOC_STRUCT(statetype); \
141 if (r300->atomname.state == NULL) \
142 return FALSE; \
143 } while (0)
144
145 static boolean r300_setup_atoms(struct r300_context* r300)
146 {
147 boolean is_rv350 = r300->screen->caps.is_rv350;
148 boolean is_r500 = r300->screen->caps.is_r500;
149 boolean has_tcl = r300->screen->caps.has_tcl;
150 boolean drm_2_6_0 = r300->screen->info.drm_minor >= 6;
151
152 /* Create the actual atom list.
153 *
154 * Some atoms never change size, others change every emit - those have
155 * the size of 0 here.
156 *
157 * NOTE: The framebuffer state is split into these atoms:
158 * - gpu_flush (unpipelined regs)
159 * - aa_state (unpipelined regs)
160 * - fb_state (unpipelined regs)
161 * - hyperz_state (unpipelined regs followed by pipelined ones)
162 * - fb_state_pipelined (pipelined regs)
163 * The motivation behind this is to be able to emit a strict
164 * subset of the regs, and to have reasonable register ordering. */
165 /* SC, GB (unpipelined), RB3D (unpipelined), ZB (unpipelined). */
166 R300_INIT_ATOM(gpu_flush, 9);
167 R300_INIT_ATOM(aa_state, 4);
168 R300_INIT_ATOM(fb_state, 0);
169 R300_INIT_ATOM(hyperz_state, is_r500 || (is_rv350 && drm_2_6_0) ? 10 : 8);
170 /* ZB (unpipelined), SC. */
171 R300_INIT_ATOM(ztop_state, 2);
172 /* ZB, FG. */
173 R300_INIT_ATOM(dsa_state, is_r500 ? (drm_2_6_0 ? 10 : 8) : 6);
174 /* RB3D. */
175 R300_INIT_ATOM(blend_state, 8);
176 R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
177 /* SC. */
178 R300_INIT_ATOM(scissor_state, 3);
179 /* GB, FG, GA, SU, SC, RB3D. */
180 R300_INIT_ATOM(invariant_state, 16 + (is_rv350 ? 4 : 0) + (is_r500 ? 4 : 0));
181 /* VAP. */
182 R300_INIT_ATOM(viewport_state, 9);
183 R300_INIT_ATOM(pvs_flush, 2);
184 R300_INIT_ATOM(vap_invariant_state, is_r500 ? 11 : 9);
185 R300_INIT_ATOM(vertex_stream_state, 0);
186 R300_INIT_ATOM(vs_state, 0);
187 R300_INIT_ATOM(vs_constants, 0);
188 R300_INIT_ATOM(clip_state, has_tcl ? 3 + (6 * 4) : 0);
189 /* VAP, RS, GA, GB, SU, SC. */
190 R300_INIT_ATOM(rs_block_state, 0);
191 R300_INIT_ATOM(rs_state, 0);
192 /* SC, US. */
193 R300_INIT_ATOM(fb_state_pipelined, 8);
194 /* US. */
195 R300_INIT_ATOM(fs, 0);
196 R300_INIT_ATOM(fs_rc_constant_state, 0);
197 R300_INIT_ATOM(fs_constants, 0);
198 /* TX. */
199 R300_INIT_ATOM(texture_cache_inval, 2);
200 R300_INIT_ATOM(textures_state, 0);
201 /* HiZ Clear */
202 R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 6 : 0);
203 /* zmask clear */
204 R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 6 : 0);
205 /* ZB (unpipelined), SU. */
206 R300_INIT_ATOM(query_start, 4);
207
208 /* Replace emission functions for r500. */
209 if (is_r500) {
210 r300->fs.emit = r500_emit_fs;
211 r300->fs_rc_constant_state.emit = r500_emit_fs_rc_constant_state;
212 r300->fs_constants.emit = r500_emit_fs_constants;
213 }
214
215 /* Some non-CSO atoms need explicit space to store the state locally. */
216 R300_ALLOC_ATOM(aa_state, r300_aa_state);
217 R300_ALLOC_ATOM(blend_color_state, r300_blend_color_state);
218 R300_ALLOC_ATOM(clip_state, r300_clip_state);
219 R300_ALLOC_ATOM(hyperz_state, r300_hyperz_state);
220 R300_ALLOC_ATOM(invariant_state, r300_invariant_state);
221 R300_ALLOC_ATOM(textures_state, r300_textures_state);
222 R300_ALLOC_ATOM(vap_invariant_state, r300_vap_invariant_state);
223 R300_ALLOC_ATOM(viewport_state, r300_viewport_state);
224 R300_ALLOC_ATOM(ztop_state, r300_ztop_state);
225 R300_ALLOC_ATOM(fb_state, pipe_framebuffer_state);
226 R300_ALLOC_ATOM(gpu_flush, pipe_framebuffer_state);
227 R300_ALLOC_ATOM(scissor_state, pipe_scissor_state);
228 R300_ALLOC_ATOM(rs_block_state, r300_rs_block);
229 R300_ALLOC_ATOM(fs_constants, r300_constant_buffer);
230 R300_ALLOC_ATOM(vs_constants, r300_constant_buffer);
231 if (!r300->screen->caps.has_tcl) {
232 R300_ALLOC_ATOM(vertex_stream_state, r300_vertex_stream_state);
233 }
234
235 /* Some non-CSO atoms don't use the state pointer. */
236 r300->fb_state_pipelined.allow_null_state = TRUE;
237 r300->fs_rc_constant_state.allow_null_state = TRUE;
238 r300->pvs_flush.allow_null_state = TRUE;
239 r300->query_start.allow_null_state = TRUE;
240 r300->texture_cache_inval.allow_null_state = TRUE;
241
242 /* Some states must be marked as dirty here to properly set up
243 * hardware in the first command stream. */
244 r300_mark_atom_dirty(r300, &r300->invariant_state);
245 r300_mark_atom_dirty(r300, &r300->pvs_flush);
246 r300_mark_atom_dirty(r300, &r300->vap_invariant_state);
247 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
248 r300_mark_atom_dirty(r300, &r300->textures_state);
249
250 return TRUE;
251 }
252
253 /* Not every state tracker calls every driver function before the first draw
254 * call and we must initialize the command buffers somehow. */
255 static void r300_init_states(struct pipe_context *pipe)
256 {
257 struct r300_context *r300 = r300_context(pipe);
258 struct pipe_blend_color bc = {{0}};
259 struct pipe_clip_state cs = {{{0}}};
260 struct pipe_scissor_state ss = {0};
261 struct r300_gpu_flush *gpuflush =
262 (struct r300_gpu_flush*)r300->gpu_flush.state;
263 struct r300_vap_invariant_state *vap_invariant =
264 (struct r300_vap_invariant_state*)r300->vap_invariant_state.state;
265 struct r300_invariant_state *invariant =
266 (struct r300_invariant_state*)r300->invariant_state.state;
267
268 CB_LOCALS;
269
270 pipe->set_blend_color(pipe, &bc);
271 pipe->set_clip_state(pipe, &cs);
272 pipe->set_scissor_state(pipe, &ss);
273
274 /* Initialize the GPU flush. */
275 {
276 BEGIN_CB(gpuflush->cb_flush_clean, 6);
277
278 /* Flush and free renderbuffer caches. */
279 OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
280 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
281 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
282 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
283 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
284 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
285
286 /* Wait until the GPU is idle.
287 * This fixes random pixels sometimes appearing probably caused
288 * by incomplete rendering. */
289 OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
290 END_CB;
291 }
292
293 /* Initialize the VAP invariant state. */
294 {
295 BEGIN_CB(vap_invariant->cb, r300->vap_invariant_state.size);
296 OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
297 OUT_CB_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
298 OUT_CB_32F(1.0);
299 OUT_CB_32F(1.0);
300 OUT_CB_32F(1.0);
301 OUT_CB_32F(1.0);
302 OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
303
304 if (r300->screen->caps.is_r500) {
305 OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
306 }
307 END_CB;
308 }
309
310 /* Initialize the invariant state. */
311 {
312 BEGIN_CB(invariant->cb, r300->invariant_state.size);
313 OUT_CB_REG(R300_GB_SELECT, 0);
314 OUT_CB_REG(R300_FG_FOG_BLEND, 0);
315 OUT_CB_REG(R300_GA_OFFSET, 0);
316 OUT_CB_REG(R300_SU_TEX_WRAP, 0);
317 OUT_CB_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
318 OUT_CB_REG(R300_SU_DEPTH_OFFSET, 0);
319 OUT_CB_REG(R300_SC_EDGERULE, 0x2DA49525);
320 OUT_CB_REG(R300_SC_SCREENDOOR, 0xffffff);
321
322 if (r300->screen->caps.is_rv350) {
323 OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
324 OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
325 }
326
327 if (r300->screen->caps.is_r500) {
328 OUT_CB_REG(R500_GA_COLOR_CONTROL_PS3, 0);
329 OUT_CB_REG(R500_SU_TEX_WRAP_PS3, 0);
330 }
331 END_CB;
332 }
333
334 /* Initialize the hyperz state. */
335 {
336 struct r300_hyperz_state *hyperz =
337 (struct r300_hyperz_state*)r300->hyperz_state.state;
338 BEGIN_CB(&hyperz->cb_flush_begin, r300->hyperz_state.size);
339 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
340 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
341 OUT_CB_REG(R300_ZB_BW_CNTL, 0);
342 OUT_CB_REG(R300_ZB_DEPTHCLEARVALUE, 0);
343 OUT_CB_REG(R300_SC_HYPERZ, R300_SC_HYPERZ_ADJ_2);
344
345 if (r300->screen->caps.is_r500 ||
346 (r300->screen->caps.is_rv350 &&
347 r300->screen->info.drm_minor >= 6)) {
348 OUT_CB_REG(R300_GB_Z_PEQ_CONFIG, 0);
349 }
350 END_CB;
351 }
352 }
353
354 struct pipe_context* r300_create_context(struct pipe_screen* screen,
355 void *priv)
356 {
357 struct r300_context* r300 = CALLOC_STRUCT(r300_context);
358 struct r300_screen* r300screen = r300_screen(screen);
359 struct radeon_winsys *rws = r300screen->rws;
360
361 if (!r300)
362 return NULL;
363
364 r300->rws = rws;
365 r300->screen = r300screen;
366
367 r300->context.screen = screen;
368 r300->context.priv = priv;
369
370 r300->context.destroy = r300_destroy_context;
371
372 util_slab_create(&r300->pool_transfers,
373 sizeof(struct pipe_transfer), 64,
374 UTIL_SLAB_SINGLETHREADED);
375
376 r300->cs = rws->cs_create(rws);
377 if (r300->cs == NULL)
378 goto fail;
379
380 if (!r300screen->caps.has_tcl) {
381 /* Create a Draw. This is used for SW TCL. */
382 r300->draw = draw_create(&r300->context);
383 if (r300->draw == NULL)
384 goto fail;
385 /* Enable our renderer. */
386 draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
387 /* Disable converting points/lines to triangles. */
388 draw_wide_line_threshold(r300->draw, 10000000.f);
389 draw_wide_point_threshold(r300->draw, 10000000.f);
390 draw_wide_point_sprites(r300->draw, FALSE);
391 draw_enable_line_stipple(r300->draw, TRUE);
392 draw_enable_point_sprites(r300->draw, FALSE);
393 }
394
395 if (!r300_setup_atoms(r300))
396 goto fail;
397
398 r300_init_blit_functions(r300);
399 r300_init_flush_functions(r300);
400 r300_init_query_functions(r300);
401 r300_init_state_functions(r300);
402 r300_init_resource_functions(r300);
403 r300_init_render_functions(r300);
404 r300_init_states(&r300->context);
405
406 r300->context.create_video_decoder = vl_create_decoder;
407 r300->context.create_video_buffer = vl_video_buffer_create;
408
409 if (r300screen->caps.has_tcl) {
410 r300->uploader = u_upload_create(&r300->context, 256 * 1024, 4,
411 PIPE_BIND_INDEX_BUFFER);
412 }
413
414 r300->blitter = util_blitter_create(&r300->context);
415 if (r300->blitter == NULL)
416 goto fail;
417 r300->blitter->draw_rectangle = r300_blitter_draw_rectangle;
418
419 rws->cs_set_flush_callback(r300->cs, r300_flush_callback, r300);
420
421 /* The KIL opcode needs the first texture unit to be enabled
422 * on r3xx-r4xx. In order to calm down the CS checker, we bind this
423 * dummy texture there. */
424 if (!r300->screen->caps.is_r500) {
425 struct pipe_resource *tex;
426 struct pipe_resource rtempl = {{0}};
427 struct pipe_sampler_view vtempl = {{0}};
428
429 rtempl.target = PIPE_TEXTURE_2D;
430 rtempl.format = PIPE_FORMAT_I8_UNORM;
431 rtempl.usage = PIPE_USAGE_IMMUTABLE;
432 rtempl.width0 = 1;
433 rtempl.height0 = 1;
434 rtempl.depth0 = 1;
435 tex = screen->resource_create(screen, &rtempl);
436
437 u_sampler_view_default_template(&vtempl, tex, tex->format);
438
439 r300->texkill_sampler = (struct r300_sampler_view*)
440 r300->context.create_sampler_view(&r300->context, tex, &vtempl);
441
442 pipe_resource_reference(&tex, NULL);
443 }
444
445 if (r300screen->caps.has_tcl) {
446 struct pipe_resource vb;
447 memset(&vb, 0, sizeof(vb));
448 vb.target = PIPE_BUFFER;
449 vb.format = PIPE_FORMAT_R8_UNORM;
450 vb.bind = PIPE_BIND_VERTEX_BUFFER;
451 vb.usage = PIPE_USAGE_IMMUTABLE;
452 vb.width0 = sizeof(float) * 16;
453 vb.height0 = 1;
454 vb.depth0 = 1;
455
456 r300->dummy_vb.buffer = screen->resource_create(screen, &vb);
457 }
458
459 {
460 struct pipe_depth_stencil_alpha_state dsa;
461 memset(&dsa, 0, sizeof(dsa));
462 dsa.depth.writemask = 1;
463
464 r300->dsa_decompress_zmask =
465 r300->context.create_depth_stencil_alpha_state(&r300->context,
466 &dsa);
467 }
468
469 r300->hyperz_time_of_last_flush = os_time_get();
470
471 /* Register allocator state */
472 rc_init_regalloc_state(&r300->fs_regalloc_state);
473
474 /* Print driver info. */
475 #ifdef DEBUG
476 {
477 #else
478 if (DBG_ON(r300, DBG_INFO)) {
479 #endif
480 fprintf(stderr,
481 "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
482 "r300: GART size: %d MB, VRAM size: %d MB\n"
483 "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
484 r300->screen->info.drm_major,
485 r300->screen->info.drm_minor,
486 r300->screen->info.drm_patchlevel,
487 screen->get_name(screen),
488 r300->screen->info.pci_id,
489 r300->screen->info.r300_num_gb_pipes,
490 r300->screen->info.r300_num_z_pipes,
491 r300->screen->info.gart_size >> 20,
492 r300->screen->info.vram_size >> 20,
493 "YES", /* XXX really? */
494 r300->screen->caps.zmask_ram ? "YES" : "NO",
495 r300->screen->caps.hiz_ram ? "YES" : "NO");
496 }
497
498 return &r300->context;
499
500 fail:
501 r300_destroy_context(&r300->context);
502 return NULL;
503 }