18ae11a3a2410b0ec6cc3e234351af536905481d
[mesa.git] / src / gallium / drivers / r300 / r300_context.h
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #ifndef R300_CONTEXT_H
24 #define R300_CONTEXT_H
25
26 #define R300_BUFFER_ALIGNMENT 64
27
28 #include "draw/draw_vertex.h"
29
30 #include "util/u_blitter.h"
31
32 #include "pipe/p_context.h"
33 #include "util/u_inlines.h"
34 #include "util/u_transfer.h"
35
36 #include "r300_defines.h"
37 #include "r300_screen.h"
38 #include "compiler/radeon_regalloc.h"
39
40 struct u_upload_mgr;
41 struct r300_context;
42 struct r300_fragment_shader;
43 struct r300_vertex_shader;
44 struct r300_stencilref_context;
45
46 enum colormask_swizzle {
47 COLORMASK_BGRA,
48 COLORMASK_RGBA,
49 COLORMASK_RRRR,
50 COLORMASK_AAAA,
51 COLORMASK_GRRG,
52 COLORMASK_ARRA,
53 COLORMASK_BGRX,
54 COLORMASK_RGBX,
55 COLORMASK_NUM_SWIZZLES
56 };
57
58 struct r300_atom {
59 /* Name, for debugging. */
60 const char* name;
61 /* Opaque state. */
62 void* state;
63 /* Emit the state to the context. */
64 void (*emit)(struct r300_context*, unsigned, void*);
65 /* Upper bound on number of dwords to emit. */
66 unsigned size;
67 /* Whether this atom should be emitted. */
68 boolean dirty;
69 /* Whether this atom may be emitted with state == NULL. */
70 boolean allow_null_state;
71 };
72
73 struct r300_aa_state {
74 struct r300_surface *dest;
75
76 uint32_t aa_config;
77 };
78
79 struct r300_blend_state {
80 struct pipe_blend_state state;
81
82 uint32_t cb_clamp[COLORMASK_NUM_SWIZZLES][8];
83 uint32_t cb_noclamp[8];
84 uint32_t cb_noclamp_noalpha[8];
85 uint32_t cb_no_readwrite[8];
86 };
87
88 struct r300_blend_color_state {
89 struct pipe_blend_color state;
90 uint32_t cb[3];
91 };
92
93 struct r300_clip_state {
94 uint32_t cb[29];
95 };
96
97 struct r300_dsa_state {
98 struct pipe_depth_stencil_alpha_state dsa;
99
100 /* This is actually a command buffer with named dwords. */
101 uint32_t cb_begin;
102 uint32_t z_buffer_control; /* R300_ZB_CNTL: 0x4f00 */
103 uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
104 uint32_t stencil_ref_mask; /* R300_ZB_STENCILREFMASK: 0x4f08 */
105 uint32_t cb_reg;
106 uint32_t stencil_ref_bf; /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
107 uint32_t cb_reg1;
108 uint32_t alpha_value; /* R500_FG_ALPHA_VALUE: 0x4be0 */
109
110 /* Same, but without ZB reads and writes. */
111 uint32_t cb_zb_no_readwrite[8]; /* ZB not bound */
112
113 /* Emitted separately: */
114 uint32_t alpha_function;
115
116 /* Whether a two-sided stencil is enabled. */
117 boolean two_sided;
118 /* Whether a fallback should be used for a two-sided stencil ref value. */
119 boolean two_sided_stencil_ref;
120 };
121
122 struct r300_hyperz_state {
123 int flush;
124 /* This is actually a command buffer with named dwords. */
125 uint32_t cb_flush_begin;
126 uint32_t zb_zcache_ctlstat; /* R300_ZB_CACHE_CNTL */
127 uint32_t cb_begin;
128 uint32_t zb_bw_cntl; /* R300_ZB_BW_CNTL */
129 uint32_t cb_reg1;
130 uint32_t zb_depthclearvalue; /* R300_ZB_DEPTHCLEARVALUE */
131 uint32_t cb_reg2;
132 uint32_t sc_hyperz; /* R300_SC_HYPERZ */
133 uint32_t cb_reg3;
134 uint32_t gb_z_peq_config; /* R300_GB_Z_PEQ_CONFIG: 0x4028 */
135 };
136
137 struct r300_gpu_flush {
138 uint32_t cb_flush_clean[6];
139 };
140
141 #define RS_STATE_MAIN_SIZE 27
142
143 struct r300_rs_state {
144 /* Original rasterizer state. */
145 struct pipe_rasterizer_state rs;
146 /* Draw-specific rasterizer state. */
147 struct pipe_rasterizer_state rs_draw;
148
149 /* Command buffers. */
150 uint32_t cb_main[RS_STATE_MAIN_SIZE];
151 uint32_t cb_poly_offset_zb16[5];
152 uint32_t cb_poly_offset_zb24[5];
153
154 /* The index to cb_main where the cull_mode register value resides. */
155 unsigned cull_mode_index;
156
157 /* Whether polygon offset is enabled. */
158 boolean polygon_offset_enable;
159
160 /* This is emitted in the draw function. */
161 uint32_t color_control; /* R300_GA_COLOR_CONTROL: 0x4278 */
162 };
163
164 struct r300_rs_block {
165 uint32_t vap_vtx_state_cntl; /* R300_VAP_VTX_STATE_CNTL: 0x2180 */
166 uint32_t vap_vsm_vtx_assm; /* R300_VAP_VSM_VTX_ASSM: 0x2184 */
167 uint32_t vap_out_vtx_fmt[2]; /* R300_VAP_OUTPUT_VTX_FMT_[0-1]: 0x2090 */
168 uint32_t gb_enable;
169
170 uint32_t ip[8]; /* R300_RS_IP_[0-7], R500_RS_IP_[0-7] */
171 uint32_t count; /* R300_RS_COUNT */
172 uint32_t inst_count; /* R300_RS_INST_COUNT */
173 uint32_t inst[8]; /* R300_RS_INST_[0-7] */
174 };
175
176 struct r300_sampler_state {
177 struct pipe_sampler_state state;
178
179 uint32_t filter0; /* R300_TX_FILTER0: 0x4400 */
180 uint32_t filter1; /* R300_TX_FILTER1: 0x4440 */
181
182 /* Min/max LOD must be clamped to [0, last_level], thus
183 * it's dependent on a currently bound texture */
184 unsigned min_lod, max_lod;
185 };
186
187 struct r300_texture_format_state {
188 uint32_t format0; /* R300_TX_FORMAT0: 0x4480 */
189 uint32_t format1; /* R300_TX_FORMAT1: 0x44c0 */
190 uint32_t format2; /* R300_TX_FORMAT2: 0x4500 */
191 uint32_t tile_config; /* R300_TX_OFFSET (subset thereof) */
192 uint32_t us_format0; /* R500_US_FORMAT0_0: 0x4640 (through 15) */
193 };
194
195 struct r300_sampler_view {
196 struct pipe_sampler_view base;
197
198 /* For resource_copy_region. */
199 unsigned width0_override;
200 unsigned height0_override;
201
202 /* Swizzles in the UTIL_FORMAT_SWIZZLE_* representation,
203 * derived from base. */
204 unsigned char swizzle[4];
205
206 /* Copy of r300_texture::texture_format_state with format-specific bits
207 * added. */
208 struct r300_texture_format_state format;
209
210 /* The texture cache region for this texture. */
211 uint32_t texcache_region;
212 };
213
214 struct r300_texture_sampler_state {
215 struct r300_texture_format_state format;
216 uint32_t filter0; /* R300_TX_FILTER0: 0x4400 */
217 uint32_t filter1; /* R300_TX_FILTER1: 0x4440 */
218 uint32_t border_color; /* R300_TX_BORDER_COLOR: 0x45c0 */
219 };
220
221 struct r300_textures_state {
222 /* Textures. */
223 struct r300_sampler_view *sampler_views[16];
224 int sampler_view_count;
225 /* Sampler states. */
226 struct r300_sampler_state *sampler_states[16];
227 int sampler_state_count;
228
229 /* This is the merge of the texture and sampler states. */
230 unsigned count;
231 uint32_t tx_enable; /* R300_TX_ENABLE: 0x4101 */
232 struct r300_texture_sampler_state regs[16];
233 };
234
235 struct r300_vertex_stream_state {
236 /* R300_VAP_PROG_STREAK_CNTL_[0-7] */
237 uint32_t vap_prog_stream_cntl[8];
238 /* R300_VAP_PROG_STREAK_CNTL_EXT_[0-7] */
239 uint32_t vap_prog_stream_cntl_ext[8];
240
241 unsigned count;
242 };
243
244 struct r300_invariant_state {
245 uint32_t cb[24];
246 };
247
248 struct r300_vap_invariant_state {
249 uint32_t cb[11];
250 };
251
252 struct r300_viewport_state {
253 float xscale; /* R300_VAP_VPORT_XSCALE: 0x2098 */
254 float xoffset; /* R300_VAP_VPORT_XOFFSET: 0x209c */
255 float yscale; /* R300_VAP_VPORT_YSCALE: 0x20a0 */
256 float yoffset; /* R300_VAP_VPORT_YOFFSET: 0x20a4 */
257 float zscale; /* R300_VAP_VPORT_ZSCALE: 0x20a8 */
258 float zoffset; /* R300_VAP_VPORT_ZOFFSET: 0x20ac */
259 uint32_t vte_control; /* R300_VAP_VTE_CNTL: 0x20b0 */
260 };
261
262 struct r300_ztop_state {
263 uint32_t z_buffer_top; /* R300_ZB_ZTOP: 0x4f14 */
264 };
265
266 /* The next several objects are not pure Radeon state; they inherit from
267 * various Gallium classes. */
268
269 struct r300_constant_buffer {
270 /* Buffer of constants */
271 uint32_t *ptr;
272 /* Remapping table. */
273 unsigned *remap_table;
274 /* const buffer base */
275 uint32_t buffer_base;
276 };
277
278 /* Query object.
279 *
280 * This is not a subclass of pipe_query because pipe_query is never
281 * actually fully defined. So, rather than have it as a member, and do
282 * subclass-style casting, we treat pipe_query as an opaque, and just
283 * trust that our state tracker does not ever mess up query objects.
284 */
285 struct r300_query {
286 /* The kind of query. Currently only OQ is supported. */
287 unsigned type;
288 /* The number of pipes where query results are stored. */
289 unsigned num_pipes;
290 /* How many results have been written, in dwords. It's incremented
291 * after end_query and flush. */
292 unsigned num_results;
293 /* if begin has been emitted */
294 boolean begin_emitted;
295
296 /* The buffer where query results are stored. */
297 struct pb_buffer *buf;
298 struct radeon_winsys_cs_handle *cs_buf;
299 };
300
301 struct r300_surface {
302 struct pipe_surface base;
303
304 /* Winsys buffer backing the texture. */
305 struct pb_buffer *buf;
306 struct radeon_winsys_cs_handle *cs_buf;
307
308 enum radeon_bo_domain domain;
309
310 uint32_t offset; /* COLOROFFSET or DEPTHOFFSET. */
311 uint32_t pitch; /* COLORPITCH or DEPTHPITCH. */
312 uint32_t pitch_zmask; /* ZMASK_PITCH */
313 uint32_t pitch_hiz; /* HIZ_PITCH */
314 uint32_t pitch_cmask; /* CMASK_PITCH */
315 uint32_t format; /* US_OUT_FMT or ZB_FORMAT. */
316
317 /* Parameters dedicated to the CBZB clear. */
318 uint32_t cbzb_width; /* Aligned width. */
319 uint32_t cbzb_height; /* Half of the height. */
320 uint32_t cbzb_midpoint_offset; /* DEPTHOFFSET. */
321 uint32_t cbzb_pitch; /* DEPTHPITCH. */
322 uint32_t cbzb_format; /* ZB_FORMAT. */
323
324 /* Whether the CBZB clear is allowed on the surface. */
325 boolean cbzb_allowed;
326
327 unsigned colormask_swizzle;
328 };
329
330 struct r300_texture_desc {
331 /* Width, height, and depth.
332 * Most of the time, these are equal to pipe_texture::width0, height0,
333 * and depth0. However, NPOT 3D textures must have dimensions aligned
334 * to POT, and this is the only case when these variables differ from
335 * pipe_texture. */
336 unsigned width0, height0, depth0;
337
338 /* Buffer tiling.
339 * Macrotiling is specified per-level because small mipmaps cannot
340 * be macrotiled. */
341 enum radeon_bo_layout microtile;
342 enum radeon_bo_layout macrotile[R300_MAX_TEXTURE_LEVELS];
343
344 /* Offsets into the buffer. */
345 unsigned offset_in_bytes[R300_MAX_TEXTURE_LEVELS];
346
347 /* Strides for each mip-level. */
348 unsigned stride_in_bytes[R300_MAX_TEXTURE_LEVELS];
349
350 /* Size of one zslice or face or 2D image based on the texture target. */
351 unsigned layer_size_in_bytes[R300_MAX_TEXTURE_LEVELS];
352
353 /* Total size of this texture, in bytes,
354 * derived from the texture properties. */
355 unsigned size_in_bytes;
356
357 /**
358 * If non-zero, override the natural texture layout with
359 * a custom stride (in bytes).
360 *
361 * \note Mipmapping fails for textures with a non-natural layout!
362 *
363 * \sa r300_texture_get_stride
364 */
365 unsigned stride_in_bytes_override;
366
367 /* Whether this texture has non-power-of-two dimensions.
368 * It can be either a regular texture or a rectangle one. */
369 boolean is_npot;
370
371 /* This flag says that hardware must use the stride for addressing
372 * instead of the width. */
373 boolean uses_stride_addressing;
374
375 /* Whether CBZB fast color clear is allowed on the miplevel. */
376 boolean cbzb_allowed[R300_MAX_TEXTURE_LEVELS];
377
378 /* Zbuffer compression info for each miplevel. */
379 boolean zcomp8x8[R300_MAX_TEXTURE_LEVELS];
380 /* If zero, then disable Z compression/HiZ. */
381 unsigned zmask_dwords[R300_MAX_TEXTURE_LEVELS];
382 unsigned hiz_dwords[R300_MAX_TEXTURE_LEVELS];
383 /* Zmask/HiZ strides for each miplevel. */
384 unsigned zmask_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
385 unsigned hiz_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
386
387 /* CMASK info for AA buffers (no mipmapping). */
388 unsigned cmask_dwords;
389 unsigned cmask_stride_in_pixels;
390 };
391
392 struct r300_resource
393 {
394 struct u_resource b;
395
396 /* Winsys buffer backing this resource. */
397 struct pb_buffer *buf;
398 struct radeon_winsys_cs_handle *cs_buf;
399 enum radeon_bo_domain domain;
400
401 /* Constant buffers and SWTCL vertex and index buffers are in user
402 * memory. */
403 uint8_t *malloced_buffer;
404
405 /* Texture description (addressing, layout, special features). */
406 struct r300_texture_desc tex;
407
408 /* This is the level tiling flags were last time set for.
409 * It's used to prevent redundant tiling-flags changes from happening.*/
410 unsigned surface_level;
411 };
412
413 struct r300_vertex_element_state {
414 unsigned count;
415 struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS];
416 unsigned format_size[PIPE_MAX_ATTRIBS];
417
418 /* The size of the vertex, in dwords. */
419 unsigned vertex_size_dwords;
420
421 struct r300_vertex_stream_state vertex_stream;
422 };
423
424 enum r300_hiz_func {
425 HIZ_FUNC_NONE,
426
427 /* The function, when determined, is set in stone
428 * until the next HiZ clear. */
429
430 /* MAX is written to the HiZ buffer.
431 * Used for LESS, LEQUAL. */
432 HIZ_FUNC_MAX,
433
434 /* MIN is written to the HiZ buffer.
435 * Used for GREATER, GEQUAL. */
436 HIZ_FUNC_MIN,
437 };
438
439 /* For deferred fragment shader state validation. */
440 enum r300_fs_validity_status {
441 FRAGMENT_SHADER_VALID, /* No need to change/validate the FS. */
442 FRAGMENT_SHADER_MAYBE_DIRTY,/* Validate the FS if external state was changed. */
443 FRAGMENT_SHADER_DIRTY /* Always validate the FS (if the FS was changed) */
444 };
445
446 struct r300_context {
447 /* Parent class */
448 struct pipe_context context;
449
450 /* The interface to the windowing system, etc. */
451 struct radeon_winsys *rws;
452 /* The submission context. */
453 struct radeon_winsys_ctx *ctx;
454 /* The command stream. */
455 struct radeon_winsys_cs *cs;
456 /* Screen. */
457 struct r300_screen *screen;
458
459 /* Draw module. Used mostly for SW TCL. */
460 struct draw_context* draw;
461 /* Vertex buffer for SW TCL. */
462 struct pb_buffer *vbo;
463 struct radeon_winsys_cs_handle *vbo_cs;
464 /* Offset and size into the SW TCL VBO. */
465 size_t draw_vbo_offset;
466
467 /* Accelerated blit support. */
468 struct blitter_context* blitter;
469 /* Stencil two-sided reference value fallback. */
470 struct r300_stencilref_context *stencilref_fallback;
471
472 /* The KIL opcode needs the first texture unit to be enabled
473 * on r3xx-r4xx. In order to calm down the CS checker, we bind this
474 * dummy texture there. */
475 struct r300_sampler_view *texkill_sampler;
476
477 /* When no vertex buffer is set, this one is used instead to prevent
478 * hardlocks. */
479 struct pipe_vertex_buffer dummy_vb;
480
481 /* The currently active query. */
482 struct r300_query *query_current;
483 /* The saved query for blitter operations. */
484 struct r300_query *blitter_saved_query;
485 /* Query list. */
486 struct r300_query query_list;
487
488 /* Various CSO state objects. */
489
490 /* Each atom is emitted in the order it appears here, which can affect
491 * performance and stability if not handled with care. */
492 /* GPU flush. */
493 struct r300_atom gpu_flush;
494 /* Clears must be emitted immediately after the flush. */
495 /* HiZ clear */
496 struct r300_atom hiz_clear;
497 /* zmask clear */
498 struct r300_atom zmask_clear;
499 /* cmask clear */
500 struct r300_atom cmask_clear;
501 /* Anti-aliasing (MSAA) state. */
502 struct r300_atom aa_state;
503 /* Framebuffer state. */
504 struct r300_atom fb_state;
505 /* HyperZ state (various SC/ZB bits). */
506 struct r300_atom hyperz_state;
507 /* ZTOP state. */
508 struct r300_atom ztop_state;
509 /* Depth, stencil, and alpha state. */
510 struct r300_atom dsa_state;
511 /* Blend state. */
512 struct r300_atom blend_state;
513 /* Blend color state. */
514 struct r300_atom blend_color_state;
515 /* Scissor state. */
516 struct r300_atom scissor_state;
517 /* Sample mask. */
518 struct r300_atom sample_mask;
519 /* Invariant state. This must be emitted to get the engine started. */
520 struct r300_atom invariant_state;
521 /* Viewport state. */
522 struct r300_atom viewport_state;
523 /* PVS flush. */
524 struct r300_atom pvs_flush;
525 /* VAP invariant state. */
526 struct r300_atom vap_invariant_state;
527 /* Vertex stream formatting state. */
528 struct r300_atom vertex_stream_state;
529 /* Vertex shader. */
530 struct r300_atom vs_state;
531 /* User clip planes. */
532 struct r300_atom clip_state;
533 /* RS block state + VAP (vertex shader) output mapping state. */
534 struct r300_atom rs_block_state;
535 /* Rasterizer state. */
536 struct r300_atom rs_state;
537 /* Framebuffer state (pipelined regs). */
538 struct r300_atom fb_state_pipelined;
539 /* Fragment shader. */
540 struct r300_atom fs;
541 /* Fragment shader RC_CONSTANT_STATE variables. */
542 struct r300_atom fs_rc_constant_state;
543 /* Fragment shader constant buffer. */
544 struct r300_atom fs_constants;
545 /* Vertex shader constant buffer. */
546 struct r300_atom vs_constants;
547 /* Texture cache invalidate. */
548 struct r300_atom texture_cache_inval;
549 /* Textures state. */
550 struct r300_atom textures_state;
551 /* Occlusion query. */
552 struct r300_atom query_start;
553
554 /* The pointers to the first and the last atom. */
555 struct r300_atom *first_dirty, *last_dirty;
556
557 /* Vertex elements for Gallium. */
558 struct r300_vertex_element_state *velems;
559
560 /* Vertex info for Draw. */
561 struct vertex_info vertex_info;
562
563 struct pipe_stencil_ref stencil_ref;
564 struct pipe_viewport_state viewport;
565
566 /* Stream locations for SWTCL. */
567 int stream_loc_notcl[16];
568
569 /* Flag indicating whether or not the HW is dirty. */
570 uint32_t dirty_hw;
571 /* Whether polygon offset is enabled. */
572 boolean polygon_offset_enabled;
573 /* Z buffer bit depth. */
574 uint32_t zbuffer_bpp;
575 /* Whether rendering is conditional and should be skipped. */
576 boolean skip_rendering;
577 /* The flag above saved by blitter. */
578 unsigned char blitter_saved_skip_rendering;
579 /* Point sprites texcoord index, 1 bit per texcoord */
580 int sprite_coord_enable;
581 /* Whether two-sided color selection is enabled (AKA light_twoside). */
582 boolean two_sided_color;
583 boolean flatshade;
584 boolean clip_halfz;
585 /* Whether fast color clear is enabled. */
586 boolean cbzb_clear;
587 /* Whether fragment shader needs to be validated. */
588 enum r300_fs_validity_status fs_status;
589 /* Framebuffer multi-write. */
590 boolean fb_multiwrite;
591 unsigned num_samples;
592 boolean msaa_enable;
593 boolean alpha_to_one;
594 boolean alpha_to_coverage;
595
596 void *dsa_decompress_zmask;
597
598 struct pipe_index_buffer index_buffer;
599 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
600 unsigned nr_vertex_buffers;
601 struct u_upload_mgr *uploader;
602
603 struct util_slab_mempool pool_transfers;
604
605 /* Stat counter. */
606 uint64_t flush_counter;
607
608 /* const tracking for VS */
609 int vs_const_base;
610
611 /* Vertex array state info */
612 boolean vertex_arrays_dirty;
613 boolean vertex_arrays_indexed;
614 int vertex_arrays_offset;
615 int vertex_arrays_instance_id;
616 boolean instancing_enabled;
617
618 /* Hyper-Z stats. */
619 boolean hyperz_enabled; /* Whether it owns Hyper-Z access. */
620 int64_t hyperz_time_of_last_flush; /* Time of the last flush with Z clear. */
621 unsigned num_z_clears; /* Since the last flush. */
622
623 /* ZMask state. */
624 boolean zmask_in_use; /* Whether ZMASK is enabled. */
625 boolean zmask_decompress; /* Whether ZMASK is being decompressed. */
626 struct pipe_surface *locked_zbuffer; /* Unbound zbuffer which still has data in ZMASK. */
627
628 /* HiZ state. */
629 boolean hiz_in_use; /* Whether HIZ is enabled. */
630 enum r300_hiz_func hiz_func; /* HiZ function. Can be either MIN or MAX. */
631 uint32_t hiz_clear_value; /* HiZ clear value. */
632
633 /* CMASK state. */
634 boolean cmask_access;
635 boolean cmask_in_use;
636 uint32_t color_clear_value; /* RGBA8 or RGBA1010102 */
637 uint32_t color_clear_value_ar; /* RGBA16F */
638 uint32_t color_clear_value_gb; /* RGBA16F */
639
640 /* Compiler state. */
641 struct rc_regalloc_state fs_regalloc_state; /* Register allocator info for
642 * fragment shaders. */
643 };
644
645 #define foreach_atom(r300, atom) \
646 for (atom = &r300->gpu_flush; atom != (&r300->query_start)+1; atom++)
647
648 #define foreach_dirty_atom(r300, atom) \
649 for (atom = r300->first_dirty; atom != r300->last_dirty; atom++)
650
651 /* Convenience cast wrappers. */
652 static inline struct r300_query* r300_query(struct pipe_query* q)
653 {
654 return (struct r300_query*)q;
655 }
656
657 static inline struct r300_surface* r300_surface(struct pipe_surface* surf)
658 {
659 return (struct r300_surface*)surf;
660 }
661
662 static inline struct r300_resource* r300_resource(struct pipe_resource* tex)
663 {
664 return (struct r300_resource*)tex;
665 }
666
667 static inline struct r300_context* r300_context(struct pipe_context* context)
668 {
669 return (struct r300_context*)context;
670 }
671
672 static inline struct r300_fragment_shader *r300_fs(struct r300_context *r300)
673 {
674 return (struct r300_fragment_shader*)r300->fs.state;
675 }
676
677 static inline void r300_mark_atom_dirty(struct r300_context *r300,
678 struct r300_atom *atom)
679 {
680 atom->dirty = TRUE;
681
682 if (!r300->first_dirty) {
683 r300->first_dirty = atom;
684 r300->last_dirty = atom+1;
685 } else {
686 if (atom < r300->first_dirty)
687 r300->first_dirty = atom;
688 else if (atom+1 > r300->last_dirty)
689 r300->last_dirty = atom+1;
690 }
691 }
692
693 static inline struct pipe_surface *
694 r300_get_nonnull_cb(struct pipe_framebuffer_state *fb, unsigned i)
695 {
696 if (fb->cbufs[i])
697 return fb->cbufs[i];
698
699 /* The i-th framebuffer is NULL, return any non-NULL one. */
700 for (i = 0; i < fb->nr_cbufs; i++)
701 if (fb->cbufs[i])
702 return fb->cbufs[i];
703
704 return NULL;
705 }
706
707 struct pipe_context* r300_create_context(struct pipe_screen* screen,
708 void *priv);
709
710 /* Context initialization. */
711 struct draw_stage* r300_draw_stage(struct r300_context* r300);
712 void r300_init_blit_functions(struct r300_context *r300);
713 void r300_init_flush_functions(struct r300_context* r300);
714 void r300_init_query_functions(struct r300_context* r300);
715 void r300_init_render_functions(struct r300_context *r300);
716 void r300_init_state_functions(struct r300_context* r300);
717 void r300_init_resource_functions(struct r300_context* r300);
718
719 /* r300_blit.c */
720 void r300_decompress_zmask(struct r300_context *r300);
721 void r300_decompress_zmask_locked_unsafe(struct r300_context *r300);
722 void r300_decompress_zmask_locked(struct r300_context *r300);
723 bool r300_is_blit_supported(enum pipe_format format);
724
725 /* r300_flush.c */
726 void r300_flush(struct pipe_context *pipe,
727 unsigned flags,
728 struct pipe_fence_handle **fence);
729
730 /* r300_hyperz.c */
731 void r300_update_hyperz_state(struct r300_context* r300);
732
733 /* r300_query.c */
734 void r300_resume_query(struct r300_context *r300,
735 struct r300_query *query);
736 void r300_stop_query(struct r300_context *r300);
737
738 /* r300_render_translate.c */
739 void r300_translate_index_buffer(struct r300_context *r300,
740 struct pipe_index_buffer *ib,
741 struct pipe_resource **out_index_buffer,
742 unsigned *index_size, unsigned index_offset,
743 unsigned *start, unsigned count);
744
745 /* r300_render_stencilref.c */
746 void r300_plug_in_stencil_ref_fallback(struct r300_context *r300);
747
748 /* r300_render.c */
749 void r500_emit_index_bias(struct r300_context *r300, int index_bias);
750 void r300_blitter_draw_rectangle(struct blitter_context *blitter,
751 int x1, int y1, int x2, int y2,
752 float depth,
753 enum blitter_attrib_type type,
754 const union pipe_color_union *attrib);
755
756 /* r300_state.c */
757 enum r300_fb_state_change {
758 R300_CHANGED_FB_STATE = 0,
759 R300_CHANGED_HYPERZ_FLAG,
760 R300_CHANGED_MULTIWRITE,
761 R300_CHANGED_CMASK_ENABLE,
762 };
763
764 void r300_mark_fb_state_dirty(struct r300_context *r300,
765 enum r300_fb_state_change change);
766 void r300_mark_fs_code_dirty(struct r300_context *r300);
767
768 struct pipe_sampler_view *
769 r300_create_sampler_view_custom(struct pipe_context *pipe,
770 struct pipe_resource *texture,
771 const struct pipe_sampler_view *templ,
772 unsigned width0_override,
773 unsigned height0_override);
774
775 /* r300_state_derived.c */
776 void r300_update_derived_state(struct r300_context* r300);
777
778 /* r300_debug.c */
779 void r500_dump_rs_block(struct r300_rs_block *rs);
780
781
782 static inline boolean CTX_DBG_ON(struct r300_context * ctx, unsigned flags)
783 {
784 return SCREEN_DBG_ON(ctx->screen, flags);
785 }
786
787 static inline void CTX_DBG(struct r300_context * ctx, unsigned flags,
788 const char * fmt, ...)
789 {
790 if (CTX_DBG_ON(ctx, flags)) {
791 va_list va;
792 va_start(va, fmt);
793 vfprintf(stderr, fmt, va);
794 va_end(va);
795 }
796 }
797
798 #define DBG_ON CTX_DBG_ON
799 #define DBG CTX_DBG
800
801 #endif /* R300_CONTEXT_H */