src/gallium/drivers/r300/r300_context.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #ifndef R300_CONTEXT_H
  24 #define R300_CONTEXT_H
  25
  26 #define R300_BUFFER_ALIGNMENT 64
  27
  28 #include "draw/draw_vertex.h"
  29
  30 #include "util/u_blitter.h"
  31
  32 #include "pipe/p_context.h"
  33 #include "util/u_inlines.h"
  34 #include "util/u_transfer.h"
  35
  36 #include "r300_defines.h"
  37 #include "r300_screen.h"
  38 #include "compiler/radeon_regalloc.h"
  39 #include "../../winsys/radeon/drm/radeon_winsys.h"
  40
  41 struct u_upload_mgr;
  42 struct r300_context;
  43 struct r300_fragment_shader;
  44 struct r300_vertex_shader;
  45 struct r300_stencilref_context;
  46
  47 enum colormask_swizzle {
  48     COLORMASK_BGRA,
  49     COLORMASK_RGBA,
  50     COLORMASK_RRRR,
  51     COLORMASK_AAAA,
  52     COLORMASK_GRRG,
  53     COLORMASK_ARRA,
  54     COLORMASK_NUM_SWIZZLES
  55 };
  56
  57 struct r300_atom {
  58     /* Name, for debugging. */
  59     const char* name;
  60     /* Opaque state. */
  61     void* state;
  62     /* Emit the state to the context. */
  63     void (*emit)(struct r300_context*, unsigned, void*);
  64     /* Upper bound on number of dwords to emit. */
  65     unsigned size;
  66     /* Whether this atom should be emitted. */
  67     boolean dirty;
  68     /* Whether this atom may be emitted with state == NULL. */
  69     boolean allow_null_state;
  70 };
  71
  72 struct r300_aa_state {
  73     struct r300_surface *dest;
  74
  75     uint32_t aa_config;
  76     uint32_t aaresolve_ctl;
  77 };
  78
  79 struct r300_blend_state {
  80     struct pipe_blend_state state;
  81
  82     uint32_t cb_clamp[COLORMASK_NUM_SWIZZLES][8];
  83     uint32_t cb_noclamp[8];
  84     uint32_t cb_no_readwrite[8];
  85 };
  86
  87 struct r300_blend_color_state {
  88     struct pipe_blend_color state;
  89     uint32_t cb[3];
  90 };
  91
  92 struct r300_clip_state {
  93     uint32_t cb[29];
  94 };
  95
  96 struct r300_dsa_state {
  97     struct pipe_depth_stencil_alpha_state dsa;
  98
  99     /* This is actually a command buffer with named dwords. */
 100     uint32_t cb_begin;
 101     uint32_t alpha_function;    /* R300_FG_ALPHA_FUNC: 0x4bd4 */
 102     uint32_t cb_reg_seq;
 103     uint32_t z_buffer_control;  /* R300_ZB_CNTL: 0x4f00 */
 104     uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
 105     uint32_t stencil_ref_mask;  /* R300_ZB_STENCILREFMASK: 0x4f08 */
 106     uint32_t cb_reg;
 107     uint32_t stencil_ref_bf;    /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
 108     uint32_t cb_reg1;
 109     uint32_t alpha_value;       /* R500_FG_ALPHA_VALUE: 0x4be0 */
 110
 111     /* The same, but for FP16 alpha test. */
 112     uint32_t cb_begin_fp16;
 113     uint32_t alpha_function_fp16;    /* R300_FG_ALPHA_FUNC: 0x4bd4 */
 114     uint32_t cb_reg_seq_fp16;
 115     uint32_t z_buffer_control_fp16;  /* R300_ZB_CNTL: 0x4f00 */
 116     uint32_t z_stencil_control_fp16; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */
 117     uint32_t stencil_ref_mask_fp16;  /* R300_ZB_STENCILREFMASK: 0x4f08 */
 118     uint32_t cb_reg_fp16;
 119     uint32_t stencil_ref_bf_fp16;    /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */
 120     uint32_t cb_reg1_fp16;
 121     uint32_t alpha_value_fp16;       /* R500_FG_ALPHA_VALUE: 0x4be0 */
 122
 123     /* The second command buffer disables zbuffer reads and writes. */
 124     uint32_t cb_zb_no_readwrite[10];
 125     uint32_t cb_fp16_zb_no_readwrite[10];
 126
 127     /* Whether a two-sided stencil is enabled. */
 128     boolean two_sided;
 129     /* Whether a fallback should be used for a two-sided stencil ref value. */
 130     boolean two_sided_stencil_ref;
 131 };
 132
 133 struct r300_hyperz_state {
 134     int flush;
 135     /* This is actually a command buffer with named dwords. */
 136     uint32_t cb_flush_begin;
 137     uint32_t zb_zcache_ctlstat;     /* R300_ZB_CACHE_CNTL */
 138     uint32_t cb_begin;
 139     uint32_t zb_bw_cntl;            /* R300_ZB_BW_CNTL */
 140     uint32_t cb_reg1;
 141     uint32_t zb_depthclearvalue;    /* R300_ZB_DEPTHCLEARVALUE */
 142     uint32_t cb_reg2;
 143     uint32_t sc_hyperz;             /* R300_SC_HYPERZ */
 144     uint32_t cb_reg3;
 145     uint32_t gb_z_peq_config;       /* R300_GB_Z_PEQ_CONFIG: 0x4028 */
 146 };
 147
 148 struct r300_gpu_flush {
 149     uint32_t cb_flush_clean[6];
 150 };
 151
 152 #define RS_STATE_MAIN_SIZE 27
 153
 154 struct r300_rs_state {
 155     /* Original rasterizer state. */
 156     struct pipe_rasterizer_state rs;
 157     /* Draw-specific rasterizer state. */
 158     struct pipe_rasterizer_state rs_draw;
 159
 160     /* Command buffers. */
 161     uint32_t cb_main[RS_STATE_MAIN_SIZE];
 162     uint32_t cb_poly_offset_zb16[5];
 163     uint32_t cb_poly_offset_zb24[5];
 164
 165     /* The index to cb_main where the cull_mode register value resides. */
 166     unsigned cull_mode_index;
 167
 168     /* Whether polygon offset is enabled. */
 169     boolean polygon_offset_enable;
 170
 171     /* This is emitted in the draw function. */
 172     uint32_t color_control;         /* R300_GA_COLOR_CONTROL: 0x4278 */
 173 };
 174
 175 struct r300_rs_block {
 176     uint32_t vap_vtx_state_cntl;  /* R300_VAP_VTX_STATE_CNTL: 0x2180 */
 177     uint32_t vap_vsm_vtx_assm;    /* R300_VAP_VSM_VTX_ASSM: 0x2184 */
 178     uint32_t vap_out_vtx_fmt[2];  /* R300_VAP_OUTPUT_VTX_FMT_[0-1]: 0x2090 */
 179     uint32_t gb_enable;
 180
 181     uint32_t ip[8]; /* R300_RS_IP_[0-7], R500_RS_IP_[0-7] */
 182     uint32_t count; /* R300_RS_COUNT */
 183     uint32_t inst_count; /* R300_RS_INST_COUNT */
 184     uint32_t inst[8]; /* R300_RS_INST_[0-7] */
 185 };
 186
 187 struct r300_sampler_state {
 188     struct pipe_sampler_state state;
 189
 190     uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
 191     uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
 192
 193     /* Min/max LOD must be clamped to [0, last_level], thus
 194      * it's dependent on a currently bound texture */
 195     unsigned min_lod, max_lod;
 196 };
 197
 198 struct r300_texture_format_state {
 199     uint32_t format0; /* R300_TX_FORMAT0: 0x4480 */
 200     uint32_t format1; /* R300_TX_FORMAT1: 0x44c0 */
 201     uint32_t format2; /* R300_TX_FORMAT2: 0x4500 */
 202     uint32_t tile_config; /* R300_TX_OFFSET (subset thereof) */
 203     uint32_t us_format0;   /* R500_US_FORMAT0_0: 0x4640 (through 15) */
 204 };
 205
 206 struct r300_sampler_view {
 207     struct pipe_sampler_view base;
 208
 209     /* For resource_copy_region. */
 210     unsigned width0_override;
 211     unsigned height0_override;
 212
 213     /* Swizzles in the UTIL_FORMAT_SWIZZLE_* representation,
 214      * derived from base. */
 215     unsigned char swizzle[4];
 216
 217     /* Copy of r300_texture::texture_format_state with format-specific bits
 218      * added. */
 219     struct r300_texture_format_state format;
 220
 221     /* The texture cache region for this texture. */
 222     uint32_t texcache_region;
 223 };
 224
 225 struct r300_texture_sampler_state {
 226     struct r300_texture_format_state format;
 227     uint32_t filter0;      /* R300_TX_FILTER0: 0x4400 */
 228     uint32_t filter1;      /* R300_TX_FILTER1: 0x4440 */
 229     uint32_t border_color; /* R300_TX_BORDER_COLOR: 0x45c0 */
 230 };
 231
 232 struct r300_textures_state {
 233     /* Textures. */
 234     struct r300_sampler_view *sampler_views[16];
 235     int sampler_view_count;
 236     /* Sampler states. */
 237     struct r300_sampler_state *sampler_states[16];
 238     int sampler_state_count;
 239
 240     /* This is the merge of the texture and sampler states. */
 241     unsigned count;
 242     uint32_t tx_enable;         /* R300_TX_ENABLE: 0x4101 */
 243     struct r300_texture_sampler_state regs[16];
 244 };
 245
 246 struct r300_vertex_stream_state {
 247     /* R300_VAP_PROG_STREAK_CNTL_[0-7] */
 248     uint32_t vap_prog_stream_cntl[8];
 249     /* R300_VAP_PROG_STREAK_CNTL_EXT_[0-7] */
 250     uint32_t vap_prog_stream_cntl_ext[8];
 251
 252     unsigned count;
 253 };
 254
 255 struct r300_invariant_state {
 256     uint32_t cb[24];
 257 };
 258
 259 struct r300_vap_invariant_state {
 260     uint32_t cb[11];
 261 };
 262
 263 struct r300_viewport_state {
 264     float xscale;         /* R300_VAP_VPORT_XSCALE:  0x2098 */
 265     float xoffset;        /* R300_VAP_VPORT_XOFFSET: 0x209c */
 266     float yscale;         /* R300_VAP_VPORT_YSCALE:  0x20a0 */
 267     float yoffset;        /* R300_VAP_VPORT_YOFFSET: 0x20a4 */
 268     float zscale;         /* R300_VAP_VPORT_ZSCALE:  0x20a8 */
 269     float zoffset;        /* R300_VAP_VPORT_ZOFFSET: 0x20ac */
 270     uint32_t vte_control; /* R300_VAP_VTE_CNTL:      0x20b0 */
 271 };
 272
 273 struct r300_ztop_state {
 274     uint32_t z_buffer_top;      /* R300_ZB_ZTOP: 0x4f14 */
 275 };
 276
 277 /* The next several objects are not pure Radeon state; they inherit from
 278  * various Gallium classes. */
 279
 280 struct r300_constant_buffer {
 281     /* Buffer of constants */
 282     uint32_t *ptr;
 283     /* Remapping table. */
 284     unsigned *remap_table;
 285     /* const buffer base */
 286     uint32_t buffer_base;
 287 };
 288
 289 /* Query object.
 290  *
 291  * This is not a subclass of pipe_query because pipe_query is never
 292  * actually fully defined. So, rather than have it as a member, and do
 293  * subclass-style casting, we treat pipe_query as an opaque, and just
 294  * trust that our state tracker does not ever mess up query objects.
 295  */
 296 struct r300_query {
 297     /* The kind of query. Currently only OQ is supported. */
 298     unsigned type;
 299     /* The number of pipes where query results are stored. */
 300     unsigned num_pipes;
 301     /* How many results have been written, in dwords. It's incremented
 302      * after end_query and flush. */
 303     unsigned num_results;
 304     /* if begin has been emitted */
 305     boolean begin_emitted;
 306
 307     /* The buffer where query results are stored. */
 308     struct pb_buffer *buf;
 309     struct radeon_winsys_cs_handle *cs_buf;
 310 };
 311
 312 struct r300_surface {
 313     struct pipe_surface base;
 314
 315     /* Winsys buffer backing the texture. */
 316     struct pb_buffer *buf;
 317     struct radeon_winsys_cs_handle *cs_buf;
 318
 319     enum radeon_bo_domain domain;
 320
 321     uint32_t offset;    /* COLOROFFSET or DEPTHOFFSET. */
 322     uint32_t pitch;     /* COLORPITCH or DEPTHPITCH. */
 323     uint32_t pitch_zmask; /* ZMASK_PITCH */
 324     uint32_t pitch_hiz;   /* HIZ_PITCH */
 325     uint32_t format;    /* US_OUT_FMT or ZB_FORMAT. */
 326
 327     /* Parameters dedicated to the CBZB clear. */
 328     uint32_t cbzb_width;            /* Aligned width. */
 329     uint32_t cbzb_height;           /* Half of the height. */
 330     uint32_t cbzb_midpoint_offset;  /* DEPTHOFFSET. */
 331     uint32_t cbzb_pitch;            /* DEPTHPITCH. */
 332     uint32_t cbzb_format;           /* ZB_FORMAT. */
 333
 334     /* Whether the CBZB clear is allowed on the surface. */
 335     boolean cbzb_allowed;
 336
 337     unsigned colormask_swizzle;
 338 };
 339
 340 struct r300_texture_desc {
 341     /* Width, height, and depth.
 342      * Most of the time, these are equal to pipe_texture::width0, height0,
 343      * and depth0. However, NPOT 3D textures must have dimensions aligned
 344      * to POT, and this is the only case when these variables differ from
 345      * pipe_texture. */
 346     unsigned width0, height0, depth0;
 347
 348     /* Buffer tiling.
 349      * Macrotiling is specified per-level because small mipmaps cannot
 350      * be macrotiled. */
 351     enum radeon_bo_layout microtile;
 352     enum radeon_bo_layout macrotile[R300_MAX_TEXTURE_LEVELS];
 353
 354     /* Offsets into the buffer. */
 355     unsigned offset_in_bytes[R300_MAX_TEXTURE_LEVELS];
 356
 357     /* Strides for each mip-level. */
 358     unsigned stride_in_bytes[R300_MAX_TEXTURE_LEVELS];
 359
 360     /* Size of one zslice or face or 2D image based on the texture target. */
 361     unsigned layer_size_in_bytes[R300_MAX_TEXTURE_LEVELS];
 362
 363     /* Total size of this texture, in bytes,
 364      * derived from the texture properties. */
 365     unsigned size_in_bytes;
 366
 367     /**
 368      * If non-zero, override the natural texture layout with
 369      * a custom stride (in bytes).
 370      *
 371      * \note Mipmapping fails for textures with a non-natural layout!
 372      *
 373      * \sa r300_texture_get_stride
 374      */
 375     unsigned stride_in_bytes_override;
 376
 377     /* Whether this texture has non-power-of-two dimensions.
 378      * It can be either a regular texture or a rectangle one. */
 379     boolean is_npot;
 380
 381     /* This flag says that hardware must use the stride for addressing
 382      * instead of the width. */
 383     boolean uses_stride_addressing;
 384
 385     /* Whether CBZB fast color clear is allowed on the miplevel. */
 386     boolean cbzb_allowed[R300_MAX_TEXTURE_LEVELS];
 387
 388     /* Zbuffer compression info for each miplevel. */
 389     boolean zcomp8x8[R300_MAX_TEXTURE_LEVELS];
 390     /* If zero, then disable Z compression/HiZ. */
 391     unsigned zmask_dwords[R300_MAX_TEXTURE_LEVELS];
 392     unsigned hiz_dwords[R300_MAX_TEXTURE_LEVELS];
 393     /* Zmask/HiZ strides for each miplevel. */
 394     unsigned zmask_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
 395     unsigned hiz_stride_in_pixels[R300_MAX_TEXTURE_LEVELS];
 396 };
 397
 398 struct r300_resource
 399 {
 400     struct u_resource b;
 401
 402     /* Winsys buffer backing this resource. */
 403     struct pb_buffer *buf;
 404     struct radeon_winsys_cs_handle *cs_buf;
 405     enum radeon_bo_domain domain;
 406
 407     /* Constant buffers and SWTCL vertex and index buffers are in user
 408      * memory. */
 409     uint8_t *malloced_buffer;
 410
 411     /* Texture description (addressing, layout, special features). */
 412     struct r300_texture_desc tex;
 413
 414     /* This is the level tiling flags were last time set for.
 415      * It's used to prevent redundant tiling-flags changes from happening.*/
 416     unsigned surface_level;
 417 };
 418
 419 struct r300_vertex_element_state {
 420     unsigned count;
 421     struct pipe_vertex_element velem[PIPE_MAX_ATTRIBS];
 422     unsigned format_size[PIPE_MAX_ATTRIBS];
 423
 424     /* The size of the vertex, in dwords. */
 425     unsigned vertex_size_dwords;
 426
 427     struct r300_vertex_stream_state vertex_stream;
 428 };
 429
 430 enum r300_hiz_func {
 431     HIZ_FUNC_NONE,
 432
 433     /* The function, when determined, is set in stone
 434      * until the next HiZ clear. */
 435
 436     /* MAX is written to the HiZ buffer.
 437      * Used for LESS, LEQUAL. */
 438     HIZ_FUNC_MAX,
 439
 440     /* MIN is written to the HiZ buffer.
 441      * Used for GREATER, GEQUAL. */
 442     HIZ_FUNC_MIN,
 443 };
 444
 445 /* For deferred fragment shader state validation. */
 446 enum r300_fs_validity_status {
 447     FRAGMENT_SHADER_VALID,      /* No need to change/validate the FS. */
 448     FRAGMENT_SHADER_MAYBE_DIRTY,/* Validate the FS if external state was changed. */
 449     FRAGMENT_SHADER_DIRTY       /* Always validate the FS (if the FS was changed) */
 450 };
 451
 452 struct r300_context {
 453     /* Parent class */
 454     struct pipe_context context;
 455
 456     /* The interface to the windowing system, etc. */
 457     struct radeon_winsys *rws;
 458     /* The command stream. */
 459     struct radeon_winsys_cs *cs;
 460     /* Screen. */
 461     struct r300_screen *screen;
 462
 463     /* Draw module. Used mostly for SW TCL. */
 464     struct draw_context* draw;
 465     /* Vertex buffer for SW TCL. */
 466     struct pipe_resource* vbo;
 467     /* Offset and size into the SW TCL VBO. */
 468     size_t draw_vbo_offset;
 469     size_t draw_vbo_size;
 470     /* Whether the VBO must not be flushed. */
 471     boolean draw_vbo_locked;
 472     boolean draw_first_emitted;
 473
 474     /* Accelerated blit support. */
 475     struct blitter_context* blitter;
 476     /* Stencil two-sided reference value fallback. */
 477     struct r300_stencilref_context *stencilref_fallback;
 478
 479     /* The KIL opcode needs the first texture unit to be enabled
 480      * on r3xx-r4xx. In order to calm down the CS checker, we bind this
 481      * dummy texture there. */
 482     struct r300_sampler_view *texkill_sampler;
 483
 484     /* When no vertex buffer is set, this one is used instead to prevent
 485      * hardlocks. */
 486     struct pipe_vertex_buffer dummy_vb;
 487
 488     /* The currently active query. */
 489     struct r300_query *query_current;
 490     /* The saved query for blitter operations. */
 491     struct r300_query *blitter_saved_query;
 492     /* Query list. */
 493     struct r300_query query_list;
 494
 495     /* Various CSO state objects. */
 496
 497     /* Each atom is emitted in the order it appears here, which can affect
 498      * performance and stability if not handled with care. */
 499     /* GPU flush. */
 500     struct r300_atom gpu_flush;
 501     /* Anti-aliasing (MSAA) state. */
 502     struct r300_atom aa_state;
 503     /* Framebuffer state. */
 504     struct r300_atom fb_state;
 505     /* HyperZ state (various SC/ZB bits). */
 506     struct r300_atom hyperz_state;
 507     /* ZTOP state. */
 508     struct r300_atom ztop_state;
 509     /* Depth, stencil, and alpha state. */
 510     struct r300_atom dsa_state;
 511     /* Blend state. */
 512     struct r300_atom blend_state;
 513     /* Blend color state. */
 514     struct r300_atom blend_color_state;
 515     /* Scissor state. */
 516     struct r300_atom scissor_state;
 517     /* Invariant state. This must be emitted to get the engine started. */
 518     struct r300_atom invariant_state;
 519     /* Viewport state. */
 520     struct r300_atom viewport_state;
 521     /* PVS flush. */
 522     struct r300_atom pvs_flush;
 523     /* VAP invariant state. */
 524     struct r300_atom vap_invariant_state;
 525     /* Vertex stream formatting state. */
 526     struct r300_atom vertex_stream_state;
 527     /* Vertex shader. */
 528     struct r300_atom vs_state;
 529     /* User clip planes. */
 530     struct r300_atom clip_state;
 531     /* RS block state + VAP (vertex shader) output mapping state. */
 532     struct r300_atom rs_block_state;
 533     /* Rasterizer state. */
 534     struct r300_atom rs_state;
 535     /* Framebuffer state (pipelined regs). */
 536     struct r300_atom fb_state_pipelined;
 537     /* Fragment shader. */
 538     struct r300_atom fs;
 539     /* Fragment shader RC_CONSTANT_STATE variables. */
 540     struct r300_atom fs_rc_constant_state;
 541     /* Fragment shader constant buffer. */
 542     struct r300_atom fs_constants;
 543     /* Vertex shader constant buffer. */
 544     struct r300_atom vs_constants;
 545     /* Texture cache invalidate. */
 546     struct r300_atom texture_cache_inval;
 547     /* Textures state. */
 548     struct r300_atom textures_state;
 549     /* HiZ clear */
 550     struct r300_atom hiz_clear;
 551     /* zmask clear */
 552     struct r300_atom zmask_clear;
 553     /* Occlusion query. */
 554     struct r300_atom query_start;
 555
 556     /* The pointers to the first and the last atom. */
 557     struct r300_atom *first_dirty, *last_dirty;
 558
 559     /* Vertex elements for Gallium. */
 560     struct r300_vertex_element_state *velems;
 561
 562     /* Vertex info for Draw. */
 563     struct vertex_info vertex_info;
 564
 565     struct pipe_stencil_ref stencil_ref;
 566     struct pipe_viewport_state viewport;
 567
 568     /* Stream locations for SWTCL. */
 569     int stream_loc_notcl[16];
 570
 571     /* Flag indicating whether or not the HW is dirty. */
 572     uint32_t dirty_hw;
 573     /* Whether polygon offset is enabled. */
 574     boolean polygon_offset_enabled;
 575     /* Z buffer bit depth. */
 576     uint32_t zbuffer_bpp;
 577     /* Whether rendering is conditional and should be skipped. */
 578     boolean skip_rendering;
 579     /* The flag above saved by blitter. */
 580     unsigned char blitter_saved_skip_rendering;
 581     /* Point sprites texcoord index,  1 bit per texcoord */
 582     int sprite_coord_enable;
 583     /* Whether two-sided color selection is enabled (AKA light_twoside). */
 584     boolean two_sided_color;
 585     /* Whether fast color clear is enabled. */
 586     boolean cbzb_clear;
 587     /* Whether fragment shader needs to be validated. */
 588     enum r300_fs_validity_status fs_status;
 589     /* Framebuffer multi-write. */
 590     boolean fb_multiwrite;
 591
 592     void *dsa_decompress_zmask;
 593
 594     struct pipe_index_buffer index_buffer;
 595     struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 596     unsigned nr_vertex_buffers;
 597     struct u_upload_mgr *uploader;
 598
 599     struct util_slab_mempool pool_transfers;
 600
 601     /* Stat counter. */
 602     uint64_t flush_counter;
 603
 604     /* const tracking for VS */
 605     int vs_const_base;
 606
 607     /* Vertex array state info */
 608     boolean vertex_arrays_dirty;
 609     boolean vertex_arrays_indexed;
 610     int vertex_arrays_offset;
 611     int vertex_arrays_instance_id;
 612     boolean instancing_enabled;
 613
 614     /* Hyper-Z stats. */
 615     boolean hyperz_enabled;     /* Whether it owns Hyper-Z access. */
 616     int64_t hyperz_time_of_last_flush; /* Time of the last flush with Z clear. */
 617     unsigned num_z_clears;      /* Since the last flush. */
 618
 619     /* ZMask state. */
 620     boolean zmask_in_use;       /* Whether ZMASK is enabled. */
 621     boolean zmask_decompress;   /* Whether ZMASK is being decompressed. */
 622     struct pipe_surface *locked_zbuffer; /* Unbound zbuffer which still has data in ZMASK. */
 623
 624     /* HiZ state. */
 625     boolean hiz_in_use;         /* Whether HIZ is enabled. */
 626     enum r300_hiz_func hiz_func; /* HiZ function. Can be either MIN or MAX. */
 627     uint32_t hiz_clear_value;   /* HiZ clear value. */
 628
 629     /* Compiler state. */
 630     struct rc_regalloc_state fs_regalloc_state; /* Register allocator info for
 631                                                  * fragment shaders. */
 632 };
 633
 634 #define foreach_atom(r300, atom) \
 635     for (atom = &r300->gpu_flush; atom != (&r300->query_start)+1; atom++)
 636
 637 #define foreach_dirty_atom(r300, atom) \
 638     for (atom = r300->first_dirty; atom != r300->last_dirty; atom++)
 639
 640 /* Convenience cast wrappers. */
 641 static INLINE struct r300_query* r300_query(struct pipe_query* q)
 642 {
 643     return (struct r300_query*)q;
 644 }
 645
 646 static INLINE struct r300_surface* r300_surface(struct pipe_surface* surf)
 647 {
 648     return (struct r300_surface*)surf;
 649 }
 650
 651 static INLINE struct r300_resource* r300_resource(struct pipe_resource* tex)
 652 {
 653     return (struct r300_resource*)tex;
 654 }
 655
 656 static INLINE struct r300_context* r300_context(struct pipe_context* context)
 657 {
 658     return (struct r300_context*)context;
 659 }
 660
 661 static INLINE struct r300_fragment_shader *r300_fs(struct r300_context *r300)
 662 {
 663     return (struct r300_fragment_shader*)r300->fs.state;
 664 }
 665
 666 static INLINE void r300_mark_atom_dirty(struct r300_context *r300,
 667                                         struct r300_atom *atom)
 668 {
 669     atom->dirty = TRUE;
 670
 671     if (!r300->first_dirty) {
 672         r300->first_dirty = atom;
 673         r300->last_dirty = atom+1;
 674     } else {
 675         if (atom < r300->first_dirty)
 676             r300->first_dirty = atom;
 677         else if (atom+1 > r300->last_dirty)
 678             r300->last_dirty = atom+1;
 679     }
 680 }
 681
 682 struct pipe_context* r300_create_context(struct pipe_screen* screen,
 683                                          void *priv);
 684
 685 /* Context initialization. */
 686 struct draw_stage* r300_draw_stage(struct r300_context* r300);
 687 void r300_init_blit_functions(struct r300_context *r300);
 688 void r300_init_flush_functions(struct r300_context* r300);
 689 void r300_init_query_functions(struct r300_context* r300);
 690 void r300_init_render_functions(struct r300_context *r300);
 691 void r300_init_state_functions(struct r300_context* r300);
 692 void r300_init_resource_functions(struct r300_context* r300);
 693
 694 /* r300_blit.c */
 695 void r300_decompress_zmask(struct r300_context *r300);
 696 void r300_decompress_zmask_locked_unsafe(struct r300_context *r300);
 697 void r300_decompress_zmask_locked(struct r300_context *r300);
 698 bool r300_is_blit_supported(enum pipe_format format);
 699
 700 /* r300_flush.c */
 701 void r300_flush(struct pipe_context *pipe,
 702                 unsigned flags,
 703                 struct pipe_fence_handle **fence);
 704
 705 /* r300_hyperz.c */
 706 void r300_update_hyperz_state(struct r300_context* r300);
 707
 708 /* r300_query.c */
 709 void r300_resume_query(struct r300_context *r300,
 710                        struct r300_query *query);
 711 void r300_stop_query(struct r300_context *r300);
 712
 713 /* r300_render_translate.c */
 714 void r300_translate_index_buffer(struct r300_context *r300,
 715                                  struct pipe_index_buffer *ib,
 716                                  struct pipe_resource **out_index_buffer,
 717                                  unsigned *index_size, unsigned index_offset,
 718                                  unsigned *start, unsigned count);
 719
 720 /* r300_render_stencilref.c */
 721 void r300_plug_in_stencil_ref_fallback(struct r300_context *r300);
 722
 723 /* r300_render.c */
 724 void r300_draw_flush_vbuf(struct r300_context *r300);
 725 void r500_emit_index_bias(struct r300_context *r300, int index_bias);
 726 void r300_blitter_draw_rectangle(struct blitter_context *blitter,
 727                                  int x1, int y1, int x2, int y2,
 728                                  float depth,
 729                                  enum blitter_attrib_type type,
 730                                  const union pipe_color_union *attrib);
 731
 732 /* r300_state.c */
 733 enum r300_fb_state_change {
 734     R300_CHANGED_FB_STATE = 0,
 735     R300_CHANGED_HYPERZ_FLAG,
 736     R300_CHANGED_MULTIWRITE
 737 };
 738
 739 void r300_mark_fb_state_dirty(struct r300_context *r300,
 740                               enum r300_fb_state_change change);
 741 void r300_mark_fs_code_dirty(struct r300_context *r300);
 742
 743 struct pipe_sampler_view *
 744 r300_create_sampler_view_custom(struct pipe_context *pipe,
 745                          struct pipe_resource *texture,
 746                          const struct pipe_sampler_view *templ,
 747                          unsigned width0_override,
 748                          unsigned height0_override);
 749
 750 /* r300_state_derived.c */
 751 void r300_update_derived_state(struct r300_context* r300);
 752
 753 /* r300_debug.c */
 754 void r500_dump_rs_block(struct r300_rs_block *rs);
 755
 756
 757 static INLINE boolean CTX_DBG_ON(struct r300_context * ctx, unsigned flags)
 758 {
 759     return SCREEN_DBG_ON(ctx->screen, flags);
 760 }
 761
 762 static INLINE void CTX_DBG(struct r300_context * ctx, unsigned flags,
 763                        const char * fmt, ...)
 764 {
 765     if (CTX_DBG_ON(ctx, flags)) {
 766         va_list va;
 767         va_start(va, fmt);
 768         vfprintf(stderr, fmt, va);
 769         va_end(va);
 770     }
 771 }
 772
 773 #define DBG_ON  CTX_DBG_ON
 774 #define DBG     CTX_DBG
 775
 776 #endif /* R300_CONTEXT_H */