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[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
29
30 #include "r300_context.h"
31 #include "r300_cs.h"
32 #include "r300_emit.h"
33 #include "r300_fs.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
36 #include "r300_vs.h"
37
38 void r300_emit_blend_state(struct r300_context* r300,
39 unsigned size, void* state)
40 {
41 struct r300_blend_state* blend = (struct r300_blend_state*)state;
42 struct pipe_framebuffer_state* fb =
43 (struct pipe_framebuffer_state*)r300->fb_state.state;
44 CS_LOCALS(r300);
45
46 BEGIN_CS(size);
47 OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop);
48 OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 3);
49 if (fb->nr_cbufs) {
50 OUT_CS(blend->blend_control);
51 OUT_CS(blend->alpha_blend_control);
52 OUT_CS(blend->color_channel_mask);
53 } else {
54 OUT_CS(0);
55 OUT_CS(0);
56 OUT_CS(0);
57 /* XXX also disable fastfill here once it's supported */
58 }
59 OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither);
60 END_CS;
61 }
62
63 void r300_emit_blend_color_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
67 CS_LOCALS(r300);
68
69 if (r300->screen->caps.is_r500) {
70 BEGIN_CS(size);
71 OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2);
72 OUT_CS(bc->blend_color_red_alpha);
73 OUT_CS(bc->blend_color_green_blue);
74 END_CS;
75 } else {
76 BEGIN_CS(size);
77 OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color);
78 END_CS;
79 }
80 }
81
82 void r300_emit_clip_state(struct r300_context* r300,
83 unsigned size, void* state)
84 {
85 struct pipe_clip_state* clip = (struct pipe_clip_state*)state;
86 int i;
87 CS_LOCALS(r300);
88
89 if (r300->screen->caps.has_tcl) {
90 BEGIN_CS(size);
91 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
92 (r300->screen->caps.is_r500 ?
93 R500_PVS_UCP_START : R300_PVS_UCP_START));
94 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
95 for (i = 0; i < 6; i++) {
96 OUT_CS_32F(clip->ucp[i][0]);
97 OUT_CS_32F(clip->ucp[i][1]);
98 OUT_CS_32F(clip->ucp[i][2]);
99 OUT_CS_32F(clip->ucp[i][3]);
100 }
101 OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
102 R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
103 END_CS;
104 } else {
105 BEGIN_CS(size);
106 OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
107 END_CS;
108 }
109
110 }
111
112 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
113 {
114 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
115 struct pipe_framebuffer_state* fb =
116 (struct pipe_framebuffer_state*)r300->fb_state.state;
117 struct pipe_stencil_ref stencil_ref = r300->stencil_ref;
118 CS_LOCALS(r300);
119
120 BEGIN_CS(size);
121 OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
122 OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
123
124 if (fb->zsbuf) {
125 OUT_CS(dsa->z_buffer_control);
126 OUT_CS(dsa->z_stencil_control);
127 } else {
128 OUT_CS(0);
129 OUT_CS(0);
130 }
131
132 OUT_CS(dsa->stencil_ref_mask | stencil_ref.ref_value[0]);
133
134 if (r300->screen->caps.is_r500) {
135 OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf | stencil_ref.ref_value[1]);
136 }
137 END_CS;
138 }
139
140 static const float * get_shader_constant(
141 struct r300_context * r300,
142 struct rc_constant * constant,
143 struct r300_constant_buffer * externals)
144 {
145 struct r300_viewport_state* viewport = r300->viewport_state.state;
146 struct r300_textures_state* texstate = r300->textures_state.state;
147 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
148 struct pipe_texture *tex;
149
150 switch(constant->Type) {
151 case RC_CONSTANT_EXTERNAL:
152 return externals->constants[constant->u.External];
153
154 case RC_CONSTANT_IMMEDIATE:
155 return constant->u.Immediate;
156
157 case RC_CONSTANT_STATE:
158 switch (constant->u.State[0]) {
159 /* Factor for converting rectangle coords to
160 * normalized coords. Should only show up on non-r500. */
161 case RC_STATE_R300_TEXRECT_FACTOR:
162 tex = texstate->fragment_sampler_views[constant->u.State[1]]->texture;
163 vec[0] = 1.0 / tex->width0;
164 vec[1] = 1.0 / tex->height0;
165 break;
166
167 /* Texture compare-fail value. Shouldn't ever show up, but if
168 * it does, we'll be ready. */
169 case RC_STATE_SHADOW_AMBIENT:
170 vec[3] = 0;
171 break;
172
173 case RC_STATE_R300_VIEWPORT_SCALE:
174 vec[0] = viewport->xscale;
175 vec[1] = viewport->yscale;
176 vec[2] = viewport->zscale;
177 break;
178
179 case RC_STATE_R300_VIEWPORT_OFFSET:
180 vec[0] = viewport->xoffset;
181 vec[1] = viewport->yoffset;
182 vec[2] = viewport->zoffset;
183 break;
184
185 default:
186 fprintf(stderr, "r300: Implementation error: "
187 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
188 }
189 break;
190
191 default:
192 fprintf(stderr, "r300: Implementation error: "
193 "Unhandled constant type %d\n", constant->Type);
194 }
195
196 /* This should either be (0, 0, 0, 1), which should be a relatively safe
197 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
198 * state factors. */
199 return vec;
200 }
201
202 /* Convert a normal single-precision float into the 7.16 format
203 * used by the R300 fragment shader.
204 */
205 static uint32_t pack_float24(float f)
206 {
207 union {
208 float fl;
209 uint32_t u;
210 } u;
211 float mantissa;
212 int exponent;
213 uint32_t float24 = 0;
214
215 if (f == 0.0)
216 return 0;
217
218 u.fl = f;
219
220 mantissa = frexpf(f, &exponent);
221
222 /* Handle -ve */
223 if (mantissa < 0) {
224 float24 |= (1 << 23);
225 mantissa = mantissa * -1.0;
226 }
227 /* Handle exponent, bias of 63 */
228 exponent += 62;
229 float24 |= (exponent << 16);
230 /* Kill 7 LSB of mantissa */
231 float24 |= (u.u & 0x7FFFFF) >> 7;
232
233 return float24;
234 }
235
236 void r300_emit_fragment_program_code(struct r300_context* r300,
237 struct rX00_fragment_program_code* generic_code)
238 {
239 struct r300_fragment_program_code * code = &generic_code->code.r300;
240 int i;
241 CS_LOCALS(r300);
242
243 BEGIN_CS(15 +
244 code->alu.length * 4 +
245 (code->tex.length ? (1 + code->tex.length) : 0));
246
247 OUT_CS_REG(R300_US_CONFIG, code->config);
248 OUT_CS_REG(R300_US_PIXSIZE, code->pixsize);
249 OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
250
251 OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
252 for(i = 0; i < 4; ++i)
253 OUT_CS(code->code_addr[i]);
254
255 OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
256 for (i = 0; i < code->alu.length; i++)
257 OUT_CS(code->alu.inst[i].rgb_inst);
258
259 OUT_CS_REG_SEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
260 for (i = 0; i < code->alu.length; i++)
261 OUT_CS(code->alu.inst[i].rgb_addr);
262
263 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
264 for (i = 0; i < code->alu.length; i++)
265 OUT_CS(code->alu.inst[i].alpha_inst);
266
267 OUT_CS_REG_SEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
268 for (i = 0; i < code->alu.length; i++)
269 OUT_CS(code->alu.inst[i].alpha_addr);
270
271 if (code->tex.length) {
272 OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
273 for(i = 0; i < code->tex.length; ++i)
274 OUT_CS(code->tex.inst[i]);
275 }
276
277 END_CS;
278 }
279
280 void r300_emit_fs_constant_buffer(struct r300_context* r300,
281 struct rc_constant_list* constants)
282 {
283 int i;
284 CS_LOCALS(r300);
285
286 if (constants->Count == 0)
287 return;
288
289 BEGIN_CS(constants->Count * 4 + 1);
290 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, constants->Count * 4);
291 for(i = 0; i < constants->Count; ++i) {
292 const float * data = get_shader_constant(r300,
293 &constants->Constants[i],
294 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
295 OUT_CS(pack_float24(data[0]));
296 OUT_CS(pack_float24(data[1]));
297 OUT_CS(pack_float24(data[2]));
298 OUT_CS(pack_float24(data[3]));
299 }
300 END_CS;
301 }
302
303 static void r300_emit_fragment_depth_config(struct r300_context* r300,
304 struct r300_fragment_shader* fs)
305 {
306 CS_LOCALS(r300);
307
308 BEGIN_CS(4);
309 if (r300_fragment_shader_writes_depth(fs)) {
310 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SHADER);
311 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W24 | R300_W_SRC_US);
312 } else {
313 OUT_CS_REG(R300_FG_DEPTH_SRC, R300_FG_DEPTH_SRC_SCAN);
314 OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0 | R300_W_SRC_US);
315 }
316 END_CS;
317 }
318
319 void r500_emit_fragment_program_code(struct r300_context* r300,
320 struct rX00_fragment_program_code* generic_code)
321 {
322 struct r500_fragment_program_code * code = &generic_code->code.r500;
323 int i;
324 CS_LOCALS(r300);
325
326 BEGIN_CS(13 +
327 ((code->inst_end + 1) * 6));
328 OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
329 OUT_CS_REG(R500_US_PIXSIZE, code->max_temp_idx);
330 OUT_CS_REG(R500_US_CODE_RANGE,
331 R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
332 OUT_CS_REG(R500_US_CODE_OFFSET, 0);
333 OUT_CS_REG(R500_US_CODE_ADDR,
334 R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(code->inst_end));
335
336 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
337 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, (code->inst_end + 1) * 6);
338 for (i = 0; i <= code->inst_end; i++) {
339 OUT_CS(code->inst[i].inst0);
340 OUT_CS(code->inst[i].inst1);
341 OUT_CS(code->inst[i].inst2);
342 OUT_CS(code->inst[i].inst3);
343 OUT_CS(code->inst[i].inst4);
344 OUT_CS(code->inst[i].inst5);
345 }
346
347 END_CS;
348 }
349
350 void r500_emit_fs_constant_buffer(struct r300_context* r300,
351 struct rc_constant_list* constants)
352 {
353 int i;
354 CS_LOCALS(r300);
355
356 if (constants->Count == 0)
357 return;
358
359 BEGIN_CS(constants->Count * 4 + 3);
360 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
361 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, constants->Count * 4);
362 for (i = 0; i < constants->Count; i++) {
363 const float * data = get_shader_constant(r300,
364 &constants->Constants[i],
365 &r300->shader_constants[PIPE_SHADER_FRAGMENT]);
366 OUT_CS_32F(data[0]);
367 OUT_CS_32F(data[1]);
368 OUT_CS_32F(data[2]);
369 OUT_CS_32F(data[3]);
370 }
371 END_CS;
372 }
373
374 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
375 {
376 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
377 struct r300_texture* tex;
378 struct pipe_surface* surf;
379 int i;
380 CS_LOCALS(r300);
381
382 BEGIN_CS(size);
383
384 /* Flush and free renderbuffer caches. */
385 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
386 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
387 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
388 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
389 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
390 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
391
392 /* Set the number of colorbuffers. */
393 if (fb->nr_cbufs > 1) {
394 if (r300->screen->caps.is_r500) {
395 OUT_CS_REG(R300_RB3D_CCTL,
396 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs) |
397 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
398 } else {
399 OUT_CS_REG(R300_RB3D_CCTL,
400 R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs));
401 }
402 } else {
403 OUT_CS_REG(R300_RB3D_CCTL, 0x0);
404 }
405
406 /* Set up colorbuffers. */
407 for (i = 0; i < fb->nr_cbufs; i++) {
408 surf = fb->cbufs[i];
409 tex = r300_texture(surf->texture);
410 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
411
412 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
413 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
414
415 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
416 OUT_CS_TEX_RELOC(tex, tex->fb_state.colorpitch[surf->level],
417 0, RADEON_GEM_DOMAIN_VRAM, 0);
418
419 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), tex->fb_state.us_out_fmt);
420 }
421 for (; i < 4; i++) {
422 OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
423 }
424
425 /* Set up a zbuffer. */
426 if (fb->zsbuf) {
427 surf = fb->zsbuf;
428 tex = r300_texture(surf->texture);
429 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
430
431 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
432 OUT_CS_TEX_RELOC(tex, surf->offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
433
434 OUT_CS_REG(R300_ZB_FORMAT, tex->fb_state.zb_format);
435
436 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
437 OUT_CS_TEX_RELOC(tex, tex->fb_state.depthpitch[surf->level],
438 0, RADEON_GEM_DOMAIN_VRAM, 0);
439 }
440
441 OUT_CS_REG(R300_GA_POINT_MINMAX,
442 (MAX2(fb->width, fb->height) * 6) << R300_GA_POINT_MINMAX_MAX_SHIFT);
443 END_CS;
444 }
445
446 void r300_emit_query_start(struct r300_context *r300)
447 {
448 struct r300_query *query = r300->query_current;
449 CS_LOCALS(r300);
450
451 if (!query)
452 return;
453
454 BEGIN_CS(4);
455 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
456 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
457 } else {
458 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
459 }
460 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
461 END_CS;
462 query->begin_emitted = TRUE;
463 }
464
465
466 static void r300_emit_query_finish(struct r300_context *r300,
467 struct r300_query *query)
468 {
469 struct r300_capabilities* caps = &r300->screen->caps;
470 CS_LOCALS(r300);
471
472 assert(caps->num_frag_pipes);
473
474 BEGIN_CS(6 * caps->num_frag_pipes + 2);
475 /* I'm not so sure I like this switch, but it's hard to be elegant
476 * when there's so many special cases...
477 *
478 * So here's the basic idea. For each pipe, enable writes to it only,
479 * then put out the relocation for ZPASS_ADDR, taking into account a
480 * 4-byte offset for each pipe. RV380 and older are special; they have
481 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
482 * so there's a chipset cap for that. */
483 switch (caps->num_frag_pipes) {
484 case 4:
485 /* pipe 3 only */
486 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
487 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
488 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 3),
489 0, RADEON_GEM_DOMAIN_GTT, 0);
490 case 3:
491 /* pipe 2 only */
492 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
493 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
494 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 2),
495 0, RADEON_GEM_DOMAIN_GTT, 0);
496 case 2:
497 /* pipe 1 only */
498 /* As mentioned above, accomodate RV380 and older. */
499 OUT_CS_REG(R300_SU_REG_DEST,
500 1 << (caps->high_second_pipe ? 3 : 1));
501 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
502 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 1),
503 0, RADEON_GEM_DOMAIN_GTT, 0);
504 case 1:
505 /* pipe 0 only */
506 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
507 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
508 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + (sizeof(uint32_t) * 0),
509 0, RADEON_GEM_DOMAIN_GTT, 0);
510 break;
511 default:
512 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
513 " pixel pipes!\n", caps->num_frag_pipes);
514 abort();
515 }
516
517 /* And, finally, reset it to normal... */
518 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
519 END_CS;
520 }
521
522 static void rv530_emit_query_single(struct r300_context *r300,
523 struct r300_query *query)
524 {
525 CS_LOCALS(r300);
526
527 BEGIN_CS(8);
528 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
529 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
530 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
531 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
532 END_CS;
533 }
534
535 static void rv530_emit_query_double(struct r300_context *r300,
536 struct r300_query *query)
537 {
538 CS_LOCALS(r300);
539
540 BEGIN_CS(14);
541 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
542 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
543 OUT_CS_BUF_RELOC(r300->oqbo, query->offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
544 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
545 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
546 OUT_CS_BUF_RELOC(r300->oqbo, query->offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
547 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
548 END_CS;
549 }
550
551 void r300_emit_query_end(struct r300_context* r300)
552 {
553 struct r300_capabilities *caps = &r300->screen->caps;
554 struct r300_query *query = r300->query_current;
555
556 if (!query)
557 return;
558
559 if (query->begin_emitted == FALSE)
560 return;
561
562 if (caps->family == CHIP_FAMILY_RV530) {
563 if (caps->num_z_pipes == 2)
564 rv530_emit_query_double(r300, query);
565 else
566 rv530_emit_query_single(r300, query);
567 } else
568 r300_emit_query_finish(r300, query);
569 }
570
571 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
572 {
573 struct r300_rs_state* rs = (struct r300_rs_state*)state;
574 float scale, offset;
575 CS_LOCALS(r300);
576
577 BEGIN_CS(size);
578 OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status);
579
580 OUT_CS_REG(R300_GB_AA_CONFIG, rs->antialiasing_config);
581
582 OUT_CS_REG(R300_GA_POINT_SIZE, rs->point_size);
583 OUT_CS_REG(R300_GA_LINE_CNTL, rs->line_control);
584
585 if (rs->polygon_offset_enable) {
586 scale = rs->depth_scale * 12;
587 offset = rs->depth_offset;
588
589 switch (r300->zbuffer_bpp) {
590 case 16:
591 offset *= 4;
592 break;
593 case 24:
594 offset *= 2;
595 break;
596 }
597
598 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
599 OUT_CS_32F(scale);
600 OUT_CS_32F(offset);
601 OUT_CS_32F(scale);
602 OUT_CS_32F(offset);
603 }
604
605 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2);
606 OUT_CS(rs->polygon_offset_enable);
607 OUT_CS(rs->cull_mode);
608 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config);
609 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value);
610 OUT_CS_REG(R300_GA_POLY_MODE, rs->polygon_mode);
611 END_CS;
612 }
613
614 void r300_emit_rs_block_state(struct r300_context* r300,
615 unsigned size, void* state)
616 {
617 struct r300_rs_block* rs = (struct r300_rs_block*)state;
618 unsigned i;
619 /* It's the same for both INST and IP tables */
620 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
621 CS_LOCALS(r300);
622
623 DBG(r300, DBG_DRAW, "r300: RS emit:\n");
624
625 BEGIN_CS(size);
626 if (r300->screen->caps.is_r500) {
627 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
628 } else {
629 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
630 }
631 for (i = 0; i < count; i++) {
632 OUT_CS(rs->ip[i]);
633 DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
634 }
635
636 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
637 OUT_CS(rs->count);
638 OUT_CS(rs->inst_count);
639
640 if (r300->screen->caps.is_r500) {
641 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
642 } else {
643 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
644 }
645 for (i = 0; i < count; i++) {
646 OUT_CS(rs->inst[i]);
647 DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
648 }
649
650 DBG(r300, DBG_DRAW, " : count: 0x%08x inst_count: 0x%08x\n",
651 rs->count, rs->inst_count);
652
653 END_CS;
654 }
655
656 void r300_emit_scissor_state(struct r300_context* r300,
657 unsigned size, void* state)
658 {
659 unsigned minx, miny, maxx, maxy;
660 uint32_t top_left, bottom_right;
661 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
662 struct pipe_framebuffer_state* fb =
663 (struct pipe_framebuffer_state*)r300->fb_state.state;
664 CS_LOCALS(r300);
665
666 minx = miny = 0;
667 maxx = fb->width;
668 maxy = fb->height;
669
670 if (r300->scissor_enabled) {
671 minx = MAX2(minx, scissor->minx);
672 miny = MAX2(miny, scissor->miny);
673 maxx = MIN2(maxx, scissor->maxx);
674 maxy = MIN2(maxy, scissor->maxy);
675 }
676
677 /* Special case for zero-area scissor.
678 *
679 * We can't allow the variables maxx and maxy to be zero because they are
680 * subtracted from later in the code, which would cause emitting ~0 and
681 * making the kernel checker angry.
682 *
683 * Let's consider we change maxx and maxy to 1, which is effectively
684 * a one-pixel area. We must then change minx and miny to a number which is
685 * greater than 1 to get the zero area back. */
686 if (!maxx || !maxy) {
687 minx = 2;
688 miny = 2;
689 maxx = 1;
690 maxy = 1;
691 }
692
693 if (r300->screen->caps.is_r500) {
694 top_left =
695 (minx << R300_SCISSORS_X_SHIFT) |
696 (miny << R300_SCISSORS_Y_SHIFT);
697 bottom_right =
698 ((maxx - 1) << R300_SCISSORS_X_SHIFT) |
699 ((maxy - 1) << R300_SCISSORS_Y_SHIFT);
700 } else {
701 /* Offset of 1440 in non-R500 chipsets. */
702 top_left =
703 ((minx + 1440) << R300_SCISSORS_X_SHIFT) |
704 ((miny + 1440) << R300_SCISSORS_Y_SHIFT);
705 bottom_right =
706 (((maxx - 1) + 1440) << R300_SCISSORS_X_SHIFT) |
707 (((maxy - 1) + 1440) << R300_SCISSORS_Y_SHIFT);
708 }
709
710 BEGIN_CS(size);
711 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
712 OUT_CS(top_left);
713 OUT_CS(bottom_right);
714 END_CS;
715 }
716
717 void r300_emit_textures_state(struct r300_context *r300,
718 unsigned size, void *state)
719 {
720 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
721 struct r300_texture_sampler_state *texstate;
722 unsigned i;
723 CS_LOCALS(r300);
724
725 BEGIN_CS(size);
726 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
727
728 for (i = 0; i < allstate->count; i++) {
729 if ((1 << i) & allstate->tx_enable) {
730 texstate = &allstate->regs[i];
731
732 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter[0]);
733 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter[1]);
734 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
735 texstate->border_color);
736
737 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format[0]);
738 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format[1]);
739 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format[2]);
740
741 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
742 OUT_CS_TEX_RELOC(r300_texture(allstate->fragment_sampler_views[i]->texture),
743 texstate->tile_config,
744 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
745 }
746 }
747 END_CS;
748 }
749
750 void r300_emit_aos(struct r300_context* r300, unsigned offset)
751 {
752 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
753 struct pipe_vertex_element *velem = r300->velems->velem;
754 int i;
755 unsigned size1, size2, aos_count = r300->velems->count;
756 unsigned packet_size = (aos_count * 3 + 1) / 2;
757 CS_LOCALS(r300);
758
759 BEGIN_CS(2 + packet_size + aos_count * 2);
760 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
761 OUT_CS(aos_count);
762
763 for (i = 0; i < aos_count - 1; i += 2) {
764 vb1 = &vbuf[velem[i].vertex_buffer_index];
765 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
766 size1 = util_format_get_blocksize(velem[i].src_format);
767 size2 = util_format_get_blocksize(velem[i+1].src_format);
768
769 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
770 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
771 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
772 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
773 }
774
775 if (aos_count & 1) {
776 vb1 = &vbuf[velem[i].vertex_buffer_index];
777 size1 = util_format_get_blocksize(velem[i].src_format);
778
779 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
780 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
781 }
782
783 for (i = 0; i < aos_count; i++) {
784 OUT_CS_BUF_RELOC_NO_OFFSET(vbuf[velem[i].vertex_buffer_index].buffer,
785 RADEON_GEM_DOMAIN_GTT, 0, 0);
786 }
787 END_CS;
788 }
789
790 void r300_emit_vertex_buffer(struct r300_context* r300)
791 {
792 CS_LOCALS(r300);
793
794 DBG(r300, DBG_DRAW, "r300: Preparing vertex buffer %p for render, "
795 "vertex size %d\n", r300->vbo,
796 r300->vertex_info.size);
797 /* Set the pointer to our vertex buffer. The emitted values are this:
798 * PACKET3 [3D_LOAD_VBPNTR]
799 * COUNT [1]
800 * FORMAT [size | stride << 8]
801 * OFFSET [offset into BO]
802 * VBPNTR [relocated BO]
803 */
804 BEGIN_CS(7);
805 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
806 OUT_CS(1);
807 OUT_CS(r300->vertex_info.size |
808 (r300->vertex_info.size << 8));
809 OUT_CS(r300->vbo_offset);
810 OUT_CS_BUF_RELOC(r300->vbo, 0, RADEON_GEM_DOMAIN_GTT, 0, 0);
811 END_CS;
812 }
813
814 void r300_emit_vertex_stream_state(struct r300_context* r300,
815 unsigned size, void* state)
816 {
817 struct r300_vertex_stream_state *streams =
818 (struct r300_vertex_stream_state*)state;
819 unsigned i;
820 CS_LOCALS(r300);
821
822 DBG(r300, DBG_DRAW, "r300: PSC emit:\n");
823
824 BEGIN_CS(size);
825 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
826 for (i = 0; i < streams->count; i++) {
827 OUT_CS(streams->vap_prog_stream_cntl[i]);
828 DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
829 streams->vap_prog_stream_cntl[i]);
830 }
831 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
832 for (i = 0; i < streams->count; i++) {
833 OUT_CS(streams->vap_prog_stream_cntl_ext[i]);
834 DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
835 streams->vap_prog_stream_cntl_ext[i]);
836 }
837 END_CS;
838 }
839
840 void r300_emit_vap_output_state(struct r300_context* r300,
841 unsigned size, void* state)
842 {
843 struct r300_vap_output_state *vap_out_state =
844 (struct r300_vap_output_state*)state;
845 CS_LOCALS(r300);
846
847 DBG(r300, DBG_DRAW, "r300: VAP emit:\n");
848
849 BEGIN_CS(size);
850 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
851 OUT_CS(vap_out_state->vap_vtx_state_cntl);
852 OUT_CS(vap_out_state->vap_vsm_vtx_assm);
853 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
854 OUT_CS(vap_out_state->vap_out_vtx_fmt[0]);
855 OUT_CS(vap_out_state->vap_out_vtx_fmt[1]);
856 END_CS;
857 }
858
859 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
860 {
861 CS_LOCALS(r300);
862
863 BEGIN_CS(size);
864 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
865 END_CS;
866 }
867
868 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
869 {
870 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
871 struct r300_vertex_program_code* code = &vs->code;
872 struct r300_screen* r300screen = r300->screen;
873 unsigned instruction_count = code->length / 4;
874 unsigned i;
875
876 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
877 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
878 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
879 unsigned temp_count = MAX2(code->num_temporaries, 1);
880
881 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
882 vtx_mem_size / output_count, 10);
883 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
884
885 CS_LOCALS(r300);
886
887 BEGIN_CS(size);
888 /* R300_VAP_PVS_CODE_CNTL_0
889 * R300_VAP_PVS_CONST_CNTL
890 * R300_VAP_PVS_CODE_CNTL_1
891 * See the r5xx docs for instructions on how to use these. */
892 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
893 OUT_CS(R300_PVS_FIRST_INST(0) |
894 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
895 R300_PVS_LAST_INST(instruction_count - 1));
896 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
897 OUT_CS(instruction_count - 1);
898
899 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
900 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
901 for (i = 0; i < code->length; i++) {
902 OUT_CS(code->body.d[i]);
903 }
904
905 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
906 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
907 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
908 R300_PVS_VF_MAX_VTX_NUM(12) |
909 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
910 END_CS;
911 }
912
913 void r300_emit_vs_constant_buffer(struct r300_context* r300,
914 struct rc_constant_list* constants)
915 {
916 unsigned i;
917 CS_LOCALS(r300);
918
919 BEGIN_CS(constants->Count * 4 + 3);
920 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
921 (r300->screen->caps.is_r500 ?
922 R500_PVS_CONST_START : R300_PVS_CONST_START));
923 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, constants->Count * 4);
924 for (i = 0; i < constants->Count; i++) {
925 const float *data = get_shader_constant(r300,
926 &constants->Constants[i],
927 &r300->shader_constants[PIPE_SHADER_VERTEX]);
928 OUT_CS_32F(data[0]);
929 OUT_CS_32F(data[1]);
930 OUT_CS_32F(data[2]);
931 OUT_CS_32F(data[3]);
932 }
933 END_CS;
934 }
935
936 void r300_emit_viewport_state(struct r300_context* r300,
937 unsigned size, void* state)
938 {
939 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
940 CS_LOCALS(r300);
941
942 BEGIN_CS(size);
943 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
944 OUT_CS_32F(viewport->xscale);
945 OUT_CS_32F(viewport->xoffset);
946 OUT_CS_32F(viewport->yscale);
947 OUT_CS_32F(viewport->yoffset);
948 OUT_CS_32F(viewport->zscale);
949 OUT_CS_32F(viewport->zoffset);
950 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
951 END_CS;
952 }
953
954 void r300_emit_ztop_state(struct r300_context* r300,
955 unsigned size, void* state)
956 {
957 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
958 CS_LOCALS(r300);
959
960 BEGIN_CS(size);
961 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
962 END_CS;
963 }
964
965 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
966 {
967 CS_LOCALS(r300);
968
969 BEGIN_CS(size);
970 OUT_CS_REG(R300_TX_INVALTAGS, 0);
971 END_CS;
972 }
973
974 void r300_emit_buffer_validate(struct r300_context *r300,
975 boolean do_validate_vertex_buffers,
976 struct pipe_buffer *index_buffer)
977 {
978 struct pipe_framebuffer_state* fb =
979 (struct pipe_framebuffer_state*)r300->fb_state.state;
980 struct r300_textures_state *texstate =
981 (struct r300_textures_state*)r300->textures_state.state;
982 struct r300_texture* tex;
983 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
984 struct pipe_vertex_element *velem = r300->velems->velem;
985 struct pipe_buffer *pbuf;
986 unsigned i;
987 boolean invalid = FALSE;
988
989 /* upload buffers first */
990 if (r300->any_user_vbs) {
991 r300_upload_user_buffers(r300);
992 r300->any_user_vbs = false;
993 }
994
995 /* Clean out BOs. */
996 r300->rws->reset_bos(r300->rws);
997
998 validate:
999 /* Color buffers... */
1000 for (i = 0; i < fb->nr_cbufs; i++) {
1001 tex = r300_texture(fb->cbufs[i]->texture);
1002 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1003 if (!r300_add_texture(r300->rws, tex,
1004 0, RADEON_GEM_DOMAIN_VRAM)) {
1005 r300->context.flush(&r300->context, 0, NULL);
1006 goto validate;
1007 }
1008 }
1009 /* ...depth buffer... */
1010 if (fb->zsbuf) {
1011 tex = r300_texture(fb->zsbuf->texture);
1012 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1013 if (!r300_add_texture(r300->rws, tex,
1014 0, RADEON_GEM_DOMAIN_VRAM)) {
1015 r300->context.flush(&r300->context, 0, NULL);
1016 goto validate;
1017 }
1018 }
1019 /* ...textures... */
1020 for (i = 0; i < texstate->count; i++) {
1021 if (!(texstate->tx_enable & (1 << i))) {
1022 continue;
1023 }
1024
1025 tex = r300_texture(texstate->fragment_sampler_views[i]->texture);
1026 if (!r300_add_texture(r300->rws, tex,
1027 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
1028 r300->context.flush(&r300->context, 0, NULL);
1029 goto validate;
1030 }
1031 }
1032 /* ...occlusion query buffer... */
1033 if (r300->dirty_state & R300_NEW_QUERY) {
1034 if (!r300_add_buffer(r300->rws, r300->oqbo,
1035 0, RADEON_GEM_DOMAIN_GTT)) {
1036 r300->context.flush(&r300->context, 0, NULL);
1037 goto validate;
1038 }
1039 }
1040 /* ...vertex buffer for SWTCL path... */
1041 if (r300->vbo) {
1042 if (!r300_add_buffer(r300->rws, r300->vbo,
1043 RADEON_GEM_DOMAIN_GTT, 0)) {
1044 r300->context.flush(&r300->context, 0, NULL);
1045 goto validate;
1046 }
1047 }
1048 /* ...vertex buffers for HWTCL path... */
1049 if (do_validate_vertex_buffers) {
1050 for (i = 0; i < r300->velems->count; i++) {
1051 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1052
1053 if (!r300_add_buffer(r300->rws, pbuf,
1054 RADEON_GEM_DOMAIN_GTT, 0)) {
1055 r300->context.flush(&r300->context, 0, NULL);
1056 goto validate;
1057 }
1058 }
1059 }
1060 /* ...and index buffer for HWTCL path. */
1061 if (index_buffer) {
1062 if (!r300_add_buffer(r300->rws, index_buffer,
1063 RADEON_GEM_DOMAIN_GTT, 0)) {
1064 r300->context.flush(&r300->context, 0, NULL);
1065 goto validate;
1066 }
1067 }
1068 if (!r300->rws->validate(r300->rws)) {
1069 r300->context.flush(&r300->context, 0, NULL);
1070 if (invalid) {
1071 /* Well, hell. */
1072 fprintf(stderr, "r300: Stuck in validation loop, gonna quit now.\n");
1073 abort();
1074 }
1075 invalid = TRUE;
1076 goto validate;
1077 }
1078 }
1079
1080 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1081 {
1082 struct r300_atom* atom;
1083 unsigned dwords = 0;
1084
1085 foreach(atom, &r300->atom_list) {
1086 if (atom->dirty || atom->always_dirty) {
1087 dwords += atom->size;
1088 }
1089 }
1090
1091 /* XXX This is the compensation for the non-atomized states. */
1092 dwords += 1024;
1093
1094 return dwords;
1095 }
1096
1097 /* Emit all dirty state. */
1098 void r300_emit_dirty_state(struct r300_context* r300)
1099 {
1100 struct r300_screen* r300screen = r300->screen;
1101 struct r300_atom* atom;
1102
1103 if (r300->dirty_state & R300_NEW_QUERY) {
1104 r300_emit_query_start(r300);
1105 r300->dirty_state &= ~R300_NEW_QUERY;
1106 }
1107
1108 foreach(atom, &r300->atom_list) {
1109 if (atom->dirty || atom->always_dirty) {
1110 atom->emit(r300, atom->size, atom->state);
1111 atom->dirty = FALSE;
1112 }
1113 }
1114
1115 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER) {
1116 r300_emit_fragment_depth_config(r300, r300->fs);
1117 if (r300screen->caps.is_r500) {
1118 r500_emit_fragment_program_code(r300, &r300->fs->shader->code);
1119 } else {
1120 r300_emit_fragment_program_code(r300, &r300->fs->shader->code);
1121 }
1122 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER;
1123 }
1124
1125 if (r300->dirty_state & R300_NEW_FRAGMENT_SHADER_CONSTANTS) {
1126 if (r300screen->caps.is_r500) {
1127 r500_emit_fs_constant_buffer(r300,
1128 &r300->fs->shader->code.constants);
1129 } else {
1130 r300_emit_fs_constant_buffer(r300,
1131 &r300->fs->shader->code.constants);
1132 }
1133 r300->dirty_state &= ~R300_NEW_FRAGMENT_SHADER_CONSTANTS;
1134 }
1135
1136 if (r300->dirty_state & R300_NEW_VERTEX_SHADER_CONSTANTS) {
1137 struct r300_vertex_shader* vs = r300->vs_state.state;
1138 if (vs->code.constants.Count) {
1139 r300_emit_vs_constant_buffer(r300, &vs->code.constants);
1140 }
1141 r300->dirty_state &= ~R300_NEW_VERTEX_SHADER_CONSTANTS;
1142 }
1143
1144 /* XXX
1145 assert(r300->dirty_state == 0);
1146 */
1147
1148 /* Emit the VBO for SWTCL. */
1149 if (!r300screen->caps.has_tcl) {
1150 r300_emit_vertex_buffer(r300);
1151 }
1152
1153 r300->dirty_hw++;
1154 }