2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 /* r300_emit: Functions for emitting state. */
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_simple_list.h"
30 #include "r300_context.h"
32 #include "r300_emit.h"
34 #include "r300_screen.h"
35 #include "r300_screen_buffer.h"
38 void r300_emit_blend_state(struct r300_context
* r300
,
39 unsigned size
, void* state
)
41 struct r300_blend_state
* blend
= (struct r300_blend_state
*)state
;
42 struct pipe_framebuffer_state
* fb
=
43 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
47 WRITE_CS_TABLE(blend
->cb
, size
);
49 WRITE_CS_TABLE(blend
->cb_no_readwrite
, size
);
53 void r300_emit_blend_color_state(struct r300_context
* r300
,
54 unsigned size
, void* state
)
56 struct r300_blend_color_state
* bc
= (struct r300_blend_color_state
*)state
;
59 WRITE_CS_TABLE(bc
->cb
, size
);
62 void r300_emit_clip_state(struct r300_context
* r300
,
63 unsigned size
, void* state
)
65 struct r300_clip_state
* clip
= (struct r300_clip_state
*)state
;
68 WRITE_CS_TABLE(clip
->cb
, size
);
71 void r300_emit_dsa_state(struct r300_context
* r300
, unsigned size
, void* state
)
73 struct r300_dsa_state
* dsa
= (struct r300_dsa_state
*)state
;
74 struct pipe_framebuffer_state
* fb
=
75 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
79 WRITE_CS_TABLE(&dsa
->cb_begin
, size
);
81 WRITE_CS_TABLE(dsa
->cb_no_readwrite
, size
);
85 static const float * get_rc_constant_state(
86 struct r300_context
* r300
,
87 struct rc_constant
* constant
)
89 struct r300_textures_state
* texstate
= r300
->textures_state
.state
;
90 static float vec
[4] = { 0.0, 0.0, 0.0, 1.0 };
91 struct pipe_resource
*tex
;
93 assert(constant
->Type
== RC_CONSTANT_STATE
);
95 switch (constant
->u
.State
[0]) {
96 /* Factor for converting rectangle coords to
97 * normalized coords. Should only show up on non-r500. */
98 case RC_STATE_R300_TEXRECT_FACTOR
:
99 tex
= texstate
->sampler_views
[constant
->u
.State
[1]]->base
.texture
;
100 vec
[0] = 1.0 / tex
->width0
;
101 vec
[1] = 1.0 / tex
->height0
;
104 case RC_STATE_R300_VIEWPORT_SCALE
:
105 vec
[0] = r300
->viewport
.scale
[0];
106 vec
[1] = r300
->viewport
.scale
[1];
107 vec
[2] = r300
->viewport
.scale
[2];
110 case RC_STATE_R300_VIEWPORT_OFFSET
:
111 vec
[0] = r300
->viewport
.translate
[0];
112 vec
[1] = r300
->viewport
.translate
[1];
113 vec
[2] = r300
->viewport
.translate
[2];
117 fprintf(stderr
, "r300: Implementation error: "
118 "Unknown RC_CONSTANT type %d\n", constant
->u
.State
[0]);
121 /* This should either be (0, 0, 0, 1), which should be a relatively safe
122 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
127 /* Convert a normal single-precision float into the 7.16 format
128 * used by the R300 fragment shader.
130 uint32_t pack_float24(float f
)
138 uint32_t float24
= 0;
145 mantissa
= frexpf(f
, &exponent
);
149 float24
|= (1 << 23);
150 mantissa
= mantissa
* -1.0;
152 /* Handle exponent, bias of 63 */
154 float24
|= (exponent
<< 16);
155 /* Kill 7 LSB of mantissa */
156 float24
|= (u
.u
& 0x7FFFFF) >> 7;
161 void r300_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
163 struct r300_fragment_shader
*fs
= r300_fs(r300
);
166 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
169 void r300_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
171 struct r300_fragment_shader
*fs
= r300_fs(r300
);
172 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
173 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
174 unsigned i
, count
= fs
->shader
->externals_count
;
181 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
, count
* 4);
182 for(i
= 0; i
< count
; ++i
) {
184 assert(constants
->Constants
[i
].Type
== RC_CONSTANT_EXTERNAL
);
185 data
= buf
->constants
[i
];
186 OUT_CS(pack_float24(data
[0]));
187 OUT_CS(pack_float24(data
[1]));
188 OUT_CS(pack_float24(data
[2]));
189 OUT_CS(pack_float24(data
[3]));
194 void r300_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
196 struct r300_fragment_shader
*fs
= r300_fs(r300
);
197 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
199 unsigned count
= fs
->shader
->rc_state_count
;
200 unsigned first
= fs
->shader
->externals_count
;
201 unsigned end
= constants
->Count
;
208 for(i
= first
; i
< end
; ++i
) {
209 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
211 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
213 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X
+ i
* 16, 4);
214 OUT_CS(pack_float24(data
[0]));
215 OUT_CS(pack_float24(data
[1]));
216 OUT_CS(pack_float24(data
[2]));
217 OUT_CS(pack_float24(data
[3]));
223 void r500_emit_fs(struct r300_context
* r300
, unsigned size
, void *state
)
225 struct r300_fragment_shader
*fs
= r300_fs(r300
);
228 WRITE_CS_TABLE(fs
->shader
->cb_code
, fs
->shader
->cb_code_size
);
231 void r500_emit_fs_constants(struct r300_context
* r300
, unsigned size
, void *state
)
233 struct r300_fragment_shader
*fs
= r300_fs(r300
);
234 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
235 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
236 unsigned i
, count
= fs
->shader
->externals_count
;
243 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
, R500_GA_US_VECTOR_INDEX_TYPE_CONST
);
244 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, count
* 4);
245 for(i
= 0; i
< count
; ++i
) {
246 assert(constants
->Constants
[i
].Type
== RC_CONSTANT_EXTERNAL
);
248 OUT_CS_TABLE(buf
->constants
, count
* 4);
252 void r500_emit_fs_rc_constant_state(struct r300_context
* r300
, unsigned size
, void *state
)
254 struct r300_fragment_shader
*fs
= r300_fs(r300
);
255 struct rc_constant_list
*constants
= &fs
->shader
->code
.constants
;
257 unsigned count
= fs
->shader
->rc_state_count
;
258 unsigned first
= fs
->shader
->externals_count
;
259 unsigned end
= constants
->Count
;
266 for(i
= first
; i
< end
; ++i
) {
267 if (constants
->Constants
[i
].Type
== RC_CONSTANT_STATE
) {
269 get_rc_constant_state(r300
, &constants
->Constants
[i
]);
271 OUT_CS_REG(R500_GA_US_VECTOR_INDEX
,
272 R500_GA_US_VECTOR_INDEX_TYPE_CONST
|
273 (i
& R500_GA_US_VECTOR_INDEX_MASK
));
274 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA
, 4);
275 OUT_CS_TABLE(data
, 4);
281 void r300_emit_fb_state(struct r300_context
* r300
, unsigned size
, void* state
)
283 struct pipe_framebuffer_state
* fb
= (struct pipe_framebuffer_state
*)state
;
284 struct r300_texture
* tex
;
285 struct pipe_surface
* surf
;
291 /* Flush and free renderbuffer caches. */
292 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT
,
293 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
294 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
295 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT
,
296 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
297 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);
299 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
300 * what we usually want. */
301 if (r300
->screen
->caps
.is_r500
) {
302 OUT_CS_REG(R300_RB3D_CCTL
,
303 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE
);
305 OUT_CS_REG(R300_RB3D_CCTL
, 0);
308 /* Set up colorbuffers. */
309 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
311 tex
= r300_texture(surf
->texture
);
312 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
314 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0
+ (4 * i
), 1);
315 OUT_CS_TEX_RELOC(tex
, surf
->offset
, 0, tex
->domain
, 0);
317 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0
+ (4 * i
), 1);
318 OUT_CS_TEX_RELOC(tex
, tex
->fb_state
.colorpitch
[surf
->level
],
321 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), tex
->fb_state
.us_out_fmt
);
324 OUT_CS_REG(R300_US_OUT_FMT_0
+ (4 * i
), R300_US_OUT_FMT_UNUSED
);
327 /* Set up a zbuffer. */
330 tex
= r300_texture(surf
->texture
);
331 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
333 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET
, 1);
334 OUT_CS_TEX_RELOC(tex
, surf
->offset
, 0, tex
->domain
, 0);
336 OUT_CS_REG(R300_ZB_FORMAT
, tex
->fb_state
.zb_format
);
338 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH
, 1);
339 OUT_CS_TEX_RELOC(tex
, tex
->fb_state
.depthpitch
[surf
->level
],
343 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL
, 2);
344 if (r300
->screen
->caps
.is_r500
) {
346 OUT_CS(((fb
->width
- 1) << R300_SCISSORS_X_SHIFT
) |
347 ((fb
->height
- 1) << R300_SCISSORS_Y_SHIFT
));
349 OUT_CS((1440 << R300_SCISSORS_X_SHIFT
) |
350 (1440 << R300_SCISSORS_Y_SHIFT
));
351 OUT_CS(((fb
->width
+ 1440-1) << R300_SCISSORS_X_SHIFT
) |
352 ((fb
->height
+ 1440-1) << R300_SCISSORS_Y_SHIFT
));
357 void r300_emit_query_start(struct r300_context
*r300
, unsigned size
, void*state
)
359 struct r300_query
*query
= r300
->query_current
;
366 if (r300
->screen
->caps
.family
== CHIP_FAMILY_RV530
) {
367 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
369 OUT_CS_REG(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
371 OUT_CS_REG(R300_ZB_ZPASS_DATA
, 0);
373 query
->begin_emitted
= TRUE
;
377 static void r300_emit_query_end_frag_pipes(struct r300_context
*r300
,
378 struct r300_query
*query
)
380 struct r300_capabilities
* caps
= &r300
->screen
->caps
;
383 assert(caps
->num_frag_pipes
);
385 BEGIN_CS(6 * caps
->num_frag_pipes
+ 2);
386 /* I'm not so sure I like this switch, but it's hard to be elegant
387 * when there's so many special cases...
389 * So here's the basic idea. For each pipe, enable writes to it only,
390 * then put out the relocation for ZPASS_ADDR, taking into account a
391 * 4-byte offset for each pipe. RV380 and older are special; they have
392 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
393 * so there's a chipset cap for that. */
394 switch (caps
->num_frag_pipes
) {
397 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 3);
398 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
399 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 3),
400 0, r300_buffer(r300
->oqbo
)->domain
, 0);
403 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 2);
404 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
405 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 2),
406 0, r300_buffer(r300
->oqbo
)->domain
, 0);
409 /* As mentioned above, accomodate RV380 and older. */
410 OUT_CS_REG(R300_SU_REG_DEST
,
411 1 << (caps
->high_second_pipe
? 3 : 1));
412 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
413 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 1),
414 0, r300_buffer(r300
->oqbo
)->domain
, 0);
417 OUT_CS_REG(R300_SU_REG_DEST
, 1 << 0);
418 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
419 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ (sizeof(uint32_t) * 0),
420 0, r300_buffer(r300
->oqbo
)->domain
, 0);
423 fprintf(stderr
, "r300: Implementation error: Chipset reports %d"
424 " pixel pipes!\n", caps
->num_frag_pipes
);
428 /* And, finally, reset it to normal... */
429 OUT_CS_REG(R300_SU_REG_DEST
, 0xF);
433 static void rv530_emit_query_end_single_z(struct r300_context
*r300
,
434 struct r300_query
*query
)
439 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
440 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
441 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
, 0, r300_buffer(r300
->oqbo
)->domain
, 0);
442 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
446 static void rv530_emit_query_end_double_z(struct r300_context
*r300
,
447 struct r300_query
*query
)
452 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
453 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
454 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
, 0, r300_buffer(r300
->oqbo
)->domain
, 0);
455 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
456 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR
, 1);
457 OUT_CS_BUF_RELOC(r300
->oqbo
, query
->offset
+ sizeof(uint32_t), 0, r300_buffer(r300
->oqbo
)->domain
, 0);
458 OUT_CS_REG(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
462 void r300_emit_query_end(struct r300_context
* r300
)
464 struct r300_capabilities
*caps
= &r300
->screen
->caps
;
465 struct r300_query
*query
= r300
->query_current
;
470 if (query
->begin_emitted
== FALSE
)
473 if (caps
->family
== CHIP_FAMILY_RV530
) {
474 if (caps
->num_z_pipes
== 2)
475 rv530_emit_query_end_double_z(r300
, query
);
477 rv530_emit_query_end_single_z(r300
, query
);
479 r300_emit_query_end_frag_pipes(r300
, query
);
481 query
->begin_emitted
= FALSE
;
484 void r300_emit_rs_state(struct r300_context
* r300
, unsigned size
, void* state
)
486 struct r300_rs_state
* rs
= (struct r300_rs_state
*)state
;
491 OUT_CS_REG(R300_VAP_CNTL_STATUS
, rs
->vap_control_status
);
493 OUT_CS_REG(R300_GB_AA_CONFIG
, rs
->antialiasing_config
);
495 OUT_CS_REG(R300_GA_POINT_SIZE
, rs
->point_size
);
496 OUT_CS_REG_SEQ(R300_GA_POINT_MINMAX
, 2);
497 OUT_CS(rs
->point_minmax
);
498 OUT_CS(rs
->line_control
);
500 if (rs
->polygon_offset_enable
) {
501 scale
= rs
->depth_scale
* 12;
502 offset
= rs
->depth_offset
;
504 switch (r300
->zbuffer_bpp
) {
513 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
520 OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE
, 2);
521 OUT_CS(rs
->polygon_offset_enable
);
522 OUT_CS(rs
->cull_mode
);
523 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG
, rs
->line_stipple_config
);
524 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE
, rs
->line_stipple_value
);
525 OUT_CS_REG(R300_GA_POLY_MODE
, rs
->polygon_mode
);
526 OUT_CS_REG(R300_SC_CLIP_RULE
, rs
->clip_rule
);
527 OUT_CS_REG(R300_GB_ENABLE
, rs
->stuffing_enable
);
528 OUT_CS_REG_SEQ(R300_GA_POINT_S0
, 4);
529 OUT_CS_32F(rs
->point_texcoord_left
);
530 OUT_CS_32F(rs
->point_texcoord_bottom
);
531 OUT_CS_32F(rs
->point_texcoord_right
);
532 OUT_CS_32F(rs
->point_texcoord_top
);
536 void r300_emit_rs_block_state(struct r300_context
* r300
,
537 unsigned size
, void* state
)
539 struct r300_rs_block
* rs
= (struct r300_rs_block
*)state
;
541 /* It's the same for both INST and IP tables */
542 unsigned count
= (rs
->inst_count
& R300_RS_INST_COUNT_MASK
) + 1;
545 if (SCREEN_DBG_ON(r300
->screen
, DBG_DRAW
)) {
546 r500_dump_rs_block(rs
);
549 DBG(r300
, DBG_DRAW
, "r300: RS emit:\n");
552 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL
, 2);
553 OUT_CS(rs
->vap_vtx_state_cntl
);
554 OUT_CS(rs
->vap_vsm_vtx_assm
);
555 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0
, 2);
556 OUT_CS(rs
->vap_out_vtx_fmt
[0]);
557 OUT_CS(rs
->vap_out_vtx_fmt
[1]);
559 if (r300
->screen
->caps
.is_r500
) {
560 OUT_CS_REG_SEQ(R500_RS_IP_0
, count
);
562 OUT_CS_REG_SEQ(R300_RS_IP_0
, count
);
564 OUT_CS_TABLE(rs
->ip
, count
);
565 for (i
= 0; i
< count
; i
++) {
566 DBG(r300
, DBG_DRAW
, " : ip %d: 0x%08x\n", i
, rs
->ip
[i
]);
569 OUT_CS_REG_SEQ(R300_RS_COUNT
, 2);
571 OUT_CS(rs
->inst_count
);
573 if (r300
->screen
->caps
.is_r500
) {
574 OUT_CS_REG_SEQ(R500_RS_INST_0
, count
);
576 OUT_CS_REG_SEQ(R300_RS_INST_0
, count
);
578 OUT_CS_TABLE(rs
->inst
, count
);
579 for (i
= 0; i
< count
; i
++) {
580 DBG(r300
, DBG_DRAW
, " : inst %d: 0x%08x\n", i
, rs
->inst
[i
]);
583 DBG(r300
, DBG_DRAW
, " : count: 0x%08x inst_count: 0x%08x\n",
584 rs
->count
, rs
->inst_count
);
589 void r300_emit_scissor_state(struct r300_context
* r300
,
590 unsigned size
, void* state
)
592 struct pipe_scissor_state
* scissor
= (struct pipe_scissor_state
*)state
;
596 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0
, 2);
597 if (r300
->screen
->caps
.is_r500
) {
598 OUT_CS((scissor
->minx
<< R300_CLIPRECT_X_SHIFT
) |
599 (scissor
->miny
<< R300_CLIPRECT_Y_SHIFT
));
600 OUT_CS(((scissor
->maxx
- 1) << R300_CLIPRECT_X_SHIFT
) |
601 ((scissor
->maxy
- 1) << R300_CLIPRECT_Y_SHIFT
));
603 OUT_CS(((scissor
->minx
+ 1440) << R300_CLIPRECT_X_SHIFT
) |
604 ((scissor
->miny
+ 1440) << R300_CLIPRECT_Y_SHIFT
));
605 OUT_CS(((scissor
->maxx
+ 1440-1) << R300_CLIPRECT_X_SHIFT
) |
606 ((scissor
->maxy
+ 1440-1) << R300_CLIPRECT_Y_SHIFT
));
611 void r300_emit_textures_state(struct r300_context
*r300
,
612 unsigned size
, void *state
)
614 struct r300_textures_state
*allstate
= (struct r300_textures_state
*)state
;
615 struct r300_texture_sampler_state
*texstate
;
616 struct r300_texture
*tex
;
621 OUT_CS_REG(R300_TX_ENABLE
, allstate
->tx_enable
);
623 for (i
= 0; i
< allstate
->count
; i
++) {
624 if ((1 << i
) & allstate
->tx_enable
) {
625 texstate
= &allstate
->regs
[i
];
626 tex
= r300_texture(allstate
->sampler_views
[i
]->base
.texture
);
628 OUT_CS_REG(R300_TX_FILTER0_0
+ (i
* 4), texstate
->filter0
);
629 OUT_CS_REG(R300_TX_FILTER1_0
+ (i
* 4), texstate
->filter1
);
630 OUT_CS_REG(R300_TX_BORDER_COLOR_0
+ (i
* 4),
631 texstate
->border_color
);
633 OUT_CS_REG(R300_TX_FORMAT0_0
+ (i
* 4), texstate
->format
.format0
);
634 OUT_CS_REG(R300_TX_FORMAT1_0
+ (i
* 4), texstate
->format
.format1
);
635 OUT_CS_REG(R300_TX_FORMAT2_0
+ (i
* 4), texstate
->format
.format2
);
637 OUT_CS_REG_SEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
638 OUT_CS_TEX_RELOC(tex
, texstate
->format
.tile_config
, tex
->domain
,
645 void r300_emit_aos(struct r300_context
* r300
, int offset
, boolean indexed
)
647 struct pipe_vertex_buffer
*vb1
, *vb2
, *vbuf
= r300
->vertex_buffer
;
648 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
649 struct r300_buffer
*buf
;
651 unsigned *hw_format_size
= r300
->velems
->hw_format_size
;
652 unsigned size1
, size2
, aos_count
= r300
->velems
->count
;
653 unsigned packet_size
= (aos_count
* 3 + 1) / 2;
656 BEGIN_CS(2 + packet_size
+ aos_count
* 2);
657 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, packet_size
);
658 OUT_CS(aos_count
| (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
660 for (i
= 0; i
< aos_count
- 1; i
+= 2) {
661 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
662 vb2
= &vbuf
[velem
[i
+1].vertex_buffer_index
];
663 size1
= hw_format_size
[i
];
664 size2
= hw_format_size
[i
+1];
666 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
) |
667 R300_VBPNTR_SIZE1(size2
) | R300_VBPNTR_STRIDE1(vb2
->stride
));
668 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
669 OUT_CS(vb2
->buffer_offset
+ velem
[i
+1].src_offset
+ offset
* vb2
->stride
);
673 vb1
= &vbuf
[velem
[i
].vertex_buffer_index
];
674 size1
= hw_format_size
[i
];
676 OUT_CS(R300_VBPNTR_SIZE0(size1
) | R300_VBPNTR_STRIDE0(vb1
->stride
));
677 OUT_CS(vb1
->buffer_offset
+ velem
[i
].src_offset
+ offset
* vb1
->stride
);
680 for (i
= 0; i
< aos_count
; i
++) {
681 buf
= r300_buffer(vbuf
[velem
[i
].vertex_buffer_index
].buffer
);
682 OUT_CS_BUF_RELOC_NO_OFFSET(&buf
->b
.b
, buf
->domain
, 0, 0);
687 void r300_emit_aos_swtcl(struct r300_context
*r300
, boolean indexed
)
691 DBG(r300
, DBG_DRAW
, "r300: Preparing vertex buffer %p for render, "
692 "vertex size %d\n", r300
->vbo
,
693 r300
->vertex_info
.size
);
694 /* Set the pointer to our vertex buffer. The emitted values are this:
695 * PACKET3 [3D_LOAD_VBPNTR]
697 * FORMAT [size | stride << 8]
698 * OFFSET [offset into BO]
699 * VBPNTR [relocated BO]
702 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR
, 3);
703 OUT_CS(1 | (!indexed
? R300_VC_FORCE_PREFETCH
: 0));
704 OUT_CS(r300
->vertex_info
.size
|
705 (r300
->vertex_info
.size
<< 8));
706 OUT_CS(r300
->vbo_offset
);
707 OUT_CS_BUF_RELOC(r300
->vbo
, 0, r300_buffer(r300
->vbo
)->domain
, 0, 0);
711 void r300_emit_vertex_stream_state(struct r300_context
* r300
,
712 unsigned size
, void* state
)
714 struct r300_vertex_stream_state
*streams
=
715 (struct r300_vertex_stream_state
*)state
;
719 DBG(r300
, DBG_DRAW
, "r300: PSC emit:\n");
722 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0
, streams
->count
);
723 OUT_CS_TABLE(streams
->vap_prog_stream_cntl
, streams
->count
);
724 for (i
= 0; i
< streams
->count
; i
++) {
725 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl%d: 0x%08x\n", i
,
726 streams
->vap_prog_stream_cntl
[i
]);
728 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0
, streams
->count
);
729 OUT_CS_TABLE(streams
->vap_prog_stream_cntl_ext
, streams
->count
);
730 for (i
= 0; i
< streams
->count
; i
++) {
731 DBG(r300
, DBG_DRAW
, " : prog_stream_cntl_ext%d: 0x%08x\n", i
,
732 streams
->vap_prog_stream_cntl_ext
[i
]);
737 void r300_emit_pvs_flush(struct r300_context
* r300
, unsigned size
, void* state
)
742 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG
, 0x0);
746 void r300_emit_vs_state(struct r300_context
* r300
, unsigned size
, void* state
)
748 struct r300_vertex_shader
* vs
= (struct r300_vertex_shader
*)state
;
749 struct r300_vertex_program_code
* code
= &vs
->code
;
750 struct r300_screen
* r300screen
= r300
->screen
;
751 unsigned instruction_count
= code
->length
/ 4;
754 unsigned vtx_mem_size
= r300screen
->caps
.is_r500
? 128 : 72;
755 unsigned input_count
= MAX2(util_bitcount(code
->InputsRead
), 1);
756 unsigned output_count
= MAX2(util_bitcount(code
->OutputsWritten
), 1);
757 unsigned temp_count
= MAX2(code
->num_temporaries
, 1);
759 unsigned pvs_num_slots
= MIN3(vtx_mem_size
/ input_count
,
760 vtx_mem_size
/ output_count
, 10);
761 unsigned pvs_num_controllers
= MIN2(vtx_mem_size
/ temp_count
, 6);
763 unsigned imm_first
= vs
->externals_count
;
764 unsigned imm_end
= vs
->code
.constants
.Count
;
765 unsigned imm_count
= vs
->immediates_count
;
770 /* R300_VAP_PVS_CODE_CNTL_0
771 * R300_VAP_PVS_CONST_CNTL
772 * R300_VAP_PVS_CODE_CNTL_1
773 * See the r5xx docs for instructions on how to use these. */
774 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0
, 3);
775 OUT_CS(R300_PVS_FIRST_INST(0) |
776 R300_PVS_XYZW_VALID_INST(instruction_count
- 1) |
777 R300_PVS_LAST_INST(instruction_count
- 1));
778 OUT_CS(R300_PVS_MAX_CONST_ADDR(code
->constants
.Count
- 1));
779 OUT_CS(instruction_count
- 1);
781 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
, 0);
782 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, code
->length
);
783 OUT_CS_TABLE(code
->body
.d
, code
->length
);
785 OUT_CS_REG(R300_VAP_CNTL
, R300_PVS_NUM_SLOTS(pvs_num_slots
) |
786 R300_PVS_NUM_CNTLRS(pvs_num_controllers
) |
787 R300_PVS_NUM_FPUS(r300screen
->caps
.num_vert_fpus
) |
788 R300_PVS_VF_MAX_VTX_NUM(12) |
789 (r300screen
->caps
.is_r500
? R500_TCL_STATE_OPTIMIZATION
: 0));
791 /* Emit immediates. */
793 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
794 (r300
->screen
->caps
.is_r500
?
795 R500_PVS_CONST_START
: R300_PVS_CONST_START
) +
797 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, imm_count
* 4);
798 for (i
= imm_first
; i
< imm_end
; i
++) {
799 const float *data
= vs
->code
.constants
.Constants
[i
].u
.Immediate
;
800 OUT_CS_TABLE(data
, 4);
806 void r300_emit_vs_constants(struct r300_context
* r300
,
807 unsigned size
, void *state
)
810 ((struct r300_vertex_shader
*)r300
->vs_state
.state
)->externals_count
;
811 struct r300_constant_buffer
*buf
= (struct r300_constant_buffer
*)state
;
818 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG
,
819 (r300
->screen
->caps
.is_r500
?
820 R500_PVS_CONST_START
: R300_PVS_CONST_START
));
821 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA
, count
* 4);
822 OUT_CS_TABLE(buf
->constants
, count
* 4);
826 void r300_emit_viewport_state(struct r300_context
* r300
,
827 unsigned size
, void* state
)
829 struct r300_viewport_state
* viewport
= (struct r300_viewport_state
*)state
;
833 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE
, 6);
834 OUT_CS_32F(viewport
->xscale
);
835 OUT_CS_32F(viewport
->xoffset
);
836 OUT_CS_32F(viewport
->yscale
);
837 OUT_CS_32F(viewport
->yoffset
);
838 OUT_CS_32F(viewport
->zscale
);
839 OUT_CS_32F(viewport
->zoffset
);
840 OUT_CS_REG(R300_VAP_VTE_CNTL
, viewport
->vte_control
);
844 void r300_emit_ztop_state(struct r300_context
* r300
,
845 unsigned size
, void* state
)
847 struct r300_ztop_state
* ztop
= (struct r300_ztop_state
*)state
;
851 OUT_CS_REG(R300_ZB_ZTOP
, ztop
->z_buffer_top
);
855 void r300_emit_texture_cache_inval(struct r300_context
* r300
, unsigned size
, void* state
)
860 OUT_CS_REG(R300_TX_INVALTAGS
, 0);
864 void r300_emit_buffer_validate(struct r300_context
*r300
,
865 boolean do_validate_vertex_buffers
,
866 struct pipe_resource
*index_buffer
)
868 struct pipe_framebuffer_state
* fb
=
869 (struct pipe_framebuffer_state
*)r300
->fb_state
.state
;
870 struct r300_textures_state
*texstate
=
871 (struct r300_textures_state
*)r300
->textures_state
.state
;
872 struct r300_texture
* tex
;
873 struct pipe_vertex_buffer
*vbuf
= r300
->vertex_buffer
;
874 struct pipe_vertex_element
*velem
= r300
->velems
->velem
;
875 struct pipe_resource
*pbuf
;
877 boolean invalid
= FALSE
;
879 /* upload buffers first */
880 if (r300
->screen
->caps
.has_tcl
&& r300
->any_user_vbs
) {
881 r300_upload_user_buffers(r300
);
882 r300
->any_user_vbs
= false;
886 r300
->rws
->reset_bos(r300
->rws
);
889 /* Color buffers... */
890 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
891 tex
= r300_texture(fb
->cbufs
[i
]->texture
);
892 assert(tex
&& tex
->buffer
&& "cbuf is marked, but NULL!");
893 if (!r300_add_texture(r300
->rws
, tex
, 0, tex
->domain
)) {
894 r300
->context
.flush(&r300
->context
, 0, NULL
);
898 /* ...depth buffer... */
900 tex
= r300_texture(fb
->zsbuf
->texture
);
901 assert(tex
&& tex
->buffer
&& "zsbuf is marked, but NULL!");
902 if (!r300_add_texture(r300
->rws
, tex
,
904 r300
->context
.flush(&r300
->context
, 0, NULL
);
909 for (i
= 0; i
< texstate
->count
; i
++) {
910 if (!(texstate
->tx_enable
& (1 << i
))) {
914 tex
= r300_texture(texstate
->sampler_views
[i
]->base
.texture
);
915 if (!r300_add_texture(r300
->rws
, tex
, tex
->domain
, 0)) {
916 r300
->context
.flush(&r300
->context
, 0, NULL
);
920 /* ...occlusion query buffer... */
921 if (r300
->query_start
.dirty
||
922 (r300
->query_current
&& r300
->query_current
->begin_emitted
)) {
923 if (!r300_add_buffer(r300
->rws
, r300
->oqbo
,
924 0, r300_buffer(r300
->oqbo
)->domain
)) {
925 r300
->context
.flush(&r300
->context
, 0, NULL
);
929 /* ...vertex buffer for SWTCL path... */
931 if (!r300_add_buffer(r300
->rws
, r300
->vbo
,
932 r300_buffer(r300
->vbo
)->domain
, 0)) {
933 r300
->context
.flush(&r300
->context
, 0, NULL
);
937 /* ...vertex buffers for HWTCL path... */
938 if (do_validate_vertex_buffers
) {
939 for (i
= 0; i
< r300
->velems
->count
; i
++) {
940 pbuf
= vbuf
[velem
[i
].vertex_buffer_index
].buffer
;
942 if (!r300_add_buffer(r300
->rws
, pbuf
,
943 r300_buffer(pbuf
)->domain
, 0)) {
944 r300
->context
.flush(&r300
->context
, 0, NULL
);
949 /* ...and index buffer for HWTCL path. */
951 if (!r300_add_buffer(r300
->rws
, index_buffer
,
952 r300_buffer(index_buffer
)->domain
, 0)) {
953 r300
->context
.flush(&r300
->context
, 0, NULL
);
957 if (!r300
->rws
->validate(r300
->rws
)) {
958 r300
->context
.flush(&r300
->context
, 0, NULL
);
961 fprintf(stderr
, "r300: Stuck in validation loop, gonna quit now.\n");
969 unsigned r300_get_num_dirty_dwords(struct r300_context
*r300
)
971 struct r300_atom
* atom
;
974 foreach(atom
, &r300
->atom_list
) {
976 dwords
+= atom
->size
;
980 /* let's reserve some more, just in case */
986 /* Emit all dirty state. */
987 void r300_emit_dirty_state(struct r300_context
* r300
)
989 struct r300_atom
* atom
;
991 foreach(atom
, &r300
->atom_list
) {
993 atom
->emit(r300
, atom
->size
, atom
->state
);
994 if (SCREEN_DBG_ON(r300
->screen
, DBG_STATS
)) {